From patchwork Wed Nov 21 07:43:05 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Evgeny Voevodin X-Patchwork-Id: 200597 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id D4D6D2C0080 for ; Wed, 21 Nov 2012 18:56:41 +1100 (EST) Received: from localhost ([::1]:50536 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Tb4yd-0000c7-Uq for incoming@patchwork.ozlabs.org; Wed, 21 Nov 2012 02:44:07 -0500 Received: from eggs.gnu.org ([208.118.235.92]:51305) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Tb4xy-0007FG-Sc for qemu-devel@nongnu.org; Wed, 21 Nov 2012 02:43:29 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Tb4xt-0000Ct-2F for qemu-devel@nongnu.org; Wed, 21 Nov 2012 02:43:26 -0500 Received: from mailout3.w1.samsung.com ([210.118.77.13]:53379) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Tb4xs-0000AZ-Qm for qemu-devel@nongnu.org; Wed, 21 Nov 2012 02:43:21 -0500 Received: from eusync4.samsung.com (mailout3.w1.samsung.com [210.118.77.13]) by mailout3.w1.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0MDT00FSCUSVAX60@mailout3.w1.samsung.com> for qemu-devel@nongnu.org; Wed, 21 Nov 2012 07:43:43 +0000 (GMT) Received: from evvoevodinPC.rnd.samsung.ru ([106.109.8.15]) by eusync4.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0MDT00BGQURZGE50@eusync4.samsung.com> for qemu-devel@nongnu.org; Wed, 21 Nov 2012 07:43:18 +0000 (GMT) From: Evgeny Voevodin To: qemu-devel@nongnu.org Date: Wed, 21 Nov 2012 11:43:05 +0400 Message-id: <1353483787-22308-4-git-send-email-e.voevodin@samsung.com> X-Mailer: git-send-email 1.7.9.5 In-reply-to: <1353483787-22308-1-git-send-email-e.voevodin@samsung.com> References: <1353483787-22308-1-git-send-email-e.voevodin@samsung.com> X-TM-AS-MML: No X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 210.118.77.13 Cc: Evgeny Voevodin , blauwirbel@gmail.com, kyungmin.park@samsung.com, edgar.iglesias@gmail.com, aurelien@aurel32.net, rth@twiddle.net Subject: [Qemu-devel] [PATCH 3/5] TCG: Use gen_opc_icount from context instead of global variable. X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Signed-off-by: Evgeny Voevodin --- target-alpha/translate.c | 2 +- target-arm/translate.c | 2 +- target-cris/translate.c | 2 +- target-i386/translate.c | 2 +- target-lm32/translate.c | 2 +- target-m68k/translate.c | 2 +- target-microblaze/translate.c | 2 +- target-mips/translate.c | 2 +- target-openrisc/translate.c | 2 +- target-ppc/translate.c | 2 +- target-s390x/translate.c | 2 +- target-sh4/translate.c | 2 +- target-sparc/translate.c | 2 +- target-unicore32/translate.c | 2 +- target-xtensa/translate.c | 2 +- translate-all.c | 2 +- 16 files changed, 16 insertions(+), 16 deletions(-) diff --git a/target-alpha/translate.c b/target-alpha/translate.c index bcde367..8b73fbb 100644 --- a/target-alpha/translate.c +++ b/target-alpha/translate.c @@ -3414,7 +3414,7 @@ static inline void gen_intermediate_code_internal(CPUAlphaState *env, } tcg_ctx.gen_opc_pc[lj] = ctx.pc; gen_opc_instr_start[lj] = 1; - gen_opc_icount[lj] = num_insns; + tcg_ctx.gen_opc_icount[lj] = num_insns; } if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO)) gen_io_start(); diff --git a/target-arm/translate.c b/target-arm/translate.c index 8ea8bba..4695d8b 100644 --- a/target-arm/translate.c +++ b/target-arm/translate.c @@ -9843,7 +9843,7 @@ static inline void gen_intermediate_code_internal(CPUARMState *env, tcg_ctx.gen_opc_pc[lj] = dc->pc; gen_opc_condexec_bits[lj] = (dc->condexec_cond << 4) | (dc->condexec_mask >> 1); gen_opc_instr_start[lj] = 1; - gen_opc_icount[lj] = num_insns; + tcg_ctx.gen_opc_icount[lj] = num_insns; } if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO)) diff --git a/target-cris/translate.c b/target-cris/translate.c index 745cd7a..6ec8c3c 100644 --- a/target-cris/translate.c +++ b/target-cris/translate.c @@ -3310,7 +3310,7 @@ gen_intermediate_code_internal(CPUCRISState *env, TranslationBlock *tb, tcg_ctx.gen_opc_pc[lj] = dc->pc; } gen_opc_instr_start[lj] = 1; - gen_opc_icount[lj] = num_insns; + tcg_ctx.gen_opc_icount[lj] = num_insns; } /* Pretty disas. */ diff --git a/target-i386/translate.c b/target-i386/translate.c index aea843c..80fb695 100644 --- a/target-i386/translate.c +++ b/target-i386/translate.c @@ -7993,7 +7993,7 @@ static inline void gen_intermediate_code_internal(CPUX86State *env, tcg_ctx.gen_opc_pc[lj] = pc_ptr; gen_opc_cc_op[lj] = dc->cc_op; gen_opc_instr_start[lj] = 1; - gen_opc_icount[lj] = num_insns; + tcg_ctx.gen_opc_icount[lj] = num_insns; } if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO)) gen_io_start(); diff --git a/target-lm32/translate.c b/target-lm32/translate.c index fcafb06..4e029e0 100644 --- a/target-lm32/translate.c +++ b/target-lm32/translate.c @@ -1056,7 +1056,7 @@ static void gen_intermediate_code_internal(CPULM32State *env, } tcg_ctx.gen_opc_pc[lj] = dc->pc; gen_opc_instr_start[lj] = 1; - gen_opc_icount[lj] = num_insns; + tcg_ctx.gen_opc_icount[lj] = num_insns; } /* Pretty disas. */ diff --git a/target-m68k/translate.c b/target-m68k/translate.c index 74772dd..0762085 100644 --- a/target-m68k/translate.c +++ b/target-m68k/translate.c @@ -3023,7 +3023,7 @@ gen_intermediate_code_internal(CPUM68KState *env, TranslationBlock *tb, } tcg_ctx.gen_opc_pc[lj] = dc->pc; gen_opc_instr_start[lj] = 1; - gen_opc_icount[lj] = num_insns; + tcg_ctx.gen_opc_icount[lj] = num_insns; } if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO)) gen_io_start(); diff --git a/target-microblaze/translate.c b/target-microblaze/translate.c index 6803f73..d975756 100644 --- a/target-microblaze/translate.c +++ b/target-microblaze/translate.c @@ -1792,7 +1792,7 @@ gen_intermediate_code_internal(CPUMBState *env, TranslationBlock *tb, } tcg_ctx.gen_opc_pc[lj] = dc->pc; gen_opc_instr_start[lj] = 1; - gen_opc_icount[lj] = num_insns; + tcg_ctx.gen_opc_icount[lj] = num_insns; } /* Pretty disas. */ diff --git a/target-mips/translate.c b/target-mips/translate.c index 17d5ece..81807cf 100644 --- a/target-mips/translate.c +++ b/target-mips/translate.c @@ -15559,7 +15559,7 @@ gen_intermediate_code_internal (CPUMIPSState *env, TranslationBlock *tb, gen_opc_hflags[lj] = ctx.hflags & MIPS_HFLAG_BMASK; gen_opc_btarget[lj] = ctx.btarget; gen_opc_instr_start[lj] = 1; - gen_opc_icount[lj] = num_insns; + tcg_ctx.gen_opc_icount[lj] = num_insns; } if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO)) gen_io_start(); diff --git a/target-openrisc/translate.c b/target-openrisc/translate.c index b7ad6a4..5b08314 100644 --- a/target-openrisc/translate.c +++ b/target-openrisc/translate.c @@ -1712,7 +1712,7 @@ static inline void gen_intermediate_code_internal(OpenRISCCPU *cpu, } tcg_ctx.gen_opc_pc[k] = dc->pc; gen_opc_instr_start[k] = 1; - gen_opc_icount[k] = num_insns; + tcg_ctx.gen_opc_icount[k] = num_insns; } if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) { diff --git a/target-ppc/translate.c b/target-ppc/translate.c index fcdfa1a..bbe2390 100644 --- a/target-ppc/translate.c +++ b/target-ppc/translate.c @@ -9683,7 +9683,7 @@ static inline void gen_intermediate_code_internal(CPUPPCState *env, } tcg_ctx.gen_opc_pc[lj] = ctx.nip; gen_opc_instr_start[lj] = 1; - gen_opc_icount[lj] = num_insns; + tcg_ctx.gen_opc_icount[lj] = num_insns; } LOG_DISAS("----------------\n"); LOG_DISAS("nip=" TARGET_FMT_lx " super=%d ir=%d\n", diff --git a/target-s390x/translate.c b/target-s390x/translate.c index ff2868f..b2774ee 100644 --- a/target-s390x/translate.c +++ b/target-s390x/translate.c @@ -5166,7 +5166,7 @@ static inline void gen_intermediate_code_internal(CPUS390XState *env, tcg_ctx.gen_opc_pc[lj] = dc.pc; gen_opc_cc_op[lj] = dc.cc_op; gen_opc_instr_start[lj] = 1; - gen_opc_icount[lj] = num_insns; + tcg_ctx.gen_opc_icount[lj] = num_insns; } if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO)) { gen_io_start(); diff --git a/target-sh4/translate.c b/target-sh4/translate.c index 4def163..ca76be5 100644 --- a/target-sh4/translate.c +++ b/target-sh4/translate.c @@ -2008,7 +2008,7 @@ gen_intermediate_code_internal(CPUSH4State * env, TranslationBlock * tb, tcg_ctx.gen_opc_pc[ii] = ctx.pc; gen_opc_hflags[ii] = ctx.flags; gen_opc_instr_start[ii] = 1; - gen_opc_icount[ii] = num_insns; + tcg_ctx.gen_opc_icount[ii] = num_insns; } if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO)) gen_io_start(); diff --git a/target-sparc/translate.c b/target-sparc/translate.c index 4f3a844..cbb8997 100644 --- a/target-sparc/translate.c +++ b/target-sparc/translate.c @@ -5287,7 +5287,7 @@ static inline void gen_intermediate_code_internal(TranslationBlock * tb, tcg_ctx.gen_opc_pc[lj] = dc->pc; gen_opc_npc[lj] = dc->npc; gen_opc_instr_start[lj] = 1; - gen_opc_icount[lj] = num_insns; + tcg_ctx.gen_opc_icount[lj] = num_insns; } } if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO)) diff --git a/target-unicore32/translate.c b/target-unicore32/translate.c index 32a4265..0562615 100644 --- a/target-unicore32/translate.c +++ b/target-unicore32/translate.c @@ -2008,7 +2008,7 @@ static inline void gen_intermediate_code_internal(CPUUniCore32State *env, } tcg_ctx.gen_opc_pc[lj] = dc->pc; gen_opc_instr_start[lj] = 1; - gen_opc_icount[lj] = num_insns; + tcg_ctx.gen_opc_icount[lj] = num_insns; } if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO)) { diff --git a/target-xtensa/translate.c b/target-xtensa/translate.c index 21126fc..e93c2e6 100644 --- a/target-xtensa/translate.c +++ b/target-xtensa/translate.c @@ -2902,7 +2902,7 @@ static void gen_intermediate_code_internal( } tcg_ctx.gen_opc_pc[lj] = dc.pc; gen_opc_instr_start[lj] = 1; - gen_opc_icount[lj] = insn_count; + tcg_ctx.gen_opc_icount[lj] = insn_count; } if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) { diff --git a/translate-all.c b/translate-all.c index d9c2e57..177e95a 100644 --- a/translate-all.c +++ b/translate-all.c @@ -148,7 +148,7 @@ int cpu_restore_state(TranslationBlock *tb, /* now find start of instruction before */ while (gen_opc_instr_start[j] == 0) j--; - env->icount_decr.u16.low -= gen_opc_icount[j]; + env->icount_decr.u16.low -= s->gen_opc_icount[j]; restore_state_to_opc(env, tb, j);