From patchwork Tue Nov 20 07:29:16 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sivaram Nair X-Patchwork-Id: 200239 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id DCE4B2C0093 for ; Tue, 20 Nov 2012 18:33:13 +1100 (EST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752291Ab2KTHaC (ORCPT ); Tue, 20 Nov 2012 02:30:02 -0500 Received: from hqemgate03.nvidia.com ([216.228.121.140]:7715 "EHLO hqemgate03.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751595Ab2KTHaA (ORCPT ); Tue, 20 Nov 2012 02:30:00 -0500 Received: from hqnvupgp05.nvidia.com (Not Verified[216.228.121.13]) by hqemgate03.nvidia.com id ; Mon, 19 Nov 2012 23:32:47 -0800 Received: from hqemhub01.nvidia.com ([172.17.108.22]) by hqnvupgp05.nvidia.com (PGP Universal service); Mon, 19 Nov 2012 23:29:49 -0800 X-PGP-Universal: processed; by hqnvupgp05.nvidia.com on Mon, 19 Nov 2012 23:29:49 -0800 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by hqemhub01.nvidia.com (172.20.150.30) with Microsoft SMTP Server id 8.3.279.1; Mon, 19 Nov 2012 23:29:48 -0800 Received: from thelma.nvidia.com (Not Verified[172.16.212.77]) by hqnvemgw02.nvidia.com with MailMarshal (v6,7,2,8378) id ; Mon, 19 Nov 2012 23:29:49 -0800 Received: from sivaramn-lnx.Nvidia.com (dhcp-10-21-25-217.nvidia.com [10.21.25.217]) by thelma.nvidia.com (8.13.8+Sun/8.8.8) with ESMTP id qAK7TgE7009814; Mon, 19 Nov 2012 23:29:43 -0800 (PST) From: Sivaram Nair To: CC: , , , , Sivaram Nair Subject: [PATCH 1/1] arm: tegra: select correct parent clk for pll_p Date: Tue, 20 Nov 2012 09:29:16 +0200 Message-ID: <1353396556-7738-1-git-send-email-sivaramn@nvidia.com> X-Mailer: git-send-email 1.7.9.5 X-NVConfidentiality: public MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org For Tegra30, pll_p clk's parent is wrongly specified as clk_m instead of pll_ref in the tegra30_clk_init_table and this is resulting in a boot-time warning. This patch fixes this by correcting the clk init table. Signed-off-by: Sivaram Nair --- arch/arm/mach-tegra/common.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/mach-tegra/common.c b/arch/arm/mach-tegra/common.c index 0816562..d54cfc5 100644 --- a/arch/arm/mach-tegra/common.c +++ b/arch/arm/mach-tegra/common.c @@ -104,7 +104,7 @@ static __initdata struct tegra_clk_init_table tegra20_clk_init_table[] = { static __initdata struct tegra_clk_init_table tegra30_clk_init_table[] = { /* name parent rate enabled */ { "clk_m", NULL, 0, true }, - { "pll_p", "clk_m", 408000000, true }, + { "pll_p", "pll_ref", 408000000, true }, { "pll_p_out1", "pll_p", 9600000, true }, { "pll_p_out4", "pll_p", 102000000, true }, { "sclk", "pll_p_out4", 102000000, true },