diff mbox

powerpc, perf: Change PMU flag representation from decimal to hex

Message ID 1353323506-17970-1-git-send-email-khandual@linux.vnet.ibm.com (mailing list archive)
State Accepted, archived
Commit 6f79cb8134c5cd9f3346087906829013dce8d460
Delegated to: Benjamin Herrenschmidt
Headers show

Commit Message

Anshuman Khandual Nov. 19, 2012, 11:11 a.m. UTC 
Change the representation of the PMU flags from decimal to hex since they
are bitfields which are easier to read in hex.

Signed-off-by: Anshuman Khandual <khandual@linux.vnet.ibm.com>
---
 Changed the 64 bit constants into 32 bit constants as it would apply to
 32 bit variable power_pmu.flags

 arch/powerpc/include/asm/perf_event_server.h | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)
diff mbox

Patch

diff --git a/arch/powerpc/include/asm/perf_event_server.h b/arch/powerpc/include/asm/perf_event_server.h
index 9710be3..d3e9748 100644
--- a/arch/powerpc/include/asm/perf_event_server.h
+++ b/arch/powerpc/include/asm/perf_event_server.h
@@ -45,11 +45,11 @@  struct power_pmu {
 /*
  * Values for power_pmu.flags
  */
-#define PPMU_LIMITED_PMC5_6	1	/* PMC5/6 have limited function */
-#define PPMU_ALT_SIPR		2	/* uses alternate posn for SIPR/HV */
-#define PPMU_NO_SIPR		4	/* no SIPR/HV in MMCRA at all */
-#define PPMU_NO_CONT_SAMPLING	8	/* no continuous sampling */
-#define PPMU_SIAR_VALID		16	/* Processor has SIAR Valid bit */
+#define PPMU_LIMITED_PMC5_6	0x00000001 /* PMC5/6 have limited function */
+#define PPMU_ALT_SIPR		0x00000002 /* uses alternate posn for SIPR/HV */
+#define PPMU_NO_SIPR		0x00000004 /* no SIPR/HV in MMCRA at all */
+#define PPMU_NO_CONT_SAMPLING	0x00000008 /* no continuous sampling */
+#define PPMU_SIAR_VALID		0x00000010 /* Processor has SIAR Valid bit */
 
 /*
  * Values for flags to get_alternatives()