From patchwork Mon Nov 19 09:43:07 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexandre Courbot X-Patchwork-Id: 199960 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 2A5E72C0098 for ; Mon, 19 Nov 2012 20:43:19 +1100 (EST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753418Ab2KSJnS (ORCPT ); Mon, 19 Nov 2012 04:43:18 -0500 Received: from hqemgate03.nvidia.com ([216.228.121.140]:6194 "EHLO hqemgate03.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753334Ab2KSJnR (ORCPT ); Mon, 19 Nov 2012 04:43:17 -0500 Received: from hqnvupgp06.nvidia.com (Not Verified[216.228.121.13]) by hqemgate03.nvidia.com id ; Mon, 19 Nov 2012 01:46:12 -0800 Received: from hqemhub01.nvidia.com ([172.17.108.22]) by hqnvupgp06.nvidia.com (PGP Universal service); Mon, 19 Nov 2012 01:43:15 -0800 X-PGP-Universal: processed; by hqnvupgp06.nvidia.com on Mon, 19 Nov 2012 01:43:15 -0800 Received: from percival.nvidia.com (172.20.144.16) by hqemhub01.nvidia.com (172.20.150.30) with Microsoft SMTP Server (TLS) id 8.3.279.1; Mon, 19 Nov 2012 01:43:14 -0800 From: Alexandre Courbot To: Stephen Warren , Mark Zhang , Thierry Reding CC: , , Alexandre Courbot Subject: [PATCH v3] ARM: tegra: ventana: enable internal display Date: Mon, 19 Nov 2012 18:43:07 +0900 Message-ID: <1353318187-26484-1-git-send-email-acourbot@nvidia.com> X-Mailer: git-send-email 1.8.0 X-NVConfidentiality: public MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Enable host1x and add the rgb output. Also add the power sequence that controls the backlight and panel. The sequence strictly follows the order and timings of the panel specification. Currently the backlight device controls both backlight and panel, this needs to be fixed once the panel framework supports power sequences. Signed-off-by: Alexandre Courbot --- arch/arm/boot/dts/tegra20-ventana.dts | 108 +++++++++++++++++++++++++++++++++- 1 file changed, 105 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/tegra20-ventana.dts b/arch/arm/boot/dts/tegra20-ventana.dts index adc4754..31c9c5c 100644 --- a/arch/arm/boot/dts/tegra20-ventana.dts +++ b/arch/arm/boot/dts/tegra20-ventana.dts @@ -10,6 +10,15 @@ reg = <0x00000000 0x40000000>; }; + host1x { + dc@54200000 { + rgb { + status = "okay"; + nvidia,ddc-i2c-bus = <&lcd_ddc>; + }; + }; + }; + pinmux { pinctrl-names = "default"; pinctrl-0 = <&state_default>; @@ -341,7 +350,7 @@ #size-cells = <0>; }; - i2c@1 { + lcd_ddc: i2c@1 { reg = <1>; #address-cells = <1>; #size-cells = <0>; @@ -516,6 +525,99 @@ bus-width = <8>; }; + backlight: backlight { + compatible = "pwm-backlight"; + brightness-levels = <0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 255>; + default-brightness-level = <12>; + + /* resources used by the power sequences */ + pwms = <&pwm 2 5000000>; + pwm-names = "backlight"; + power-supply = <&vdd_bl_reg>; + panel-supply = <&vdd_panel_reg>; + + power-sequences { + power-on { + /* + * Panel power and LVDS enable. + * TODO: move into the panel device as soon as + * panel framework supports power sequences. + */ + step0 { + type = "regulator"; + id = "panel"; + enable; + }; + step1 { + type = "gpio"; + gpio = <&gpio 10 0>; + value = <1>; + }; + step2 { + type = "delay"; + delay = <200000>; + }; + /* Backlight sequence. This belongs here. */ + step3 { + type = "regulator"; + id = "power"; + enable; + }; + step4 { + type = "delay"; + delay = <10000>; + }; + step5 { + type = "pwm"; + id = "backlight"; + enable; + }; + step6 { + type = "gpio"; + gpio = <&gpio 28 0>; + value = <1>; + }; + }; + + power-off { + step0 { + type = "gpio"; + gpio = <&gpio 28 0>; + value = <0>; + }; + step1 { + type = "pwm"; + id = "backlight"; + disable; + }; + step2 { + type = "delay"; + delay = <10000>; + }; + step3 { + type = "regulator"; + id = "power"; + disable; + }; + /* This also belongs to the panel sequence */ + step4 { + type = "delay"; + delay = <200000>; + }; + step5 { + type = "gpio"; + gpio = <&gpio 10 0>; + value = <0>; + }; + step6 { + type = "regulator"; + id = "panel"; + disable; + }; + }; + }; + }; + regulators { compatible = "simple-bus"; #address-cells = <1>; @@ -549,7 +651,7 @@ enable-active-high; }; - regulator@3 { + vdd_panel_reg: regulator@3 { compatible = "regulator-fixed"; reg = <3>; regulator-name = "vdd_pnl"; @@ -559,7 +661,7 @@ enable-active-high; }; - regulator@4 { + vdd_bl_reg: regulator@4 { compatible = "regulator-fixed"; reg = <4>; regulator-name = "vdd_bl";