From patchwork Fri Nov 16 21:20:05 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 199771 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 5CBDF2C0090 for ; Sat, 17 Nov 2012 08:35:19 +1100 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 621094A3B4; Fri, 16 Nov 2012 22:34:24 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id Z6ZrZFaNZt0L; Fri, 16 Nov 2012 22:34:23 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 7E3754A235; Fri, 16 Nov 2012 22:30:43 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 7122D4A17C for ; Fri, 16 Nov 2012 22:29:24 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id no5s6lqccJ6s for ; Fri, 16 Nov 2012 22:29:23 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail-vc0-f202.google.com (mail-vc0-f202.google.com [209.85.220.202]) by theia.denx.de (Postfix) with ESMTPS id 070E14A1A5 for ; Fri, 16 Nov 2012 22:28:51 +0100 (CET) Received: by mail-vc0-f202.google.com with SMTP id fy27so349310vcb.3 for ; Fri, 16 Nov 2012 13:28:49 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references :x-gm-message-state; bh=d5nvp7TXDYHJbdGVUeTge3wUM/O9jDzpXnvmME6fj2o=; b=guwtLsb923xkfomGnXrJ4atgiUeZDe4ixZdni4a5spqI7XxO/1SaTPTVvt9mIEL5Ge Lv4uQyl6nHVvrSM4dqJ8lkT1YQ+3BixVUwfCZhEExYE3kqxHr65nlLACVYwEEV/WX5St 9IDpSilMHNRAfa75doVNZoVRCCDrwPoXJlZRm4xkaduQlrBNlOTthU4anOVW8FcjwHht /lAQNefLjxMG0CtNSL5PVuQj1c7dHCvTnc7l3IpRHRSJLZQmNGYakB2fRc4+tvwi9hkO +XK6mFI4AshfHhCV/EHK0vlqNf7JmLl+38IiSgZqYJTn6dgXne4L/oFMmViLjqPVUCp9 u4yg== Received: by 10.236.173.201 with SMTP id v49mr4065183yhl.19.1353101329556; Fri, 16 Nov 2012 13:28:49 -0800 (PST) Received: from wpzn3.hot.corp.google.com (216-239-44-65.google.com [216.239.44.65]) by gmr-mx.google.com with ESMTPS id i7si210383yhj.6.2012.11.16.13.28.49 (version=TLSv1/SSLv3 cipher=AES128-SHA); Fri, 16 Nov 2012 13:28:49 -0800 (PST) Received: from kaka.mtv.corp.google.com (kaka.mtv.corp.google.com [172.22.73.79]) by wpzn3.hot.corp.google.com (Postfix) with ESMTP id 53E09100048; Fri, 16 Nov 2012 13:28:49 -0800 (PST) Received: by kaka.mtv.corp.google.com (Postfix, from userid 121222) id 333BF1608CB; Fri, 16 Nov 2012 13:28:49 -0800 (PST) From: Simon Glass To: U-Boot Mailing List Date: Fri, 16 Nov 2012 13:20:05 -0800 Message-Id: <1353100842-20126-21-git-send-email-sjg@chromium.org> X-Mailer: git-send-email 1.7.7.3 In-Reply-To: <1353100842-20126-1-git-send-email-sjg@chromium.org> References: <1353100842-20126-1-git-send-email-sjg@chromium.org> X-Gm-Message-State: ALoCoQkQVCQP6Lz7DX1sOdkdsj4TSKHqwDVQz5BaH7o56o4I6jTrj82qpQE429LSPEifHNrP/acivpqdrk9zdkj5TytvdWklAyJ0+/iRIZAmmfhiwq4Ios31VPmPN/GTsvtU75BCB9l10BzccRgU3UUE8ZP4bbYvKgVMWxuX0rwlRUmI0VomWVnkgonKgLHLZATZc8Pm5GOw Cc: Kim Phillips , Kumar Gala , Andy Fleming , Tom Rini , Stefan Roese Subject: [U-Boot] [PATCH 20/57] ppc: Move CONFIG_QE to arch_global_data X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de Move the quantative easing fields into arch_global_data and tidy up. Signed-off-by: Simon Glass --- arch/powerpc/cpu/mpc83xx/speed.c | 5 +++-- arch/powerpc/cpu/mpc85xx/speed.c | 4 ++-- arch/powerpc/include/asm/global_data.h | 14 ++++++-------- drivers/qe/fdt.c | 8 ++++---- drivers/qe/qe.c | 19 ++++++++++--------- 5 files changed, 25 insertions(+), 25 deletions(-) diff --git a/arch/powerpc/cpu/mpc83xx/speed.c b/arch/powerpc/cpu/mpc83xx/speed.c index a40a055..ba8b285 100644 --- a/arch/powerpc/cpu/mpc83xx/speed.c +++ b/arch/powerpc/cpu/mpc83xx/speed.c @@ -495,7 +495,7 @@ int get_clocks(void) gd->arch.mem_sec_clk = mem_sec_clk; #endif #if defined(CONFIG_QE) - gd->qe_clk = qe_clk; + gd->arch.qe_clk = qe_clk; gd->arch.brg_clk = brg_clk; #endif #if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \ @@ -541,7 +541,8 @@ static int do_clocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) printf(" Coherent System Bus: %-4s MHz\n", strmhz(buf, gd->arch.csb_clk)); #if defined(CONFIG_QE) - printf(" QE: %-4s MHz\n", strmhz(buf, gd->qe_clk)); + printf(" QE: %-4s MHz\n", + strmhz(buf, gd->arch.qe_clk)); printf(" BRG: %-4s MHz\n", strmhz(buf, gd->arch.brg_clk)); #endif diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c index 81c80e7..7173c07 100644 --- a/arch/powerpc/cpu/mpc85xx/speed.c +++ b/arch/powerpc/cpu/mpc85xx/speed.c @@ -394,8 +394,8 @@ int get_clocks (void) gd->arch.lbc_clk = sys_info.freqLocalBus; #ifdef CONFIG_QE - gd->qe_clk = sys_info.freqQE; - gd->arch.brg_clk = gd->qe_clk / 2; + gd->arch.qe_clk = sys_info.freqQE; + gd->arch.brg_clk = gd->arch.qe_clk / 2; #endif /* * The base clock for I2C depends on the actual SOC. Unfortunately, diff --git a/arch/powerpc/include/asm/global_data.h b/arch/powerpc/include/asm/global_data.h index b710f25..760cdab 100644 --- a/arch/powerpc/include/asm/global_data.h +++ b/arch/powerpc/include/asm/global_data.h @@ -39,9 +39,6 @@ struct arch_global_data { unsigned long scc_clk; unsigned long brg_clk; #endif -#if defined(CONFIG_QE) - u32 brg_clk; -#endif /* TODO: sjg@chromium.org: Should these be unslgned long? */ #if defined(CONFIG_MPC83xx) /* There are other clocks in the MPC83XX */ @@ -85,6 +82,12 @@ struct arch_global_data { u32 i2c1_clk; u32 i2c2_clk; #endif +#if defined(CONFIG_QE) + u32 qe_clk; + u32 brg_clk; + uint mp_alloc_base; + uint mp_alloc_top; +#endif /* CONFIG_QE */ }; /* @@ -107,11 +110,6 @@ typedef struct global_data { #if defined(CONFIG_FSL_ESDHC) u32 sdhc_clk; #endif -#if defined(CONFIG_QE) - u32 qe_clk; - uint mp_alloc_base; - uint mp_alloc_top; -#endif /* CONFIG_QE */ #if defined(CONFIG_FSL_LAW) u32 used_laws; #endif diff --git a/drivers/qe/fdt.c b/drivers/qe/fdt.c index 1a123b8..5a0f277 100644 --- a/drivers/qe/fdt.c +++ b/drivers/qe/fdt.c @@ -75,16 +75,16 @@ error: void ft_qe_setup(void *blob) { do_fixup_by_prop_u32(blob, "device_type", "qe", 4, - "bus-frequency", gd->qe_clk, 1); + "bus-frequency", gd->arch.qe_clk, 1); do_fixup_by_prop_u32(blob, "device_type", "qe", 4, "brg-frequency", gd->arch.brg_clk, 1); do_fixup_by_compat_u32(blob, "fsl,qe", - "clock-frequency", gd->qe_clk, 1); + "clock-frequency", gd->arch.qe_clk, 1); do_fixup_by_compat_u32(blob, "fsl,qe", - "bus-frequency", gd->qe_clk, 1); + "bus-frequency", gd->arch.qe_clk, 1); do_fixup_by_compat_u32(blob, "fsl,qe", "brg-frequency", gd->arch.brg_clk, 1); do_fixup_by_compat_u32(blob, "fsl,qe-gtm", - "clock-frequency", gd->qe_clk / 2, 1); + "clock-frequency", gd->arch.qe_clk / 2, 1); fdt_fixup_qe_firmware(blob); } diff --git a/drivers/qe/qe.c b/drivers/qe/qe.c index 72c585c..5fd2135 100644 --- a/drivers/qe/qe.c +++ b/drivers/qe/qe.c @@ -58,21 +58,22 @@ uint qe_muram_alloc(uint size, uint align) uint savebase; align_mask = align - 1; - savebase = gd->mp_alloc_base; + savebase = gd->arch.mp_alloc_base; - if ((off = (gd->mp_alloc_base & align_mask)) != 0) - gd->mp_alloc_base += (align - off); + off = gd->arch.mp_alloc_base & align_mask; + if (off != 0) + gd->arch.mp_alloc_base += (align - off); if ((off = size & align_mask) != 0) size += (align - off); - if ((gd->mp_alloc_base + size) >= gd->mp_alloc_top) { - gd->mp_alloc_base = savebase; + if ((gd->arch.mp_alloc_base + size) >= gd->arch.mp_alloc_top) { + gd->arch.mp_alloc_base = savebase; printf("%s: ran out of ram.\n", __FUNCTION__); } - retloc = gd->mp_alloc_base; - gd->mp_alloc_base += size; + retloc = gd->arch.mp_alloc_base; + gd->arch.mp_alloc_base += size; memset((void *)&qe_immr->muram[retloc], 0, size); @@ -183,8 +184,8 @@ void qe_init(uint qe_base) out_be32(&qe_immr->iram.iready,QE_IRAM_READY); #endif - gd->mp_alloc_base = QE_DATAONLY_BASE; - gd->mp_alloc_top = gd->mp_alloc_base + QE_DATAONLY_SIZE; + gd->arch.mp_alloc_base = QE_DATAONLY_BASE; + gd->arch.mp_alloc_top = gd->arch.mp_alloc_base + QE_DATAONLY_SIZE; qe_sdma_init(); qe_snums_init();