From patchwork Wed Nov 14 14:38:21 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Subject: mips/malta: fix CBUS UART interrupt pin Date: Wed, 14 Nov 2012 04:38:21 -0000 From: Aurelien Jarno X-Patchwork-Id: 198922 Message-Id: <1352903901-8797-1-git-send-email-aurelien@aurel32.net> To: qemu-devel@nongnu.org Cc: Aurelien Jarno According to the MIPS Malta Developement Platform User's Manual, the i8259 interrupt controller is supposed to be connected to the hardware IRQ0, and the CBUS UART to the hardware interrupt 2. In QEMU they are both connected to hardware interrupt 0, the CBUS UART interrupt being wrong. This patch fixes that. It should be noted that the irq array in QEMU includes the software interrupts, hence env->irq[2] is the first hardware interrupt. Cc: Ralf Baechle Signed-off-by: Aurelien Jarno Reviewed-by: Eric Johnson --- hw/mips_malta.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/hw/mips_malta.c b/hw/mips_malta.c index 0571d58..4d2464a 100644 --- a/hw/mips_malta.c +++ b/hw/mips_malta.c @@ -861,7 +861,8 @@ void mips_malta_init(QEMUMachineInitArgs *args) be = 0; #endif /* FPGA */ - malta_fpga_init(system_memory, FPGA_ADDRESS, env->irq[2], serial_hds[2]); + /* The CBUS UART is attached to the MIPS CPU INT2 pin, ie interrupt 4 */ + malta_fpga_init(system_memory, FPGA_ADDRESS, env->irq[4], serial_hds[2]); /* Load firmware in flash / BIOS. */ dinfo = drive_get(IF_PFLASH, 0, fl_idx);