From patchwork Tue Nov 13 19:57:14 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Beno=C3=AEt_Th=C3=A9baudeau?= X-Patchwork-Id: 198766 X-Patchwork-Delegate: sbabic@denx.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 61C812C0087 for ; Wed, 14 Nov 2012 06:50:37 +1100 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 2556D4A20F; Tue, 13 Nov 2012 20:50:36 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id E3DX6DUyGhf2; Tue, 13 Nov 2012 20:50:35 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id AAA0F4A1E6; Tue, 13 Nov 2012 20:50:34 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id EE8094A1E3 for ; Tue, 13 Nov 2012 20:50:32 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id PLtNaHvkartA for ; Tue, 13 Nov 2012 20:50:32 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from zose-mta11.web4all.fr (zose-mta-11.w4a.fr [178.33.204.86]) by theia.denx.de (Postfix) with ESMTP id 159174A020 for ; Tue, 13 Nov 2012 20:50:30 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by zose-mta11.web4all.fr (Postfix) with ESMTP id 7127A4A01E; Tue, 13 Nov 2012 20:56:49 +0100 (CET) X-Virus-Scanned: amavisd-new at zose1.web4all.fr Received: from zose-mta11.web4all.fr ([127.0.0.1]) by localhost (zose-mta11.web4all.fr [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id S3V716vcxe6r; Tue, 13 Nov 2012 20:56:49 +0100 (CET) Received: from zose-store12.web4all.fr (zose-store12.web4all.fr [178.33.204.49]) by zose-mta11.web4all.fr (Postfix) with ESMTP id 2CEA74A002; Tue, 13 Nov 2012 20:56:49 +0100 (CET) Date: Tue, 13 Nov 2012 20:57:14 +0100 (CET) From: =?utf-8?Q?Beno=C3=AEt_Th=C3=A9baudeau?= To: U-Boot-Users ML Message-ID: <1600403813.1238946.1352836634019.JavaMail.root@advansee.com> In-Reply-To: <288431028.1238905.1352836530889.JavaMail.root@advansee.com> MIME-Version: 1.0 X-Originating-IP: [88.188.188.98] X-Mailer: Zimbra 7.2.0_GA_2669 (ZimbraWebClient - FF3.0 (Win)/7.2.0_GA_2669) Cc: Marek Vasut Subject: [U-Boot] [PATCH v3 07/13] ehci-mx5: Add missing OC_DIS for i.MX53 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de The i.MX53 has MXC_H*_UCTRL_H*_OC_DIS_BIT bits to disable the oc pin. Signed-off-by: Benoît Thébaudeau Cc: Marek Vasut Cc: Stefano Babic --- Changes for v2: None. Changes for v3: None. .../drivers/usb/host/ehci-mx5.c | 24 ++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git u-boot-usb-76454b2.orig/drivers/usb/host/ehci-mx5.c u-boot-usb-76454b2/drivers/usb/host/ehci-mx5.c index 4f4b98a..6f7fe80 100644 --- u-boot-usb-76454b2.orig/drivers/usb/host/ehci-mx5.c +++ u-boot-usb-76454b2/drivers/usb/host/ehci-mx5.c @@ -32,12 +32,14 @@ #define MXC_OTG_OFFSET 0 #define MXC_H1_OFFSET 0x200 #define MXC_H2_OFFSET 0x400 +#define MXC_H3_OFFSET 0x600 #define MXC_USBCTRL_OFFSET 0 #define MXC_USB_PHY_CTR_FUNC_OFFSET 0x8 #define MXC_USB_PHY_CTR_FUNC2_OFFSET 0xc #define MXC_USB_CTRL_1_OFFSET 0x10 #define MXC_USBH2CTRL_OFFSET 0x14 +#define MXC_USBH3CTRL_OFFSET 0x18 /* USB_CTRL */ /* OTG wakeup intr enable */ @@ -58,10 +60,16 @@ #define MXC_H1_OC_DIS_BIT (1 << 5) /* USBH2CTRL */ +#define MXC_H2_UCTRL_H2_OC_DIS_BIT (1 << 30) #define MXC_H2_UCTRL_H2UIE_BIT (1 << 8) #define MXC_H2_UCTRL_H2WIE_BIT (1 << 7) #define MXC_H2_UCTRL_H2PM_BIT (1 << 4) +/* USBH3CTRL */ +#define MXC_H3_UCTRL_H3_OC_DIS_BIT (1 << 30) +#define MXC_H3_UCTRL_H3UIE_BIT (1 << 8) +#define MXC_H3_UCTRL_H3WIE_BIT (1 << 7) + /* USB_CTRL_1 */ #define MXC_USB_CTRL_UH1_EXT_CLK_EN (1 << 25) @@ -203,8 +211,24 @@ int mxc_set_usbcontrol(int port, unsigned int flags) else v |= MXC_H2_UCTRL_H2PM_BIT; /* H2 power mask used */ #endif +#ifdef CONFIG_MX53 + if (flags & MXC_EHCI_POWER_PINS_ENABLED) + v &= ~MXC_H2_UCTRL_H2_OC_DIS_BIT; /* OC is used */ + else + v |= MXC_H2_UCTRL_H2_OC_DIS_BIT; /* OC is not used */ +#endif __raw_writel(v, usbother_base + MXC_USBH2CTRL_OFFSET); break; +#ifdef CONFIG_MX53 + case 3: /* Host 3 ULPI */ + v = __raw_readl(usbother_base + MXC_USBH3CTRL_OFFSET); + if (flags & MXC_EHCI_POWER_PINS_ENABLED) + v &= ~MXC_H3_UCTRL_H3_OC_DIS_BIT; /* OC is used */ + else + v |= MXC_H3_UCTRL_H3_OC_DIS_BIT; /* OC is not used */ + __raw_writel(v, usbother_base + MXC_USBH3CTRL_OFFSET); + break; +#endif } return ret;