Patchwork Document __ATOMIC_HLE_ACQUIRE/RELEASE

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Submitter Andi Kleen
Date Nov. 9, 2012, 3:04 p.m.
Message ID <1352473455-12009-1-git-send-email-andi@firstfloor.org>
Download mbox | patch
Permalink /patch/198096/
State New
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Comments

Andi Kleen - Nov. 9, 2012, 3:04 p.m.
From: Andi Kleen <ak@linux.intel.com>

Make a first stab at the undocumented HLE_ACQUIRE/RELEASE
memory model modifiers in the documentation

gcc/:
2012-11-09 Andi Kleen  <ak@linux.intel.com>

	* doc/extend.texi: Document __ATOMIC_HLE_ACQUIRE and RELEASE.
---
 gcc/doc/extend.texi | 10 ++++++++++
 1 file changed, 10 insertions(+)
Jakub Jelinek - Nov. 9, 2012, 3:19 p.m.
On Fri, Nov 09, 2012 at 04:04:15PM +0100, Andi Kleen wrote:
> +Additional target specific flags that can be ored with the memory models.
> +@table  @code
> +@item __ATOMIC_HLE_ACQUIRE
> +(on i386/x86_64). Start a Hardware Lock Elision transaction with the atomic
> +operation. The memory model must be @code{__ATOMIC_ACQUIRE} or stronger.

Two spaces after . instead of just one.

> +@item __ATOMIC_HLE_RELEASE
> +(on i386/x86_64). Commit a Hardware Lock Elision transaction with the atomic
> +operation. The memory model must be @code{__ATOMIC_RELEASE} or stronger.
> +@end table
> +
>  When implementing patterns for these built-in functions, the memory model
>  parameter can be ignored as long as the pattern implements the most
>  restrictive @code{__ATOMIC_SEQ_CST} model.  Any of the other memory models

	Jakub

Patch

diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi
index 54fd548..248977d 100644
--- a/gcc/doc/extend.texi
+++ b/gcc/doc/extend.texi
@@ -7194,6 +7194,16 @@  Full barrier in both directions and synchronizes with acquire loads and
 release stores in all threads.
 @end table
 
+Additional target specific flags that can be ored with the memory models.
+@table  @code
+@item __ATOMIC_HLE_ACQUIRE
+(on i386/x86_64). Start a Hardware Lock Elision transaction with the atomic
+operation. The memory model must be @code{__ATOMIC_ACQUIRE} or stronger.
+@item __ATOMIC_HLE_RELEASE
+(on i386/x86_64). Commit a Hardware Lock Elision transaction with the atomic
+operation. The memory model must be @code{__ATOMIC_RELEASE} or stronger.
+@end table
+
 When implementing patterns for these built-in functions, the memory model
 parameter can be ignored as long as the pattern implements the most
 restrictive @code{__ATOMIC_SEQ_CST} model.  Any of the other memory models