Message ID | 1352441953-29096-10-git-send-email-mikey@neuling.org (mailing list archive) |
---|---|
State | Accepted, archived |
Headers | show |
> --- a/arch/powerpc/include/asm/reg.h > +++ b/arch/powerpc/include/asm/reg.h > @@ -249,6 +249,8 @@ > #define LPCR_RMLS 0x1C000000 /* impl dependent rmo limit > sel */ > #define LPCR_RMLS_SH (63-37) > #define LPCR_ILE 0x02000000 /* !HV irqs set MSR:LE */ > +#define LPCR_AIL_0 0x00000000 /* MMU off IRQ location 0x0 */ > +#define LPCR_AIL_3 0x01800000 /* MMU on IRQ location > 0xc00...4xxx */ s/IRQ location/exception offset/ ? > --- a/arch/powerpc/kernel/cpu_setup_power.S > +++ b/arch/powerpc/kernel/cpu_setup_power.S > @@ -54,6 +54,7 @@ _GLOBAL(__setup_cpu_power8) > li r0,0 > mtspr SPRN_LPID,r0 > mfspr r3,SPRN_LPCR > + oris r3, r3, LPCR_AIL_3@h Is the AIL field only two bits? If not, you probably want to clear the other bits. This series looks really nice btw :-) Segher
Segher Boessenkool <segher@kernel.crashing.org> wrote: > > --- a/arch/powerpc/include/asm/reg.h > > +++ b/arch/powerpc/include/asm/reg.h > > @@ -249,6 +249,8 @@ > > #define LPCR_RMLS 0x1C000000 /* impl dependent rmo limit sel */ > > #define LPCR_RMLS_SH (63-37) > > #define LPCR_ILE 0x02000000 /* !HV irqs set MSR:LE */ > > +#define LPCR_AIL_0 0x00000000 /* MMU off IRQ location 0x0 */ > > +#define LPCR_AIL_3 0x01800000 /* MMU on IRQ location 0xc00...4xxx */ > > s/IRQ location/exception offset/ ? Sure, updated. > > > --- a/arch/powerpc/kernel/cpu_setup_power.S > > +++ b/arch/powerpc/kernel/cpu_setup_power.S > > @@ -54,6 +54,7 @@ _GLOBAL(__setup_cpu_power8) > > li r0,0 > > mtspr SPRN_LPID,r0 > > mfspr r3,SPRN_LPCR > > + oris r3, r3, LPCR_AIL_3@h > > Is the AIL field only two bits? If not, you probably want to clear > the other bits. Yes it only 2 bits. > This series looks really nice btw :-) Cheers, Mikey
diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h index 7b44a6e..886ab8e 100644 --- a/arch/powerpc/include/asm/reg.h +++ b/arch/powerpc/include/asm/reg.h @@ -249,6 +249,8 @@ #define LPCR_RMLS 0x1C000000 /* impl dependent rmo limit sel */ #define LPCR_RMLS_SH (63-37) #define LPCR_ILE 0x02000000 /* !HV irqs set MSR:LE */ +#define LPCR_AIL_0 0x00000000 /* MMU off IRQ location 0x0 */ +#define LPCR_AIL_3 0x01800000 /* MMU on IRQ location 0xc00...4xxx */ #define LPCR_PECE 0x00007000 /* powersave exit cause enable */ #define LPCR_PECE0 0x00004000 /* ext. exceptions can cause exit */ #define LPCR_PECE1 0x00002000 /* decrementer can cause exit */ diff --git a/arch/powerpc/kernel/cpu_setup_power.S b/arch/powerpc/kernel/cpu_setup_power.S index 52dd033..57cf140 100644 --- a/arch/powerpc/kernel/cpu_setup_power.S +++ b/arch/powerpc/kernel/cpu_setup_power.S @@ -54,6 +54,7 @@ _GLOBAL(__setup_cpu_power8) li r0,0 mtspr SPRN_LPID,r0 mfspr r3,SPRN_LPCR + oris r3, r3, LPCR_AIL_3@h bl __init_LPCR bl __init_TLB mtlr r11 @@ -67,6 +68,7 @@ _GLOBAL(__restore_cpu_power8) li r0,0 mtspr SPRN_LPID,r0 mfspr r3,SPRN_LPCR + oris r3, r3, LPCR_AIL_3@h bl __init_LPCR bl __init_TLB mtlr r11