From patchwork Thu Nov 8 20:28:39 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Beno=C3=AEt_Th=C3=A9baudeau?= X-Patchwork-Id: 197882 X-Patchwork-Delegate: sbabic@denx.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id B33752C00BF for ; Fri, 9 Nov 2012 07:22:25 +1100 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 1E4394A8A3; Thu, 8 Nov 2012 21:22:24 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id YYnP1fcSN4-j; Thu, 8 Nov 2012 21:22:23 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id DAE5F4A8A4; Thu, 8 Nov 2012 21:22:21 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id E28D74A8A4 for ; Thu, 8 Nov 2012 21:22:20 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id gk803NfYolSm for ; Thu, 8 Nov 2012 21:22:20 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from zose-mta12.web4all.fr (zose-mta12.web4all.fr [178.33.204.89]) by theia.denx.de (Postfix) with ESMTP id 0E8EA4A8A3 for ; Thu, 8 Nov 2012 21:22:18 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by zose-mta12.web4all.fr (Postfix) with ESMTP id 74ED4908BA; Thu, 8 Nov 2012 21:25:37 +0100 (CET) X-Virus-Scanned: amavisd-new at zose1.web4all.fr Received: from zose-mta12.web4all.fr ([127.0.0.1]) by localhost (zose-mta12.web4all.fr [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 9uVY7Cy7yJFv; Thu, 8 Nov 2012 21:25:35 +0100 (CET) Received: from zose-store12.web4all.fr (zose-store12.web4all.fr [178.33.204.49]) by zose-mta12.web4all.fr (Postfix) with ESMTP id 30077904F0; Thu, 8 Nov 2012 21:25:35 +0100 (CET) Date: Thu, 8 Nov 2012 21:28:39 +0100 (CET) From: =?utf-8?Q?Beno=C3=AEt_Th=C3=A9baudeau?= To: U-Boot-Users ML Message-ID: <959120630.872111.1352406519905.JavaMail.root@advansee.com> In-Reply-To: <1221800138.872097.1352406463706.JavaMail.root@advansee.com> MIME-Version: 1.0 X-Originating-IP: [88.188.188.98] X-Mailer: Zimbra 7.2.0_GA_2669 (ZimbraWebClient - FF3.0 (Win)/7.2.0_GA_2669) Cc: Marek Vasut Subject: [U-Boot] [PATCH v2 03/13] ehci-mx5: Clean up X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de Clean up ehci-mx5: - Fix column alignments. - Fix comments. Signed-off-by: Benoît Thébaudeau Cc: Marek Vasut Cc: Stefano Babic --- Changes for v2: None. .../drivers/usb/host/ehci-mx5.c | 34 ++++++++++---------- 1 file changed, 17 insertions(+), 17 deletions(-) diff --git u-boot-usb-76454b2.orig/drivers/usb/host/ehci-mx5.c u-boot-usb-76454b2/drivers/usb/host/ehci-mx5.c index 9a2c295..66ab25d 100644 --- u-boot-usb-76454b2.orig/drivers/usb/host/ehci-mx5.c +++ u-boot-usb-76454b2/drivers/usb/host/ehci-mx5.c @@ -29,9 +29,9 @@ #define MX5_USBOTHER_REGS_OFFSET 0x800 -#define MXC_OTG_OFFSET 0 -#define MXC_H1_OFFSET 0x200 -#define MXC_H2_OFFSET 0x400 +#define MXC_OTG_OFFSET 0 +#define MXC_H1_OFFSET 0x200 +#define MXC_H2_OFFSET 0x400 #define MXC_USBCTRL_OFFSET 0 #define MXC_USB_PHY_CTR_FUNC_OFFSET 0x8 @@ -40,23 +40,23 @@ #define MXC_USBH2CTRL_OFFSET 0x14 /* USB_CTRL */ -#define MXC_OTG_UCTRL_OWIE_BIT (1 << 27) /* OTG wakeup intr enable */ -#define MXC_OTG_UCTRL_OPM_BIT (1 << 24) /* OTG power mask */ -#define MXC_H1_UCTRL_H1UIE_BIT (1 << 12) /* Host1 ULPI interrupt enable */ -#define MXC_H1_UCTRL_H1WIE_BIT (1 << 11) /* HOST1 wakeup intr enable */ -#define MXC_H1_UCTRL_H1PM_BIT (1 << 8) /* HOST1 power mask */ +#define MXC_OTG_UCTRL_OWIE_BIT (1 << 27) /* OTG wakeup intr enable */ +#define MXC_OTG_UCTRL_OPM_BIT (1 << 24) /* OTG power mask */ +#define MXC_H1_UCTRL_H1UIE_BIT (1 << 12) /* Host1 ULPI interrupt enable */ +#define MXC_H1_UCTRL_H1WIE_BIT (1 << 11) /* HOST1 wakeup intr enable */ +#define MXC_H1_UCTRL_H1PM_BIT (1 << 8) /* HOST1 power mask */ /* USB_PHY_CTRL_FUNC */ -#define MXC_OTG_PHYCTRL_OC_DIS_BIT (1 << 8) /* OTG Disable Overcurrent Event */ -#define MXC_H1_OC_DIS_BIT (1 << 5) /* UH1 Disable Overcurrent Event */ +#define MXC_OTG_PHYCTRL_OC_DIS_BIT (1 << 8) /* OTG Disable Overcurrent Event */ +#define MXC_H1_OC_DIS_BIT (1 << 5) /* UH1 Disable Overcurrent Event */ /* USBH2CTRL */ -#define MXC_H2_UCTRL_H2UIE_BIT (1 << 8) -#define MXC_H2_UCTRL_H2WIE_BIT (1 << 7) -#define MXC_H2_UCTRL_H2PM_BIT (1 << 4) +#define MXC_H2_UCTRL_H2UIE_BIT (1 << 8) +#define MXC_H2_UCTRL_H2WIE_BIT (1 << 7) +#define MXC_H2_UCTRL_H2PM_BIT (1 << 4) /* USB_CTRL_1 */ -#define MXC_USB_CTRL_UH1_EXT_CLK_EN (1 << 25) +#define MXC_USB_CTRL_UH1_EXT_CLK_EN (1 << 25) /* USB pin configuration */ #define USB_PAD_CONFIG (PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST | \ @@ -160,7 +160,7 @@ int mxc_set_usbcontrol(int port, unsigned int flags) __raw_writel(v, usbother_base + MXC_USBCTRL_OFFSET); } break; - case 1: /* Host 1 Host ULPI */ + case 1: /* Host 1 ULPI */ #ifdef CONFIG_MX51 /* The clock for the USBH1 ULPI port will come externally from the PHY. */ @@ -171,7 +171,7 @@ int mxc_set_usbcontrol(int port, unsigned int flags) v = __raw_readl(usbother_base + MXC_USBCTRL_OFFSET); if (flags & MXC_EHCI_POWER_PINS_ENABLED) - v &= ~MXC_H1_UCTRL_H1PM_BIT; /* HOST1 power mask used */ + v &= ~MXC_H1_UCTRL_H1PM_BIT; /* HOST1 power mask unused */ else v |= MXC_H1_UCTRL_H1PM_BIT; /* HOST1 power mask used */ __raw_writel(v, usbother_base + MXC_USBCTRL_OFFSET); @@ -187,7 +187,7 @@ int mxc_set_usbcontrol(int port, unsigned int flags) case 2: /* Host 2 ULPI */ v = __raw_readl(usbother_base + MXC_USBH2CTRL_OFFSET); if (flags & MXC_EHCI_POWER_PINS_ENABLED) - v &= ~MXC_H2_UCTRL_H2PM_BIT; /* HOST2 power mask used */ + v &= ~MXC_H2_UCTRL_H2PM_BIT; /* HOST2 power mask unused */ else v |= MXC_H2_UCTRL_H2PM_BIT; /* HOST2 power mask used */