| Submitter | Prabhakar Kushwaha |
|---|---|
| Date | Nov. 8, 2012, 7:52 a.m. |
| Message ID | <1352361147-21959-1-git-send-email-prabhakar@freescale.com> |
| Download | mbox | patch |
| Permalink | /patch/197791/ |
| State | Accepted |
| Delegated to: | Scott Wood |
| Headers | show |
Comments
On Wed, Nov 07, 2012 at 09:52:27PM -0000, Prabhakar Kushwaha wrote: > IFC_FIR_OP_CMD0 issues command for execution without checking flash > readiness. It may cause problem if flash is not ready. Instead use > IFC_FIR_OP_CW0 which Wait for tWB time and poll R/B to return high or > time-out, before issuing command. > > NAND_CMD_READID command implemention does not fulfill above requirement. So > update its programming. > > Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> > Signed-off-by: Hemant Nautiyal <hemant.nautiyal@freescale.com> > > --- > Please note this patch depends upon following patch: > "driver/mtd:IFC NAND:Initialise internal SRAM before any write" > http://patchwork.ozlabs.org/patch/183550/ > > > drivers/mtd/nand/fsl_ifc_nand.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) Applied to u-boot-nand-flash -- I missed it earlier. Next time please make sure "nand" is in the subject line. Ideally prefix it as "nand/fsl_ifc: wait tWB time..." rather than "driver/mtd/IFC:Wait tWB time...". -Scott
Patch
diff --git a/drivers/mtd/nand/fsl_ifc_nand.c b/drivers/mtd/nand/fsl_ifc_nand.c index 6619ecf..8c119e0 100644 --- a/drivers/mtd/nand/fsl_ifc_nand.c +++ b/drivers/mtd/nand/fsl_ifc_nand.c @@ -391,7 +391,7 @@ static void fsl_ifc_cmdfunc(struct mtd_info *mtd, unsigned int command, timing = IFC_FIR_OP_RBCD; out_be32(&ifc->ifc_nand.nand_fir0, - (IFC_FIR_OP_CMD0 << IFC_NAND_FIR0_OP0_SHIFT) | + (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) | (IFC_FIR_OP_UA << IFC_NAND_FIR0_OP1_SHIFT) | (timing << IFC_NAND_FIR0_OP2_SHIFT)); out_be32(&ifc->ifc_nand.nand_fcr0, @@ -758,7 +758,7 @@ static void fsl_ifc_sram_init(void) /* READID */ out_be32(&ifc->ifc_nand.nand_fir0, - (IFC_FIR_OP_CMD0 << IFC_NAND_FIR0_OP0_SHIFT) | + (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) | (IFC_FIR_OP_UA << IFC_NAND_FIR0_OP1_SHIFT) | (IFC_FIR_OP_RB << IFC_NAND_FIR0_OP2_SHIFT)); out_be32(&ifc->ifc_nand.nand_fcr0,