| Message ID | 509A2C42.5060401@linux.vnet.ibm.com |
|---|---|
| State | New |
| Headers | show |
On Wed, 7 Nov 2012, Andreas Krebbel wrote: > Sure. What about something like this? > > Index: htdocs/index.html > =================================================================== > RCS file: /cvs/gcc/wwwdocs/htdocs/index.html,v > retrieving revision 1.865 > diff -u -r1.865 index.html > --- htdocs/index.html 6 Nov 2012 12:17:13 -0000 1.865 > +++ htdocs/index.html 7 Nov 2012 09:36:17 -0000 > @@ -53,6 +53,12 @@ > > <dl class="news"> > > +<dt><span>IBM zEnterprise EC12 support</span> > + <span class="date">[2012-10-10]</span></dt> > +<dd>Support for the latest release of the System z mainframe > +<a href="http://www.ibm.com/systems/z/hardware/zenterprise/zec12.html">zEC12</a> > +has been added to the architecture back-end.</dd> Note that RMS has asked us to not add links to products/companies that are not (doing) exclusively free software. This is why you generally won't find links to corporate home pages in this section. (Where it goes for technical references such as readings.html, I believe we can/should be pragmatic.) Also, don't you want to add acknowledgements who did the work and which company contributed it? (Slightly obvious as far as the latter goes, I think, but... ;-) > Index: htdocs/gcc-4.8/changes.html > =================================================================== > + <li>Register pressure sensitive insn scheduling is enabled by > + default.</li> I'd use "instruction scheduling". > + <li>The IFUNC function attribute is enabled by default.</li> <code>IFUNC</code> > + <li>memcpy and memcmp invokations on big memory chunks or with <code>memcpy</code> and <code>memcmp</code> > + runtime lengths are not generated inline anymore when tuning for > + z10 or higher. The purpose is to make use of the IFUNC > + optimized versions in Glibc.</li> Note http://gcc.gnu.org/codingconventions.html as far as the use of "runtime" goes. This is fine with these minor adjustments; thanks! Gerald
Index: htdocs/index.html =================================================================== RCS file: /cvs/gcc/wwwdocs/htdocs/index.html,v retrieving revision 1.865 diff -u -r1.865 index.html --- htdocs/index.html 6 Nov 2012 12:17:13 -0000 1.865 +++ htdocs/index.html 7 Nov 2012 09:36:17 -0000 @@ -53,6 +53,12 @@ <dl class="news"> +<dt><span>IBM zEnterprise EC12 support</span> + <span class="date">[2012-10-10]</span></dt> +<dd>Support for the latest release of the System z mainframe +<a href="http://www.ibm.com/systems/z/hardware/zenterprise/zec12.html">zEC12</a> +has been added to the architecture back-end.</dd> + <dt><span><a href="gcc-4.7/">GCC 4.7.2</a> released</span> <span class="date">[2012-09-20]</span></dt> <dd></dd> Index: htdocs/gcc-4.8/changes.html =================================================================== RCS file: /cvs/gcc/wwwdocs/htdocs/gcc-4.8/changes.html,v retrieving revision 1.53 diff -u -r1.53 changes.html --- htdocs/gcc-4.8/changes.html 4 Nov 2012 15:22:03 -0000 1.53 +++ htdocs/gcc-4.8/changes.html 7 Nov 2012 09:36:17 -0000 @@ -325,6 +325,29 @@ command-line option.</li> </ul> +<h3>S/390, System z</h3> + <ul> + <li>Support for the IBM zEnterprise zEC12 processor has been + added. When using the <code>-march=zEC12</code> option, the + compiler will generate code making use of the following new + instructions: + <ul> + <li>load and trap instructions</li> + <li>2 new compare and trap instructions</li> + <li>rotate and insert selected bits - without CC clobber</li> + </ul> + The <code>-mtune=zEC12</code> option enables zEC12 specific + instruction scheduling without making use of new + instructions.</li> + <li>Register pressure sensitive insn scheduling is enabled by + default.</li> + <li>The IFUNC function attribute is enabled by default.</li> + <li>memcpy and memcmp invokations on big memory chunks or with + runtime lengths are not generated inline anymore when tuning for + z10 or higher. The purpose is to make use of the IFUNC + optimized versions in Glibc.</li> + </ul> + <h3 id="sh">SH</h3> <ul> <li>The default alignment settings have been reduced to be less aggressive.