From patchwork Mon Nov 5 07:29:45 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aurelien Jarno X-Patchwork-Id: 197153 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id C429B2C00D0 for ; Mon, 5 Nov 2012 18:33:34 +1100 (EST) Received: from localhost ([::1]:42002 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TVH8r-0006Wg-Ns for incoming@patchwork.ozlabs.org; Mon, 05 Nov 2012 02:30:41 -0500 Received: from eggs.gnu.org ([208.118.235.92]:35913) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TVH8D-0005EF-I1 for qemu-devel@nongnu.org; Mon, 05 Nov 2012 02:30:05 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1TVH8C-0005AU-Gb for qemu-devel@nongnu.org; Mon, 05 Nov 2012 02:30:01 -0500 Received: from hall.aurel32.net ([2001:470:1f15:c4f::1]:49878) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TVH8C-0005AJ-9f for qemu-devel@nongnu.org; Mon, 05 Nov 2012 02:30:00 -0500 Received: from 37-8-191-163.coucou-networks.fr ([37.8.191.163] helo=ohm.aurel32.net) by hall.aurel32.net with esmtpsa (TLS1.0:DHE_RSA_AES_128_CBC_SHA1:16) (Exim 4.72) (envelope-from ) id 1TVH8B-0003C9-3v; Mon, 05 Nov 2012 08:29:59 +0100 Received: from aurel32 by ohm.aurel32.net with local (Exim 4.80) (envelope-from ) id 1TVH80-00055L-9z; Mon, 05 Nov 2012 08:29:48 +0100 From: Aurelien Jarno To: qemu-devel@nongnu.org Date: Mon, 5 Nov 2012 08:29:45 +0100 Message-Id: <1352100585-19415-4-git-send-email-aurelien@aurel32.net> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1352100585-19415-1-git-send-email-aurelien@aurel32.net> References: <1352100585-19415-1-git-send-email-aurelien@aurel32.net> X-detected-operating-system: by eggs.gnu.org: Error: Malformed IPv6 address (bad octet value). X-Received-From: 2001:470:1f15:c4f::1 Cc: Jia Liu , Aurelien Jarno , qemu-stable@nongnu.org Subject: [Qemu-devel] [PATCH v3 for 1.3 3/3] target-openrisc: remove conflicting definitions from cpu.h X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org On an ARM host, the registers definitions from cpu.h clash with /usr/include/sys/ucontext.h. As there are unused, just remove them. Cc: Jia Liu Cc: qemu-stable@nongnu.org Reviewed-by: Peter Maydell Signed-off-by: Aurelien Jarno --- target-openrisc/cpu.h | 18 ------------------ 1 file changed, 18 deletions(-) diff --git a/target-openrisc/cpu.h b/target-openrisc/cpu.h index d42ffb0..ebb5ad3 100644 --- a/target-openrisc/cpu.h +++ b/target-openrisc/cpu.h @@ -89,24 +89,6 @@ enum { /* Interrupt */ #define NR_IRQS 32 -/* Registers */ -enum { - R0 = 0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, - R11, R12, R13, R14, R15, R16, R17, R18, R19, R20, - R21, R22, R23, R24, R25, R26, R27, R28, R29, R30, - R31 -}; - -/* Register aliases */ -enum { - R_ZERO = R0, - R_SP = R1, - R_FP = R2, - R_LR = R9, - R_RV = R11, - R_RVH = R12 -}; - /* Unit presece register */ enum { UPR_UP = (1 << 0),