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[U-Boot,17/20] x86: drop unused code in coreboot.c

Message ID 1351978902-23719-18-git-send-email-sjg@chromium.org
State Accepted, archived
Delegated to: Simon Glass
Headers show

Commit Message

Simon Glass Nov. 3, 2012, 9:41 p.m. UTC 
From: Stefan Reinauer <reinauer@chromium.org>

The function setup_pcat_compatibility() is weak and implemented as empty
function in board.c hence we don't have to override that with another
empty function.

monitor_flash_len is unused, drop it.

Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
---
 arch/x86/cpu/coreboot/coreboot.c |    7 -------
 1 files changed, 0 insertions(+), 7 deletions(-)
diff mbox

Patch

diff --git a/arch/x86/cpu/coreboot/coreboot.c b/arch/x86/cpu/coreboot/coreboot.c
index da722e9..a3a1a4e 100644
--- a/arch/x86/cpu/coreboot/coreboot.c
+++ b/arch/x86/cpu/coreboot/coreboot.c
@@ -35,8 +35,6 @@ 
 
 DECLARE_GLOBAL_DATA_PTR;
 
-unsigned long monitor_flash_len = CONFIG_SYS_MONITOR_LEN;
-
 /*
  * Miscellaneous platform dependent initializations
  */
@@ -93,7 +91,6 @@  void show_boot_progress(int val)
 	outb(val, 0x80);
 }
 
-
 int last_stage_init(void)
 {
 	return 0;
@@ -111,10 +108,6 @@  int board_eth_init(bd_t *bis)
 	return pci_eth_init(bis);
 }
 
-void setup_pcat_compatibility()
-{
-}
-
 #define MTRR_TYPE_WP          5
 #define MTRRcap_MSR           0xfe
 #define MTRRphysBase_MSR(reg) (0x200 + 2 * (reg))