From patchwork Sat Nov 3 21:41:34 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 196948 X-Patchwork-Delegate: sjg@chromium.org Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 28D5A2C00C2 for ; Sun, 4 Nov 2012 08:45:02 +1100 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 95AAC4A197; Sat, 3 Nov 2012 22:43:58 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id xp33sUgQeJtA; Sat, 3 Nov 2012 22:43:58 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id A3BEA4A199; Sat, 3 Nov 2012 22:42:31 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id B09EC4A179 for ; Sat, 3 Nov 2012 22:42:20 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 8C+b2Y8JLB0w for ; Sat, 3 Nov 2012 22:42:18 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail-gg0-f202.google.com (mail-gg0-f202.google.com [209.85.161.202]) by theia.denx.de (Postfix) with ESMTPS id 594B84A15A for ; Sat, 3 Nov 2012 22:42:05 +0100 (CET) Received: by mail-gg0-f202.google.com with SMTP id i4so544050ggm.3 for ; Sat, 03 Nov 2012 14:42:03 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references :x-gm-message-state; bh=Y0JiZcKbNZNJeoXgzapciAc37TkmbQSBP3pzvI43FMY=; b=jbtGiUOwlC+Gs59bsOFE0sYrYX71o1g9m3+TwnbVNJuTBBRVITHCb7LDfa0hrkzcrI zn0gVYNkyWnmvRS6sbs7mzFDPua+3OO3yAFYtIov0ZnpkmK7no0Wbc9loMzm1xUvGn6U XLCMXi8e+EsndRH+nKo0xlNG5yIzmm+sc3o3b84eAFR2QE0BM1Vmv6RnuRm13nIpbN9M GLifj2D6QLKRpXsawgVHHRQ70C2CtLTx6rl1LfQNzex4gGzmXhSHLcKd2/tMTd9bL8Nt S7WyiTwjURyLIuebLrhy4ecMlVuE69/DOPgg3+slm6U2lVisrubNDTNR69WISxA9q4WY 9Akw== Received: by 10.101.139.18 with SMTP id r18mr931852ann.26.1351978923789; Sat, 03 Nov 2012 14:42:03 -0700 (PDT) Received: from wpzn3.hot.corp.google.com (216-239-44-65.google.com [216.239.44.65]) by gmr-mx.google.com with ESMTPS id u20si222654anj.3.2012.11.03.14.42.03 (version=TLSv1/SSLv3 cipher=AES128-SHA); Sat, 03 Nov 2012 14:42:03 -0700 (PDT) Received: from kaka.mtv.corp.google.com (kaka.mtv.corp.google.com [172.22.73.79]) by wpzn3.hot.corp.google.com (Postfix) with ESMTP id 7F1F7100062; Sat, 3 Nov 2012 14:42:03 -0700 (PDT) Received: by kaka.mtv.corp.google.com (Postfix, from userid 121222) id 33E3C16192C; Sat, 3 Nov 2012 14:42:03 -0700 (PDT) From: Simon Glass To: U-Boot Mailing List Date: Sat, 3 Nov 2012 14:41:34 -0700 Message-Id: <1351978902-23719-13-git-send-email-sjg@chromium.org> X-Mailer: git-send-email 1.7.7.3 In-Reply-To: <1351978902-23719-1-git-send-email-sjg@chromium.org> References: <1351978902-23719-1-git-send-email-sjg@chromium.org> X-Gm-Message-State: ALoCoQkU6KeWh2mqUHvIKFHhmFYlVx6BERf7UmrQOmrMKigmJ8S+tBhAu9j5bX6Ob9D5vujk41hDW5FlgdKW82Ur8JhfbwBVmktMYmbMgcvqqNTExd5XuptmYKDd9z+4xJmE2T2CZfZvhkkvI+qpEVEquJvi5SpIHEzjbNImHBs8nLqCzswcLD3rUQxLYRITUzkZh1yrSwyC Cc: Duncan Laurie Subject: [U-Boot] [PATCH 12/20] x86: Fix MTRR clear to detect which MTRR to use X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de From: Duncan Laurie Coreboot was always using MTRR 7 for the write-protect cache entry that covers the ROM and U-boot was removing it. However with 4GB configs we need more MTRRs for the BIOS and so the WP MTRR needs to move. Instead coreboot will always use the last available MTRR that is normally set aside for OS use and U-boot can clear it before the OS. Signed-off-by: Duncan Laurie Signed-off-by: Simon Glass --- arch/x86/cpu/coreboot/coreboot.c | 19 +++++++++++++++---- 1 files changed, 15 insertions(+), 4 deletions(-) diff --git a/arch/x86/cpu/coreboot/coreboot.c b/arch/x86/cpu/coreboot/coreboot.c index 2912443..ff42661 100644 --- a/arch/x86/cpu/coreboot/coreboot.c +++ b/arch/x86/cpu/coreboot/coreboot.c @@ -94,6 +94,8 @@ void setup_pcat_compatibility() { } +#define MTRR_TYPE_WP 5 +#define MTRRcap_MSR 0xfe #define MTRRphysBase_MSR(reg) (0x200 + 2 * (reg)) #define MTRRphysMask_MSR(reg) (0x200 + 2 * (reg) + 1) @@ -101,11 +103,20 @@ int board_final_cleanup(void) { /* Un-cache the ROM so the kernel has one * more MTRR available. + * + * Coreboot should have assigned this to the + * top available variable MTRR. */ - disable_cache(); - wrmsr(MTRRphysBase_MSR(7), 0); - wrmsr(MTRRphysMask_MSR(7), 0); - enable_cache(); + u8 top_mtrr = (rdmsr(MTRRcap_MSR) & 0xff) - 1; + u8 top_type = rdmsr(MTRRphysBase_MSR(top_mtrr)) & 0xff; + + /* Make sure this MTRR is the correct Write-Protected type */ + if (top_type == MTRR_TYPE_WP) { + disable_cache(); + wrmsr(MTRRphysBase_MSR(top_mtrr), 0); + wrmsr(MTRRphysMask_MSR(top_mtrr), 0); + enable_cache(); + } return 0; }