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[U-Boot,12/20] x86: Fix MTRR clear to detect which MTRR to use

Message ID 1351978902-23719-13-git-send-email-sjg@chromium.org
State Superseded, archived
Delegated to: Simon Glass
Headers show

Commit Message

Simon Glass Nov. 3, 2012, 9:41 p.m. UTC 
From: Duncan Laurie <dlaurie@chromium.org>

Coreboot was always using MTRR 7 for the write-protect
cache entry that covers the ROM and U-boot was removing it.
However with 4GB configs we need more MTRRs for the BIOS
and so the WP MTRR needs to move.  Instead coreboot will
always use the last available MTRR that is normally set
aside for OS use and U-boot can clear it before the OS.

Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
---
 arch/x86/cpu/coreboot/coreboot.c |   19 +++++++++++++++----
 1 files changed, 15 insertions(+), 4 deletions(-)
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Patch

diff --git a/arch/x86/cpu/coreboot/coreboot.c b/arch/x86/cpu/coreboot/coreboot.c
index 2912443..ff42661 100644
--- a/arch/x86/cpu/coreboot/coreboot.c
+++ b/arch/x86/cpu/coreboot/coreboot.c
@@ -94,6 +94,8 @@  void setup_pcat_compatibility()
 {
 }
 
+#define MTRR_TYPE_WP          5
+#define MTRRcap_MSR           0xfe
 #define MTRRphysBase_MSR(reg) (0x200 + 2 * (reg))
 #define MTRRphysMask_MSR(reg) (0x200 + 2 * (reg) + 1)
 
@@ -101,11 +103,20 @@  int board_final_cleanup(void)
 {
 	/* Un-cache the ROM so the kernel has one
 	 * more MTRR available.
+	 *
+	 * Coreboot should have assigned this to the
+	 * top available variable MTRR.
 	 */
-	disable_cache();
-	wrmsr(MTRRphysBase_MSR(7), 0);
-	wrmsr(MTRRphysMask_MSR(7), 0);
-	enable_cache();
+	u8 top_mtrr = (rdmsr(MTRRcap_MSR) & 0xff) - 1;
+	u8 top_type = rdmsr(MTRRphysBase_MSR(top_mtrr)) & 0xff;
+
+	/* Make sure this MTRR is the correct Write-Protected type */
+	if (top_type == MTRR_TYPE_WP) {
+		disable_cache();
+		wrmsr(MTRRphysBase_MSR(top_mtrr), 0);
+		wrmsr(MTRRphysMask_MSR(top_mtrr), 0);
+		enable_cache();
+	}
 
 	return 0;
 }