Patchwork [U-Boot,SPEAr13xx,6/7] spear1340evb: Add SPL support

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Submitter Vipin Kumar
Date Nov. 2, 2012, 5:39 p.m.
Message ID <d256cd1487959f40e5c6e2447f86fbda36f5cbc5.1351877394.git.vipin.kumar@st.com>
Download mbox | patch
Permalink /patch/196752/
State New
Delegated to: Vipin Kumar
Headers show

Comments

Vipin Kumar - Nov. 2, 2012, 5:39 p.m.
This patch adds SPL support for spear1340-evb. The major piece of code is
addition of
  * system initialization code
  * ddr driver code

This patch also factors the code for spear13xx and board support etc. In other
words, it also paves way for other spear13xx architecture based SoCs and other
boards based on spear1340

The source of the original code is git@git.bri.st.com:/spear/xloader.git

Another change is the way xloader runs, xloader now returns to BootROM for all
cases. The return value determines how the next level bootloader will be booted.

Signed-off-by: Vipin Kumar <vipin.kumar@st.com>
---
 arch/arm/cpu/armv7/Makefile                        |   6 +
 arch/arm/cpu/armv7/spear13xx/Makefile              |  26 +-
 arch/arm/cpu/armv7/spear13xx/spear13xx.c           |  30 +
 arch/arm/cpu/armv7/spear13xx/spl-boot.c            |  76 +++
 arch/arm/cpu/armv7/spear13xx/spl-lvl_gatetrn.c     | 239 ++++++++
 arch/arm/cpu/armv7/spear13xx/spl-lvl_read.c        | 229 ++++++++
 arch/arm/cpu/armv7/spear13xx/spl-lvl_write.c       | 608 +++++++++++++++++++++
 arch/arm/cpu/armv7/spear13xx/spl-spear1340.c       | 210 +++++++
 arch/arm/cpu/armv7/spear13xx/spl-spear13xx.c       | 162 ++++++
 arch/arm/cpu/armv7/spear13xx/spl-swlvl.c           |  93 ++++
 arch/arm/cpu/armv7/spear13xx/start.S               | 137 +++++
 arch/arm/cpu/armv7/spear13xx/u-boot-spl.lds        |  45 ++
 arch/arm/cpu/armv7/spear13xx/wakeup.S              |  60 ++
 arch/arm/include/asm/arch-spear13xx/boot.h         | 106 ++++
 arch/arm/include/asm/arch-spear13xx/generic.h      |   8 +
 arch/arm/include/asm/arch-spear13xx/mpmc.h         | 332 +++++++++++
 .../include/asm/arch-spear13xx/spear1340_misc.h    |  76 ++-
 arch/arm/include/asm/arch-spear13xx/spear13xx.h    |   4 +
 board/st/spear13xx/Makefile                        |   5 +
 board/st/spear13xx/config.mk                       |   4 +
 board/st/spear13xx/ddr/Makefile                    |  64 +++
 board/st/spear13xx/ddr/h5tq2g63bfr_pbc_400_cl6.c   | 238 ++++++++
 board/st/spear13xx/ddr/h5tq2g63bfr_pbc_533_cl8.c   | 238 ++++++++
 board/st/spear13xx/ddr/k4b2g1646c_k0_400_cl6.c     | 238 ++++++++
 board/st/spear13xx/ddr/k4b2g1646c_k0_533_cl8.c     | 238 ++++++++
 .../ddr/mt41j128m16_15e_400_cl6_dqs_dq_term_en.c   | 238 ++++++++
 .../ddr/mt41j256m8187e_400_cl6_dqs_dq_term_en.c    | 246 +++++++++
 .../ddr/mt41j256m8187e_533_cl7_dqs_dq_term_en.c    | 246 +++++++++
 .../ddr/mt41j64m16_15e_400_cl6_dqs_dq_term_en.c    | 238 ++++++++
 .../ddr/mt41j64m16_15e_533_cl7_dqs_dq_term_en.c    | 238 ++++++++
 .../spear13xx/ddr/mt47h128m16rt187e_400_cl6_ddr2.c | 239 ++++++++
 .../spear13xx/ddr/mt47h128m16rt187e_533_cl7_ddr2.c | 239 ++++++++
 board/st/spear13xx/spl-spear1340evb.c              |  57 ++
 include/configs/spear1340-evb.h                    |   5 +
 include/configs/spear13xx.h                        |  51 +-
 spl/Makefile                                       |   6 +
 36 files changed, 5245 insertions(+), 30 deletions(-)
 create mode 100644 arch/arm/cpu/armv7/spear13xx/spl-boot.c
 create mode 100644 arch/arm/cpu/armv7/spear13xx/spl-lvl_gatetrn.c
 create mode 100644 arch/arm/cpu/armv7/spear13xx/spl-lvl_read.c
 create mode 100644 arch/arm/cpu/armv7/spear13xx/spl-lvl_write.c
 create mode 100644 arch/arm/cpu/armv7/spear13xx/spl-spear1340.c
 create mode 100644 arch/arm/cpu/armv7/spear13xx/spl-spear13xx.c
 create mode 100644 arch/arm/cpu/armv7/spear13xx/spl-swlvl.c
 create mode 100644 arch/arm/cpu/armv7/spear13xx/start.S
 create mode 100644 arch/arm/cpu/armv7/spear13xx/u-boot-spl.lds
 create mode 100644 arch/arm/cpu/armv7/spear13xx/wakeup.S
 create mode 100644 arch/arm/include/asm/arch-spear13xx/boot.h
 create mode 100644 arch/arm/include/asm/arch-spear13xx/mpmc.h
 create mode 100644 board/st/spear13xx/ddr/Makefile
 create mode 100644 board/st/spear13xx/ddr/h5tq2g63bfr_pbc_400_cl6.c
 create mode 100644 board/st/spear13xx/ddr/h5tq2g63bfr_pbc_533_cl8.c
 create mode 100644 board/st/spear13xx/ddr/k4b2g1646c_k0_400_cl6.c
 create mode 100644 board/st/spear13xx/ddr/k4b2g1646c_k0_533_cl8.c
 create mode 100644 board/st/spear13xx/ddr/mt41j128m16_15e_400_cl6_dqs_dq_term_en.c
 create mode 100644 board/st/spear13xx/ddr/mt41j256m8187e_400_cl6_dqs_dq_term_en.c
 create mode 100644 board/st/spear13xx/ddr/mt41j256m8187e_533_cl7_dqs_dq_term_en.c
 create mode 100644 board/st/spear13xx/ddr/mt41j64m16_15e_400_cl6_dqs_dq_term_en.c
 create mode 100644 board/st/spear13xx/ddr/mt41j64m16_15e_533_cl7_dqs_dq_term_en.c
 create mode 100644 board/st/spear13xx/ddr/mt47h128m16rt187e_400_cl6_ddr2.c
 create mode 100644 board/st/spear13xx/ddr/mt47h128m16rt187e_533_cl7_ddr2.c
 create mode 100644 board/st/spear13xx/spl-spear1340evb.c

Patch

diff --git a/arch/arm/cpu/armv7/Makefile b/arch/arm/cpu/armv7/Makefile
index 3ef01f6..6d670ca 100644
--- a/arch/arm/cpu/armv7/Makefile
+++ b/arch/arm/cpu/armv7/Makefile
@@ -37,6 +37,12 @@  ifneq ($(CONFIG_AM33XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TEGRA20),)
 SOBJS-y	+= lowlevel_init.o
 endif
 
+ifdef	CONFIG_SPL_BUILD
+ifdef	CONFIG_SPL_NO_CPU_SUPPORT_CODE
+START	:=
+endif
+endif
+
 COBJS	:= $(sort $(COBJS-y))
 SOBJS	:= $(sort $(SOBJS-y))
 SRCS	:= $(START:.o=.S) $(COBJS:.o=.c)
diff --git a/arch/arm/cpu/armv7/spear13xx/Makefile b/arch/arm/cpu/armv7/spear13xx/Makefile
index cacf268..daeffa2 100644
--- a/arch/arm/cpu/armv7/spear13xx/Makefile
+++ b/arch/arm/cpu/armv7/spear13xx/Makefile
@@ -28,19 +28,37 @@  include $(TOPDIR)/config.mk
 
 LIB	= $(obj)lib$(SOC).o
 
+SOBJS-y	:=
+COBJS-y	:=
+
 COBJS-$(CONFIG_ARCH_SPEAR13XX) += spear13xx.o
 COBJS-$(CONFIG_SOC_SPEAR1310) += spear1310.o
 COBJS-$(CONFIG_SOC_SPEAR1310) += spear1310-pinmux.o
 COBJS-$(CONFIG_SOC_SPEAR1340) += spear1340.o
 COBJS-$(CONFIG_SOC_SPEAR1340) += spear1340-pinmux.o
 
-SRCS	:= $(COBJS-y:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS-y))
+ifdef CONFIG_SPL_BUILD
+SOBJS-y	+= wakeup.o
+
+COBJS-y	+= spl-boot.o
+COBJS-$(CONFIG_ARCH_SPEAR13XX) += spl-spear13xx.o
+COBJS-$(CONFIG_ARCH_SPEAR13XX) += spl-lvl_gatetrn.o
+COBJS-$(CONFIG_ARCH_SPEAR13XX) += spl-lvl_read.o
+COBJS-$(CONFIG_ARCH_SPEAR13XX) += spl-lvl_write.o
+COBJS-$(CONFIG_ARCH_SPEAR13XX) += spl-swlvl.o
+COBJS-$(CONFIG_SOC_SPEAR1340) += spl-spear1340.o
+endif
+
+COBJS	:= $(sort $(COBJS-y))
+SOBJS	:= $(sort $(SOBJS-y))
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
 
 all:	$(obj).depend $(LIB)
 
-$(LIB):	$(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
+$(LIB):	$(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
 
 #########################################################################
 
diff --git a/arch/arm/cpu/armv7/spear13xx/spear13xx.c b/arch/arm/cpu/armv7/spear13xx/spear13xx.c
index 351e8cd..13e5422 100644
--- a/arch/arm/cpu/armv7/spear13xx/spear13xx.c
+++ b/arch/arm/cpu/armv7/spear13xx/spear13xx.c
@@ -30,3 +30,33 @@  void enable_caches(void)
 	dcache_enable();
 #endif
 }
+
+#ifdef CONFIG_POST
+int arch_memory_test_prepare(u32 *vstart, u32 *size, phys_addr_t *phys_offset)
+{
+	/*
+	 * Run the POST test on 64 MB memory starting from CONFIG_SYS_LOAD_ADDR
+	 * The assumption here is that the DDR present on board is >= 128MB.
+	 *
+	 * The test runs before relocation (after the code copy has taken
+	 * place), so it can not touch either before or after relocation areas
+	 * of U-boot
+	 *
+	 * DDR usage
+	 * <--------->|<---------------- / --------------->|<---------->
+	 *   U-boot		Area to be used for		U-boot
+	 *   before		POST test			after
+	 *   relocation						relocation
+	 */
+
+	*vstart = CONFIG_SYS_LOAD_ADDR;
+	*size = 64 << 20;
+
+	return 0;
+}
+
+void arch_memory_failure_handle(void)
+{
+	hang();
+}
+#endif
diff --git a/arch/arm/cpu/armv7/spear13xx/spl-boot.c b/arch/arm/cpu/armv7/spear13xx/spl-boot.c
new file mode 100644
index 0000000..fb903ed
--- /dev/null
+++ b/arch/arm/cpu/armv7/spear13xx/spl-boot.c
@@ -0,0 +1,76 @@ 
+/*
+ * (C) Copyright 2012
+ * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/boot.h>
+#include <linux/mtd/st_smi.h>
+
+ulong spl_boot(void)
+{
+	ulong ret;
+
+#if defined(CONFIG_SPEAR_USBTTY)
+	return 0;
+#endif
+
+	switch (get_boot_type()) {
+	case BOOT_TYPE_BYPASS:
+	case BOOT_TYPE_SMI:
+		/* SNOR-SMI initialization */
+		smi_init();
+		ret = (ulong)CONFIG_SYS_SNOR_BOOT_BASE;
+		break;
+
+	case BOOT_TYPE_NAND:
+		ret = (ulong)CONFIG_SYS_NAND_BOOT_BASE;
+		break;
+
+	case BOOT_TYPE_PNOR8:
+	case BOOT_TYPE_PNOR16:
+	case BOOT_TYPE_PNOR32:
+		ret = (ulong)CONFIG_SYS_PNOR_BOOT_BASE;
+		break;
+
+	case BOOT_TYPE_USBD:
+	case BOOT_TYPE_TFTP:
+	case BOOT_TYPE_PCIE:
+	case BOOT_TYPE_UART:
+		ret = 0;
+		break;
+
+	case BOOT_TYPE_MMC:
+		ret = (ulong)CONFIG_SYS_MMC_BOOT_FILE;
+		break;
+
+	case BOOT_TYPE_I2C:
+	case BOOT_TYPE_SPI:
+	case BOOT_TYPE_RESERVED:
+	case BOOT_TYPE_UNSUPPORTED:
+	default:
+		ret = (ulong)-1;
+		break;
+	}
+
+	return ret;
+}
diff --git a/arch/arm/cpu/armv7/spear13xx/spl-lvl_gatetrn.c b/arch/arm/cpu/armv7/spear13xx/spl-lvl_gatetrn.c
new file mode 100644
index 0000000..2b9df8f
--- /dev/null
+++ b/arch/arm/cpu/armv7/spear13xx/spl-lvl_gatetrn.c
@@ -0,0 +1,239 @@ 
+/*
+ * (C) Copyright 2012
+ * Vipin Kumar, ST Microelectronics, vipin.kumar@st.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/mpmc.h>
+
+#define MIN_1_8TH_CYCLE_PREAMBLE	6
+#define MIN_NO_OF_1_8TH_CYCLE		2
+#define MAX_NO_OF_1_8TH_CYCLE		6
+static struct mpmc_regs *mpmc_p = (struct mpmc_regs *)CONFIG_SYS_MPMC_BASE;
+
+static void prog_rdlvl_gate_delay(u32 slice, u32 delay)
+{
+	u32 *rdlvl_gate_delay_reg = &mpmc_p->reg86;
+	u32 shift = (slice % 2) ? 0 : 16;
+
+	rdlvl_gate_delay_reg += (slice + 1) >> 1;
+	writel_field(delay << shift, 0xFFFF << shift, rdlvl_gate_delay_reg);
+}
+
+#if defined(CONFIG_DDR2)
+void ddr2_lvl_gatetrn(void)
+{
+	u32 *phy_ctrl_reg0 = &mpmc_p->reg124;
+	u32 *phy_ctrl_reg6 = &mpmc_p->reg155;
+	u32 final_gate_counter[DATA_SLICE_MAX];
+	u32 slice;
+
+	u32 phy_ctrl_reg6_dqs_assertval[] = {
+		(0x0 << 0) | (0x0 << 20),
+		(0x0 << 0) | (0x0 << 20),
+		(0x8 << 0) | (0x8 << 20),
+		(0x9 << 0) | (0x9 << 20),
+		(0xa << 0) | (0xa << 20),
+		(0xb << 0) | (0xb << 20)
+	};
+	u32 phy_ctrl_reg6_dqs_deassertval[] = {
+		(0x00 << 5) | (0x00 << 25),
+		(0x10 << 5) | (0x10 << 25),
+		(0x11 << 5) | (0x11 << 25),
+		(0x12 << 5) | (0x12 << 25),
+		(0x13 << 5) | (0x13 << 25),
+		(0x14 << 5) | (0x14 << 25)
+	};
+
+	int RDLVL_GATE_DELAY_VALUE[5] = {32, 32, 32, 32, 32};
+
+	RDLVL_GATE_DELAY_VALUE[0] = RDLVL_GATE_DELAY_VALUE_0;
+	RDLVL_GATE_DELAY_VALUE[1] = RDLVL_GATE_DELAY_VALUE_1;
+	RDLVL_GATE_DELAY_VALUE[2] = RDLVL_GATE_DELAY_VALUE_2;
+	RDLVL_GATE_DELAY_VALUE[3] = RDLVL_GATE_DELAY_VALUE_3;
+	RDLVL_GATE_DELAY_VALUE[4] = RDLVL_GATE_DELAY_VALUE_4;
+
+	for (slice = 0; slice < DATA_SLICE_MAX; slice++) {
+		final_gate_counter[slice] = RDLVL_GATE_DELAY_VALUE[slice];
+		writel_field((final_gate_counter[slice] / 8) << 20, 7 << 20,
+				phy_ctrl_reg0 + slice);
+		prog_rdlvl_gate_delay(slice, final_gate_counter[slice] % 8);
+	}
+
+	for (slice = 0; slice < DATA_SLICE_MAX; slice++) {
+		writel_field(phy_ctrl_reg6_dqs_assertval[final_gate_counter[slice] / 8],
+				(0x1F << 0) | (0x1F << 20), phy_ctrl_reg6 + slice);
+		writel_field(phy_ctrl_reg6_dqs_deassertval[final_gate_counter[slice] / 8],
+				(0x1F << 5) | (0x1F << 25), phy_ctrl_reg6 + slice);
+	}
+}
+#elif defined(CONFIG_DDR3)
+static void set_gate_parms(u32 gate_cnt, u32 slice)
+{
+	u32 *phy_ctrl_reg0 = &mpmc_p->reg124;
+
+	writel_field((gate_cnt / 8) << 20, 7 << 20, phy_ctrl_reg0 + slice);
+	prog_rdlvl_gate_delay(slice, gate_cnt % 8);
+
+	swlvl_load();
+	wait_op_done();
+}
+
+static void set_gate_parms_resp(u32 *gate_cnt_p, u32 slice, u32 loopon)
+{
+	do {
+		(*gate_cnt_p)++;
+		set_gate_parms(*gate_cnt_p, slice);
+	} while (read_resp(slice) == loopon);
+}
+
+void ddr3_lvl_gatetrn(void)
+{
+	u32 *phy_ctrl_reg0 = &mpmc_p->reg124;
+	u32 *phy_ctrl_reg6 = &mpmc_p->reg155;
+	u32 *phy_ctrl_reg7 = &mpmc_p->reg160;
+	u32 final_gate_counter[DATA_SLICE_MAX];
+	u32 slice, gate_counter, resp;
+	u32 prelim_preamble_start = 8, prelim_rise_edge = 8, prelim_fall_edge;
+	u32 prelim_dqs_low_start, prelim_dqs_low_end;
+
+	u32 phy_ctrl_reg6_dqs_assertval[] = {
+		(0x0 << 0) | (0x0 << 20),
+		(0x0 << 0) | (0x0 << 20),
+		(0x8 << 0) | (0x8 << 20),
+		(0x9 << 0) | (0x9 << 20),
+		(0xa << 0) | (0xa << 20),
+		(0xb << 0) | (0xb << 20)
+	};
+	u32 phy_ctrl_reg6_dqs_deassertval[] = {
+		(0x00 << 5) | (0x00 << 25),
+		(0x10 << 5) | (0x10 << 25),
+		(0x11 << 5) | (0x11 << 25),
+		(0x12 << 5) | (0x12 << 25),
+		(0x13 << 5) | (0x13 << 25),
+		(0x14 << 5) | (0x14 << 25)
+	};
+
+	writel_field(TDFI_RDLVL_RR, TDFI_RDLVL_RR_MSK, &mpmc_p->reg64);
+
+	for (slice = 0; slice < DATA_SLICE_MAX; slice++) {
+		writel_field(0 << 0, 7 << 0, phy_ctrl_reg6 + slice);
+		writel_field(0 << 3, 3 << 3, phy_ctrl_reg6 + slice);
+		writel_field(3 << 5, 7 << 5, phy_ctrl_reg6 + slice);
+		writel_field(2 << 8, 3 << 8, phy_ctrl_reg6 + slice);
+
+		writel_field(1 << 0, 7 << 0, phy_ctrl_reg7 + slice);
+	}
+
+	set_swlvl_mode(GATE_LVL);
+	swlvl_start();
+	wait_op_done();
+
+	for (slice = 0; slice < DATA_SLICE_MAX; slice++) {
+		gate_counter = 7;
+		set_gate_parms(++gate_counter, slice);
+
+		resp = read_resp(slice);
+		if (resp == 0) {
+			prelim_preamble_start = gate_counter;
+			set_gate_parms_resp(&gate_counter, slice, 0);
+			prelim_rise_edge = gate_counter;
+		} else if (resp == 1) {
+			set_gate_parms_resp(&gate_counter, slice, 1);
+			prelim_preamble_start = gate_counter;
+
+			set_gate_parms_resp(&gate_counter, slice, 0);
+			prelim_rise_edge = gate_counter;
+		}
+
+step_14:
+		while (prelim_rise_edge - prelim_preamble_start < MIN_1_8TH_CYCLE_PREAMBLE) {
+			set_gate_parms_resp(&gate_counter, slice, 1);
+			prelim_preamble_start = gate_counter;
+
+			set_gate_parms_resp(&gate_counter, slice, 0);
+			prelim_rise_edge = gate_counter;
+		}
+
+		if (prelim_rise_edge - prelim_preamble_start >= MIN_1_8TH_CYCLE_PREAMBLE) {
+			set_gate_parms_resp(&gate_counter, slice, 1);
+			prelim_fall_edge = gate_counter;
+		}
+
+		if ((prelim_fall_edge - prelim_rise_edge < MIN_NO_OF_1_8TH_CYCLE) ||
+			(prelim_fall_edge - prelim_rise_edge > MAX_NO_OF_1_8TH_CYCLE)) {
+
+			prelim_preamble_start = gate_counter;
+
+			set_gate_parms_resp(&gate_counter, slice, 0);
+			prelim_rise_edge = gate_counter;
+
+			goto step_14;
+		}
+
+		if ((prelim_fall_edge - prelim_rise_edge >= MIN_NO_OF_1_8TH_CYCLE) &&
+			(prelim_fall_edge - prelim_rise_edge <= MAX_NO_OF_1_8TH_CYCLE)) {
+
+			prelim_dqs_low_start = gate_counter;
+
+			set_gate_parms_resp(&gate_counter, slice, 0);
+			prelim_dqs_low_end = gate_counter;
+		}
+
+		if ((prelim_dqs_low_end - prelim_dqs_low_start < MIN_NO_OF_1_8TH_CYCLE) ||
+			(prelim_dqs_low_end - prelim_dqs_low_start > MAX_NO_OF_1_8TH_CYCLE)) {
+
+			set_gate_parms_resp(&gate_counter, slice, 1);
+			prelim_preamble_start = gate_counter;
+
+			set_gate_parms_resp(&gate_counter, slice, 0);
+			prelim_rise_edge = gate_counter;
+
+			goto step_14;
+		}
+
+		if ((prelim_dqs_low_end - prelim_dqs_low_start >= MIN_NO_OF_1_8TH_CYCLE) &&
+			(prelim_dqs_low_end - prelim_dqs_low_start <= MAX_NO_OF_1_8TH_CYCLE)) {
+
+			final_gate_counter[slice] = prelim_rise_edge;
+		}
+
+		final_gate_counter[slice] -= 7;
+		writel_field((final_gate_counter[slice] / 8) << 20, 7 << 20, phy_ctrl_reg0 + slice);
+		prog_rdlvl_gate_delay(slice, final_gate_counter[slice] % 8);
+
+		swlvl_load();
+		wait_op_done();
+	}
+
+	swlvl_exit();
+	wait_op_done();
+
+	for (slice = 0; slice < DATA_SLICE_MAX; slice++) {
+		writel_field(phy_ctrl_reg6_dqs_assertval[final_gate_counter[slice] / 8],
+				(0x1F << 0) | (0x1F << 20), phy_ctrl_reg6 + slice);
+		writel_field(phy_ctrl_reg6_dqs_deassertval[final_gate_counter[slice] / 8],
+				(0x1F << 5) | (0x1F << 25), phy_ctrl_reg6 + slice);
+	}
+}
+#endif
diff --git a/arch/arm/cpu/armv7/spear13xx/spl-lvl_read.c b/arch/arm/cpu/armv7/spear13xx/spl-lvl_read.c
new file mode 100644
index 0000000..db1a219
--- /dev/null
+++ b/arch/arm/cpu/armv7/spear13xx/spl-lvl_read.c
@@ -0,0 +1,229 @@ 
+/*
+ * (C) Copyright 2012
+ * Vipin Kumar, ST Microelectronics, vipin.kumar@st.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/mpmc.h>
+
+static struct mpmc_regs *mpmc_p = (struct mpmc_regs *)CONFIG_SYS_MPMC_BASE;
+
+static void prog_rdlvl_delay(u32 slice, u32 rdlvl_delay)
+{
+	u32 *rdlvl_delay_reg = &mpmc_p->reg81;
+	u32 shift;
+
+	rdlvl_delay_reg += (slice + 1) >> 1;
+	shift = (slice & 0x1) ? 0 : 16;
+	writel_field(rdlvl_delay << shift, 0xFFFF << shift, rdlvl_delay_reg);
+}
+
+u32 find_rdlvl_value(u32 *start, u32 *end)
+{
+	u32 edge_delta[2];
+	int diff;
+	u32 rdlvl_value;
+
+	edge_delta[0] = end[0] - start[0];
+	edge_delta[1] = end[1] - start[1];
+
+	if ((edge_delta[0] == 0) && (edge_delta[1] == 0)) {
+		if (start[0] != start[1])
+			goto error;
+		else
+			rdlvl_value = start[0];
+	} else if ((edge_delta[0] == 0) && (edge_delta[1] != 0)) {
+		if ((start[0] == start[1]) || (start[0] == (start[1] + 1)))
+			rdlvl_value = start[0];
+		else
+			goto error;
+	} else if ((edge_delta[0] != 0) && (edge_delta[1] == 0)) {
+		if ((start[1] == start[0]) || (start[1] == (start[0] + 1)))
+			rdlvl_value = start[1];
+		else
+			goto error;
+	} else {
+		diff = start[0] - start[1];
+		if (diff < 0)
+			diff = start[1] - start[0];
+
+		if ((start[1] == start[0]) && (edge_delta[0] > 2) && (edge_delta[1] > 2)) {
+			if (start[0] > 6)
+				rdlvl_value = start[0] + 1;
+			else
+				rdlvl_value = start[0] + 2;
+		} else {
+
+			if (start[1] == start[0]) {
+				rdlvl_value = start[1] + 1;
+			} else if (diff < 2) {
+				if ((edge_delta[0] == 1) && (edge_delta[1] == 1)) {
+					if (start[1] == (start[0] + 1))
+						rdlvl_value = start[1];
+					else if (start[0] == (start[1] + 1))
+						rdlvl_value = start[0];
+					else
+						goto error;
+				} else if (edge_delta[0] == edge_delta[1]) {
+					if (start[1] == (start[0] + 1))
+						rdlvl_value = start[1] + 1;
+					else if (start[0] == (start[1] + 1))
+						rdlvl_value = start[0] + 1;
+					else
+						goto error;
+				} else if (edge_delta[0] > edge_delta[1]) {
+					if (start[1] == (start[0] + 1))
+						rdlvl_value = start[0] + 2;
+					else if (start[0] == (start[1] + 1)) {
+						if (edge_delta[1] == 1)
+							rdlvl_value = start[1] + 1;
+						else
+							rdlvl_value = start[1] + 2;
+					} else
+						goto error;
+				} else {
+					if (start[0] == (start[1] + 1))
+						rdlvl_value = start[1] + 2;
+					else if (start[1] == (start[0] + 1)) {
+						if (edge_delta[0] == 1)
+							rdlvl_value = start[0] + 1;
+						else
+							rdlvl_value = start[0] + 2;
+					} else
+						goto error;
+				}
+			} else
+				goto error;
+		}
+	}
+
+	/* if allowed from actual read leveling data, adjust read phase to the default centered value 8 */
+	if ((rdlvl_value == 9) && (start[0] < 9) && (start[1] < 9))
+		return --rdlvl_value;
+	else if ((rdlvl_value == 7) && (end[0] > 7) && (end[1] > 7))
+		return ++rdlvl_value;
+	else
+		return rdlvl_value;
+
+error:
+	/* loop infinitly on read levelling error else it gets un-noticed */
+	while (1)
+		;
+
+	/*
+	 * other possibility is to reset the system
+	 * in case of a leveling error
+	 */
+	reset_cpu(0);
+}
+
+#if defined(CONFIG_DDR2)
+void ddr2_lvl_read(void)
+{
+	u32 slice;
+	int RDLVL_DELAY_VALUE[5] = {8, 8, 8, 8, 8};
+
+	RDLVL_DELAY_VALUE[0] = RDLVL_DELAY_VALUE_0;
+	RDLVL_DELAY_VALUE[1] = RDLVL_DELAY_VALUE_1;
+	RDLVL_DELAY_VALUE[2] = RDLVL_DELAY_VALUE_2;
+	RDLVL_DELAY_VALUE[3] = RDLVL_DELAY_VALUE_3;
+	RDLVL_DELAY_VALUE[4] = RDLVL_DELAY_VALUE_4;
+
+	for (slice = 0; slice < DATA_SLICE_MAX; slice++)
+		prog_rdlvl_delay(slice, RDLVL_DELAY_VALUE[slice]);
+}
+
+#elif defined(CONFIG_DDR3)
+void ddr3_lvl_read(void)
+{
+	u8 resp_array[DATA_SLICE_MAX][RDLVL_DELAY_VALS][2];
+	u32 i, j, k;
+	u32 count = 0;
+	u32 *phy_ctrl_reg0 = &mpmc_p->reg124;
+	u32 *phy_ctrl_reg2 = &mpmc_p->reg135;
+	u32 *phy_ctrl_reg3 = &mpmc_p->reg140;
+	u32 slice, rdlvl_delay, start_point_found, rdlvl_edge;
+	u32 delay_vals;
+	u32 start_point_0[2], end_point_0[2];
+
+	writel_field(0xffff, 0xffff, &mpmc_p->reg182);
+	writel_field(0x10 << 16, 0xff << 16, &mpmc_p->reg64);
+	writel_field(0x12 << 8, 0xff << 8, &mpmc_p->reg59);
+
+	for (i = 0; i < DATA_SLICE_MAX; i++)
+		for (j = 0; j < RDLVL_DELAY_VALS; j++)
+			for (k = 0; k < 2; k++)
+				resp_array[i][j][k] = 0x0;
+
+	for (slice = 0; slice < DATA_SLICE_MAX; slice++) {
+		writel_field(0x21 << 14, 0x3F << 14, phy_ctrl_reg0 + slice);
+		writel_field(0x21 << 8, 0x3F << 8, phy_ctrl_reg0 + slice);
+
+		writel_field(0x1 << 24, 0x3F << 24, phy_ctrl_reg2 + slice);
+		writel_field(0x1 << 24, 0x3F << 24, phy_ctrl_reg3 + slice);
+	}
+
+	set_swlvl_mode(READ_LVL);
+	swlvl_start();
+	wait_op_done();
+
+	swlvl_load();
+	wait_op_done();
+	for (count = 0; count < 100; count++) {
+		for (slice = 0; slice < DATA_SLICE_MAX; slice++) {
+			for (rdlvl_edge = 0; rdlvl_edge <= 1; rdlvl_edge++) {
+				writel_field(rdlvl_edge << 0, 1 << 0, &mpmc_p->reg7);
+				for (delay_vals = 0; delay_vals < RDLVL_DELAY_VALS; delay_vals++) {
+					prog_rdlvl_delay(slice, delay_vals + RDLVL_DELAY_INIT);
+					swlvl_load();
+					wait_op_done();
+
+					resp_array[slice][delay_vals][rdlvl_edge] |= read_resp(slice);
+				}
+			}
+		}
+	}
+	for (slice = 0; slice < DATA_SLICE_MAX; slice++) {
+		for (rdlvl_edge = 0; rdlvl_edge <= 1; rdlvl_edge++) {
+			start_point_found = 0;
+			for (delay_vals = 0; delay_vals < RDLVL_DELAY_VALS; delay_vals++) {
+				if ((resp_array[slice][delay_vals][rdlvl_edge] == 0) && !start_point_found) {
+					start_point_0[rdlvl_edge] = delay_vals + RDLVL_DELAY_INIT;
+					start_point_found = 1;
+				}
+				if ((resp_array[slice][delay_vals][rdlvl_edge] != 0) && start_point_found) {
+					end_point_0[rdlvl_edge] = delay_vals + RDLVL_DELAY_INIT - 1;
+					break;
+				}
+			}
+		}
+
+		rdlvl_delay = find_rdlvl_value(start_point_0, end_point_0);
+		prog_rdlvl_delay(slice, rdlvl_delay);
+		swlvl_load();
+		wait_op_done();
+	}
+	swlvl_exit();
+	wait_op_done();
+}
+#endif
diff --git a/arch/arm/cpu/armv7/spear13xx/spl-lvl_write.c b/arch/arm/cpu/armv7/spear13xx/spl-lvl_write.c
new file mode 100644
index 0000000..fdb005f
--- /dev/null
+++ b/arch/arm/cpu/armv7/spear13xx/spl-lvl_write.c
@@ -0,0 +1,608 @@ 
+/*
+ * (C) Copyright 2012
+ * Vipin Kumar, ST Microelectronics, vipin.kumar@st.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/mpmc.h>
+
+static struct mpmc_regs *mpmc_p = (struct mpmc_regs *)CONFIG_SYS_MPMC_BASE;
+
+static u32 source_sel_cal(u32 pattern)
+{
+	if ((pattern & 0xE1) == 0x60)
+		return 1;
+	else if ((pattern & 0xF0) == 0x30)
+		return 2;
+	else if ((pattern & 0x78) == 0x18)
+		return 3;
+	else if ((pattern & 0x3C) == 0x0C)
+		return 4;
+	else if ((pattern & 0x1E) == 0x06)
+		return 5;
+	else if ((pattern & 0x0F) == 0x03)
+		return 6;
+	else if ((pattern & 0x87) == 0x81)
+		return 7;
+	else
+		return 0;
+}
+
+static void reset_phy_ctrl_reg(u32 *reg)
+{
+	int i;
+
+	writel(readl(reg) | 0x1, reg);
+	for (i = 0; i < PHY_CTRL_DELAY; i++)
+		;
+	writel(readl(reg) & ~0x1, reg);
+}
+
+static void prog_wrlvl_delay(u32 slice, u32 wrlvl_delay)
+{
+	u32 *wrlvl_delay_reg = &mpmc_p->reg100;
+	u32 shift;
+
+	wrlvl_delay_reg += slice >> 1;
+	shift = (slice & 0x1) ? 16 : 0;
+	writel_field(wrlvl_delay << shift, 0xFFFF << shift, wrlvl_delay_reg);
+}
+
+static u32 get_wrlvl_start(u32 wrlvl_base_off)
+{
+	u32 cal_clk_byte_patt, cal_ref_byte_patt;
+	u32 clk_source_sel_cal_pre, ref_source_sel_cal_pre;
+	int wrlvl_base, wrlvl_start;
+
+	writel_field(wrlvl_base_off << 20, 7 << 20, &mpmc_p->reg129);
+	cal_clk_byte_patt = readl_field(0, 0xFF, &mpmc_p->reg181);
+	cal_ref_byte_patt = readl_field(8, 0xFF << 8, &mpmc_p->reg181);
+
+	clk_source_sel_cal_pre = source_sel_cal(cal_clk_byte_patt);
+	ref_source_sel_cal_pre = source_sel_cal(cal_ref_byte_patt);
+
+	wrlvl_base = ref_source_sel_cal_pre - clk_source_sel_cal_pre;
+	wrlvl_base &= 7;
+	wrlvl_start = wrlvl_base - wrlvl_base_off;
+	wrlvl_start &= 7;
+
+	return wrlvl_start;
+}
+
+static void set_wrlvldelay(u32 wrlvl_start, u32 *final_wrlvl_delay)
+{
+	u32 *phy_ctrl_reg1 = &mpmc_p->reg130;
+	u32 *phy_ctrl_reg0 = &mpmc_p->reg124;
+	u32 wrlvl_delay, slice, start_search;
+	u32 start_wrlvl_delay_mod, i;
+	u32 phy_ctrl_reg1_dqsgate_assertval[] = {
+		(0 << 0) | (1 << 3),
+		(0 << 0) | (2 << 3),
+		(0 << 0) | (1 << 3),
+		(0 << 0) | (2 << 3)
+	};
+	u32 phy_ctrl_reg1_dqsgate_deassertval[] = {
+		(0 << 5) | (2 << 8),
+		(0 << 5) | (1 << 8),
+		(0 << 5) | (2 << 8),
+		(0 << 5) | (1 << 8)
+	};
+	u8 resp_total[DATA_SLICE_MAX][WRLVL_DELAY_MAX];
+
+	/*
+	 * Start write leveling operation to find the wrlvldelay parameters for
+	 * each data slice
+	 */
+	for (slice = 0; slice < DATA_SLICE_MAX; slice++) {
+		swlvl_start();
+		wait_op_done();
+
+		for (wrlvl_delay = 0; wrlvl_delay < WRLVL_DELAY_MAX; wrlvl_delay++) {
+			start_wrlvl_delay_mod = wrlvl_start + wrlvl_delay;
+			reset_phy_ctrl_reg(phy_ctrl_reg0 + slice);
+			prog_wrlvl_delay(slice, wrlvl_delay);
+
+			writel_field(phy_ctrl_reg1_dqsgate_assertval[start_wrlvl_delay_mod/4],
+					DQSGATE_ASSERT_MSK, phy_ctrl_reg1 + slice);
+			writel_field(phy_ctrl_reg1_dqsgate_deassertval[start_wrlvl_delay_mod/4],
+					DQSGATE_DEASSERT_MSK, phy_ctrl_reg1 + slice);
+
+			resp_total[slice][wrlvl_delay] = 0;
+
+			for (i = 0; i < 4; i++) {
+				swlvl_load();
+				wait_op_done();
+
+				resp_total[slice][wrlvl_delay] += read_resp(slice);
+			}
+		}
+
+		start_search = 0;
+		for (wrlvl_delay = 0; wrlvl_delay < WRLVL_DELAY_MAX; wrlvl_delay++) {
+			if ((resp_total[slice][wrlvl_delay] < 4) && !start_search)
+				start_search = 1;
+			if ((resp_total[slice][wrlvl_delay] == 4) && start_search)
+				break;
+		}
+
+		/*
+		 * added 1 phase to DQS position
+		 * original was final_wrlvl_delay[slice] = wrlvl_delay - 1
+		 */
+		final_wrlvl_delay[slice] = wrlvl_delay;
+
+		prog_wrlvl_delay(slice, final_wrlvl_delay[slice]);
+		start_wrlvl_delay_mod = wrlvl_start + final_wrlvl_delay[slice];
+
+		writel_field(phy_ctrl_reg1_dqsgate_assertval[start_wrlvl_delay_mod/4],
+				DQSGATE_ASSERT_MSK, phy_ctrl_reg1 + slice);
+		writel_field(phy_ctrl_reg1_dqsgate_deassertval[start_wrlvl_delay_mod/4],
+				DQSGATE_DEASSERT_MSK, phy_ctrl_reg1 + slice);
+
+		swlvl_load();
+		wait_op_done();
+
+		swlvl_exit();
+		wait_op_done();
+	}
+}
+
+static u32 get_match_pre(u32 slice)
+{
+	u32 *obs_reg = &mpmc_p->reg175;
+	u32 dqs_byte_patt_mux_dqs = (readl(obs_reg + slice) >> 8) & 0xFF;
+
+	if ((dqs_byte_patt_mux_dqs & 0xE1) == 0x60)
+		return 1;
+	else if ((dqs_byte_patt_mux_dqs & 0xF0) == 0x30)
+		return 2;
+	else if ((dqs_byte_patt_mux_dqs & 0x78) == 0x18)
+		return 3;
+	else if ((dqs_byte_patt_mux_dqs & 0x3C) == 0x0C)
+		return 4;
+	else if ((dqs_byte_patt_mux_dqs & 0x1E) == 0x06)
+		return 5;
+	else if ((dqs_byte_patt_mux_dqs & 0x0F) == 0x03)
+		return 6;
+	else if ((dqs_byte_patt_mux_dqs & 0x87) == 0x81)
+		return 7;
+	else
+		return 0;
+}
+
+static u32 get_match0_pre(u32 slice)
+{
+	u32 *obs_reg = &mpmc_p->reg175;
+	u32 dqs_byte_patt_mux_data = (readl(obs_reg + slice) >> 16) & 0xFF;
+
+	if ((dqs_byte_patt_mux_data & 0x1F) == 0x00)
+		return 8;
+	else if ((dqs_byte_patt_mux_data & 0xF8) == 0xF8)
+		return 9;
+	else if ((dqs_byte_patt_mux_data & 0xF8) == 0x78)
+		return 1;
+	else if ((dqs_byte_patt_mux_data & 0xFC) == 0x3C)
+		return 2;
+	else if ((dqs_byte_patt_mux_data & 0xFE) == 0x1E)
+		return 3;
+	else if ((dqs_byte_patt_mux_data & 0xFF) == 0x0F)
+		return 4;
+	else if ((dqs_byte_patt_mux_data & 0x7F) == 0x07)
+		return 5;
+	else if ((dqs_byte_patt_mux_data & 0x3F) == 0x03)
+		return 6;
+	else if ((dqs_byte_patt_mux_data & 0x1F) == 0x01)
+		return 7;
+	else
+		return 0xF;
+}
+
+static u32 get_match1_pre(u32 slice)
+{
+	u32 *obs_reg = &mpmc_p->reg170;
+	u32 dqs_byte_patt_mux_data1 = (readl(obs_reg + slice) >> 23) & 0xFF;
+
+	if ((dqs_byte_patt_mux_data1 & 0x1F) == 0x00)
+		return 8;
+	else if ((dqs_byte_patt_mux_data1 & 0xF8) == 0xF8)
+		return 9;
+	else if ((dqs_byte_patt_mux_data1 & 0xF8) == 0x78)
+		return 1;
+	else if ((dqs_byte_patt_mux_data1 & 0xFC) == 0x3C)
+		return 2;
+	else if ((dqs_byte_patt_mux_data1 & 0xFE) == 0x1E)
+		return 3;
+	else if ((dqs_byte_patt_mux_data1 & 0xFF) == 0x0F)
+		return 4;
+	else if ((dqs_byte_patt_mux_data1 & 0x7F) == 0x07)
+		return 5;
+	else if ((dqs_byte_patt_mux_data1 & 0x3F) == 0x03)
+		return 6;
+	else if ((dqs_byte_patt_mux_data1 & 0x1F) == 0x01)
+		return 7;
+	else
+		return 0xF;
+}
+
+static void set_dqs_parms(u32 wrlvl_start, u32 *final_wrlvl_delay)
+{
+	u32 *phy_ctrl_reg1 = &mpmc_p->reg130;
+	u32 *phy_ctrl_reg4 = &mpmc_p->reg145;
+	u32 *phy_ctrl_reg5 = &mpmc_p->reg150;
+	u32 *phy_ctrl_reg6 = &mpmc_p->reg155;
+	u32 *phy_ctrl_reg7 = &mpmc_p->reg160;
+
+	u32 wr_dq_a_timing_reg, start_wrlvl_delay_mod, slice, dqtim;
+	u32 phy_clk_phase_match_pre, dq_clk_phase_match0_pre, dq_clk_phase_match1_pre;
+	u32 dq_clk_phase_match_pre;
+
+	u32 dqs_dq_clk_phase_match_delta;
+
+	u8 dqs_dq_clk_phase_match_delta_value[DATA_SLICE_MAX];
+	u8 dqs_dq_clk_phase_match_delta_offset[DATA_SLICE_MAX];
+
+	u32 dqs_dq_clk_phase_match_delta_expected;
+
+	u8 start_wrlvl_delay_mod_value[DATA_SLICE_MAX];
+	u8 start_wrlvl_delay_mod_offset_value[DATA_SLICE_MAX];
+
+	static u32 phy_ctrl_reg1_dqsgate_assertval[] = {
+		(0 << 0) | (1 << 3),
+		(0 << 0) | (2 << 3),
+		(1 << 0) | (1 << 3),
+		(1 << 0) | (2 << 3)
+	};
+	static u32 phy_ctrl_reg1_dqsgate_deassertval[] = {
+		(0 << 5) | (1 << 8),
+		(0 << 5) | (2 << 8),
+		(1 << 5) | (1 << 8),
+		(1 << 5) | (2 << 8)
+	};
+	static u32 phy_ctrl_reg1_dqsoe_assertval[] = {
+		(0 << 10) | (1 << 13),
+		(0 << 10) | (2 << 13),
+		(1 << 10) | (1 << 13),
+		(1 << 10) | (2 << 13)
+	};
+	static u32 phy_ctrl_reg1_dqsoe_deassertval[] = {
+		(1 << 15) | (2 << 18),
+		(2 << 15) | (1 << 18),
+		(2 << 15) | (2 << 18),
+		(3 << 15) | (1 << 18)
+	};
+	static u32 phy_ctrl_reg6_dqs_assertval[] = {
+		(0 << 10) | (1 << 13),
+		(0 << 10) | (2 << 13),
+		(1 << 10) | (1 << 13),
+		(1 << 10) | (2 << 13)
+	};
+	static u32 phy_ctrl_reg6_dqs_deassertval[] = {
+		(1 << 15) | (2 << 18),
+		(2 << 15) | (1 << 18),
+		(2 << 15) | (2 << 18),
+		(3 << 15) | (1 << 18)
+	};
+	static u16 phy_ctrl_reg5_assertval[4][15] = {
+		{0, 0, 0x08, 0x08, 0x08, 0x08, 0x10, 0x10, 0x10, 0x10, 0x09, 0x09, 0x09, 0x09, 0x11},
+		{0, 0, 0x00, 0x08, 0x08, 0x08, 0x08, 0x10, 0x10, 0x10, 0x10, 0x09, 0x09, 0x09, 0x09},
+		{0, 0, 0x00, 0x00, 0x08, 0x08, 0x08, 0x08, 0x10, 0x10, 0x10, 0x10, 0x09, 0x09, 0x09},
+		{0, 0, 0x00, 0x00, 0x00, 0x08, 0x08, 0x08, 0x08, 0x10, 0x10, 0x10, 0x10, 0x09, 0x09}
+	};
+	static u16 phy_ctrl_reg5_deassertval[4][15] = {
+		{0, 0, 0x100, 0x100, 0x100, 0x100, 0x200, 0x200, 0x200, 0x200, 0x120, 0x120, 0x120, 0x120, 0x220},
+		{0, 0, 0x000, 0x100, 0x100, 0x100, 0x100, 0x200, 0x200, 0x200, 0x200, 0x120, 0x120, 0x120, 0x120},
+		{0, 0, 0x000, 0x000, 0x100, 0x100, 0x100, 0x100, 0x200, 0x200, 0x200, 0x200, 0x120, 0x120, 0x120},
+		{0, 0, 0x000, 0x000, 0x000, 0x100, 0x100, 0x100, 0x100, 0x200, 0x200, 0x200, 0x200, 0x120, 0x120}
+	};
+	static u32 phy_ctrl_reg1_assertval[] = {
+		(0 << 20) | (1 << 23),
+		(0 << 20) | (2 << 23),
+		(1 << 20) | (1 << 23),
+		(1 << 20) | (2 << 23)
+	};
+	static u32 phy_ctrl_reg1_deassertval[] = {
+		(1 << 25) | (2 << 28),
+		(2 << 25) | (1 << 28),
+		(2 << 25) | (2 << 28),
+		(3 << 25) | (1 << 28)
+	};
+	static u32 phy_ctrl_reg7_assertval[] = {
+		(0 << 18) | (1 << 21),
+		(0 << 18) | (2 << 21),
+		(1 << 18) | (1 << 21),
+		(1 << 18) | (2 << 21)
+	};
+	static u32 phy_ctrl_reg7_deassertval[] = {
+		(1 << 23) | (2 << 26),
+		(2 << 23) | (1 << 26),
+		(2 << 23) | (2 << 26),
+		(3 << 23) | (1 << 26)
+	};
+
+	/*
+	 * first for cycle
+	 * data collection on dqs_dq_clk_phase_match_delta_value[slice]
+	 * data collection on start_wrlvl_delay_mod_value[slice]
+	 */
+	for (slice = 0; slice < DATA_SLICE_MAX; slice++) {
+
+		start_wrlvl_delay_mod = wrlvl_start + final_wrlvl_delay[slice];
+
+		writel_field(phy_ctrl_reg1_dqsgate_assertval[start_wrlvl_delay_mod/4],
+				DQSGATE_ASSERT_MSK, phy_ctrl_reg1 + slice);
+		writel_field(phy_ctrl_reg1_dqsgate_deassertval[start_wrlvl_delay_mod/4],
+				DQSGATE_DEASSERT_MSK, phy_ctrl_reg1 + slice);
+
+		writel_field(phy_ctrl_reg1_dqsoe_assertval[start_wrlvl_delay_mod/4],
+				DQSOE_ASSERT_MSK, phy_ctrl_reg1 + slice);
+		writel_field(phy_ctrl_reg1_dqsoe_deassertval[start_wrlvl_delay_mod/4],
+				DQSOE_DEASSERT_MSK, phy_ctrl_reg1 + slice);
+
+		writel_field(phy_ctrl_reg6_dqs_assertval[start_wrlvl_delay_mod/4],
+				REG6_DQS_ASSERT_MSK, phy_ctrl_reg6 + slice);
+		writel_field(phy_ctrl_reg6_dqs_deassertval[start_wrlvl_delay_mod/4],
+				REG6_DQS_DEASSERT_MSK, phy_ctrl_reg6 + slice);
+
+		phy_clk_phase_match_pre = get_match_pre(slice);
+		dq_clk_phase_match0_pre = get_match0_pre(slice);
+		dq_clk_phase_match1_pre = get_match1_pre(slice);
+
+		if ((dq_clk_phase_match0_pre & 0x8) == 0)
+			dq_clk_phase_match_pre = dq_clk_phase_match0_pre & 0xF;
+		else
+			dq_clk_phase_match_pre = dq_clk_phase_match1_pre & 0xF;
+
+		phy_clk_phase_match_pre &= 0xF;
+
+		if (phy_clk_phase_match_pre > dq_clk_phase_match_pre)
+			dqs_dq_clk_phase_match_delta = phy_clk_phase_match_pre - dq_clk_phase_match_pre;
+		else
+			dqs_dq_clk_phase_match_delta = dq_clk_phase_match_pre - phy_clk_phase_match_pre;
+		dqs_dq_clk_phase_match_delta &= 0xF;
+
+		if (dqs_dq_clk_phase_match_delta > 3) {
+			/* if delta is too high recalculate */
+			if ((dq_clk_phase_match0_pre & 0x8) == 0)
+				dq_clk_phase_match_pre = dq_clk_phase_match1_pre & 0xF;
+			else
+				dq_clk_phase_match_pre = dq_clk_phase_match0_pre & 0xF;
+
+			phy_clk_phase_match_pre &= 0xF;
+
+			if (phy_clk_phase_match_pre > dq_clk_phase_match_pre)
+				dqs_dq_clk_phase_match_delta = phy_clk_phase_match_pre - dq_clk_phase_match_pre;
+			else
+				dqs_dq_clk_phase_match_delta = dq_clk_phase_match_pre - phy_clk_phase_match_pre;
+			dqs_dq_clk_phase_match_delta &= 0xF;
+
+			if (dqs_dq_clk_phase_match_delta > 3)
+				hang();
+		}
+
+		dqs_dq_clk_phase_match_delta_value[slice] = dqs_dq_clk_phase_match_delta;
+		start_wrlvl_delay_mod_value[slice] = start_wrlvl_delay_mod;
+	}
+
+	/* dqs_dq_clk_phase_match_delta_expected calculation on slices 0,1,2 */
+	dqs_dq_clk_phase_match_delta_expected = (unsigned int) (((dqs_dq_clk_phase_match_delta_value[0] +
+						dqs_dq_clk_phase_match_delta_value[1] +
+						dqs_dq_clk_phase_match_delta_value[2] + (3/2))/3));
+
+	/*
+	 * second for cycle
+	 * start_wrlvl_delay_mod_offset_value calculation
+	 */
+	for (slice = 0; slice < DATA_SLICE_MAX; slice++) {
+			dqs_dq_clk_phase_match_delta_offset[slice] =
+		(u32) (dqs_dq_clk_phase_match_delta_expected -
+			dqs_dq_clk_phase_match_delta_value[slice]);
+
+		start_wrlvl_delay_mod_offset_value[slice] =
+		(u32) (start_wrlvl_delay_mod_value[slice] -
+			dqs_dq_clk_phase_match_delta_offset[slice]);
+	}
+
+	/* third for cycle, write leveling settings */
+	for (slice = 0; slice < DATA_SLICE_MAX; slice++) {
+
+		start_wrlvl_delay_mod = wrlvl_start + final_wrlvl_delay[slice];
+
+		writel_field(phy_ctrl_reg1_dqsgate_assertval[start_wrlvl_delay_mod/4],
+				DQSGATE_ASSERT_MSK, phy_ctrl_reg1 + slice);
+		writel_field(phy_ctrl_reg1_dqsgate_deassertval[start_wrlvl_delay_mod/4],
+				DQSGATE_DEASSERT_MSK, phy_ctrl_reg1 + slice);
+
+		writel_field(phy_ctrl_reg1_dqsoe_assertval[start_wrlvl_delay_mod/4],
+				DQSOE_ASSERT_MSK, phy_ctrl_reg1 + slice);
+		writel_field(phy_ctrl_reg1_dqsoe_deassertval[start_wrlvl_delay_mod/4],
+				DQSOE_DEASSERT_MSK, phy_ctrl_reg1 + slice);
+
+		writel_field(phy_ctrl_reg6_dqs_assertval[start_wrlvl_delay_mod/4],
+				REG6_DQS_ASSERT_MSK, phy_ctrl_reg6 + slice);
+		writel_field(phy_ctrl_reg6_dqs_deassertval[start_wrlvl_delay_mod/4],
+				REG6_DQS_DEASSERT_MSK, phy_ctrl_reg6 + slice);
+
+		phy_clk_phase_match_pre = get_match_pre(slice);
+		dq_clk_phase_match0_pre = get_match0_pre(slice);
+		dq_clk_phase_match1_pre = get_match1_pre(slice);
+
+		if ((dq_clk_phase_match0_pre & 0x8) == 0)
+			dq_clk_phase_match_pre = dq_clk_phase_match0_pre & 0xF;
+		else
+			dq_clk_phase_match_pre = dq_clk_phase_match1_pre & 0xF;
+
+		phy_clk_phase_match_pre &= 0xF;
+
+		if (phy_clk_phase_match_pre > dq_clk_phase_match_pre)
+			dqs_dq_clk_phase_match_delta = phy_clk_phase_match_pre - dq_clk_phase_match_pre;
+		else
+			dqs_dq_clk_phase_match_delta = dq_clk_phase_match_pre - phy_clk_phase_match_pre;
+		dqs_dq_clk_phase_match_delta &= 0xF;
+
+		if (dqs_dq_clk_phase_match_delta > 3) {
+			/* if delta is too high recalculate */
+			if ((dq_clk_phase_match0_pre & 0x8) == 0)
+				dq_clk_phase_match_pre = dq_clk_phase_match1_pre & 0xF;
+			else
+				dq_clk_phase_match_pre = dq_clk_phase_match0_pre & 0xF;
+
+			phy_clk_phase_match_pre &= 0xF;
+
+			if (phy_clk_phase_match_pre > dq_clk_phase_match_pre)
+				dqs_dq_clk_phase_match_delta = phy_clk_phase_match_pre - dq_clk_phase_match_pre;
+			else
+				dqs_dq_clk_phase_match_delta = dq_clk_phase_match_pre - phy_clk_phase_match_pre;
+			dqs_dq_clk_phase_match_delta &= 0xF;
+
+			if (dqs_dq_clk_phase_match_delta > 3)
+				hang();
+		}
+
+		/* here we use start_wrlvl_delay_mod_offset_value[slice], phy_ctrl_reg4 and phy_ctrl_reg5 are related to DQ phase  */
+		dqtim = (start_wrlvl_delay_mod_offset_value[slice] - 2) & 0x7;
+		wr_dq_a_timing_reg = (dqtim << 0) | (dqtim << 3) | (dqtim << 6) | (dqtim << 9) |
+			(dqtim << 12) | (dqtim << 15) | (dqtim << 18) | (dqtim << 21) | (dqtim << 24);
+
+		writel(wr_dq_a_timing_reg, phy_ctrl_reg4 + slice);
+
+		writel_field(phy_ctrl_reg5_assertval[dqs_dq_clk_phase_match_delta][start_wrlvl_delay_mod_offset_value[slice]],
+				REG5_ASSERT_MSK, phy_ctrl_reg5 + slice);
+		writel_field(phy_ctrl_reg5_deassertval[dqs_dq_clk_phase_match_delta][start_wrlvl_delay_mod_offset_value[slice]],
+				REG5_DEASSERT_MSK, phy_ctrl_reg5 + slice);
+
+		/* here we use start_wrlvl_delay_mod, phy_ctrl_reg1 and phy_ctrl_reg7 are related to DQS phase  */
+		writel_field(phy_ctrl_reg1_assertval[start_wrlvl_delay_mod/4],
+				REG1_ASSERT_MSK, phy_ctrl_reg1 + slice);
+		writel_field(phy_ctrl_reg1_deassertval[start_wrlvl_delay_mod/4],
+				REG1_DEASSERT_MSK, phy_ctrl_reg1 + slice);
+		writel_field(phy_ctrl_reg7_assertval[start_wrlvl_delay_mod/4],
+				REG7_ASSERT_MSK, phy_ctrl_reg7 + slice);
+		writel_field(phy_ctrl_reg7_deassertval[start_wrlvl_delay_mod/4],
+				REG7_DEASSERT_MSK, phy_ctrl_reg7 + slice);
+	}
+}
+
+#if defined(CONFIG_DDR2)
+static void set_wrlvldelay_ddr2(u32 wrlvl_start, u32 *final_wrlvl_delay)
+{
+	u32 *phy_ctrl_reg1 = &mpmc_p->reg130;
+	u32 *phy_ctrl_reg0 = &mpmc_p->reg124;
+	u32 slice;
+	u32 start_wrlvl_delay_mod;
+	u32 phy_ctrl_reg1_dqsgate_assertval[] = {
+		(0 << 0) | (1 << 3),
+		(0 << 0) | (2 << 3),
+		(0 << 0) | (1 << 3),
+		(0 << 0) | (2 << 3)
+	};
+	u32 phy_ctrl_reg1_dqsgate_deassertval[] = {
+		(0 << 5) | (2 << 8),
+		(0 << 5) | (1 << 8),
+		(0 << 5) | (2 << 8),
+		(0 << 5) | (1 << 8)
+	};
+	int WRLVL_DELAY_VALUE[5] = {2, 2, 2, 2, 2};
+
+	WRLVL_DELAY_VALUE[0] = WRLVL_DELAY_VALUE_0;
+	WRLVL_DELAY_VALUE[1] = WRLVL_DELAY_VALUE_1;
+	WRLVL_DELAY_VALUE[2] = WRLVL_DELAY_VALUE_2;
+	WRLVL_DELAY_VALUE[3] = WRLVL_DELAY_VALUE_3;
+	WRLVL_DELAY_VALUE[4] = WRLVL_DELAY_VALUE_4;
+
+	for (slice = 0; slice < DATA_SLICE_MAX; slice++) {
+
+		reset_phy_ctrl_reg(phy_ctrl_reg0 + slice);
+
+		final_wrlvl_delay[slice] = WRLVL_DELAY_VALUE[slice];
+
+		prog_wrlvl_delay(slice, final_wrlvl_delay[slice]);
+		start_wrlvl_delay_mod = wrlvl_start + final_wrlvl_delay[slice];
+
+		writel_field(phy_ctrl_reg1_dqsgate_assertval[start_wrlvl_delay_mod/4],
+				DQSGATE_ASSERT_MSK, phy_ctrl_reg1 + slice);
+		writel_field(phy_ctrl_reg1_dqsgate_deassertval[start_wrlvl_delay_mod/4],
+				DQSGATE_DEASSERT_MSK, phy_ctrl_reg1 + slice);
+	}
+}
+
+void ddr2_lvl_write(void)
+{
+
+	int wrlvl_start;
+	u32 final_wrlvl_delay[DATA_SLICE_MAX];
+	u32 wrlvl_base_offset_reg = 0;
+
+	wrlvl_base_offset_reg = WRLVL_BASE_OFFSET_REG_VALUE;
+
+	/* enable also wrlvl_reg_en, rdlvl_gate_reg_en, rdlvl_reg_en when START MPMC parameter is enabled  */
+	writel(readl(&mpmc_p->reg15) | WRLVL_REG_EN, &mpmc_p->reg15);
+	writel(readl(&mpmc_p->reg8) | RDLVL_GATE_REG_EN, &mpmc_p->reg8);
+	writel(readl(&mpmc_p->reg9) | RDLVL_REG_EN, &mpmc_p->reg9);
+
+	wrlvl_start = get_wrlvl_start(wrlvl_base_offset_reg);
+
+	set_wrlvldelay_ddr2(wrlvl_start, final_wrlvl_delay);
+
+	set_dqs_parms(wrlvl_start, final_wrlvl_delay);
+}
+#elif defined(CONFIG_DDR3)
+
+void ddr3_lvl_write(void)
+{
+	int wrlvl_start;
+	u32 wrlvl_base_offset_reg;
+	u32 final_wrlvl_delay[DATA_SLICE_MAX];
+	u32 wrlvl_base_offset_check;
+	u32 slice;
+
+	wrlvl_base_offset_reg = 2; /* start from default value */
+
+	do {
+		set_swlvl_mode(WRITE_LVL);
+		swlvl_start();
+		wait_op_done();
+
+		wrlvl_start = get_wrlvl_start(wrlvl_base_offset_reg);
+		swlvl_exit();
+		wait_op_done();
+
+		/* Set wrlvl_delay parameters through write leveling */
+		set_wrlvldelay(wrlvl_start, final_wrlvl_delay);
+
+		wrlvl_base_offset_check = 0;
+
+		for (slice = 0; slice < DATA_SLICE_MAX; slice++)
+			if (final_wrlvl_delay[slice] >= 8)
+				wrlvl_base_offset_check++;
+
+		if (wrlvl_base_offset_check > 0)
+			wrlvl_base_offset_reg++;
+
+		if (wrlvl_base_offset_reg >= 8)
+			wrlvl_base_offset_reg = 0;
+
+	} while ((wrlvl_base_offset_check != 0));
+
+	set_dqs_parms(wrlvl_start, final_wrlvl_delay);
+}
+#endif
diff --git a/arch/arm/cpu/armv7/spear13xx/spl-spear1340.c b/arch/arm/cpu/armv7/spear13xx/spl-spear1340.c
new file mode 100644
index 0000000..501c4d4
--- /dev/null
+++ b/arch/arm/cpu/armv7/spear13xx/spl-spear1340.c
@@ -0,0 +1,210 @@ 
+/*
+ * (C) Copyright 2012
+ * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/generic.h>
+#include <asm/arch/misc.h>
+#include <asm/arch/mpmc.h>
+
+static void pll_init(void)
+{
+	struct spear1340_misc_regs *const misc_p =
+		(struct spear1340_misc_regs *)CONFIG_SYS_MISC_BASE;
+	u32 usbphycfg;
+
+	/* Initialize PLLs */
+	writel(SPEAR1340_FREQ_1000, &misc_p->pll1_frq);
+	writel(readl(&misc_p->pll1_ctr) | SPEAR1340_PLLENABLE, &misc_p->pll1_ctr);
+
+	writel(SPEAR1340_FREQ_125, &misc_p->pll2_frq);
+	writel(readl(&misc_p->pll2_ctr) | SPEAR1340_PLLENABLE, &misc_p->pll2_ctr);
+
+	writel(SPEAR1340_FREQ_332, &misc_p->pll3_frq);
+	writel(readl(&misc_p->pll3_ctr) | SPEAR1340_PLLENABLE, &misc_p->pll3_ctr);
+#if defined(CONFIG_SPEAR_DDRFREQ400)
+	writel(SPEAR1340_FREQ_400, &misc_p->pll4_frq);
+#elif defined(CONFIG_SPEAR_DDRFREQ533)
+	writel(SPEAR1340_FREQ_533, &misc_p->pll4_frq);
+#else
+#error Define one of the valid DDR frequency(CONFIG_SPEAR_DDRFREQ[533/400])
+#endif
+	/* strobing required for pll4 */
+	writel(0x60A, &misc_p->pll4_ctr);
+	writel(0x60E, &misc_p->pll4_ctr);
+	writel(0x606, &misc_p->pll4_ctr);
+	writel(0x60E, &misc_p->pll4_ctr);
+
+	usbphycfg = readl(&misc_p->usbphy_gen_cfg);
+	usbphycfg &= ~(SPEAR1340_COMMON_PWDN | SPEAR1340_USBPHY_POR);
+	usbphycfg |= SPEAR1340_USBPHY_RST;
+	writel(usbphycfg, &misc_p->usbphy_gen_cfg);
+
+	while (!(readl(&misc_p->usbphy_gen_cfg) & SPEAR1340_USB_PLL_LOCK))
+		;
+
+	/* AHB Master Burst is not supported for SPEAr1340 */
+	usbphycfg = readl(&misc_p->usbphy_gen_cfg);
+
+	usbphycfg |= SPEAR1340_AUTOPPD_ON_OVRCURR | \
+		     SPEAR1340_UTMI_XFER_RST0 | \
+		     SPEAR1340_UTMI_XFER_RST1 | \
+		     SPEAR1340_UTMI_XFER_RST2;
+
+	writel(usbphycfg, &misc_p->usbphy_gen_cfg);
+
+	/* wait for pll locks */
+	while (!(readl(&misc_p->pll1_ctr) & SPEAR1340_PLLLOCK))
+		;
+	while (!(readl(&misc_p->pll2_ctr) & SPEAR1340_PLLLOCK))
+		;
+	while (!(readl(&misc_p->pll3_ctr) & SPEAR1340_PLLLOCK))
+		;
+	while (!(readl(&misc_p->pll4_ctr) & SPEAR1340_PLLLOCK))
+		;
+}
+
+static void sys_init(void)
+{
+	struct spear1340_misc_regs *const misc_p =
+		(struct spear1340_misc_regs *)CONFIG_SYS_MISC_BASE;
+	u32 sysclkctrl;
+
+	/* Set system state to SLOW */
+	sysclkctrl = readl(&misc_p->sys_clk_ctrl);
+	sysclkctrl &= ~SPEAR1340_SYS_MODE_MASK;
+	sysclkctrl |= SPEAR1340_XTAL_TIMEOUT_ENB | \
+		      SPEAR1340_PLL_TIMEOUT_ENB | \
+		      SPEAR1340_SYS_MODE_REQ_SLOW;
+	writel(sysclkctrl, &misc_p->sys_clk_ctrl);
+
+	writel(SPEAR1340_PLL_TIM, &misc_p->sys_clk_plltimer);
+	writel(SPEAR1340_OSCI_TIM, &misc_p->sys_clk_oscitimer);
+
+	/* Initialize PLLs */
+	pll_init();
+
+	/* Set system state to NORMAL */
+	sysclkctrl = readl(&misc_p->sys_clk_ctrl);
+	sysclkctrl &= ~SPEAR1340_SYS_MODE_MASK;
+	sysclkctrl |= SPEAR1340_XTAL_TIMEOUT_ENB | \
+		      SPEAR1340_PLL_TIMEOUT_ENB | \
+		      SPEAR1340_SYS_MODE_REQ_NORMAL;
+	writel(sysclkctrl, &misc_p->sys_clk_ctrl);
+
+	/* Wait for system to switch to normal mode */
+	while ((readl(&misc_p->sys_clk_ctrl) & SPEAR1340_SYS_STATE_MASK) !=
+			SPEAR1340_SYS_STATE_NORMAL)
+		;
+#if defined(CONFIG_C3)
+	writel(readl(&misc_p->perip1_clk_enb) | SPEAR1340_C3_CLKEN,
+			&misc_p->perip1_clk_enb);
+#endif
+}
+
+static void ddr_clock_init(void)
+{
+	struct spear1340_misc_regs *const misc_p =
+		(struct spear1340_misc_regs *)CONFIG_SYS_MISC_BASE;
+	u32 perip_clkcfg, perip2_clkenb, perip2_swrst;
+
+	perip_clkcfg = readl(&misc_p->perip_clk_cfg);
+	perip_clkcfg |= SPEAR1340_MPMCCLKPLL4;
+	writel(perip_clkcfg, &misc_p->perip_clk_cfg);
+
+	perip2_clkenb = readl(&misc_p->perip2_clk_enb);
+	perip2_clkenb |= SPEAR1340_DDRCTRL_CLKEN | SPEAR1340_DDRCORE_CLKEN;
+	writel(perip2_clkenb, &misc_p->perip2_clk_enb);
+
+	/*
+	 * MISC compensation_ddr_cfg before mpmc reset
+	 * disable automatic ddr pad compensation
+	 * use fixed comzcp=0000 and comzcn=0000
+	 */
+	writel(0x00000000, &misc_p->compensation_ddr_cfg);
+
+	perip2_swrst = readl(&misc_p->perip2_sw_rst);
+	perip2_swrst |= SPEAR1340_DDRCTRL_RST | SPEAR1340_DDRCORE_RST;
+	writel(perip2_swrst, &misc_p->perip2_sw_rst);
+
+	perip2_swrst = readl(&misc_p->perip2_sw_rst);
+	perip2_swrst &= ~(SPEAR1340_DDRCTRL_RST | SPEAR1340_DDRCORE_RST);
+	writel(perip2_swrst, &misc_p->perip2_sw_rst);
+}
+
+static void ddr_pad_compensation(u8 enable)
+{
+	struct spear1340_misc_regs *const misc_p =
+		(struct spear1340_misc_regs *)CONFIG_SYS_MISC_BASE;
+
+	if (enable) {
+		writel(0x00000400, &misc_p->compensation_ddr_cfg);
+		writel(0x00000400, &misc_p->compensation_ddr_cfg);
+		writel(0x00000400, &misc_p->compensation_ddr_cfg);
+
+		/* wait for comzcrdy done */
+		while (!(readl(&misc_p->compensation_ddr_cfg) & 0x1))
+			;
+	} else {
+		writel(0x00000000, &misc_p->compensation_ddr_cfg);
+		writel(0x00000000, &misc_p->compensation_ddr_cfg);
+		writel(0x00000000, &misc_p->compensation_ddr_cfg);
+	}
+}
+
+void ddr_init(void)
+{
+	struct spear1340_misc_regs *const misc_p =
+		(struct spear1340_misc_regs *)CONFIG_SYS_MISC_BASE;
+
+	/* Clock related settings for DDR */
+	ddr_clock_init();
+
+	/* Initialize mpmc register values */
+	spear13xx_mpmc_init((u32 *)CONFIG_SYS_MPMC_BASE, CONFIG_SPEAR_MPMCREGS);
+
+	writel(SPEAR1340_PAD_VREF | SPEAR1340_DATA_PROGB | \
+		SPEAR1340_DATA_PROGA | SPEAR1340_CLK_PROGB | \
+		SPEAR1340_CLK_PROGA | SPEAR1340_CTRL_PROGB | \
+		SPEAR1340_CTRL_PROGA,
+		&misc_p->ddr_pad_cfg);
+
+	ddr_pad_compensation(0);
+	spear13xx_ddr_level();
+	ddr_pad_compensation(1);
+}
+
+void soc_init(void)
+{
+	struct spear1340_misc_regs *const misc_p =
+		(struct spear1340_misc_regs *)CONFIG_SYS_MISC_BASE;
+
+	/* Initialize PLLs */
+	sys_init();
+
+	/* Enable IPs (release reset) */
+	writel(SPEAR1340_PERIPH1_RST_ALL, &misc_p->perip1_sw_rst);
+	writel(SPEAR1340_PERIPH2_RST_ALL, &misc_p->perip2_sw_rst);
+	writel(SPEAR1340_PERIPH3_RST_ALL, &misc_p->perip3_sw_rst);
+}
diff --git a/arch/arm/cpu/armv7/spear13xx/spl-spear13xx.c b/arch/arm/cpu/armv7/spear13xx/spl-spear13xx.c
new file mode 100644
index 0000000..49b6043
--- /dev/null
+++ b/arch/arm/cpu/armv7/spear13xx/spl-spear13xx.c
@@ -0,0 +1,162 @@ 
+/*
+ * (C) Copyright 2012
+ * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <post.h>
+#include <asm/io.h>
+#include <asm/arch/c3.h>
+#include <asm/arch/generic.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/mpmc.h>
+
+static void spear13xx_init(void)
+{
+	/*
+	 * Enable the filtering at L2 cache controller level.
+	 * This code limits the address range which can be accessed through the
+	 * two ports coming out of ARM core.
+	 *
+	 * Port 0 access -> All - (Port 1 access range)
+	 * Port 1 access -> 0x0 - 0x4000,0000 (1GB) all DDR space
+	 * available on evaluation board
+	 */
+
+	/* L2 cache controller filtering registers */
+	writel(0x40000000, CONFIG_SYS_L2CACHE_BASE + 0xC04);
+	writel(0x00000000 | 0x1, CONFIG_SYS_L2CACHE_BASE + 0xC00);
+
+	cpu2_wake();
+
+	cleanup_before_linux();
+}
+
+void spear13xx_mpmc_init(u32 *mpmcbase, u32 reg_num)
+{
+	u32 i;
+	u32 *mpmc_reg_p = mpmcbase;
+	u32 *mpmc_val_p = &mpmc_conf_vals[0];
+
+	for (i = 0; i < reg_num; i++, mpmc_reg_p++, mpmc_val_p++)
+		writel(*mpmc_val_p, mpmc_reg_p);
+
+	mpmc_reg_p = mpmcbase;
+
+	/*
+	 * Enable default DDR pad termination settings during read operations
+	 * Modify MPMC registers 160-164
+	 */
+	for (i = 160; i <= 164; i++)
+		writel((readl(&mpmc_reg_p[i]) & ~0x3FFFF) | 0x03219,
+				&mpmc_reg_p[i]);
+
+	/*
+	 * MPMC register25 rewrite
+	 * MPMC controller start
+	 */
+	writel(0x03070700, &mpmc_reg_p[25]);
+	writel(0x01000101, &mpmc_reg_p[11]);
+
+	while (!(readl(&mpmc_reg_p[105]) & 0x200))
+		;
+}
+
+void spear13xx_ddr_level(void)
+{
+#if defined(CONFIG_DDR2)
+	ddr2_lvl_write();
+	ddr2_lvl_read();
+	ddr2_lvl_gatetrn();
+#elif defined(CONFIG_DDR3)
+	ddr3_lvl_write();
+	ddr3_lvl_gatetrn();
+	ddr3_lvl_read();
+#endif
+}
+
+static void spear13xx_ddrecc_init(void)
+{
+	/*
+	 * The complete memory has to be initialized so that the ECC DDR gets
+	 * populated and it starts working
+	 *
+	 * There are two ways to handle this
+	 * - Through CPU. Cache has to be enabled to make it faster.
+	 * - Through accelarator (C3)
+	 */
+#if defined(CONFIG_DDR_ECC_ENABLE)
+	u32 ram_size = get_ram_size(CONFIG_SYS_SDRAM_BASE, SDRAM_MAX_SIZE);
+	u32 *mpmc_reg_p = (u32 *)CONFIG_SYS_MPMC_BASE;
+	u32 reg18;
+
+	reg18 = readl(&mpmc_reg_p[18]);
+	reg18 &= ~MPMC_REG18_ECC_MASK;
+	reg18 |= MPMC_REG18_ECC_CORR_ON;
+	writel(reg18, &mpmc_reg_p[18]);
+
+	while ((readl(&mpmc_reg_p[18]) & MPMC_REG18_ECC_MASK) !=
+			MPMC_REG18_ECC_CORR_ON)
+		;
+#if defined(CONFIG_C3)
+	c3_init();
+	c3_memset((void *)0, 0, ram_size);
+#else
+#error Define CONFIG_C3 for DDR ECC support
+#endif
+#endif /* CONFIG_DDR_ECC_ENABLE */
+}
+
+void __def_board_init(void)
+{
+	return;
+}
+void board_pre_ddrinit(void) __attribute__((weak, alias("__def_board_init")));
+void board_post_ddrinit(void) __attribute__((weak, alias("__def_board_init")));
+
+void lowlevel_init(void)
+{
+	/* ARCH specific initialization */
+	spear13xx_init();
+
+	/* Board initializations required for ddr initialization */
+	board_pre_ddrinit();
+
+	/* Initialize the SoC */
+	soc_init();
+
+	/* Initialize RAM */
+	ddr_init();
+
+	/* DDR ECC related initialization */
+	spear13xx_ddrecc_init();
+
+	/* Board initializations independent of DDR */
+	board_post_ddrinit();
+
+	/* A memory test is placed in U-Boot */
+}
+
+inline void hang(void)
+{
+	while(1)
+		;
+}
diff --git a/arch/arm/cpu/armv7/spear13xx/spl-swlvl.c b/arch/arm/cpu/armv7/spear13xx/spl-swlvl.c
new file mode 100644
index 0000000..d680e90
--- /dev/null
+++ b/arch/arm/cpu/armv7/spear13xx/spl-swlvl.c
@@ -0,0 +1,93 @@ 
+/*
+ * (C) Copyright 2012
+ * Vipin Kumar, ST Microelectronics, vipin.kumar@st.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/mpmc.h>
+
+static struct mpmc_regs *mpmc_p = (struct mpmc_regs *)CONFIG_SYS_MPMC_BASE;
+
+void writel_field(u32 value, u32 mask, u32 *address)
+{
+	u32 reg;
+	reg = readl(address);
+	reg &= ~mask;
+	reg |= value;
+	writel(reg, address);
+}
+
+u32 readl_field(u32 shift, u32 mask, u32 *address)
+{
+	u32 reg = readl(address);
+	return (reg & mask) >> shift;
+}
+
+void set_swlvl_mode(u32 lvlmode)
+{
+	switch (lvlmode) {
+	case WRITE_LVL:
+		writel_field(WRITE_LVL, SWLVL_MODE_MSK, &mpmc_p->reg20);
+		break;
+	case GATE_LVL:
+		writel_field(GATE_LVL, SWLVL_MODE_MSK, &mpmc_p->reg20);
+		break;
+	case READ_LVL:
+		writel_field(READ_LVL, SWLVL_MODE_MSK, &mpmc_p->reg20);
+		break;
+	}
+}
+
+void swlvl_start(void)
+{
+	writel(readl(&mpmc_p->reg13) | SWLVL_START, &mpmc_p->reg13);
+}
+
+void swlvl_load(void)
+{
+	writel(readl(&mpmc_p->reg12) | SWLVL_LOAD, &mpmc_p->reg12);
+}
+
+void swlvl_exit(void)
+{
+	writel(readl(&mpmc_p->reg12) | SWLVL_EXIT, &mpmc_p->reg12);
+}
+
+void wait_op_done(void)
+{
+	while (!(readl(&mpmc_p->reg13) & SWLVL_OP_DONE))
+		;
+}
+
+u32 read_resp(u32 slice)
+{
+	u32 *resp_reg = &mpmc_p->reg57;
+
+	if (slice < 2)
+		return (readl(resp_reg) >> (slice * 8 + 16)) & 0x1;
+
+	resp_reg = &mpmc_p->reg58;
+
+	/* return (readl(resp_reg) >> ((slice - 2) * 8)) & 0xFF; */
+	return (readl(resp_reg) >> ((slice - 2) * 8)) & 0x1;
+}
diff --git a/arch/arm/cpu/armv7/spear13xx/start.S b/arch/arm/cpu/armv7/spear13xx/start.S
new file mode 100644
index 0000000..8860933
--- /dev/null
+++ b/arch/arm/cpu/armv7/spear13xx/start.S
@@ -0,0 +1,137 @@ 
+/*
+ *  Startup Code for SPEAr13xx
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <asm-offsets.h>
+#include <config.h>
+#include <asm/system.h>
+#include <linux/linkage.h>
+
+.syntax	unified
+
+.globl _start
+_start:
+	.word 0xe59f0000 	@ ldr	r0, [pc, #0]	; <thumb_loc>
+	.word 0xe12fff10 	@ bx	r0
+
+thumb_loc:
+#ifdef __thumb__
+	.word thumb + 1
+#else
+	.word thumb
+#endif
+
+#ifdef __thumb__
+.thumb
+#endif
+
+/*
+ * the actual reset code (Thumb compatible)
+ * Startup Code (reset vector)
+ *
+ * Critical initializations already taken place in BootROM.
+ * So, these are not taken care in Xloader
+ * 1. Relocation to RAM
+ * 2. Initializing stacks
+ */
+
+/******************************************************************************
+	PLACE ALL INITIALIZATION CODE ONLY AFTER THIS LOCATION
+ ******************************************************************************/
+
+thumb:
+
+/*
+ * Xloader has to return back to BootROM in a few cases.
+ * eg. Ethernet boot, UART boot, USB boot
+ * Saving registers for returning back
+ */
+	push	{r1-r12, lr}
+
+	/* Relocate data if needed and Clear BSS */
+	ldr	r0, =__bss_start
+	ldr	r1, =__bss_end
+	mov	r2, #0x00000000		/* clear			    */
+
+clbss_l:
+	cmp	r0, r1			/* clear loop... */
+	bhs	clbss_e			/* if reached end of bss, exit */
+	str	r2, [r0]
+	add	r0, r0, #4
+	b	clbss_l
+clbss_e:
+
+	bl	cpu_init_cp15
+	bl	cpu_init_crit
+
+	bl	spl_boot
+	pop	{r1-r12, pc}
+
+/*************************************************************************
+ *
+ * cpu_init_cp15
+ *
+ * Setup CP15 registers (cache, MMU, TLBs)
+ *
+ *************************************************************************/
+ENTRY(cpu_init_cp15)
+	/*
+	 * Invalidate L1 I/D
+	 */
+	mov	r0, #0			@ set up for MCR
+	mcr	p15, 0, r0, c8, c7, 0	@ invalidate TLBs
+	mcr	p15, 0, r0, c7, c5, 0	@ invalidate icache
+	mcr	p15, 0, r0, c7, c5, 6	@ invalidate BP array
+	mcr     p15, 0, r0, c7, c10, 4	@ DSB
+	mcr     p15, 0, r0, c7, c5, 4	@ ISB
+
+	/*
+	 * disable MMU stuff and caches
+	 */
+	mrc	p15, 0, r0, c1, c0, 0
+	bic	r0, r0, #0x00002000	@ clear bits 13 (--V-)
+	bic	r0, r0, #0x00000007	@ clear bits 2:0 (-CAM)
+	orr	r0, r0, #0x00000002	@ set bit 1 (--A-) Align
+	orr	r0, r0, #0x00000800	@ set bit 11 (Z---) BTB
+	orr	r0, r0, #0x00001000	@ set bit 12 (I) I-cache
+	mcr	p15, 0, r0, c1, c0, 0
+	mov	pc, lr			@ back to my caller
+ENDPROC(cpu_init_cp15)
+
+/*************************************************************************
+ *
+ * CPU_init_critical registers
+ *
+ * setup important registers
+ * setup memory timing
+ *
+ *************************************************************************/
+ENTRY(cpu_init_crit)
+	/*
+	 * Jump to board specific initialization...
+	 * The Mask ROM will have already initialized
+	 * basic memory. Go here to bump up clock rate and handle
+	 * wake up conditions.
+	 */
+	push	{lr}
+	bl	lowlevel_init		@ go setup pll,mux,memory
+	pop	{pc}
+ENDPROC(cpu_init_crit)
diff --git a/arch/arm/cpu/armv7/spear13xx/u-boot-spl.lds b/arch/arm/cpu/armv7/spear13xx/u-boot-spl.lds
new file mode 100644
index 0000000..dfc2d47
--- /dev/null
+++ b/arch/arm/cpu/armv7/spear13xx/u-boot-spl.lds
@@ -0,0 +1,45 @@ 
+/*
+ * (C) Copyright 2012
+ * Vipin Kumar, ST Microelectronics, <vipin.kumar@st.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+
+MEMORY
+{
+	xloader : ORIGIN = 0xB3801504 , LENGTH = 0x2AFC
+	xloader_bss : ORIGIN = 0xB3804000 , LENGTH = 0x1000
+}
+
+SECTIONS
+{
+	.text :
+	{
+		arch/arm/cpu/armv7/spear13xx/start.o	(.text)
+		*(.text); . = ALIGN(4);
+	} > xloader
+
+	.rodata : { *(.rodata*); . = ALIGN(4); } > xloader
+	.data : { *(.data*); . = ALIGN(4); } > xloader
+	.bss : { __bss_start = .; *(.bss*); . = ALIGN(4); __bss_end = .;} > xloader_bss
+}
diff --git a/arch/arm/cpu/armv7/spear13xx/wakeup.S b/arch/arm/cpu/armv7/spear13xx/wakeup.S
new file mode 100644
index 0000000..82a5cac
--- /dev/null
+++ b/arch/arm/cpu/armv7/spear13xx/wakeup.S
@@ -0,0 +1,60 @@ 
+/*
+ * (C) Copyright 2012
+ * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+
+.syntax	unified
+
+.global cleanup_before_linux
+.global cpu2_wake
+cpu2_wake:
+	push	{r0 - r1}
+	ldr	r0,=CONFIG_SPEAR13XX_ARM2PHOLD
+	adr	r1,cpu2_jump
+	str	r1,[r0]
+	dmb
+	dsb
+	sev
+	pop	{r0 - r1}
+	bx	r14
+
+/* CPU2 starts running from here */
+cpu2_jump:
+	/* stack init, needed for calling C routine */
+	ldr	r13,=CONFIG_SPEAR13XX_ARM2STACK
+
+	bl	cleanup_before_linux
+
+	ldr	r0,=CONFIG_SPEAR13XX_ARM2PHOLD
+	ldr	r1,=0xdeadbeef
+	str	r1,[r0]
+	dmb
+	dsb
+1:
+	wfe
+	ldr	r2,=0xdeadbeef
+	ldr	r1,[r0]
+	cmp	r1,r2
+	beq	1b
+
+	blx	r1
diff --git a/arch/arm/include/asm/arch-spear13xx/boot.h b/arch/arm/include/asm/arch-spear13xx/boot.h
new file mode 100644
index 0000000..391333a
--- /dev/null
+++ b/arch/arm/include/asm/arch-spear13xx/boot.h
@@ -0,0 +1,106 @@ 
+/*
+ * (C) Copyright 2012
+ * Vipin Kumar, ST Microelectronics, vipin.kumar@st.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __ASM_ARCH_BOOT_H
+#define __ASM_ARCH_BOOT_H
+
+#include <linux/compiler.h>
+
+/* This file defines the BootROM <-> Xloader interface for spear13xx devices */
+
+/*****************************************************************************
+ * SPEAr1310 as well as SPEAr1340 device support the same table version ie 2.1
+ *****************************************************************************/
+
+/*
+ * BootROM provides a table as an interface for its routines to be used in
+ * xloader. This file needs to be compatible with all the supported spear13xx
+ * bootrom table interfaces.
+ *
+ * All the following definitions are for using already existing BootROM routines
+ */
+
+struct soc_type_s {
+	u8	soc;
+	u8	revision;
+};
+
+struct table_2_1 {
+	struct soc_type_s *	(*get_soc_type)(void);
+	u8			(*get_boot_type)(void);
+
+	void *			nand_info;
+	int			(*nand_read)(void *nand, size_t offset,
+					size_t *length, u_char *buffer);
+	u8 *			(*get_version)(void);
+
+	int			(*get_otpbits)(u32 bit_off, u32 bit_cnt,
+					u32 *buffer);
+
+	u32			(*hamming_encode)(u32 parity, void *data,
+					unsigned int d, unsigned int nr);
+	void			(*hamming_fix)(void *data, unsigned int d,
+					unsigned int nr, unsigned int fix);
+};
+
+union table_u {
+	struct table_2_1	table_2_1;
+};
+
+struct table_s {
+	u32			table_version;
+#define TABLE_VERSION_2_1  3
+
+	union table_u		table_u;
+} __packed;
+
+/* These routines are encapsulated based on the table version */
+/*
+ * getboottype routine returns one of these independent of the spear platform
+ */
+#define BOOT_TYPE_BYPASS	1
+#define BOOT_TYPE_SMI		2
+#define BOOT_TYPE_NAND		3
+#define BOOT_TYPE_RESERVED	4
+#define BOOT_TYPE_I2C		5
+#define BOOT_TYPE_SPI		6
+#define BOOT_TYPE_USBD		7
+#define BOOT_TYPE_TFTP		8
+#define BOOT_TYPE_PCIE		9
+#define BOOT_TYPE_UART		10
+#define BOOT_TYPE_MMC		11
+#define BOOT_TYPE_PNOR8		12
+#define BOOT_TYPE_PNOR16	13
+#define BOOT_TYPE_PNOR32	14
+#define BOOT_TYPE_UNSUPPORTED	0xff
+
+static inline u8 get_boot_type(void)
+{
+	struct table_s *table = (struct table_s *)0xFFFF7F00;
+
+	if (table->table_version == TABLE_VERSION_2_1)
+		return (*table->table_u.table_2_1.get_boot_type)();
+
+	return BOOT_TYPE_UNSUPPORTED;
+}
+#endif
diff --git a/arch/arm/include/asm/arch-spear13xx/generic.h b/arch/arm/include/asm/arch-spear13xx/generic.h
index 7beb1c2..eb066d4 100644
--- a/arch/arm/include/asm/arch-spear13xx/generic.h
+++ b/arch/arm/include/asm/arch-spear13xx/generic.h
@@ -30,4 +30,12 @@  extern void spear1310_usbh_stop(void);
 extern void spear1340_usbh_stop(void);
 #endif
 
+#if defined(CONFIG_SPL_BUILD)
+extern void cpu2_wake(void);
+extern void soc_init(void);
+extern void board_pre_ddrinit(void);
+extern void ddr_init(void);
+extern void board_post_ddrinit(void);
+#endif
+
 #endif
diff --git a/arch/arm/include/asm/arch-spear13xx/mpmc.h b/arch/arm/include/asm/arch-spear13xx/mpmc.h
new file mode 100644
index 0000000..24aef91
--- /dev/null
+++ b/arch/arm/include/asm/arch-spear13xx/mpmc.h
@@ -0,0 +1,332 @@ 
+/*
+ * (C) Copyright 2012
+ * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef SPR13XX_MPMC_H
+#define SPR13XX_MPMC_H
+
+struct mpmc_regs {
+	u32 reg0;
+	u32 reg1;
+	u32 reg2;
+	u32 reg3;
+	u32 reg4;
+	u32 reg5;
+	u32 reg6;
+	u32 reg7;
+	u32 reg8;
+	u32 reg9;
+	u32 reg10;
+	u32 reg11;
+	u32 reg12;
+	u32 reg13;
+	u32 reg14;
+	u32 reg15;
+	u32 reg16;
+	u32 reg17;
+	u32 reg18;
+	u32 reg19;
+	u32 reg20;
+	u32 reg21;
+	u32 reg22;
+	u32 reg23;
+	u32 reg24;
+	u32 reg25;
+	u32 reg26;
+	u32 reg27;
+	u32 reg28;
+	u32 reg29;
+	u32 reg30;
+	u32 reg31;
+	u32 reg32;
+	u32 reg33;
+	u32 reg34;
+	u32 reg35;
+	u32 reg36;
+	u32 reg37;
+	u32 reg38;
+	u32 reg39;
+	u32 reg40;
+	u32 reg41;
+	u32 reg42;
+	u32 reg43;
+	u32 reg44;
+	u32 reg45;
+	u32 reg46;
+	u32 reg47;
+	u32 reg48;
+	u32 reg49;
+	u32 reg50;
+	u32 reg51;
+	u32 reg52;
+	u32 reg53;
+	u32 reg54;
+	u32 reg55;
+	u32 reg56;
+	u32 reg57;
+	u32 reg58;
+	u32 reg59;
+	u32 reg60;
+	u32 reg61;
+	u32 reg62;
+	u32 reg63;
+	u32 reg64;
+	u32 reg65;
+	u32 reg66;
+	u32 reg67;
+	u32 reg68;
+	u32 reg69;
+	u32 reg70;
+	u32 reg71;
+	u32 reg72;
+	u32 reg73;
+	u32 reg74;
+	u32 reg75;
+	u32 reg76;
+	u32 reg77;
+	u32 reg78;
+	u32 reg79;
+	u32 reg80;
+	u32 reg81;
+	u32 reg82;
+	u32 reg83;
+	u32 reg84;
+	u32 reg85;
+	u32 reg86;
+	u32 reg87;
+	u32 reg88;
+	u32 reg89;
+	u32 reg90;
+	u32 reg91;
+	u32 reg92;
+	u32 reg93;
+	u32 reg94;
+	u32 reg95;
+	u32 reg96;
+	u32 reg97;
+	u32 reg98;
+	u32 reg99;
+	u32 reg100;
+	u32 reg101;
+	u32 reg102;
+	u32 reg103;
+	u32 reg104;
+	u32 reg105;
+	u32 reg106;
+	u32 reg107;
+	u32 reg108;
+	u32 reg109;
+	u32 reg110;
+	u32 reg111;
+	u32 reg112;
+	u32 reg113;
+	u32 reg114;
+	u32 reg115;
+	u32 reg116;
+	u32 reg117;
+	u32 reg118;
+	u32 reg119;
+	u32 reg120;
+	u32 reg121;
+	u32 reg122;
+	u32 reg123;
+	u32 reg124;
+	u32 reg125;
+	u32 reg126;
+	u32 reg127;
+	u32 reg128;
+	u32 reg129;
+	u32 reg130;
+	u32 reg131;
+	u32 reg132;
+	u32 reg133;
+	u32 reg134;
+	u32 reg135;
+	u32 reg136;
+	u32 reg137;
+	u32 reg138;
+	u32 reg139;
+	u32 reg140;
+	u32 reg141;
+	u32 reg142;
+	u32 reg143;
+	u32 reg144;
+	u32 reg145;
+	u32 reg146;
+	u32 reg147;
+	u32 reg148;
+	u32 reg149;
+	u32 reg150;
+	u32 reg151;
+	u32 reg152;
+	u32 reg153;
+	u32 reg154;
+	u32 reg155;
+	u32 reg156;
+	u32 reg157;
+	u32 reg158;
+	u32 reg159;
+	u32 reg160;
+	u32 reg161;
+	u32 reg162;
+	u32 reg163;
+	u32 reg164;
+	u32 reg165;
+	u32 reg166;
+	u32 reg167;
+	u32 reg168;
+	u32 reg169;
+	u32 reg170;
+	u32 reg171;
+	u32 reg172;
+	u32 reg173;
+	u32 reg174;
+	u32 reg175;
+	u32 reg176;
+	u32 reg177;
+	u32 reg178;
+	u32 reg179;
+	u32 reg180;
+	u32 reg181;
+	u32 reg182;
+	u32 reg183;
+	u32 reg184;
+	u32 reg185;
+	u32 reg186;
+	u32 reg187;
+	u32 reg188;
+	u32 reg189;
+	u32 reg190;
+	u32 reg191;
+	u32 reg192;
+	u32 reg193;
+	u32 reg194;
+	u32 reg195;
+	u32 reg196;
+	u32 reg197;
+	u32 reg198;
+	u32 reg199;
+	u32 reg200;
+	u32 reg201;
+	u32 reg202;
+	u32 reg203;
+	u32 reg204;
+	u32 reg205;
+	u32 reg206;
+	u32 reg207;
+	u32 reg208;
+	u32 reg209;
+};
+
+#define PHY_CTRL_DELAY			200
+
+#ifdef CONFIG_DDR_ECC_ENABLE
+#define DATA_SLICE_MAX			5
+#else
+#define DATA_SLICE_MAX			4
+#endif
+
+#define WRLVL_DELAY_MAX			8
+#define RDLVL_DELAY_VALS		8
+#define RDLVL_DELAY_INIT		4
+
+#define MPMC_REG18_ECC_MASK		(3 << 8)
+#define MPMC_REG18_NO_ECC		(0 << 8)
+#define MPMC_REG18_ECC_REPORT_ON	(1 << 8)
+#define MPMC_REG18_ECC_CORR_ON		(3 << 8)
+
+/* DDR2 settings*/
+#define WRLVL_BASE_OFFSET_REG_VALUE	0
+
+#define WRLVL_DELAY_VALUE_0	2
+#define WRLVL_DELAY_VALUE_1	2
+#define WRLVL_DELAY_VALUE_2	2
+#define WRLVL_DELAY_VALUE_3	2
+#define WRLVL_DELAY_VALUE_4	2
+
+#define RDLVL_GATE_DELAY_VALUE_0	31
+#define RDLVL_GATE_DELAY_VALUE_1	26
+#define RDLVL_GATE_DELAY_VALUE_2	26
+#define RDLVL_GATE_DELAY_VALUE_3	31
+#define RDLVL_GATE_DELAY_VALUE_4	31
+
+#define RDLVL_DELAY_VALUE_0	8
+#define RDLVL_DELAY_VALUE_1	8
+#define RDLVL_DELAY_VALUE_2	8
+#define RDLVL_DELAY_VALUE_3	8
+#define RDLVL_DELAY_VALUE_4	8
+
+/* mpmc register definitions */
+#define SWLVL_MODE_MSK			(3 << 8)
+#define NO_LVL				(0 << 8)
+#define WRITE_LVL			(1 << 8)
+#define READ_LVL			(2 << 8)
+#define GATE_LVL			(3 << 8)
+#define SWLVL_START			(1 << 8)
+#define SWLVL_LOAD			(1 << 24)
+#define SWLVL_EXIT			(1 << 16)
+#define SWLVL_OP_DONE			(1 << 0)
+#define WRLVL_REG_EN			(1 << 8)
+#define RDLVL_GATE_REG_EN		(1 << 0)
+#define RDLVL_REG_EN			(1 << 24)
+
+#define TDFI_RDLVL_RR			(0x10 << 16)
+#define TDFI_RDLVL_RR_MSK		(0x3FF << 16)
+#define DQSGATE_ASSERT_MSK		(0x1F << 0)
+#define DQSGATE_DEASSERT_MSK		(0x1F << 5)
+#define DQSOE_ASSERT_MSK		(0x1F << 10)
+#define DQSOE_DEASSERT_MSK		(0x1F << 15)
+#define REG1_ASSERT_MSK			(0x1F << 20)
+#define REG1_DEASSERT_MSK		(0x1F << 25)
+#define REG5_ASSERT_MSK			(0x1F << 0)
+#define REG5_DEASSERT_MSK		(0x1F << 5)
+#define REG6_DQS_ASSERT_MSK		(0x1F << 10)
+#define REG6_DQS_DEASSERT_MSK		(0x1F << 15)
+#define REG7_ASSERT_MSK			(0x1F << 18)
+#define REG7_DEASSERT_MSK		(0x1F << 23)
+
+/* externs */
+extern void writel_field(u32, u32, u32 *);
+extern u32 readl_field(u32, u32, u32 *);
+extern void swlvl_load(void);
+extern void wait_op_done(void);
+extern u32 read_resp(u32);
+extern void set_swlvl_mode(u32);
+extern void swlvl_start(void);
+extern void swlvl_exit(void);
+
+extern void spear13xx_mpmc_init(u32 *, u32);
+extern void spear13xx_ddr_level(void);
+
+extern u32 mpmc_conf_vals[];
+
+#if defined(CONFIG_DDR3)
+extern void ddr3_lvl_write(void);
+extern void ddr3_lvl_gatetrn(void);
+extern void ddr3_lvl_read(void);
+#elif defined(CONFIG_DDR2)
+extern void ddr2_lvl_write(void);
+extern void ddr2_lvl_gatetrn(void);
+extern void ddr2_lvl_read(void);
+#endif
+
+#endif
diff --git a/arch/arm/include/asm/arch-spear13xx/spear1340_misc.h b/arch/arm/include/asm/arch-spear13xx/spear1340_misc.h
index 090de1c..1e9c04c 100644
--- a/arch/arm/include/asm/arch-spear13xx/spear1340_misc.h
+++ b/arch/arm/include/asm/arch-spear13xx/spear1340_misc.h
@@ -235,28 +235,11 @@  struct spear1340_misc_regs {
 	u32 misc_cfg;				/* 0x1008 */
 };
 
-/* PHERIP1_CLOCK ENABLE */
-#define SPEAR1340_C3_CLKEN		0x20000000
-#define SPEAR1340_GPT1_CLKEN		0x00200000
-#define SPEAR1340_I2C_CLKEN		0x00040000
-#define SPEAR1340_SSP_CLKEN		0x00020000
-#define SPEAR1340_UART_CLKEN		0x00008000
-#define SPEAR1340_UDC_UPD_CLKEN		0x00000800
-#define SPEAR1340_UHC1_CLKEN		0x00000200
-#define SPEAR1340_GETH_CLKEN		0x00000100
-#define SPEAR1340_SD_CLKEN		0x00000040
-#define SPEAR1340_SMI_CLKEN		0x00000020
-#define SPEAR1340_FSMC_CLKEN		0x00000010
-
-/* perip1_sw_rst */
-#define SPEAR1340_C3_SWRST		0x20000000
-#define SPEAR1340_UDC_UPD_SWRST		0x00000800
-#define SPEAR1340_UHC1_SWRST		0x00000200
-
+/* sys_clk_ctrl definitions */
 #define SPEAR1340_SYS_MODE_MASK		0x00000007
-#define SPEAR1340_SYS_MODE_DOZE		0x00000001
-#define SPEAR1340_SYS_MODE_SLOW		0x00000002
-#define SPEAR1340_SYS_MODE_NORMAL	0x00000004
+#define SPEAR1340_SYS_MODE_REQ_DOZE	0x00000001
+#define SPEAR1340_SYS_MODE_REQ_SLOW	0x00000002
+#define SPEAR1340_SYS_MODE_REQ_NORMAL	0x00000004
 #define SPEAR1340_PLL_TIMEOUT_ENB	0x00000008
 #define SPEAR1340_XTAL_TIMEOUT_ENB	0x00000010
 #define SPEAR1340_SYS_STATE_MASK	0x000F0000
@@ -268,14 +251,17 @@  struct spear1340_misc_regs {
 
 /* pll_freq definitions in MHz */
 #define SPEAR1340_FREQ_1000		0x7D000006
-#define SPEAR1340_FREQ_996		0x53000004
+#define SPEAR1340_FREQ_533		0x6F000105
+#define SPEAR1340_FREQ_400		0x64000106
 #define SPEAR1340_FREQ_332		0x53000203
+#define SPEAR1340_FREQ_125		0x7D000306
 
 /* pll_ctr definitions */
 #define SPEAR1340_PLLLOCK		0x00000001
 #define SPEAR1340_PLLENABLE		0x00000004
 
 /* perip_clk_cfg definitions */
+#define SPEAR1340_MPMCCLKPLL4		0x00000400
 #define SPEAR1340_GPTCLKSRC		0x00000100
 #define SPEAR1340_UARTCLKMSK		0x00000030
 #define SPEAR1340_UART48M		0x00000000
@@ -294,10 +280,13 @@  struct spear1340_misc_regs {
 
 /* usbphy_gen_cfg definitions */
 #define SPEAR1340_USB_PLL_LOCK		0x01000000
-#define SPEAR1340_USBPHY_RST		0x00008000
-#define SPEAR1340_USBPHY_PRSNT		0x00002000
+#define SPEAR1340_UTMI_XFER_RST2	0x00010000
+#define SPEAR1340_UTMI_XFER_RST1	0x00008000
+#define SPEAR1340_UTMI_XFER_RST0	0x00004000
+#define SPEAR1340_USBPHY_RST		0x00002000
 #define SPEAR1340_USBPHY_POR		0x00001000
-#define SPEAR1340_COMMON_PWDN		0x00000000
+#define SPEAR1340_AUTOPPD_ON_OVRCURR	0x00000020
+#define SPEAR1340_COMMON_PWDN		0x00000001
 
 /* perip_cfg definitions */
 #define SPEAR1340_HS_SSP_EN		0x00200000
@@ -328,4 +317,41 @@  struct spear1340_misc_regs {
 #define SPEAR1340_SYNT_Y_5		0x00000005
 #define SPEAR1340_SYNT_Y_21		0x00000015
 
+/* PHERIP1_CLOCK ENABLE */
+#define SPEAR1340_C3_CLKEN		0x20000000
+#define SPEAR1340_GPT1_CLKEN		0x00200000
+#define SPEAR1340_I2C_CLKEN		0x00040000
+#define SPEAR1340_SSP_CLKEN		0x00020000
+#define SPEAR1340_UART_CLKEN		0x00008000
+#define SPEAR1340_UDC_UPD_CLKEN		0x00000800
+#define SPEAR1340_UHC1_CLKEN		0x00000200
+#define SPEAR1340_GETH_CLKEN		0x00000100
+#define SPEAR1340_SD_CLKEN		0x00000040
+#define SPEAR1340_SMI_CLKEN		0x00000020
+#define SPEAR1340_FSMC_CLKEN		0x00000010
+#define SPEAR1340_DDRCORE_CLKEN		0x00000002
+#define SPEAR1340_DDRCTRL_CLKEN		0x00000001
+
+/* perip1_sw_rst */
+#define SPEAR1340_C3_SWRST		0x20000000
+#define SPEAR1340_UDC_UPD_SWRST		0x00000800
+#define SPEAR1340_UHC1_SWRST		0x00000200
+#define SPEAR1340_DDRCORE_RST		0x00000002
+#define SPEAR1340_DDRCTRL_RST		0x00000001
+#define SPEAR1340_PERIPH1_RST_ALL	0x00000000
+#define SPEAR1340_PERIPH2_RST_ALL	0x00000000
+#define SPEAR1340_PERIPH3_RST_ALL	0x00000000
+
+/* ddr_pad_cfg definitions */
+#define SPEAR1340_PAD_VREF		0x00000200
+#define SPEAR1340_DATA_PROGB		0x00000100
+#define SPEAR1340_DATA_PROGA		0x00000080
+#define SPEAR1340_CLK_PROGB		0x00000040
+#define SPEAR1340_CLK_PROGA		0x00000020
+#define SPEAR1340_CTRL_PROGB		0x00000010
+#define SPEAR1340_CTRL_PROGA		0x00000008
+#define SPEAR1340_DDR3_PAD_SW_SEL	0x00000004
+#define SPEAR1340_DDR3_PAD_SEL		0x00000002
+#define SPEAR1340_DDR3_SW_SEL		0x00000001
+
 #endif
diff --git a/arch/arm/include/asm/arch-spear13xx/spear13xx.h b/arch/arm/include/asm/arch-spear13xx/spear13xx.h
index a4fca51..916175b 100644
--- a/arch/arm/include/asm/arch-spear13xx/spear13xx.h
+++ b/arch/arm/include/asm/arch-spear13xx/spear13xx.h
@@ -26,6 +26,10 @@ 
 
 #define CONFIG_SPEAR_CORTEXBASE		0xEC800000
 #define CONFIG_ARMV7_LTIMER_BASE	(CONFIG_SPEAR_CORTEXBASE + 0x600)
+#define CONFIG_SYS_L2CACHE_BASE		0xED000000
+
+#define CONFIG_SYS_MPMC_BASE		0xEC000000
+#define CONFIG_SPEAR_MPMCREGS		208
 
 #define CONFIG_SYS_C3_BASE		0xE1800000
 #define CONFIG_SYS_USBD_BASE		0xE3800000
diff --git a/board/st/spear13xx/Makefile b/board/st/spear13xx/Makefile
index a662ac4..ca87ee9 100644
--- a/board/st/spear13xx/Makefile
+++ b/board/st/spear13xx/Makefile
@@ -28,10 +28,15 @@  LIB	= $(obj)lib$(BOARD).o
 SOBJS-y	:=
 COBJS-y	:=
 
+ifdef CONFIG_SPL_BUILD
+COBJS-$(CONFIG_MACH_SPEAR1310EVB) += spl-spear1310evb.o
+COBJS-$(CONFIG_MACH_SPEAR1340EVB) += spl-spear1340evb.o
+else
 COBJS-y	+= spear13xx_common.o
 COBJS-$(CONFIG_MACH_SPEAR1310EVB) += spear1310evb.o
 COBJS-$(CONFIG_MACH_SPEAR1340EVB) += spear1340evb.o
 COBJS-$(CONFIG_MACH_SPEAR1340LCAD) += spear1340lcad.o
+endif
 
 COBJS	:= $(sort $(COBJS-y))
 SOBJS	:= $(sort $(SOBJS-y))
diff --git a/board/st/spear13xx/config.mk b/board/st/spear13xx/config.mk
index 9d5de65..a8f67d4 100644
--- a/board/st/spear13xx/config.mk
+++ b/board/st/spear13xx/config.mk
@@ -23,4 +23,8 @@ 
 
 ifndef CONFIG_SPL_BUILD
 ALL-y += $(obj)u-boot.img
+
+ifdef CONFIG_MACH_SPEAR1340EVB
+ALL-y += $(obj)spl/u-boot-spl.img
+endif
 endif
diff --git a/board/st/spear13xx/ddr/Makefile b/board/st/spear13xx/ddr/Makefile
new file mode 100644
index 0000000..0f5ee7b
--- /dev/null
+++ b/board/st/spear13xx/ddr/Makefile
@@ -0,0 +1,64 @@ 
+#
+# (C) Copyright 2012
+# Vipin Kumar, ST Microelectronics, vipin.kumar@st.com
+#
+# (C) Copyright 2000-2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD)ddr.o
+
+SOBJS-y	:=
+COBJS-y	:=
+
+ifdef CONFIG_SPL_BUILD
+COBJS-$(CONFIG_DDR_H5TQ2G63BFRPBC) += h5tq2g63bfr_pbc_400_cl6.o
+COBJS-$(CONFIG_DDR_H5TQ2G63BFRPBC) += h5tq2g63bfr_pbc_533_cl8.o
+COBJS-$(CONFIG_DDR_K4B2G1646CK0) += k4b2g1646c_k0_400_cl6.o
+COBJS-$(CONFIG_DDR_K4B2G1646CK0) += k4b2g1646c_k0_533_cl8.o
+COBJS-$(CONFIG_DDR_MT41J128M16) += mt41j128m16_15e_400_cl6_dqs_dq_term_en.o
+COBJS-$(CONFIG_DDR_MT41J256M8) += mt41j256m8187e_400_cl6_dqs_dq_term_en.o
+COBJS-$(CONFIG_DDR_MT41J256M8) += mt41j256m8187e_533_cl7_dqs_dq_term_en.o
+COBJS-$(CONFIG_DDR_MT41J64M16) += mt41j64m16_15e_400_cl6_dqs_dq_term_en.o
+COBJS-$(CONFIG_DDR_MT41J64M16) += mt41j64m16_15e_533_cl7_dqs_dq_term_en.o
+COBJS-$(CONFIG_DDR_MT47H128M16) += mt47h128m16rt187e_400_cl6_ddr2.o
+COBJS-$(CONFIG_DDR_MT47H128M16) += mt47h128m16rt187e_533_cl7_ddr2.o
+endif
+
+COBJS	:= $(sort $(COBJS-y))
+SOBJS	:= $(sort $(SOBJS-y))
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/st/spear13xx/ddr/h5tq2g63bfr_pbc_400_cl6.c b/board/st/spear13xx/ddr/h5tq2g63bfr_pbc_400_cl6.c
new file mode 100644
index 0000000..fa9f322
--- /dev/null
+++ b/board/st/spear13xx/ddr/h5tq2g63bfr_pbc_400_cl6.c
@@ -0,0 +1,238 @@ 
+/*
+ * (C) Copyright 2000-2009
+ * Vikas Manocha, ST Microelectronics, vikas.manocha@st.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/hardware.h>
+
+#if defined(CONFIG_SPEAR_DDRFREQ400)
+const u32 mpmc_conf_vals[CONFIG_SPEAR_MPMCREGS] = {
+	0x00000100, /* MPMC_REG_00 0x00000100 */
+	0x00010100, /* MPMC_REG_01 0x00000100 */
+	0x01000000, /* MPMC_REG_02 0x01000000 */
+	0x00010100, /* MPMC_REG_03 0x00000100 */
+	0x00000000, /* MPMC_REG_04 0x00000000 */
+	0x00010100, /* MPMC_REG_05 0x00010101 */
+	0x00000001, /* MPMC_REG_06 0x00000001 */
+	0x00000000, /* MPMC_REG_07 0x00000000 */
+	0x00000000, /* MPMC_REG_08 0x00000000 */
+	0x00000000, /* MPMC_REG_09 0x00000000 */
+	0x00000000, /* MPMC_REG_10 0x00000000 */
+	0x00000101, /* MPMC_REG_11 0x00000101 */
+	0x00000101, /* MPMC_REG_12 0x00000101 */
+	0x01010000, /* MPMC_REG_13 0x01010000 */
+	0x00000000, /* MPMC_REG_14 0x00000000 */
+	0x01000000, /* MPMC_REG_15 0x01000000 */
+	0x00000000, /* MPMC_REG_16 0x00000000 */
+	0x00000000, /* MPMC_REG_17 0x00000000 */
+	0x00000201, /* MPMC_REG_18 0x00000201 */
+	0x02010102, /* MPMC_REG_19 0x02010102 */
+	0x00020000, /* MPMC_REG_20 0x00020000 */
+	0x03030001, /* MPMC_REG_21 0x07070000 */
+	0x02030301, /* MPMC_REG_22 0x00070700 */
+	0x03030303, /* MPMC_REG_23 0x07000707 */
+	0x03030403, /* MPMC_REG_24 0x00000007 */
+	0x03030305, /* MPMC_REG_25 0x03070700 */
+	0x00000400, /* MPMC_REG_26 0x00000400 */
+	0x02000100, /* MPMC_REG_27 0x02000100 */
+	0x04020402, /* MPMC_REG_28 0x04030402 */
+	0x01000104, /* MPMC_REG_29 0x01000104 */
+	0x04000000, /* MPMC_REG_30 0x04000000 */
+	0x0606060a, /* MPMC_REG_31 0x0606060a */
+	0x06060606, /* MPMC_REG_32 0x06060606 */
+	0x05050506, /* MPMC_REG_33 0x05050506 */
+	0x05050505, /* MPMC_REG_34 0x05050505 */
+	0x04040405, /* MPMC_REG_35 0x04040405 */
+	0x04040404, /* MPMC_REG_36 0x04040404 */
+	0x03030304, /* MPMC_REG_37 0x03030304 */
+	0x03030303, /* MPMC_REG_38 0x03030303 */
+	0x02020203, /* MPMC_REG_39 0x02020203 */
+	0x02020202, /* MPMC_REG_40 0x02020202 */
+	0x01010102, /* MPMC_REG_41 0x01010102 */
+	0x01010101, /* MPMC_REG_42 0x01010101 */
+	0x06000c01, /* MPMC_REG_43 0x06000c01 */
+	0x00000000, /* MPMC_REG_44 0x00000000 */
+	0x00000204, /* MPMC_REG_45 0x00000204 */
+	0x04070600, /* MPMC_REG_46 0x04070602 */
+	0x02000505, /* MPMC_REG_47 0x02000505 */
+	0x0000000c, /* MPMC_REG_48 0x0000000c */
+	0x0c040406, /* MPMC_REG_49 0x0c040406 */
+	0x0600000c, /* MPMC_REG_50 0x0602000c */
+	0x3f003f06, /* MPMC_REG_51 0x3f003f06 */
+	0x19141200, /* MPMC_REG_52 0x19150f00 */
+	0x00000028, /* MPMC_REG_53 0x00000028 */
+	0x00000000, /* MPMC_REG_54 0x00000000 */
+	0x00000000, /* MPMC_REG_55 0x00000000 */
+	0x00000000, /* MPMC_REG_56 0x00000000 */
+	0x00004000, /* MPMC_REG_57 0x00004000 */
+	0x03000000, /* MPMC_REG_58 0x03000000 */
+	0x03031703, /* MPMC_REG_59 0x03031703 */
+	0x060e0c04, /* MPMC_REG_60 0x060f0c04 */
+	0x00006400, /* MPMC_REG_61 0x00006456 */
+	0x00640064, /* MPMC_REG_62 0x00640064 */
+	0x00640064, /* MPMC_REG_63 0x00640064 */
+	0x000f0064, /* MPMC_REG_64 0x000f0064 */
+	0x0000000a, /* MPMC_REG_65 0x0000000a */
+	0x00400100, /* MPMC_REG_66 0x00400100 */
+	0x0c2d0200, /* MPMC_REG_67 0x0c2d0200 */
+	0x02000c2d, /* MPMC_REG_68 0x02000c2d */
+	0x02000200, /* MPMC_REG_69 0x02000200 */
+	0x0c2d0200, /* MPMC_REG_70 0x0c2d0200 */
+	0x04200420, /* MPMC_REG_71 0x04200420 */
+	0x00440044, /* MPMC_REG_72 0x00440044 */
+	0x00000000, /* MPMC_REG_73 0x00000000 */
+	0x00000000, /* MPMC_REG_74 0x00000000 */
+	0xff005555, /* MPMC_REG_75 0xff005555 */
+	0xaaaa00ff, /* MPMC_REG_76 0xaaaa00ff */
+	0xff005555, /* MPMC_REG_77 0xff005555 */
+	0x00000007, /* MPMC_REG_78 0x00000007 */
+	0x00000000, /* MPMC_REG_79 0x00000000 */
+	0x00000000, /* MPMC_REG_80 0x00000000 */
+	0x00070000, /* MPMC_REG_81 0x00070000 */
+	0x00070007, /* MPMC_REG_82 0x00070007 */
+	0x00070007, /* MPMC_REG_83 0x00070007 */
+	0x00000000, /* MPMC_REG_84 0x00000000 */
+	0x00000000, /* MPMC_REG_85 0x00000000 */
+	0x00030000, /* MPMC_REG_86 0x00030000 */
+	0x00030003, /* MPMC_REG_87 0x00030003 */
+	0x00030003, /* MPMC_REG_88 0x00030003 */
+	0xffff0010, /* MPMC_REG_89 0xffff0010 */
+	0x00000000, /* MPMC_REG_90 0x00000000 */
+	0x00000000, /* MPMC_REG_91 0x00000000 */
+	0x00000000, /* MPMC_REG_92 0x00000000 */
+	0x00000000, /* MPMC_REG_93 0x00000000 */
+	0x00000000, /* MPMC_REG_94 0x00000000 */
+	0x00000000, /* MPMC_REG_95 0x00000000 */
+	0x02000000, /* MPMC_REG_96 0x02000000 */
+	0x00000003, /* MPMC_REG_97 0x6da60003 */
+	0x0044000a, /* MPMC_REG_98 0x0044000a */
+	0x00000200, /* MPMC_REG_99 0x00000200 */
+	0x00000000, /* MPMC_REG_100 0x00000000 */
+	0x00000000, /* MPMC_REG_101 0x00000000 */
+	0x00000000, /* MPMC_REG_102 0x00000000 */
+	0x00000000, /* MPMC_REG_103 0x00000000 */
+	0x00000000, /* MPMC_REG_104 0x00000000 */
+	0x00000000, /* MPMC_REG_105 0x00000000 */
+	0x00000000, /* MPMC_REG_106 0x00000000 */
+	0x00000001, /* MPMC_REG_107 0x00000001 */
+	0x00000001, /* MPMC_REG_108 0x00000001 */
+	0x00000001, /* MPMC_REG_109 0x00000001 */
+	0x00000001, /* MPMC_REG_110 0x00000001 */
+	0x00000001, /* MPMC_REG_111 0x00000001 */
+	0x00000004, /* MPMC_REG_112 0x0000ffff */
+	0x00000000, /* MPMC_REG_113 0x00000000 */
+	0x00030d40, /* MPMC_REG_114 0x00030d40 */
+	0x00000050, /* MPMC_REG_115 0x00000050 */
+	0x00000050, /* MPMC_REG_116 0x00000050 */
+	0x00000050, /* MPMC_REG_117 0x00000050 */
+	0x00000050, /* MPMC_REG_118 0x00000050 */
+	0x00000050, /* MPMC_REG_119 0x00000050 */
+	0x00000050, /* MPMC_REG_120 0x00000050 */
+	0x00000000, /* MPMC_REG_121 0x00000000 */
+	0x00000000, /* MPMC_REG_122 0x00000000 */
+	0x000f1133, /* MPMC_REG_123 0x000f1133 */
+	0x00304000, /* MPMC_REG_124 0x00304000 */
+	0x00304000, /* MPMC_REG_125 0x00304000 */
+	0x00304000, /* MPMC_REG_126 0x00304000 */
+	0x00304000, /* MPMC_REG_127 0x00304000 */
+	0x00304000, /* MPMC_REG_128 0x00304000 */
+	0x00000002, /* MPMC_REG_129 0x00000002 */
+	0x1208a108, /* MPMC_REG_130 0x1208a108 */
+	0x1208a108, /* MPMC_REG_131 0x1208a108 */
+	0x1208a108, /* MPMC_REG_132 0x1208a108 */
+	0x1208a108, /* MPMC_REG_133 0x1208a108 */
+	0x1208a108, /* MPMC_REG_134 0x1208a108 */
+	0x01000000, /* MPMC_REG_135 0x01000000 */
+	0x01000000, /* MPMC_REG_136 0x01000000 */
+	0x01000000, /* MPMC_REG_137 0x01000000 */
+	0x01000000, /* MPMC_REG_138 0x01000000 */
+	0x01000000, /* MPMC_REG_139 0x01000000 */
+	0x01000000, /* MPMC_REG_140 0x01000000 */
+	0x01000000, /* MPMC_REG_141 0x01000000 */
+	0x01000000, /* MPMC_REG_142 0x01000000 */
+	0x01000000, /* MPMC_REG_143 0x01000000 */
+	0x01000000, /* MPMC_REG_144 0x01000000 */
+	0x06db6db6, /* MPMC_REG_145 0x06db6db6 */
+	0x06db6db6, /* MPMC_REG_146 0x06db6db6 */
+	0x06db6db6, /* MPMC_REG_147 0x06db6db6 */
+	0x06db6db6, /* MPMC_REG_148 0x06db6db6 */
+	0x06db6db6, /* MPMC_REG_149 0x06db6db6 */
+	0x00000000, /* MPMC_REG_150 0x00000000 */
+	0x00000000, /* MPMC_REG_151 0x00000000 */
+	0x00000000, /* MPMC_REG_152 0x00000000 */
+	0x00000000, /* MPMC_REG_153 0x00000000 */
+	0x00000000, /* MPMC_REG_154 0x00000000 */
+	0x2498a249, /* MPMC_REG_155 0x2498a249 */
+	0x2498a249, /* MPMC_REG_156 0x2498a249 */
+	0x2498a249, /* MPMC_REG_157 0x2498a249 */
+	0x2498a249, /* MPMC_REG_158 0x2498a249 */
+	0x2498a249, /* MPMC_REG_159 0x2498a249 */
+	0x04803219, /* MPMC_REG_160 0x04803219 */
+	0x04803219, /* MPMC_REG_161 0x04803219 */
+	0x04803219, /* MPMC_REG_162 0x04803219 */
+	0x04803219, /* MPMC_REG_163 0x04803219 */
+	0x04803219, /* MPMC_REG_164 0x04803219 */
+	0x00000000, /* MPMC_REG_165 0x00000000 */
+	0x00000000, /* MPMC_REG_166 0x00000000 */
+	0x00000000, /* MPMC_REG_167 0x00000000 */
+	0x00000000, /* MPMC_REG_168 0x00000000 */
+	0x00000000, /* MPMC_REG_169 0x00000000 */
+	0x00000000, /* MPMC_REG_170 0x00000000 */
+	0x00000000, /* MPMC_REG_171 0x00000000 */
+	0x00000000, /* MPMC_REG_172 0x00000000 */
+	0x00000000, /* MPMC_REG_173 0x00000000 */
+	0x00000000, /* MPMC_REG_174 0x00000000 */
+	0x00000000, /* MPMC_REG_175 0x00000000 */
+	0x00000000, /* MPMC_REG_176 0x00000000 */
+	0x00000000, /* MPMC_REG_177 0x00000000 */
+	0x00000000, /* MPMC_REG_178 0x00000000 */
+	0x00000000, /* MPMC_REG_179 0x00000000 */
+	0x00000000, /* MPMC_REG_180 0x00000000 */
+	0x00000000, /* MPMC_REG_181 0x00000000 */
+	0x00000c2d, /* MPMC_REG_182 0x00000c2d */
+	0x00000c2d, /* MPMC_REG_183 0x00000c2d */
+	0x00000000, /* MPMC_REG_184 0x00000000 */
+	0x00000c2d, /* MPMC_REG_185 0x00000c2d */
+	0x00013880, /* MPMC_REG_186 0x00013880 */
+	0x00000000, /* MPMC_REG_187 0x00000000 */
+	0x00000000, /* MPMC_REG_188 0x00000000 */
+	0x00000000, /* MPMC_REG_189 0x00000000 */
+	0x00000000, /* MPMC_REG_190 0x00000000 */
+	0x00000000, /* MPMC_REG_191 0x00000000 */
+	0x00000000, /* MPMC_REG_192 0x00000000 */
+	0x00000000, /* MPMC_REG_193 0x00000000 */
+	0x00000000, /* MPMC_REG_194 0x00000000 */
+	0x00000000, /* MPMC_REG_195 0x00000000 */
+	0x00000000, /* MPMC_REG_196 0x00000000 */
+	0x00000000, /* MPMC_REG_197 0x00000000 */
+	0x07000000, /* MPMC_REG_198 0x07000000 */
+	0x00000007, /* MPMC_REG_199 0x00000007 */
+	0x00000000, /* MPMC_REG_200 0x00000000 */
+	0x00006db0, /* MPMC_REG_201 0x00006db0 */
+	0x00000040, /* MPMC_REG_202 0x00000040 */
+	0x00000000, /* MPMC_REG_203 0x00000000 */
+	0x00000000, /* MPMC_REG_204 0x00000000 */
+	0x02000000, /* MPMC_REG_205 0x02000000 */
+	0x00000000, /* MPMC_REG_206 0x00000000 */
+	0x00003ce1, /* MPMC_REG_207 0x00003ce1 */
+};
+#endif
diff --git a/board/st/spear13xx/ddr/h5tq2g63bfr_pbc_533_cl8.c b/board/st/spear13xx/ddr/h5tq2g63bfr_pbc_533_cl8.c
new file mode 100644
index 0000000..7e862df
--- /dev/null
+++ b/board/st/spear13xx/ddr/h5tq2g63bfr_pbc_533_cl8.c
@@ -0,0 +1,238 @@ 
+/*
+ * (C) Copyright 2000-2009
+ * Vikas Manocha, ST Microelectronics, vikas.manocha@st.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/hardware.h>
+
+#if defined(CONFIG_SPEAR_DDRFREQ533)
+const u32 mpmc_conf_vals[CONFIG_SPEAR_MPMCREGS] = {
+	0x00000100, /* MPMC_REG_00 0x00000100 */
+	0x00010100, /* MPMC_REG_01 0x00000100 */
+	0x01000000, /* MPMC_REG_02 0x01000000 */
+	0x00010100, /* MPMC_REG_03 0x00000100 */
+	0x00000000, /* MPMC_REG_04 0x00000000 */
+	0x00010100, /* MPMC_REG_05 0x00010101 */
+	0x00000001, /* MPMC_REG_06 0x00000001 */
+	0x00000000, /* MPMC_REG_07 0x00000000 */
+	0x00000000, /* MPMC_REG_08 0x00000000 */
+	0x00000000, /* MPMC_REG_09 0x00000000 */
+	0x00000000, /* MPMC_REG_10 0x00000000 */
+	0x00000101, /* MPMC_REG_11 0x00000101 */
+	0x00000101, /* MPMC_REG_12 0x00000101 */
+	0x01010000, /* MPMC_REG_13 0x01010000 */
+	0x00000000, /* MPMC_REG_14 0x00000000 */
+	0x01000000, /* MPMC_REG_15 0x01000000 */
+	0x00000000, /* MPMC_REG_16 0x00000000 */
+	0x00000000, /* MPMC_REG_17 0x00000000 */
+	0x00000201, /* MPMC_REG_18 0x00000201 */
+	0x02010102, /* MPMC_REG_19 0x02010102 */
+	0x00020000, /* MPMC_REG_20 0x00020000 */
+	0x03030001, /* MPMC_REG_21 0x07070000 */
+	0x02030301, /* MPMC_REG_22 0x00070700 */
+	0x03030303, /* MPMC_REG_23 0x07000707 */
+	0x03030403, /* MPMC_REG_24 0x00000007 */
+	0x03030305, /* MPMC_REG_25 0x03070700 */
+	0x00000400, /* MPMC_REG_26 0x00000400 */
+	0x02000100, /* MPMC_REG_27 0x02000100 */
+	0x04030402, /* MPMC_REG_28 0x04030402 */
+	0x01000104, /* MPMC_REG_29 0x01000104 */
+	0x04000000, /* MPMC_REG_30 0x04000000 */
+	0x0606060a, /* MPMC_REG_31 0x0606060a */
+	0x06060606, /* MPMC_REG_32 0x06060606 */
+	0x05050506, /* MPMC_REG_33 0x05050506 */
+	0x05050505, /* MPMC_REG_34 0x05050505 */
+	0x04040405, /* MPMC_REG_35 0x04040405 */
+	0x04040404, /* MPMC_REG_36 0x04040404 */
+	0x03030304, /* MPMC_REG_37 0x03030304 */
+	0x03030303, /* MPMC_REG_38 0x03030303 */
+	0x02020203, /* MPMC_REG_39 0x02020203 */
+	0x02020202, /* MPMC_REG_40 0x02020202 */
+	0x01010102, /* MPMC_REG_41 0x01010102 */
+	0x01010101, /* MPMC_REG_42 0x01010101 */
+	0x06000c01, /* MPMC_REG_43 0x06000c01 */
+	0x00000000, /* MPMC_REG_44 0x00000000 */
+	0x00000204, /* MPMC_REG_45 0x00000204 */
+	0x04090800, /* MPMC_REG_46 0x04070602 */
+	0x02000606, /* MPMC_REG_47 0x02000505 */
+	0x00000010, /* MPMC_REG_48 0x0000000c */
+	0x10040408, /* MPMC_REG_49 0x0c040406 */
+	0x0800000d, /* MPMC_REG_50 0x0602000c */
+	0x3f003f08, /* MPMC_REG_51 0x3f003f06 */
+	0x191a1800, /* MPMC_REG_52 0x19150f00 */
+	0x00000028, /* MPMC_REG_53 0x00000028 */
+	0x00000000, /* MPMC_REG_54 0x00000000 */
+	0x00000000, /* MPMC_REG_55 0x00000000 */
+	0x00000000, /* MPMC_REG_56 0x00000000 */
+	0x00004000, /* MPMC_REG_57 0x00004000 */
+	0x03000000, /* MPMC_REG_58 0x03000000 */
+	0x03031a03, /* MPMC_REG_59 0x03031703 */
+	0x08130c04, /* MPMC_REG_60 0x060f0c04 */
+	0x00006400, /* MPMC_REG_61 0x00006456 */
+	0x00640064, /* MPMC_REG_62 0x00640064 */
+	0x00640064, /* MPMC_REG_63 0x00640064 */
+	0x000f0064, /* MPMC_REG_64 0x000f0064 */
+	0x0000000a, /* MPMC_REG_65 0x0000000a */
+	0x00400100, /* MPMC_REG_66 0x00400100 */
+	0x102d0200, /* MPMC_REG_67 0x0c280200 */
+	0x0200102d, /* MPMC_REG_68 0x02000c28 */
+	0x02000200, /* MPMC_REG_69 0x02000200 */
+	0x102d0200, /* MPMC_REG_70 0x0c280200 */
+	0x08400840, /* MPMC_REG_71 0x04200420 */
+	0x00440044, /* MPMC_REG_72 0x00440044 */
+	0x00080008, /* MPMC_REG_73 0x00000000 */
+	0x00000000, /* MPMC_REG_74 0x00000000 */
+	0xff005555, /* MPMC_REG_75 0xff005555 */
+	0xaaaa00ff, /* MPMC_REG_76 0xaaaa00ff */
+	0xff005555, /* MPMC_REG_77 0xff005555 */
+	0x00000007, /* MPMC_REG_78 0x00000007 */
+	0x00000000, /* MPMC_REG_79 0x00000000 */
+	0x00000000, /* MPMC_REG_80 0x00000000 */
+	0x00070000, /* MPMC_REG_81 0x00070000 */
+	0x00070007, /* MPMC_REG_82 0x00070007 */
+	0x00070007, /* MPMC_REG_83 0x00070007 */
+	0x00000000, /* MPMC_REG_84 0x00000000 */
+	0x00000000, /* MPMC_REG_85 0x00000000 */
+	0x00030000, /* MPMC_REG_86 0x00030000 */
+	0x00030003, /* MPMC_REG_87 0x00030003 */
+	0x00030003, /* MPMC_REG_88 0x00030003 */
+	0xffff0010, /* MPMC_REG_89 0xffff0010 */
+	0x00000000, /* MPMC_REG_90 0x00000000 */
+	0x00000000, /* MPMC_REG_91 0x00000000 */
+	0x00000000, /* MPMC_REG_92 0x00000000 */
+	0x00000000, /* MPMC_REG_93 0x00000000 */
+	0x00000000, /* MPMC_REG_94 0x00000000 */
+	0x00000000, /* MPMC_REG_95 0x00000000 */
+	0x02000000, /* MPMC_REG_96 0x02000000 */
+	0x00000004, /* MPMC_REG_97 0x6da60003 */
+	0x005b000d, /* MPMC_REG_98 0x0044000a */
+	0x00000200, /* MPMC_REG_99 0x00000200 */
+	0x00000000, /* MPMC_REG_100 0x00000000 */
+	0x00000000, /* MPMC_REG_101 0x00000000 */
+	0x00000000, /* MPMC_REG_102 0x00000000 */
+	0x00000000, /* MPMC_REG_103 0x00000000 */
+	0x00000000, /* MPMC_REG_104 0x00000000 */
+	0x00000000, /* MPMC_REG_105 0x00000000 */
+	0x00000000, /* MPMC_REG_106 0x00000000 */
+	0x00000001, /* MPMC_REG_107 0x00000001 */
+	0x00000001, /* MPMC_REG_108 0x00000001 */
+	0x00000001, /* MPMC_REG_109 0x00000001 */
+	0x00000001, /* MPMC_REG_110 0x00000001 */
+	0x00000001, /* MPMC_REG_111 0x00000001 */
+	0x00000006, /* MPMC_REG_112 0x0000ffff */
+	0x00000000, /* MPMC_REG_113 0x00000000 */
+	0x00040ee6, /* MPMC_REG_114 0x00030d40 */
+	0x00000050, /* MPMC_REG_115 0x00000050 */
+	0x00000050, /* MPMC_REG_116 0x00000050 */
+	0x00000050, /* MPMC_REG_117 0x00000050 */
+	0x00000050, /* MPMC_REG_118 0x00000050 */
+	0x00000050, /* MPMC_REG_119 0x00000050 */
+	0x00000050, /* MPMC_REG_120 0x00000050 */
+	0x00000000, /* MPMC_REG_121 0x00000000 */
+	0x00000000, /* MPMC_REG_122 0x00000000 */
+	0x000f1133, /* MPMC_REG_123 0x000f1133 */
+	0x00404000, /* MPMC_REG_124 0x00304000 */
+	0x00404000, /* MPMC_REG_125 0x00304000 */
+	0x00404000, /* MPMC_REG_126 0x00304000 */
+	0x00404000, /* MPMC_REG_127 0x00304000 */
+	0x00404000, /* MPMC_REG_128 0x00304000 */
+	0x00000002, /* MPMC_REG_129 0x00000002 */
+	0x1208a108, /* MPMC_REG_130 0x1208a108 */
+	0x1208a108, /* MPMC_REG_131 0x1208a108 */
+	0x1208a108, /* MPMC_REG_132 0x1208a108 */
+	0x1208a108, /* MPMC_REG_133 0x1208a108 */
+	0x1208a108, /* MPMC_REG_134 0x1208a108 */
+	0x01000000, /* MPMC_REG_135 0x01000000 */
+	0x01000000, /* MPMC_REG_136 0x01000000 */
+	0x01000000, /* MPMC_REG_137 0x01000000 */
+	0x01000000, /* MPMC_REG_138 0x01000000 */
+	0x01000000, /* MPMC_REG_139 0x01000000 */
+	0x01000000, /* MPMC_REG_140 0x01000000 */
+	0x01000000, /* MPMC_REG_141 0x01000000 */
+	0x01000000, /* MPMC_REG_142 0x01000000 */
+	0x01000000, /* MPMC_REG_143 0x01000000 */
+	0x01000000, /* MPMC_REG_144 0x01000000 */
+	0x06db6db6, /* MPMC_REG_145 0x06db6db6 */
+	0x06db6db6, /* MPMC_REG_146 0x06db6db6 */
+	0x06db6db6, /* MPMC_REG_147 0x06db6db6 */
+	0x06db6db6, /* MPMC_REG_148 0x06db6db6 */
+	0x06db6db6, /* MPMC_REG_149 0x06db6db6 */
+	0x00000000, /* MPMC_REG_150 0x00000000 */
+	0x00000000, /* MPMC_REG_151 0x00000000 */
+	0x00000000, /* MPMC_REG_152 0x00000000 */
+	0x00000000, /* MPMC_REG_153 0x00000000 */
+	0x00000000, /* MPMC_REG_154 0x00000000 */
+	0x2498a249, /* MPMC_REG_155 0x2498a249 */
+	0x2498a249, /* MPMC_REG_156 0x2498a249 */
+	0x2498a249, /* MPMC_REG_157 0x2498a249 */
+	0x2498a249, /* MPMC_REG_158 0x2498a249 */
+	0x2498a249, /* MPMC_REG_159 0x2498a249 */
+	0x04803219, /* MPMC_REG_160 0x04803219 */
+	0x04803219, /* MPMC_REG_161 0x04803219 */
+	0x04803219, /* MPMC_REG_162 0x04803219 */
+	0x04803219, /* MPMC_REG_163 0x04803219 */
+	0x04803219, /* MPMC_REG_164 0x04803219 */
+	0x00000000, /* MPMC_REG_165 0x00000000 */
+	0x00000000, /* MPMC_REG_166 0x00000000 */
+	0x00000000, /* MPMC_REG_167 0x00000000 */
+	0x00000000, /* MPMC_REG_168 0x00000000 */
+	0x00000000, /* MPMC_REG_169 0x00000000 */
+	0x00000000, /* MPMC_REG_170 0x00000000 */
+	0x00000000, /* MPMC_REG_171 0x00000000 */
+	0x00000000, /* MPMC_REG_172 0x00000000 */
+	0x00000000, /* MPMC_REG_173 0x00000000 */
+	0x00000000, /* MPMC_REG_174 0x00000000 */
+	0x00000000, /* MPMC_REG_175 0x00000000 */
+	0x00000000, /* MPMC_REG_176 0x00000000 */
+	0x00000000, /* MPMC_REG_177 0x00000000 */
+	0x00000000, /* MPMC_REG_178 0x00000000 */
+	0x00000000, /* MPMC_REG_179 0x00000000 */
+	0x00000000, /* MPMC_REG_180 0x00000000 */
+	0x00000000, /* MPMC_REG_181 0x00000000 */
+	0x0000102d, /* MPMC_REG_182 0x00000c28 */
+	0x0000102d, /* MPMC_REG_183 0x00000c28 */
+	0x00000000, /* MPMC_REG_184 0x00000000 */
+	0x0000102d, /* MPMC_REG_185 0x00000c28 */
+	0x00019f8f, /* MPMC_REG_186 0x00013880 */
+	0x00000000, /* MPMC_REG_187 0x00000000 */
+	0x00000000, /* MPMC_REG_188 0x00000000 */
+	0x00000000, /* MPMC_REG_189 0x00000000 */
+	0x00000000, /* MPMC_REG_190 0x00000000 */
+	0x00000000, /* MPMC_REG_191 0x00000000 */
+	0x00000000, /* MPMC_REG_192 0x00000000 */
+	0x00000000, /* MPMC_REG_193 0x00000000 */
+	0x00000000, /* MPMC_REG_194 0x00000000 */
+	0x00000000, /* MPMC_REG_195 0x00000000 */
+	0x00000000, /* MPMC_REG_196 0x00000000 */
+	0x00000000, /* MPMC_REG_197 0x00000000 */
+	0x07000000, /* MPMC_REG_198 0x07000000 */
+	0x00000007, /* MPMC_REG_199 0x00000007 */
+	0x00000000, /* MPMC_REG_200 0x00000000 */
+	0x000091dd, /* MPMC_REG_201 0x00006db0 */
+	0x00000056, /* MPMC_REG_202 0x00000040 */
+	0x00000000, /* MPMC_REG_203 0x00000000 */
+	0x00000000, /* MPMC_REG_204 0x00000000 */
+	0x02000000, /* MPMC_REG_205 0x02000000 */
+	0x00000000, /* MPMC_REG_206 0x00000000 */
+	0x000050e1, /* MPMC_REG_207 0x00003cc8 */
+};
+#endif
diff --git a/board/st/spear13xx/ddr/k4b2g1646c_k0_400_cl6.c b/board/st/spear13xx/ddr/k4b2g1646c_k0_400_cl6.c
new file mode 100644
index 0000000..c603906
--- /dev/null
+++ b/board/st/spear13xx/ddr/k4b2g1646c_k0_400_cl6.c
@@ -0,0 +1,238 @@ 
+/*
+ * (C) Copyright 2000-2009
+ * Vikas Manocha, ST Microelectronics, vikas.manocha@st.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/hardware.h>
+
+#if defined(CONFIG_SPEAR_DDRFREQ400)
+const u32 mpmc_conf_vals[CONFIG_SPEAR_MPMCREGS] = {
+	0x00000100, /* MPMC_REG_00 0x00000100 */
+	0x00010100, /* MPMC_REG_01 0x00000100 */
+	0x01000000, /* MPMC_REG_02 0x01000000 */
+	0x00010100, /* MPMC_REG_03 0x00000100 */
+	0x00000000, /* MPMC_REG_04 0x00000000 */
+	0x00010100, /* MPMC_REG_05 0x00010101 */
+	0x00000001, /* MPMC_REG_06 0x00000001 */
+	0x00000000, /* MPMC_REG_07 0x00000000 */
+	0x00000000, /* MPMC_REG_08 0x00000000 */
+	0x00000000, /* MPMC_REG_09 0x00000000 */
+	0x00000000, /* MPMC_REG_10 0x00000000 */
+	0x00000101, /* MPMC_REG_11 0x00000101 */
+	0x00000101, /* MPMC_REG_12 0x00000101 */
+	0x01010000, /* MPMC_REG_13 0x01010000 */
+	0x00000000, /* MPMC_REG_14 0x00000000 */
+	0x01000000, /* MPMC_REG_15 0x01000000 */
+	0x00000000, /* MPMC_REG_16 0x00000000 */
+	0x00000000, /* MPMC_REG_17 0x00000000 */
+	0x00000201, /* MPMC_REG_18 0x00000201 */
+	0x02010102, /* MPMC_REG_19 0x02010102 */
+	0x00020000, /* MPMC_REG_20 0x00020000 */
+	0x03030001, /* MPMC_REG_21 0x07070000 */
+	0x02030301, /* MPMC_REG_22 0x00070700 */
+	0x03030303, /* MPMC_REG_23 0x07000707 */
+	0x03030403, /* MPMC_REG_24 0x00000007 */
+	0x03030305, /* MPMC_REG_25 0x03070700 */
+	0x00000400, /* MPMC_REG_26 0x00000400 */
+	0x02000100, /* MPMC_REG_27 0x02000100 */
+	0x04020402, /* MPMC_REG_28 0x04030402 */
+	0x01000104, /* MPMC_REG_29 0x01000104 */
+	0x04000000, /* MPMC_REG_30 0x04000000 */
+	0x0606060a, /* MPMC_REG_31 0x0606060a */
+	0x06060606, /* MPMC_REG_32 0x06060606 */
+	0x05050506, /* MPMC_REG_33 0x05050506 */
+	0x05050505, /* MPMC_REG_34 0x05050505 */
+	0x04040405, /* MPMC_REG_35 0x04040405 */
+	0x04040404, /* MPMC_REG_36 0x04040404 */
+	0x03030304, /* MPMC_REG_37 0x03030304 */
+	0x03030303, /* MPMC_REG_38 0x03030303 */
+	0x02020203, /* MPMC_REG_39 0x02020203 */
+	0x02020202, /* MPMC_REG_40 0x02020202 */
+	0x01010102, /* MPMC_REG_41 0x01010102 */
+	0x01010101, /* MPMC_REG_42 0x01010101 */
+	0x06000c01, /* MPMC_REG_43 0x06000c01 */
+	0x00000000, /* MPMC_REG_44 0x00000000 */
+	0x00000204, /* MPMC_REG_45 0x00000204 */
+	0x04070600, /* MPMC_REG_46 0x04070602 */
+	0x02000505, /* MPMC_REG_47 0x02000505 */
+	0x0000000c, /* MPMC_REG_48 0x0000000c */
+	0x0c040406, /* MPMC_REG_49 0x0c040406 */
+	0x0600000c, /* MPMC_REG_50 0x0602000c */
+	0x3f003f06, /* MPMC_REG_51 0x3f003f06 */
+	0x19141000, /* MPMC_REG_52 0x19150f00 */
+	0x00000028, /* MPMC_REG_53 0x00000028 */
+	0x00000000, /* MPMC_REG_54 0x00000000 */
+	0x00000000, /* MPMC_REG_55 0x00000000 */
+	0x00000000, /* MPMC_REG_56 0x00000000 */
+	0x00004000, /* MPMC_REG_57 0x00004000 */
+	0x03000000, /* MPMC_REG_58 0x03000000 */
+	0x03031703, /* MPMC_REG_59 0x03031703 */
+	0x060e0c04, /* MPMC_REG_60 0x060f0c04 */
+	0x00006400, /* MPMC_REG_61 0x00006456 */
+	0x00640064, /* MPMC_REG_62 0x00640064 */
+	0x00640064, /* MPMC_REG_63 0x00640064 */
+	0x000f0064, /* MPMC_REG_64 0x000f0064 */
+	0x0000000a, /* MPMC_REG_65 0x0000000a */
+	0x00400100, /* MPMC_REG_66 0x00400100 */
+	0x0c280200, /* MPMC_REG_67 0x0c280200 */
+	0x02000c28, /* MPMC_REG_68 0x02000c28 */
+	0x02000200, /* MPMC_REG_69 0x02000200 */
+	0x0c280200, /* MPMC_REG_70 0x0c280200 */
+	0x04200420, /* MPMC_REG_71 0x04200420 */
+	0x00440044, /* MPMC_REG_72 0x00440044 */
+	0x00000000, /* MPMC_REG_73 0x00000000 */
+	0x00000000, /* MPMC_REG_74 0x00000000 */
+	0xff005555, /* MPMC_REG_75 0xff005555 */
+	0xaaaa00ff, /* MPMC_REG_76 0xaaaa00ff */
+	0xff005555, /* MPMC_REG_77 0xff005555 */
+	0x00000007, /* MPMC_REG_78 0x00000007 */
+	0x00000000, /* MPMC_REG_79 0x00000000 */
+	0x00000000, /* MPMC_REG_80 0x00000000 */
+	0x00070000, /* MPMC_REG_81 0x00070000 */
+	0x00070007, /* MPMC_REG_82 0x00070007 */
+	0x00070007, /* MPMC_REG_83 0x00070007 */
+	0x00000000, /* MPMC_REG_84 0x00000000 */
+	0x00000000, /* MPMC_REG_85 0x00000000 */
+	0x00030000, /* MPMC_REG_86 0x00030000 */
+	0x00030003, /* MPMC_REG_87 0x00030003 */
+	0x00030003, /* MPMC_REG_88 0x00030003 */
+	0xffff0010, /* MPMC_REG_89 0xffff0010 */
+	0x00000000, /* MPMC_REG_90 0x00000000 */
+	0x00000000, /* MPMC_REG_91 0x00000000 */
+	0x00000000, /* MPMC_REG_92 0x00000000 */
+	0x00000000, /* MPMC_REG_93 0x00000000 */
+	0x00000000, /* MPMC_REG_94 0x00000000 */
+	0x00000000, /* MPMC_REG_95 0x00000000 */
+	0x02000000, /* MPMC_REG_96 0x02000000 */
+	0x00000003, /* MPMC_REG_97 0x6da60003 */
+	0x0044000a, /* MPMC_REG_98 0x0044000a */
+	0x00000200, /* MPMC_REG_99 0x00000200 */
+	0x00000000, /* MPMC_REG_100 0x00000000 */
+	0x00000000, /* MPMC_REG_101 0x00000000 */
+	0x00000000, /* MPMC_REG_102 0x00000000 */
+	0x00000000, /* MPMC_REG_103 0x00000000 */
+	0x00000000, /* MPMC_REG_104 0x00000000 */
+	0x00000000, /* MPMC_REG_105 0x00000000 */
+	0x00000000, /* MPMC_REG_106 0x00000000 */
+	0x00000001, /* MPMC_REG_107 0x00000001 */
+	0x00000001, /* MPMC_REG_108 0x00000001 */
+	0x00000001, /* MPMC_REG_109 0x00000001 */
+	0x00000001, /* MPMC_REG_110 0x00000001 */
+	0x00000001, /* MPMC_REG_111 0x00000001 */
+	0x00000004, /* MPMC_REG_112 0x0000ffff */
+	0x00000000, /* MPMC_REG_113 0x00000000 */
+	0x00030d40, /* MPMC_REG_114 0x00030d40 */
+	0x00000050, /* MPMC_REG_115 0x00000050 */
+	0x00000050, /* MPMC_REG_116 0x00000050 */
+	0x00000050, /* MPMC_REG_117 0x00000050 */
+	0x00000050, /* MPMC_REG_118 0x00000050 */
+	0x00000050, /* MPMC_REG_119 0x00000050 */
+	0x00000050, /* MPMC_REG_120 0x00000050 */
+	0x00000000, /* MPMC_REG_121 0x00000000 */
+	0x00000000, /* MPMC_REG_122 0x00000000 */
+	0x000f1133, /* MPMC_REG_123 0x000f1133 */
+	0x00304000, /* MPMC_REG_124 0x00304000 */
+	0x00304000, /* MPMC_REG_125 0x00304000 */
+	0x00304000, /* MPMC_REG_126 0x00304000 */
+	0x00304000, /* MPMC_REG_127 0x00304000 */
+	0x00304000, /* MPMC_REG_128 0x00304000 */
+	0x00000002, /* MPMC_REG_129 0x00000002 */
+	0x1208a108, /* MPMC_REG_130 0x1208a108 */
+	0x1208a108, /* MPMC_REG_131 0x1208a108 */
+	0x1208a108, /* MPMC_REG_132 0x1208a108 */
+	0x1208a108, /* MPMC_REG_133 0x1208a108 */
+	0x1208a108, /* MPMC_REG_134 0x1208a108 */
+	0x01000000, /* MPMC_REG_135 0x01000000 */
+	0x01000000, /* MPMC_REG_136 0x01000000 */
+	0x01000000, /* MPMC_REG_137 0x01000000 */
+	0x01000000, /* MPMC_REG_138 0x01000000 */
+	0x01000000, /* MPMC_REG_139 0x01000000 */
+	0x01000000, /* MPMC_REG_140 0x01000000 */
+	0x01000000, /* MPMC_REG_141 0x01000000 */
+	0x01000000, /* MPMC_REG_142 0x01000000 */
+	0x01000000, /* MPMC_REG_143 0x01000000 */
+	0x01000000, /* MPMC_REG_144 0x01000000 */
+	0x06db6db6, /* MPMC_REG_145 0x06db6db6 */
+	0x06db6db6, /* MPMC_REG_146 0x06db6db6 */
+	0x06db6db6, /* MPMC_REG_147 0x06db6db6 */
+	0x06db6db6, /* MPMC_REG_148 0x06db6db6 */
+	0x06db6db6, /* MPMC_REG_149 0x06db6db6 */
+	0x00000000, /* MPMC_REG_150 0x00000000 */
+	0x00000000, /* MPMC_REG_151 0x00000000 */
+	0x00000000, /* MPMC_REG_152 0x00000000 */
+	0x00000000, /* MPMC_REG_153 0x00000000 */
+	0x00000000, /* MPMC_REG_154 0x00000000 */
+	0x2498a249, /* MPMC_REG_155 0x2498a249 */
+	0x2498a249, /* MPMC_REG_156 0x2498a249 */
+	0x2498a249, /* MPMC_REG_157 0x2498a249 */
+	0x2498a249, /* MPMC_REG_158 0x2498a249 */
+	0x2498a249, /* MPMC_REG_159 0x2498a249 */
+	0x04803219, /* MPMC_REG_160 0x04803219 */
+	0x04803219, /* MPMC_REG_161 0x04803219 */
+	0x04803219, /* MPMC_REG_162 0x04803219 */
+	0x04803219, /* MPMC_REG_163 0x04803219 */
+	0x04803219, /* MPMC_REG_164 0x04803219 */
+	0x00000000, /* MPMC_REG_165 0x00000000 */
+	0x00000000, /* MPMC_REG_166 0x00000000 */
+	0x00000000, /* MPMC_REG_167 0x00000000 */
+	0x00000000, /* MPMC_REG_168 0x00000000 */
+	0x00000000, /* MPMC_REG_169 0x00000000 */
+	0x00000000, /* MPMC_REG_170 0x00000000 */
+	0x00000000, /* MPMC_REG_171 0x00000000 */
+	0x00000000, /* MPMC_REG_172 0x00000000 */
+	0x00000000, /* MPMC_REG_173 0x00000000 */
+	0x00000000, /* MPMC_REG_174 0x00000000 */
+	0x00000000, /* MPMC_REG_175 0x00000000 */
+	0x00000000, /* MPMC_REG_176 0x00000000 */
+	0x00000000, /* MPMC_REG_177 0x00000000 */
+	0x00000000, /* MPMC_REG_178 0x00000000 */
+	0x00000000, /* MPMC_REG_179 0x00000000 */
+	0x00000000, /* MPMC_REG_180 0x00000000 */
+	0x00000000, /* MPMC_REG_181 0x00000000 */
+	0x00000c28, /* MPMC_REG_182 0x00000c28 */
+	0x00000c28, /* MPMC_REG_183 0x00000c28 */
+	0x00000000, /* MPMC_REG_184 0x00000000 */
+	0x00000c28, /* MPMC_REG_185 0x00000c28 */
+	0x00013880, /* MPMC_REG_186 0x00013880 */
+	0x00000000, /* MPMC_REG_187 0x00000000 */
+	0x00000000, /* MPMC_REG_188 0x00000000 */
+	0x00000000, /* MPMC_REG_189 0x00000000 */
+	0x00000000, /* MPMC_REG_190 0x00000000 */
+	0x00000000, /* MPMC_REG_191 0x00000000 */
+	0x00000000, /* MPMC_REG_192 0x00000000 */
+	0x00000000, /* MPMC_REG_193 0x00000000 */
+	0x00000000, /* MPMC_REG_194 0x00000000 */
+	0x00000000, /* MPMC_REG_195 0x00000000 */
+	0x00000000, /* MPMC_REG_196 0x00000000 */
+	0x00000000, /* MPMC_REG_197 0x00000000 */
+	0x07000000, /* MPMC_REG_198 0x07000000 */
+	0x00000007, /* MPMC_REG_199 0x00000007 */
+	0x00000000, /* MPMC_REG_200 0x00000000 */
+	0x00006db0, /* MPMC_REG_201 0x00006db0 */
+	0x00000040, /* MPMC_REG_202 0x00000040 */
+	0x00000000, /* MPMC_REG_203 0x00000000 */
+	0x00000000, /* MPMC_REG_204 0x00000000 */
+	0x02000000, /* MPMC_REG_205 0x02000000 */
+	0x00000000, /* MPMC_REG_206 0x00000000 */
+	0x00003cc8, /* MPMC_REG_207 0x00003cc8 */
+};
+#endif
diff --git a/board/st/spear13xx/ddr/k4b2g1646c_k0_533_cl8.c b/board/st/spear13xx/ddr/k4b2g1646c_k0_533_cl8.c
new file mode 100644
index 0000000..159d3d7
--- /dev/null
+++ b/board/st/spear13xx/ddr/k4b2g1646c_k0_533_cl8.c
@@ -0,0 +1,238 @@ 
+/*
+ * (C) Copyright 2000-2009
+ * Vikas Manocha, ST Microelectronics, vikas.manocha@st.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/hardware.h>
+
+#if defined(CONFIG_SPEAR_DDRFREQ533)
+const u32 mpmc_conf_vals[CONFIG_SPEAR_MPMCREGS] = {
+	0x00000100, /* MPMC_REG_00 0x00000100 */
+	0x00010100, /* MPMC_REG_01 0x00000100 */
+	0x01000000, /* MPMC_REG_02 0x01000000 */
+	0x00010100, /* MPMC_REG_03 0x00000100 */
+	0x00000000, /* MPMC_REG_04 0x00000000 */
+	0x00010100, /* MPMC_REG_05 0x00010101 */
+	0x00000001, /* MPMC_REG_06 0x00000001 */
+	0x00000000, /* MPMC_REG_07 0x00000000 */
+	0x00000000, /* MPMC_REG_08 0x00000000 */
+	0x00000000, /* MPMC_REG_09 0x00000000 */
+	0x00000000, /* MPMC_REG_10 0x00000000 */
+	0x00000101, /* MPMC_REG_11 0x00000101 */
+	0x00000101, /* MPMC_REG_12 0x00000101 */
+	0x01010000, /* MPMC_REG_13 0x01010000 */
+	0x00000000, /* MPMC_REG_14 0x00000000 */
+	0x01000000, /* MPMC_REG_15 0x01000000 */
+	0x00000000, /* MPMC_REG_16 0x00000000 */
+	0x00000000, /* MPMC_REG_17 0x00000000 */
+	0x00000201, /* MPMC_REG_18 0x00000201 */
+	0x02010102, /* MPMC_REG_19 0x02010102 */
+	0x00020000, /* MPMC_REG_20 0x00020000 */
+	0x03030001, /* MPMC_REG_21 0x07070000 */
+	0x02030301, /* MPMC_REG_22 0x00070700 */
+	0x03030303, /* MPMC_REG_23 0x07000707 */
+	0x03030403, /* MPMC_REG_24 0x00000007 */
+	0x03030305, /* MPMC_REG_25 0x03070700 */
+	0x00000400, /* MPMC_REG_26 0x00000400 */
+	0x02000100, /* MPMC_REG_27 0x02000100 */
+	0x04030402, /* MPMC_REG_28 0x04030402 */
+	0x01000104, /* MPMC_REG_29 0x01000104 */
+	0x04000000, /* MPMC_REG_30 0x04000000 */
+	0x0606060a, /* MPMC_REG_31 0x0606060a */
+	0x06060606, /* MPMC_REG_32 0x06060606 */
+	0x05050506, /* MPMC_REG_33 0x05050506 */
+	0x05050505, /* MPMC_REG_34 0x05050505 */
+	0x04040405, /* MPMC_REG_35 0x04040405 */
+	0x04040404, /* MPMC_REG_36 0x04040404 */
+	0x03030304, /* MPMC_REG_37 0x03030304 */
+	0x03030303, /* MPMC_REG_38 0x03030303 */
+	0x02020203, /* MPMC_REG_39 0x02020203 */
+	0x02020202, /* MPMC_REG_40 0x02020202 */
+	0x01010102, /* MPMC_REG_41 0x01010102 */
+	0x01010101, /* MPMC_REG_42 0x01010101 */
+	0x06000c01, /* MPMC_REG_43 0x06000c01 */
+	0x00000000, /* MPMC_REG_44 0x00000000 */
+	0x00000204, /* MPMC_REG_45 0x00000204 */
+	0x04090800, /* MPMC_REG_46 0x04070602 */
+	0x02000606, /* MPMC_REG_47 0x02000505 */
+	0x00000010, /* MPMC_REG_48 0x0000000c */
+	0x10040408, /* MPMC_REG_49 0x0c040406 */
+	0x0800000d, /* MPMC_REG_50 0x0602000c */
+	0x3f003f08, /* MPMC_REG_51 0x3f003f06 */
+	0x191a1600, /* MPMC_REG_52 0x19150f00 */
+	0x00000028, /* MPMC_REG_53 0x00000028 */
+	0x00000000, /* MPMC_REG_54 0x00000000 */
+	0x00000000, /* MPMC_REG_55 0x00000000 */
+	0x00000000, /* MPMC_REG_56 0x00000000 */
+	0x00004000, /* MPMC_REG_57 0x00004000 */
+	0x03000000, /* MPMC_REG_58 0x03000000 */
+	0x03031a03, /* MPMC_REG_59 0x03031703 */
+	0x08130c04, /* MPMC_REG_60 0x060f0c04 */
+	0x00006400, /* MPMC_REG_61 0x00006456 */
+	0x00640064, /* MPMC_REG_62 0x00640064 */
+	0x00640064, /* MPMC_REG_63 0x00640064 */
+	0x000f0064, /* MPMC_REG_64 0x000f0064 */
+	0x0000000a, /* MPMC_REG_65 0x0000000a */
+	0x00400100, /* MPMC_REG_66 0x00400100 */
+	0x102d0200, /* MPMC_REG_67 0x0c280200 */
+	0x0200102d, /* MPMC_REG_68 0x02000c28 */
+	0x02000200, /* MPMC_REG_69 0x02000200 */
+	0x102d0200, /* MPMC_REG_70 0x0c280200 */
+	0x08400840, /* MPMC_REG_71 0x04200420 */
+	0x00440044, /* MPMC_REG_72 0x00440044 */
+	0x00080008, /* MPMC_REG_73 0x00000000 */
+	0x00000000, /* MPMC_REG_74 0x00000000 */
+	0xff005555, /* MPMC_REG_75 0xff005555 */
+	0xaaaa00ff, /* MPMC_REG_76 0xaaaa00ff */
+	0xff005555, /* MPMC_REG_77 0xff005555 */
+	0x00000007, /* MPMC_REG_78 0x00000007 */
+	0x00000000, /* MPMC_REG_79 0x00000000 */
+	0x00000000, /* MPMC_REG_80 0x00000000 */
+	0x00070000, /* MPMC_REG_81 0x00070000 */
+	0x00070007, /* MPMC_REG_82 0x00070007 */
+	0x00070007, /* MPMC_REG_83 0x00070007 */
+	0x00000000, /* MPMC_REG_84 0x00000000 */
+	0x00000000, /* MPMC_REG_85 0x00000000 */
+	0x00030000, /* MPMC_REG_86 0x00030000 */
+	0x00030003, /* MPMC_REG_87 0x00030003 */
+	0x00030003, /* MPMC_REG_88 0x00030003 */
+	0xffff0010, /* MPMC_REG_89 0xffff0010 */
+	0x00000000, /* MPMC_REG_90 0x00000000 */
+	0x00000000, /* MPMC_REG_91 0x00000000 */
+	0x00000000, /* MPMC_REG_92 0x00000000 */
+	0x00000000, /* MPMC_REG_93 0x00000000 */
+	0x00000000, /* MPMC_REG_94 0x00000000 */
+	0x00000000, /* MPMC_REG_95 0x00000000 */
+	0x02000000, /* MPMC_REG_96 0x02000000 */
+	0x00000004, /* MPMC_REG_97 0x6da60003 */
+	0x005b000d, /* MPMC_REG_98 0x0044000a */
+	0x00000200, /* MPMC_REG_99 0x00000200 */
+	0x00000000, /* MPMC_REG_100 0x00000000 */
+	0x00000000, /* MPMC_REG_101 0x00000000 */
+	0x00000000, /* MPMC_REG_102 0x00000000 */
+	0x00000000, /* MPMC_REG_103 0x00000000 */
+	0x00000000, /* MPMC_REG_104 0x00000000 */
+	0x00000000, /* MPMC_REG_105 0x00000000 */
+	0x00000000, /* MPMC_REG_106 0x00000000 */
+	0x00000001, /* MPMC_REG_107 0x00000001 */
+	0x00000001, /* MPMC_REG_108 0x00000001 */
+	0x00000001, /* MPMC_REG_109 0x00000001 */
+	0x00000001, /* MPMC_REG_110 0x00000001 */
+	0x00000001, /* MPMC_REG_111 0x00000001 */
+	0x00000006, /* MPMC_REG_112 0x0000ffff */
+	0x00000000, /* MPMC_REG_113 0x00000000 */
+	0x00040ee6, /* MPMC_REG_114 0x00030d40 */
+	0x00000050, /* MPMC_REG_115 0x00000050 */
+	0x00000050, /* MPMC_REG_116 0x00000050 */
+	0x00000050, /* MPMC_REG_117 0x00000050 */
+	0x00000050, /* MPMC_REG_118 0x00000050 */
+	0x00000050, /* MPMC_REG_119 0x00000050 */
+	0x00000050, /* MPMC_REG_120 0x00000050 */
+	0x00000000, /* MPMC_REG_121 0x00000000 */
+	0x00000000, /* MPMC_REG_122 0x00000000 */
+	0x000f1133, /* MPMC_REG_123 0x000f1133 */
+	0x00404000, /* MPMC_REG_124 0x00304000 */
+	0x00404000, /* MPMC_REG_125 0x00304000 */
+	0x00404000, /* MPMC_REG_126 0x00304000 */
+	0x00404000, /* MPMC_REG_127 0x00304000 */
+	0x00404000, /* MPMC_REG_128 0x00304000 */
+	0x00000002, /* MPMC_REG_129 0x00000002 */
+	0x1208a108, /* MPMC_REG_130 0x1208a108 */
+	0x1208a108, /* MPMC_REG_131 0x1208a108 */
+	0x1208a108, /* MPMC_REG_132 0x1208a108 */
+	0x1208a108, /* MPMC_REG_133 0x1208a108 */
+	0x1208a108, /* MPMC_REG_134 0x1208a108 */
+	0x01000000, /* MPMC_REG_135 0x01000000 */
+	0x01000000, /* MPMC_REG_136 0x01000000 */
+	0x01000000, /* MPMC_REG_137 0x01000000 */
+	0x01000000, /* MPMC_REG_138 0x01000000 */
+	0x01000000, /* MPMC_REG_139 0x01000000 */
+	0x01000000, /* MPMC_REG_140 0x01000000 */
+	0x01000000, /* MPMC_REG_141 0x01000000 */
+	0x01000000, /* MPMC_REG_142 0x01000000 */
+	0x01000000, /* MPMC_REG_143 0x01000000 */
+	0x01000000, /* MPMC_REG_144 0x01000000 */
+	0x06db6db6, /* MPMC_REG_145 0x06db6db6 */
+	0x06db6db6, /* MPMC_REG_146 0x06db6db6 */
+	0x06db6db6, /* MPMC_REG_147 0x06db6db6 */
+	0x06db6db6, /* MPMC_REG_148 0x06db6db6 */
+	0x06db6db6, /* MPMC_REG_149 0x06db6db6 */
+	0x00000000, /* MPMC_REG_150 0x00000000 */
+	0x00000000, /* MPMC_REG_151 0x00000000 */
+	0x00000000, /* MPMC_REG_152 0x00000000 */
+	0x00000000, /* MPMC_REG_153 0x00000000 */
+	0x00000000, /* MPMC_REG_154 0x00000000 */
+	0x2498a249, /* MPMC_REG_155 0x2498a249 */
+	0x2498a249, /* MPMC_REG_156 0x2498a249 */
+	0x2498a249, /* MPMC_REG_157 0x2498a249 */
+	0x2498a249, /* MPMC_REG_158 0x2498a249 */
+	0x2498a249, /* MPMC_REG_159 0x2498a249 */
+	0x04803219, /* MPMC_REG_160 0x04803219 */
+	0x04803219, /* MPMC_REG_161 0x04803219 */
+	0x04803219, /* MPMC_REG_162 0x04803219 */
+	0x04803219, /* MPMC_REG_163 0x04803219 */
+	0x04803219, /* MPMC_REG_164 0x04803219 */
+	0x00000000, /* MPMC_REG_165 0x00000000 */
+	0x00000000, /* MPMC_REG_166 0x00000000 */
+	0x00000000, /* MPMC_REG_167 0x00000000 */
+	0x00000000, /* MPMC_REG_168 0x00000000 */
+	0x00000000, /* MPMC_REG_169 0x00000000 */
+	0x00000000, /* MPMC_REG_170 0x00000000 */
+	0x00000000, /* MPMC_REG_171 0x00000000 */
+	0x00000000, /* MPMC_REG_172 0x00000000 */
+	0x00000000, /* MPMC_REG_173 0x00000000 */
+	0x00000000, /* MPMC_REG_174 0x00000000 */
+	0x00000000, /* MPMC_REG_175 0x00000000 */
+	0x00000000, /* MPMC_REG_176 0x00000000 */
+	0x00000000, /* MPMC_REG_177 0x00000000 */
+	0x00000000, /* MPMC_REG_178 0x00000000 */
+	0x00000000, /* MPMC_REG_179 0x00000000 */
+	0x00000000, /* MPMC_REG_180 0x00000000 */
+	0x00000000, /* MPMC_REG_181 0x00000000 */
+	0x0000102d, /* MPMC_REG_182 0x00000c28 */
+	0x0000102d, /* MPMC_REG_183 0x00000c28 */
+	0x00000000, /* MPMC_REG_184 0x00000000 */
+	0x0000102d, /* MPMC_REG_185 0x00000c28 */
+	0x00019f8f, /* MPMC_REG_186 0x00013880 */
+	0x00000000, /* MPMC_REG_187 0x00000000 */
+	0x00000000, /* MPMC_REG_188 0x00000000 */
+	0x00000000, /* MPMC_REG_189 0x00000000 */
+	0x00000000, /* MPMC_REG_190 0x00000000 */
+	0x00000000, /* MPMC_REG_191 0x00000000 */
+	0x00000000, /* MPMC_REG_192 0x00000000 */
+	0x00000000, /* MPMC_REG_193 0x00000000 */
+	0x00000000, /* MPMC_REG_194 0x00000000 */
+	0x00000000, /* MPMC_REG_195 0x00000000 */
+	0x00000000, /* MPMC_REG_196 0x00000000 */
+	0x00000000, /* MPMC_REG_197 0x00000000 */
+	0x07000000, /* MPMC_REG_198 0x07000000 */
+	0x00000007, /* MPMC_REG_199 0x00000007 */
+	0x00000000, /* MPMC_REG_200 0x00000000 */
+	0x000091dd, /* MPMC_REG_201 0x00006db0 */
+	0x00000056, /* MPMC_REG_202 0x00000040 */
+	0x00000000, /* MPMC_REG_203 0x00000000 */
+	0x00000000, /* MPMC_REG_204 0x00000000 */
+	0x02000000, /* MPMC_REG_205 0x02000000 */
+	0x00000000, /* MPMC_REG_206 0x00000000 */
+	0x000050e1, /* MPMC_REG_207 0x00003cc8 */
+};
+#endif
diff --git a/board/st/spear13xx/ddr/mt41j128m16_15e_400_cl6_dqs_dq_term_en.c b/board/st/spear13xx/ddr/mt41j128m16_15e_400_cl6_dqs_dq_term_en.c
new file mode 100644
index 0000000..1260ba1
--- /dev/null
+++ b/board/st/spear13xx/ddr/mt41j128m16_15e_400_cl6_dqs_dq_term_en.c
@@ -0,0 +1,238 @@ 
+/*
+ * (C) Copyright 2000-2009
+ * Vikas Manocha, ST Microelectronics, vikas.manocha@st.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/hardware.h>
+
+#if defined(CONFIG_SPEAR_DDRFREQ400)
+const u32 mpmc_conf_vals[CONFIG_SPEAR_MPMCREGS] = {
+	0x00000100, /* MPMC_REG_00 0x00000100 */
+	0x00010100, /* MPMC_REG_01 0x00000100 */
+	0x01000000, /* MPMC_REG_02 0x01000000 */
+	0x00010100, /* MPMC_REG_03 0x00000100 */
+	0x00000000, /* MPMC_REG_04 0x00000000 */
+	0x00010100, /* MPMC_REG_05 0x00010101 */
+	0x00000001, /* MPMC_REG_06 0x00000001 */
+	0x00000000, /* MPMC_REG_07 0x00000000 */
+	0x00000000, /* MPMC_REG_08 0x00000000 */
+	0x00000000, /* MPMC_REG_09 0x00000000 */
+	0x00000000, /* MPMC_REG_10 0x00000000 */
+	0x00000101, /* MPMC_REG_11 0x00000101 */
+	0x00000101, /* MPMC_REG_12 0x00000101 */
+	0x01010000, /* MPMC_REG_13 0x01010000 */
+	0x00000000, /* MPMC_REG_14 0x00000000 */
+	0x01000000, /* MPMC_REG_15 0x01000000 */
+	0x00000000, /* MPMC_REG_16 0x00000000 */
+	0x00000000, /* MPMC_REG_17 0x00000000 */
+	0x00000201, /* MPMC_REG_18 0x00000201 */
+	0x02010102, /* MPMC_REG_19 0x02010102 */
+	0x00020000, /* MPMC_REG_20 0x00020000 */
+	0x03030001, /* MPMC_REG_21 0x07070000 */
+	0x02030301, /* MPMC_REG_22 0x00070700 */
+	0x03030303, /* MPMC_REG_23 0x07000707 */
+	0x03030403, /* MPMC_REG_24 0x00000007 */
+	0x03030305, /* MPMC_REG_25 0x03070700 */
+	0x00000400, /* MPMC_REG_26 0x00000400 */
+	0x02000100, /* MPMC_REG_27 0x02000100 */
+	0x04030402, /* MPMC_REG_28 0x04030402 */
+	0x01000104, /* MPMC_REG_29 0x01000104 */
+	0x04000000, /* MPMC_REG_30 0x04000000 */
+	0x0606060a, /* MPMC_REG_31 0x0606060a */
+	0x06060606, /* MPMC_REG_32 0x06060606 */
+	0x05050506, /* MPMC_REG_33 0x05050506 */
+	0x05050505, /* MPMC_REG_34 0x05050505 */
+	0x04040405, /* MPMC_REG_35 0x04040405 */
+	0x04040404, /* MPMC_REG_36 0x04040404 */
+	0x03030304, /* MPMC_REG_37 0x03030304 */
+	0x03030303, /* MPMC_REG_38 0x03030303 */
+	0x02020203, /* MPMC_REG_39 0x02020203 */
+	0x02020202, /* MPMC_REG_40 0x02020202 */
+	0x01010102, /* MPMC_REG_41 0x01010102 */
+	0x01010101, /* MPMC_REG_42 0x01010101 */
+	0x06000c01, /* MPMC_REG_43 0x06000c01 */
+	0x00000000, /* MPMC_REG_44 0x00000000 */
+	0x00000204, /* MPMC_REG_45 0x00000204 */
+	0x04070600, /* MPMC_REG_46 0x04070602 */
+	0x02000505, /* MPMC_REG_47 0x02000505 */
+	0x0000000c, /* MPMC_REG_48 0x0000000c */
+	0x0c040406, /* MPMC_REG_49 0x0c040406 */
+	0x0600000c, /* MPMC_REG_50 0x0602000c */
+	0x3f003f06, /* MPMC_REG_51 0x3f003f06 */
+	0x19141200, /* MPMC_REG_52 0x19150f00 */
+	0x00000028, /* MPMC_REG_53 0x00000028 */
+	0x00000000, /* MPMC_REG_54 0x00000000 */
+	0x00000000, /* MPMC_REG_55 0x00000000 */
+	0x00000000, /* MPMC_REG_56 0x00000000 */
+	0x00004000, /* MPMC_REG_57 0x00004000 */
+	0x03000000, /* MPMC_REG_58 0x03000000 */
+	0x03031703, /* MPMC_REG_59 0x03031703 */
+	0x060f0c04, /* MPMC_REG_60 0x060f0c04 */
+	0x00006400, /* MPMC_REG_61 0x00006456 */
+	0x00640064, /* MPMC_REG_62 0x00640064 */
+	0x00640064, /* MPMC_REG_63 0x00640064 */
+	0x000f0064, /* MPMC_REG_64 0x000f0064 */
+	0x0000000a, /* MPMC_REG_65 0x0000000a */
+	0x00400100, /* MPMC_REG_66 0x00400100 */
+	0x0c2d0200, /* MPMC_REG_67 0x0c2d0200 */
+	0x02000c2d, /* MPMC_REG_68 0x02000c2d */
+	0x02000200, /* MPMC_REG_69 0x02000200 */
+	0x0c2d0200, /* MPMC_REG_70 0x0c2d0200 */
+	0x04200420, /* MPMC_REG_71 0x04200420 */
+	0x00440044, /* MPMC_REG_72 0x00440044 */
+	0x00000000, /* MPMC_REG_73 0x00000000 */
+	0x00000000, /* MPMC_REG_74 0x00000000 */
+	0xff005555, /* MPMC_REG_75 0xff005555 */
+	0xaaaa00ff, /* MPMC_REG_76 0xaaaa00ff */
+	0xff005555, /* MPMC_REG_77 0xff005555 */
+	0x00000007, /* MPMC_REG_78 0x00000007 */
+	0x00000000, /* MPMC_REG_79 0x00000000 */
+	0x00000000, /* MPMC_REG_80 0x00000000 */
+	0x00070000, /* MPMC_REG_81 0x00070000 */
+	0x00070007, /* MPMC_REG_82 0x00070007 */
+	0x00070007, /* MPMC_REG_83 0x00070007 */
+	0x00000000, /* MPMC_REG_84 0x00000000 */
+	0x00000000, /* MPMC_REG_85 0x00000000 */
+	0x00030000, /* MPMC_REG_86 0x00030000 */
+	0x00030003, /* MPMC_REG_87 0x00030003 */
+	0x00030003, /* MPMC_REG_88 0x00030003 */
+	0xffff0010, /* MPMC_REG_89 0xffff0010 */
+	0x00000000, /* MPMC_REG_90 0x00000000 */
+	0x00000000, /* MPMC_REG_91 0x00000000 */
+	0x00000000, /* MPMC_REG_92 0x00000000 */
+	0x00000000, /* MPMC_REG_93 0x00000000 */
+	0x00000000, /* MPMC_REG_94 0x00000000 */
+	0x00000000, /* MPMC_REG_95 0x00000000 */
+	0x02000000, /* MPMC_REG_96 0x02000000 */
+	0x00000003, /* MPMC_REG_97 0x6da60003 */
+	0x0044000a, /* MPMC_REG_98 0x0044000a */
+	0x00000200, /* MPMC_REG_99 0x00000200 */
+	0x00000000, /* MPMC_REG_100 0x00000000 */
+	0x00000000, /* MPMC_REG_101 0x00000000 */
+	0x00000000, /* MPMC_REG_102 0x00000000 */
+	0x00000000, /* MPMC_REG_103 0x00000000 */
+	0x00000000, /* MPMC_REG_104 0x00000000 */
+	0x00000000, /* MPMC_REG_105 0x00000000 */
+	0x00000000, /* MPMC_REG_106 0x00000000 */
+	0x00000001, /* MPMC_REG_107 0x00000001 */
+	0x00000001, /* MPMC_REG_108 0x00000001 */
+	0x00000001, /* MPMC_REG_109 0x00000001 */
+	0x00000001, /* MPMC_REG_110 0x00000001 */
+	0x00000001, /* MPMC_REG_111 0x00000001 */
+	0x00000004, /* MPMC_REG_112 0x0000ffff */
+	0x00000000, /* MPMC_REG_113 0x00000000 */
+	0x00030d40, /* MPMC_REG_114 0x00030d40 */
+	0x00000050, /* MPMC_REG_115 0x00000050 */
+	0x00000050, /* MPMC_REG_116 0x00000050 */
+	0x00000050, /* MPMC_REG_117 0x00000050 */
+	0x00000050, /* MPMC_REG_118 0x00000050 */
+	0x00000050, /* MPMC_REG_119 0x00000050 */
+	0x00000050, /* MPMC_REG_120 0x00000050 */
+	0x00000000, /* MPMC_REG_121 0x00000000 */
+	0x00000000, /* MPMC_REG_122 0x00000000 */
+	0x000f1133, /* MPMC_REG_123 0x000f1133 */
+	0x00304000, /* MPMC_REG_124 0x00304000 */
+	0x00304000, /* MPMC_REG_125 0x00304000 */
+	0x00304000, /* MPMC_REG_126 0x00304000 */
+	0x00304000, /* MPMC_REG_127 0x00304000 */
+	0x00304000, /* MPMC_REG_128 0x00304000 */
+	0x00000002, /* MPMC_REG_129 0x00000002 */
+	0x1208a108, /* MPMC_REG_130 0x1208a108 */
+	0x1208a108, /* MPMC_REG_131 0x1208a108 */
+	0x1208a108, /* MPMC_REG_132 0x1208a108 */
+	0x1208a108, /* MPMC_REG_133 0x1208a108 */
+	0x1208a108, /* MPMC_REG_134 0x1208a108 */
+	0x01000000, /* MPMC_REG_135 0x01000000 */
+	0x01000000, /* MPMC_REG_136 0x01000000 */
+	0x01000000, /* MPMC_REG_137 0x01000000 */
+	0x01000000, /* MPMC_REG_138 0x01000000 */
+	0x01000000, /* MPMC_REG_139 0x01000000 */
+	0x01000000, /* MPMC_REG_140 0x01000000 */
+	0x01000000, /* MPMC_REG_141 0x01000000 */
+	0x01000000, /* MPMC_REG_142 0x01000000 */
+	0x01000000, /* MPMC_REG_143 0x01000000 */
+	0x01000000, /* MPMC_REG_144 0x01000000 */
+	0x06db6db6, /* MPMC_REG_145 0x06db6db6 */
+	0x06db6db6, /* MPMC_REG_146 0x06db6db6 */
+	0x06db6db6, /* MPMC_REG_147 0x06db6db6 */
+	0x06db6db6, /* MPMC_REG_148 0x06db6db6 */
+	0x06db6db6, /* MPMC_REG_149 0x06db6db6 */
+	0x00000000, /* MPMC_REG_150 0x00000000 */
+	0x00000000, /* MPMC_REG_151 0x00000000 */
+	0x00000000, /* MPMC_REG_152 0x00000000 */
+	0x00000000, /* MPMC_REG_153 0x00000000 */
+	0x00000000, /* MPMC_REG_154 0x00000000 */
+	0x2498a249, /* MPMC_REG_155 0x2498a249 */
+	0x2498a249, /* MPMC_REG_156 0x2498a249 */
+	0x2498a249, /* MPMC_REG_157 0x2498a249 */
+	0x2498a249, /* MPMC_REG_158 0x2498a249 */
+	0x2498a249, /* MPMC_REG_159 0x2498a249 */
+	0x04803219, /* MPMC_REG_160 0x04803219 */
+	0x04803219, /* MPMC_REG_161 0x04803219 */
+	0x04803219, /* MPMC_REG_162 0x04803219 */
+	0x04803219, /* MPMC_REG_163 0x04803219 */
+	0x04803219, /* MPMC_REG_164 0x04803219 */
+	0x00000000, /* MPMC_REG_165 0x00000000 */
+	0x00000000, /* MPMC_REG_166 0x00000000 */
+	0x00000000, /* MPMC_REG_167 0x00000000 */
+	0x00000000, /* MPMC_REG_168 0x00000000 */
+	0x00000000, /* MPMC_REG_169 0x00000000 */
+	0x00000000, /* MPMC_REG_170 0x00000000 */
+	0x00000000, /* MPMC_REG_171 0x00000000 */
+	0x00000000, /* MPMC_REG_172 0x00000000 */
+	0x00000000, /* MPMC_REG_173 0x00000000 */
+	0x00000000, /* MPMC_REG_174 0x00000000 */
+	0x00000000, /* MPMC_REG_175 0x00000000 */
+	0x00000000, /* MPMC_REG_176 0x00000000 */
+	0x00000000, /* MPMC_REG_177 0x00000000 */
+	0x00000000, /* MPMC_REG_178 0x00000000 */
+	0x00000000, /* MPMC_REG_179 0x00000000 */
+	0x00000000, /* MPMC_REG_180 0x00000000 */
+	0x00000000, /* MPMC_REG_181 0x00000000 */
+	0x00000c2d, /* MPMC_REG_182 0x00000c2d */
+	0x00000c2d, /* MPMC_REG_183 0x00000c2d */
+	0x00000000, /* MPMC_REG_184 0x00000000 */
+	0x00000c2d, /* MPMC_REG_185 0x00000c2d */
+	0x00013880, /* MPMC_REG_186 0x00013880 */
+	0x00000000, /* MPMC_REG_187 0x00000000 */
+	0x00000000, /* MPMC_REG_188 0x00000000 */
+	0x00000000, /* MPMC_REG_189 0x00000000 */
+	0x00000000, /* MPMC_REG_190 0x00000000 */
+	0x00000000, /* MPMC_REG_191 0x00000000 */
+	0x00000000, /* MPMC_REG_192 0x00000000 */
+	0x00000000, /* MPMC_REG_193 0x00000000 */
+	0x00000000, /* MPMC_REG_194 0x00000000 */
+	0x00000000, /* MPMC_REG_195 0x00000000 */
+	0x00000000, /* MPMC_REG_196 0x00000000 */
+	0x00000000, /* MPMC_REG_197 0x00000000 */
+	0x07000000, /* MPMC_REG_198 0x07000000 */
+	0x00000007, /* MPMC_REG_199 0x00000007 */
+	0x00000000, /* MPMC_REG_200 0x00000000 */
+	0x00006db0, /* MPMC_REG_201 0x00006db0 */
+	0x00000040, /* MPMC_REG_202 0x00000040 */
+	0x00000000, /* MPMC_REG_203 0x00000000 */
+	0x00000000, /* MPMC_REG_204 0x00000000 */
+	0x02000000, /* MPMC_REG_205 0x02000000 */
+	0x00000000, /* MPMC_REG_206 0x00000000 */
+	0x00003ce1, /* MPMC_REG_207 0x00003ce1 */
+};
+#endif
diff --git a/board/st/spear13xx/ddr/mt41j256m8187e_400_cl6_dqs_dq_term_en.c b/board/st/spear13xx/ddr/mt41j256m8187e_400_cl6_dqs_dq_term_en.c
new file mode 100644
index 0000000..8ee680b
--- /dev/null
+++ b/board/st/spear13xx/ddr/mt41j256m8187e_400_cl6_dqs_dq_term_en.c
@@ -0,0 +1,246 @@ 
+/*
+ * (C) Copyright 2000-2009
+ * Vikas Manocha, ST Microelectronics, vikas.manocha@st.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/hardware.h>
+
+#if defined(CONFIG_SPEAR_DDRFREQ400)
+const u32 mpmc_conf_vals[CONFIG_SPEAR_MPMCREGS] = {
+	0x00000100, /* MPMC_REG_00 */
+	0x00000100, /* MPMC_REG_01 */
+	0x01000000, /* MPMC_REG_02 */
+#ifdef CONFIG_DDR_ECC_ENABLE
+	0x00000101, /* MPMC_REG_03 */
+#else
+	0x00000100, /* MPMC_REG_03 */
+#endif
+	0x00000000, /* MPMC_REG_04 */
+	0x00010101, /* MPMC_REG_05 */
+	0x00000001, /* MPMC_REG_06 */
+	0x00000000, /* MPMC_REG_07 */
+	0x00000000, /* MPMC_REG_08 */
+	0x00000000, /* MPMC_REG_09 */
+	0x00000000, /* MPMC_REG_10 */
+	0x00000101, /* MPMC_REG_11 */
+	0x00000101, /* MPMC_REG_12 */
+	0x01010000, /* MPMC_REG_13 */
+	0x00000000, /* MPMC_REG_14 */
+	0x01000000, /* MPMC_REG_15 */
+	0x00000000, /* MPMC_REG_16 */
+	0x00000000, /* MPMC_REG_17 */
+#ifdef CONFIG_DDR_ECC_ENABLE
+	0x00000001, /* MPMC_REG_18 */
+#else
+	0x00000201, /* MPMC_REG_18 */
+#endif
+	0x02010102, /* MPMC_REG_19 */
+	0x00020000, /* MPMC_REG_20 */
+	0x07070000, /* MPMC_REG_21 */
+	0x00070700, /* MPMC_REG_22 */
+	0x07000707, /* MPMC_REG_23 */
+	0x00000007, /* MPMC_REG_24 */
+	0x03070700, /* MPMC_REG_25 */
+	0x00000400, /* MPMC_REG_26 */
+	0x02000100, /* MPMC_REG_27 */
+	0x04030402, /* MPMC_REG_28 */
+	0x01000104, /* MPMC_REG_29 */
+	0x04000000, /* MPMC_REG_30 */
+	0x0606060a, /* MPMC_REG_31 */
+	0x06060606, /* MPMC_REG_32 */
+	0x05050506, /* MPMC_REG_33 */
+	0x05050505, /* MPMC_REG_34 */
+	0x04040405, /* MPMC_REG_35 */
+	0x04040404, /* MPMC_REG_36 */
+	0x03030304, /* MPMC_REG_37 */
+	0x03030303, /* MPMC_REG_38 */
+	0x02020203, /* MPMC_REG_39 */
+	0x02020202, /* MPMC_REG_40 */
+	0x01010102, /* MPMC_REG_41 */
+	0x01010101, /* MPMC_REG_42 */
+	0x06000c01, /* MPMC_REG_43 */
+	0x00000000, /* MPMC_REG_44 */
+	0x00000204, /* MPMC_REG_45 */
+	0x04070602, /* MPMC_REG_46 */
+	0x02000505, /* MPMC_REG_47 */
+	0x0000000c, /* MPMC_REG_48 */
+	0x0c040406, /* MPMC_REG_49 */
+	0x0602000c, /* MPMC_REG_50 */
+	0x3f003f06, /* MPMC_REG_51 */
+	0x19150f00, /* MPMC_REG_52 */
+	0x00000028, /* MPMC_REG_53 */
+	0x00000000, /* MPMC_REG_54 */
+	0x00000000, /* MPMC_REG_55 */
+	0x00000000, /* MPMC_REG_56 */
+	0x00004000, /* MPMC_REG_57 */
+	0x03000000, /* MPMC_REG_58 */
+	0x03031703, /* MPMC_REG_59 */
+	0x060f0c04, /* MPMC_REG_60 */
+	0x00006456, /* MPMC_REG_61 */
+	0x00640064, /* MPMC_REG_62 */
+	0x00640064, /* MPMC_REG_63 */
+	0x000f0064, /* MPMC_REG_64 */
+	0x0000000a, /* MPMC_REG_65 */
+	0x00400100, /* MPMC_REG_66 */
+	0x0c2d0200, /* MPMC_REG_67 */
+	0x02000c2d, /* MPMC_REG_68 */
+	0x02000200, /* MPMC_REG_69 */
+	0x0c2d0200, /* MPMC_REG_70 */
+	0x04200420, /* MPMC_REG_71 */
+	0x00440044, /* MPMC_REG_72 */
+	0x00000000, /* MPMC_REG_73 */
+	0x00000000, /* MPMC_REG_74 */
+	0xff005555, /* MPMC_REG_75 */
+	0xaaaa00ff, /* MPMC_REG_76 */
+	0xff005555, /* MPMC_REG_77 */
+	0x00000007, /* MPMC_REG_78 */
+	0x00000000, /* MPMC_REG_79 */
+	0x00000000, /* MPMC_REG_80 */
+	0x00070000, /* MPMC_REG_81 */
+	0x00070007, /* MPMC_REG_82 */
+	0x00070007, /* MPMC_REG_83 */
+	0x00000000, /* MPMC_REG_84 */
+	0x00000000, /* MPMC_REG_85 */
+	0x00030000, /* MPMC_REG_86 */
+	0x00030003, /* MPMC_REG_87 */
+	0x00030003, /* MPMC_REG_88 */
+	0xffff0010, /* MPMC_REG_89 */
+	0x00000000, /* MPMC_REG_90 */
+	0x00000000, /* MPMC_REG_91 */
+	0x00000000, /* MPMC_REG_92 */
+	0x00000000, /* MPMC_REG_93 */
+	0x00000000, /* MPMC_REG_94 */
+	0x00000000, /* MPMC_REG_95 */
+	0x02000000, /* MPMC_REG_96 */
+	0x6da60003, /* MPMC_REG_97 */
+	0x0044000a, /* MPMC_REG_98 */
+	0x00000200, /* MPMC_REG_99 */
+	0x00000000, /* MPMC_REG_100 */
+	0x00000000, /* MPMC_REG_101 */
+	0x00000000, /* MPMC_REG_102 */
+	0x00000000, /* MPMC_REG_103 */
+	0x00000000, /* MPMC_REG_104 */
+	0x00000000, /* MPMC_REG_105 */
+	0x00000000, /* MPMC_REG_106 */
+	0x00000001, /* MPMC_REG_107 */
+	0x00000001, /* MPMC_REG_108 */
+	0x00000001, /* MPMC_REG_109 */
+	0x00000001, /* MPMC_REG_110 */
+	0x00000001, /* MPMC_REG_111 */
+	0x0000ffff, /* MPMC_REG_112 */
+	0x00000000, /* MPMC_REG_113 */
+	0x00030d40, /* MPMC_REG_114 */
+	0x00000050, /* MPMC_REG_115 */
+	0x00000050, /* MPMC_REG_116 */
+	0x00000050, /* MPMC_REG_117 */
+	0x00000050, /* MPMC_REG_118 */
+	0x00000050, /* MPMC_REG_119 */
+	0x00000050, /* MPMC_REG_120 */
+	0x00000000, /* MPMC_REG_121 */
+	0x00000000, /* MPMC_REG_122 */
+	0x000f1133, /* MPMC_REG_123 */
+	0x00304000, /* MPMC_REG_124 */
+	0x00304000, /* MPMC_REG_125 */
+	0x00304000, /* MPMC_REG_126 */
+	0x00304000, /* MPMC_REG_127 */
+	0x00304000, /* MPMC_REG_128 */
+	0x00000002, /* MPMC_REG_129 */
+	0x1208a108, /* MPMC_REG_130 */
+	0x1208a108, /* MPMC_REG_131 */
+	0x1208a108, /* MPMC_REG_132 */
+	0x1208a108, /* MPMC_REG_133 */
+	0x1208a108, /* MPMC_REG_134 */
+	0x01000000, /* MPMC_REG_135 */
+	0x01000000, /* MPMC_REG_136 */
+	0x01000000, /* MPMC_REG_137 */
+	0x01000000, /* MPMC_REG_138 */
+	0x01000000, /* MPMC_REG_139 */
+	0x01000000, /* MPMC_REG_140 */
+	0x01000000, /* MPMC_REG_141 */
+	0x01000000, /* MPMC_REG_142 */
+	0x01000000, /* MPMC_REG_143 */
+	0x01000000, /* MPMC_REG_144 */
+	0x06db6db6, /* MPMC_REG_145 */
+	0x06db6db6, /* MPMC_REG_146 */
+	0x06db6db6, /* MPMC_REG_147 */
+	0x06db6db6, /* MPMC_REG_148 */
+	0x06db6db6, /* MPMC_REG_149 */
+	0x00000000, /* MPMC_REG_150 */
+	0x00000000, /* MPMC_REG_151 */
+	0x00000000, /* MPMC_REG_152 */
+	0x00000000, /* MPMC_REG_153 */
+	0x00000000, /* MPMC_REG_154 */
+	0x2498a249, /* MPMC_REG_155 */
+	0x2498a249, /* MPMC_REG_156 */
+	0x2498a249, /* MPMC_REG_157 */
+	0x2498a249, /* MPMC_REG_158 */
+	0x2498a249, /* MPMC_REG_159 */
+	0x04803219, /* MPMC_REG_160 */
+	0x04803219, /* MPMC_REG_161 */
+	0x04803219, /* MPMC_REG_162 */
+	0x04803219, /* MPMC_REG_163 */
+	0x04803219, /* MPMC_REG_164 */
+	0x00000000, /* MPMC_REG_165 */
+	0x00000000, /* MPMC_REG_166 */
+	0x00000000, /* MPMC_REG_167 */
+	0x00000000, /* MPMC_REG_168 */
+	0x00000000, /* MPMC_REG_169 */
+	0x00000000, /* MPMC_REG_170 */
+	0x00000000, /* MPMC_REG_171 */
+	0x00000000, /* MPMC_REG_172 */
+	0x00000000, /* MPMC_REG_173 */
+	0x00000000, /* MPMC_REG_174 */
+	0x00000000, /* MPMC_REG_175 */
+	0x00000000, /* MPMC_REG_176 */
+	0x00000000, /* MPMC_REG_177 */
+	0x00000000, /* MPMC_REG_178 */
+	0x00000000, /* MPMC_REG_179 */
+	0x00000000, /* MPMC_REG_180 */
+	0x00000000, /* MPMC_REG_181 */
+	0x00000c2d, /* MPMC_REG_182 */
+	0x00000c2d, /* MPMC_REG_183 */
+	0x00000000, /* MPMC_REG_184 */
+	0x00000c2d, /* MPMC_REG_185 */
+	0x00013880, /* MPMC_REG_186 */
+	0x00000000, /* MPMC_REG_187 */
+	0x00000000, /* MPMC_REG_188 */
+	0x00000000, /* MPMC_REG_189 */
+	0x00000000, /* MPMC_REG_190 */
+	0x00000000, /* MPMC_REG_191 */
+	0x00000000, /* MPMC_REG_192 */
+	0x00000000, /* MPMC_REG_193 */
+	0x00000000, /* MPMC_REG_194 */
+	0x00000000, /* MPMC_REG_195 */
+	0x00000000, /* MPMC_REG_196 */
+	0x00000000, /* MPMC_REG_197 */
+	0x07000000, /* MPMC_REG_198 */
+	0x00000007, /* MPMC_REG_199 */
+	0x00000000, /* MPMC_REG_200 */
+	0x00006db0, /* MPMC_REG_201 */
+	0x00000040, /* MPMC_REG_202 */
+	0x00000000, /* MPMC_REG_203 */
+	0x00000000, /* MPMC_REG_204 */
+	0x02000000, /* MPMC_REG_205 */
+	0x00000000, /* MPMC_REG_206 */
+	0x00003ce1, /* MPMC_REG_207 */
+};
+#endif
diff --git a/board/st/spear13xx/ddr/mt41j256m8187e_533_cl7_dqs_dq_term_en.c b/board/st/spear13xx/ddr/mt41j256m8187e_533_cl7_dqs_dq_term_en.c
new file mode 100644
index 0000000..0d11b36
--- /dev/null
+++ b/board/st/spear13xx/ddr/mt41j256m8187e_533_cl7_dqs_dq_term_en.c
@@ -0,0 +1,246 @@ 
+/*
+ * (C) Copyright 2000-2009
+ * Vikas Manocha, ST Microelectronics, vikas.manocha@st.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/hardware.h>
+
+#if defined(CONFIG_SPEAR_DDRFREQ533)
+const u32 mpmc_conf_vals[CONFIG_SPEAR_MPMCREGS] = {
+	0x00000100, /* MPMC_REG_00 */
+	0x00000100, /* MPMC_REG_01 */
+	0x01000000, /* MPMC_REG_02 */
+#ifdef CONFIG_DDR_ECC_ENABLE
+	0x00000101, /* MPMC_REG_03 */
+#else
+	0x00000100, /* MPMC_REG_03 */
+#endif
+	0x00000000, /* MPMC_REG_04 */
+	0x00010101, /* MPMC_REG_05 */
+	0x00000001, /* MPMC_REG_06 */
+	0x00000000, /* MPMC_REG_07 */
+	0x00000000, /* MPMC_REG_08 */
+	0x00000000, /* MPMC_REG_09 */
+	0x00000000, /* MPMC_REG_10 */
+	0x00000101, /* MPMC_REG_11 */
+	0x00000101, /* MPMC_REG_12 */
+	0x01010000, /* MPMC_REG_13 */
+	0x00000000, /* MPMC_REG_14 */
+	0x01000000, /* MPMC_REG_15 */
+	0x00000000, /* MPMC_REG_16 */
+	0x00000000, /* MPMC_REG_17 */
+#ifdef CONFIG_DDR_ECC_ENABLE
+	0x00000001, /* MPMC_REG_18 */
+#else
+	0x00000201, /* MPMC_REG_18 */
+#endif
+	0x02010102, /* MPMC_REG_19 */
+	0x00020000, /* MPMC_REG_20 */
+	0x07070000, /* MPMC_REG_21 */
+	0x00070700, /* MPMC_REG_22 */
+	0x07000707, /* MPMC_REG_23 */
+	0x00000007, /* MPMC_REG_24 */
+	0x03070700, /* MPMC_REG_25 */
+	0x00000400, /* MPMC_REG_26 */
+	0x02000100, /* MPMC_REG_27 */
+	0x04030402, /* MPMC_REG_28 */
+	0x01000104, /* MPMC_REG_29 */
+	0x04000000, /* MPMC_REG_30 */
+	0x0606060a, /* MPMC_REG_31 */
+	0x06060606, /* MPMC_REG_32 */
+	0x05050506, /* MPMC_REG_33 */
+	0x05050505, /* MPMC_REG_34 */
+	0x04040405, /* MPMC_REG_35 */
+	0x04040404, /* MPMC_REG_36 */
+	0x03030304, /* MPMC_REG_37 */
+	0x03030303, /* MPMC_REG_38 */
+	0x02020203, /* MPMC_REG_39 */
+	0x02020202, /* MPMC_REG_40 */
+	0x01010102, /* MPMC_REG_41 */
+	0x01010101, /* MPMC_REG_42 */
+	0x06000c01, /* MPMC_REG_43 */
+	0x00000000, /* MPMC_REG_44 */
+	0x00000204, /* MPMC_REG_45 */
+	0x04080702, /* MPMC_REG_46 */
+	0x02000606, /* MPMC_REG_47 */
+	0x0000000e, /* MPMC_REG_48 */
+	0x0f040407, /* MPMC_REG_49 */
+	0x0802000d, /* MPMC_REG_50 */
+	0x3f003f08, /* MPMC_REG_51 */
+	0x191b1400, /* MPMC_REG_52 */
+	0x00000028, /* MPMC_REG_53 */
+	0x00000000, /* MPMC_REG_54 */
+	0x00000000, /* MPMC_REG_55 */
+	0x00000000, /* MPMC_REG_56 */
+	0x00004000, /* MPMC_REG_57 */
+	0x03000000, /* MPMC_REG_58 */
+	0x03031903, /* MPMC_REG_59 */
+	0x07140c04, /* MPMC_REG_60 */
+	0x00006456, /* MPMC_REG_61 */
+	0x00640064, /* MPMC_REG_62 */
+	0x00640064, /* MPMC_REG_63 */
+	0x000f0064, /* MPMC_REG_64 */
+	0x0000000a, /* MPMC_REG_65 */
+	0x00400100, /* MPMC_REG_66 */
+	0x10330200, /* MPMC_REG_67 */
+	0x02001033, /* MPMC_REG_68 */
+	0x02000200, /* MPMC_REG_69 */
+	0x10330200, /* MPMC_REG_70 */
+	0x08300830, /* MPMC_REG_71 */
+	0x00440044, /* MPMC_REG_72 */
+	0x00080008, /* MPMC_REG_73 */
+	0x00000000, /* MPMC_REG_74 */
+	0xff005555, /* MPMC_REG_75 */
+	0xaaaa00ff, /* MPMC_REG_76 */
+	0xff005555, /* MPMC_REG_77 */
+	0x00000007, /* MPMC_REG_78 */
+	0x00000000, /* MPMC_REG_79 */
+	0x00000000, /* MPMC_REG_80 */
+	0x00070000, /* MPMC_REG_81 */
+	0x00070007, /* MPMC_REG_82 */
+	0x00070007, /* MPMC_REG_83 */
+	0x00000000, /* MPMC_REG_84 */
+	0x00000000, /* MPMC_REG_85 */
+	0x00030000, /* MPMC_REG_86 */
+	0x00030003, /* MPMC_REG_87 */
+	0x00030003, /* MPMC_REG_88 */
+	0xffff0010, /* MPMC_REG_89 */
+	0x00000000, /* MPMC_REG_90 */
+	0x00000000, /* MPMC_REG_91 */
+	0x00000000, /* MPMC_REG_92 */
+	0x00000000, /* MPMC_REG_93 */
+	0x00000000, /* MPMC_REG_94 */
+	0x00000000, /* MPMC_REG_95 */
+	0x02000000, /* MPMC_REG_96 */
+	0x91d30004, /* MPMC_REG_97 */
+	0x005b000d, /* MPMC_REG_98 */
+	0x00000200, /* MPMC_REG_99 */
+	0x00000000, /* MPMC_REG_100 */
+	0x00000000, /* MPMC_REG_101 */
+	0x00000000, /* MPMC_REG_102 */
+	0x00000000, /* MPMC_REG_103 */
+	0x00000000, /* MPMC_REG_104 */
+	0x00000000, /* MPMC_REG_105 */
+	0x00000000, /* MPMC_REG_106 */
+	0x00000001, /* MPMC_REG_107 */
+	0x00000001, /* MPMC_REG_108 */
+	0x00000001, /* MPMC_REG_109 */
+	0x00000001, /* MPMC_REG_110 */
+	0x00000001, /* MPMC_REG_111 */
+	0x0000ffff, /* MPMC_REG_112 */
+	0x00000000, /* MPMC_REG_113 */
+	0x00040ee6, /* MPMC_REG_114 */
+	0x00000050, /* MPMC_REG_115 */
+	0x00000050, /* MPMC_REG_116 */
+	0x00000050, /* MPMC_REG_117 */
+	0x00000050, /* MPMC_REG_118 */
+	0x00000050, /* MPMC_REG_119 */
+	0x00000050, /* MPMC_REG_120 */
+	0x00000000, /* MPMC_REG_121 */
+	0x00000000, /* MPMC_REG_122 */
+	0x000f1133, /* MPMC_REG_123 */
+	0x00404000, /* MPMC_REG_124 */
+	0x00404000, /* MPMC_REG_125 */
+	0x00404000, /* MPMC_REG_126 */
+	0x00404000, /* MPMC_REG_127 */
+	0x00404000, /* MPMC_REG_128 */
+	0x00000002, /* MPMC_REG_129 */
+	0x1208a108, /* MPMC_REG_130 */
+	0x1208a108, /* MPMC_REG_131 */
+	0x1208a108, /* MPMC_REG_132 */
+	0x1208a108, /* MPMC_REG_133 */
+	0x1208a108, /* MPMC_REG_134 */
+	0x01000000, /* MPMC_REG_135 */
+	0x01000000, /* MPMC_REG_136 */
+	0x01000000, /* MPMC_REG_137 */
+	0x01000000, /* MPMC_REG_138 */
+	0x01000000, /* MPMC_REG_139 */
+	0x01000000, /* MPMC_REG_140 */
+	0x01000000, /* MPMC_REG_141 */
+	0x01000000, /* MPMC_REG_142 */
+	0x01000000, /* MPMC_REG_143 */
+	0x01000000, /* MPMC_REG_144 */
+	0x06db6db6, /* MPMC_REG_145 */
+	0x06db6db6, /* MPMC_REG_146 */
+	0x06db6db6, /* MPMC_REG_147 */
+	0x06db6db6, /* MPMC_REG_148 */
+	0x06db6db6, /* MPMC_REG_149 */
+	0x00000000, /* MPMC_REG_150 */
+	0x00000000, /* MPMC_REG_151 */
+	0x00000000, /* MPMC_REG_152 */
+	0x00000000, /* MPMC_REG_153 */
+	0x00000000, /* MPMC_REG_154 */
+	0x2498a249, /* MPMC_REG_155 */
+	0x2498a249, /* MPMC_REG_156 */
+	0x2498a249, /* MPMC_REG_157 */
+	0x2498a249, /* MPMC_REG_158 */
+	0x2498a249, /* MPMC_REG_159 */
+	0x04803219, /* MPMC_REG_160 */
+	0x04803219, /* MPMC_REG_161 */
+	0x04803219, /* MPMC_REG_162 */
+	0x04803219, /* MPMC_REG_163 */
+	0x04803219, /* MPMC_REG_164 */
+	0x00000000, /* MPMC_REG_165 */
+	0x00000000, /* MPMC_REG_166 */
+	0x00000000, /* MPMC_REG_167 */
+	0x00000000, /* MPMC_REG_168 */
+	0x00000000, /* MPMC_REG_169 */
+	0x00000000, /* MPMC_REG_170 */
+	0x00000000, /* MPMC_REG_171 */
+	0x00000000, /* MPMC_REG_172 */
+	0x00000000, /* MPMC_REG_173 */
+	0x00000000, /* MPMC_REG_174 */
+	0x00000000, /* MPMC_REG_175 */
+	0x00000000, /* MPMC_REG_176 */
+	0x00000000, /* MPMC_REG_177 */
+	0x00000000, /* MPMC_REG_178 */
+	0x00000000, /* MPMC_REG_179 */
+	0x00000000, /* MPMC_REG_180 */
+	0x00000000, /* MPMC_REG_181 */
+	0x00001033, /* MPMC_REG_182 */
+	0x00001033, /* MPMC_REG_183 */
+	0x00000000, /* MPMC_REG_184 */
+	0x00001033, /* MPMC_REG_185 */
+	0x00019f8f, /* MPMC_REG_186 */
+	0x00000000, /* MPMC_REG_187 */
+	0x00000000, /* MPMC_REG_188 */
+	0x00000000, /* MPMC_REG_189 */
+	0x00000000, /* MPMC_REG_190 */
+	0x00000000, /* MPMC_REG_191 */
+	0x00000000, /* MPMC_REG_192 */
+	0x00000000, /* MPMC_REG_193 */
+	0x00000000, /* MPMC_REG_194 */
+	0x00000000, /* MPMC_REG_195 */
+	0x00000000, /* MPMC_REG_196 */
+	0x00000000, /* MPMC_REG_197 */
+	0x07000000, /* MPMC_REG_198 */
+	0x00000007, /* MPMC_REG_199 */
+	0x00000000, /* MPMC_REG_200 */
+	0x000091dd, /* MPMC_REG_201 */
+	0x00000056, /* MPMC_REG_202 */
+	0x00000000, /* MPMC_REG_203 */
+	0x00000000, /* MPMC_REG_204 */
+	0x02000000, /* MPMC_REG_205 */
+	0x00000000, /* MPMC_REG_206 */
+	0x000050ff, /* MPMC_REG_207 */
+};
+#endif
diff --git a/board/st/spear13xx/ddr/mt41j64m16_15e_400_cl6_dqs_dq_term_en.c b/board/st/spear13xx/ddr/mt41j64m16_15e_400_cl6_dqs_dq_term_en.c
new file mode 100644
index 0000000..708c87d
--- /dev/null
+++ b/board/st/spear13xx/ddr/mt41j64m16_15e_400_cl6_dqs_dq_term_en.c
@@ -0,0 +1,238 @@ 
+/*
+ * (C) Copyright 2000-2009
+ * Vikas Manocha, ST Microelectronics, vikas.manocha@st.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/hardware.h>
+
+#if defined(CONFIG_SPEAR_DDRFREQ400)
+const u32 mpmc_conf_vals[CONFIG_SPEAR_MPMCREGS] = {
+	0x00000100, /* MPMC_REG_00 0x00000100 */
+	0x00010100, /* MPMC_REG_01 0x00000100 */
+	0x01000000, /* MPMC_REG_02 0x01000000 */
+	0x00010100, /* MPMC_REG_03 0x00000100 */
+	0x00000000, /* MPMC_REG_04 0x00000000 */
+	0x00010100, /* MPMC_REG_05 0x00010101 */
+	0x00000001, /* MPMC_REG_06 0x00000001 */
+	0x00000000, /* MPMC_REG_07 0x00000000 */
+	0x00000000, /* MPMC_REG_08 0x00000000 */
+	0x00000000, /* MPMC_REG_09 0x00000000 */
+	0x00000000, /* MPMC_REG_10 0x00000000 */
+	0x00000101, /* MPMC_REG_11 0x00000101 */
+	0x00000101, /* MPMC_REG_12 0x00000101 */
+	0x01010000, /* MPMC_REG_13 0x01010000 */
+	0x00000000, /* MPMC_REG_14 0x00000000 */
+	0x01000000, /* MPMC_REG_15 0x01000000 */
+	0x00000000, /* MPMC_REG_16 0x00000000 */
+	0x00000000, /* MPMC_REG_17 0x00000000 */
+	0x00000201, /* MPMC_REG_18 0x00000201 */
+	0x02010102, /* MPMC_REG_19 0x02010102 */
+	0x00020000, /* MPMC_REG_20 0x00020000 */
+	0x03030002, /* MPMC_REG_21 0x07070000 */
+	0x02030301, /* MPMC_REG_22 0x00070700 */
+	0x03030303, /* MPMC_REG_23 0x07000707 */
+	0x03030403, /* MPMC_REG_24 0x00000007 */
+	0x03030305, /* MPMC_REG_25 0x03070700 */
+	0x00000400, /* MPMC_REG_26 0x00000400 */
+	0x02000100, /* MPMC_REG_27 0x02000100 */
+	0x04030402, /* MPMC_REG_28 0x04030402 */
+	0x01000104, /* MPMC_REG_29 0x01000104 */
+	0x04000000, /* MPMC_REG_30 0x04000000 */
+	0x0606060a, /* MPMC_REG_31 0x0606060a */
+	0x06060606, /* MPMC_REG_32 0x06060606 */
+	0x05050506, /* MPMC_REG_33 0x05050506 */
+	0x05050505, /* MPMC_REG_34 0x05050505 */
+	0x04040405, /* MPMC_REG_35 0x04040405 */
+	0x04040404, /* MPMC_REG_36 0x04040404 */
+	0x03030304, /* MPMC_REG_37 0x03030304 */
+	0x03030303, /* MPMC_REG_38 0x03030303 */
+	0x02020203, /* MPMC_REG_39 0x02020203 */
+	0x02020202, /* MPMC_REG_40 0x02020202 */
+	0x01010102, /* MPMC_REG_41 0x01010102 */
+	0x01010101, /* MPMC_REG_42 0x01010101 */
+	0x06000c01, /* MPMC_REG_43 0x06000c01 */
+	0x00000000, /* MPMC_REG_44 0x00000000 */
+	0x00000204, /* MPMC_REG_45 0x00000204 */
+	0x04070600, /* MPMC_REG_46 0x04070602 */
+	0x02000505, /* MPMC_REG_47 0x02000505 */
+	0x0000000c, /* MPMC_REG_48 0x0000000c */
+	0x0c040406, /* MPMC_REG_49 0x0c040406 */
+	0x0600000c, /* MPMC_REG_50 0x0602000c */
+	0x3f003f06, /* MPMC_REG_51 0x3f003f06 */
+	0x19141200, /* MPMC_REG_52 0x19150f00 */
+	0x00000028, /* MPMC_REG_53 0x00000028 */
+	0x00000000, /* MPMC_REG_54 0x00000000 */
+	0x00000000, /* MPMC_REG_55 0x00000000 */
+	0x00000000, /* MPMC_REG_56 0x00000000 */
+	0x00004000, /* MPMC_REG_57 0x00004000 */
+	0x03000000, /* MPMC_REG_58 0x03000000 */
+	0x03031703, /* MPMC_REG_59 0x03031703 */
+	0x060f0c04, /* MPMC_REG_60 0x060f0c04 */
+	0x00006400, /* MPMC_REG_61 0x00006456 */
+	0x00640064, /* MPMC_REG_62 0x00640064 */
+	0x00640064, /* MPMC_REG_63 0x00640064 */
+	0x000f0064, /* MPMC_REG_64 0x000f0064 */
+	0x0000000a, /* MPMC_REG_65 0x0000000a */
+	0x00400100, /* MPMC_REG_66 0x00400100 */
+	0x0c2d0200, /* MPMC_REG_67 0x0c2d0200 */
+	0x02000c2d, /* MPMC_REG_68 0x02000c2d */
+	0x02000200, /* MPMC_REG_69 0x02000200 */
+	0x0c2d0200, /* MPMC_REG_70 0x0c2d0200 */
+	0x04200420, /* MPMC_REG_71 0x04200420 */
+	0x00440044, /* MPMC_REG_72 0x00440044 */
+	0x00000000, /* MPMC_REG_73 0x00000000 */
+	0x00000000, /* MPMC_REG_74 0x00000000 */
+	0xff005555, /* MPMC_REG_75 0xff005555 */
+	0xaaaa00ff, /* MPMC_REG_76 0xaaaa00ff */
+	0xff005555, /* MPMC_REG_77 0xff005555 */
+	0x00000007, /* MPMC_REG_78 0x00000007 */
+	0x00000000, /* MPMC_REG_79 0x00000000 */
+	0x00000000, /* MPMC_REG_80 0x00000000 */
+	0x00070000, /* MPMC_REG_81 0x00070000 */
+	0x00070007, /* MPMC_REG_82 0x00070007 */
+	0x00070007, /* MPMC_REG_83 0x00070007 */
+	0x00000000, /* MPMC_REG_84 0x00000000 */
+	0x00000000, /* MPMC_REG_85 0x00000000 */
+	0x00030000, /* MPMC_REG_86 0x00030000 */
+	0x00030003, /* MPMC_REG_87 0x00030003 */
+	0x00030003, /* MPMC_REG_88 0x00030003 */
+	0xffff0010, /* MPMC_REG_89 0xffff0010 */
+	0x00000000, /* MPMC_REG_90 0x00000000 */
+	0x00000000, /* MPMC_REG_91 0x00000000 */
+	0x00000000, /* MPMC_REG_92 0x00000000 */
+	0x00000000, /* MPMC_REG_93 0x00000000 */
+	0x00000000, /* MPMC_REG_94 0x00000000 */
+	0x00000000, /* MPMC_REG_95 0x00000000 */
+	0x02000000, /* MPMC_REG_96 0x02000000 */
+	0x00000003, /* MPMC_REG_97 0x6da60003 */
+	0x0030000a, /* MPMC_REG_98 0x0044000a */
+	0x00000200, /* MPMC_REG_99 0x00000200 */
+	0x00000000, /* MPMC_REG_100 0x00000000 */
+	0x00000000, /* MPMC_REG_101 0x00000000 */
+	0x00000000, /* MPMC_REG_102 0x00000000 */
+	0x00000000, /* MPMC_REG_103 0x00000000 */
+	0x00000000, /* MPMC_REG_104 0x00000000 */
+	0x00000000, /* MPMC_REG_105 0x00000000 */
+	0x00000000, /* MPMC_REG_106 0x00000000 */
+	0x00000001, /* MPMC_REG_107 0x00000001 */
+	0x00000001, /* MPMC_REG_108 0x00000001 */
+	0x00000001, /* MPMC_REG_109 0x00000001 */
+	0x00000001, /* MPMC_REG_110 0x00000001 */
+	0x00000001, /* MPMC_REG_111 0x00000001 */
+	0x00000004, /* MPMC_REG_112 0x0000ffff */
+	0x00000000, /* MPMC_REG_113 0x00000000 */
+	0x00030d40, /* MPMC_REG_114 0x00030d40 */
+	0x00000050, /* MPMC_REG_115 0x00000050 */
+	0x00000050, /* MPMC_REG_116 0x00000050 */
+	0x00000050, /* MPMC_REG_117 0x00000050 */
+	0x00000050, /* MPMC_REG_118 0x00000050 */
+	0x00000050, /* MPMC_REG_119 0x00000050 */
+	0x00000050, /* MPMC_REG_120 0x00000050 */
+	0x00000000, /* MPMC_REG_121 0x00000000 */
+	0x00000000, /* MPMC_REG_122 0x00000000 */
+	0x000f1133, /* MPMC_REG_123 0x000f1133 */
+	0x00304000, /* MPMC_REG_124 0x00304000 */
+	0x00304000, /* MPMC_REG_125 0x00304000 */
+	0x00304000, /* MPMC_REG_126 0x00304000 */
+	0x00304000, /* MPMC_REG_127 0x00304000 */
+	0x00304000, /* MPMC_REG_128 0x00304000 */
+	0x00000002, /* MPMC_REG_129 0x00000002 */
+	0x1208a108, /* MPMC_REG_130 0x1208a108 */
+	0x1208a108, /* MPMC_REG_131 0x1208a108 */
+	0x1208a108, /* MPMC_REG_132 0x1208a108 */
+	0x1208a108, /* MPMC_REG_133 0x1208a108 */
+	0x1208a108, /* MPMC_REG_134 0x1208a108 */
+	0x01000000, /* MPMC_REG_135 0x01000000 */
+	0x01000000, /* MPMC_REG_136 0x01000000 */
+	0x01000000, /* MPMC_REG_137 0x01000000 */
+	0x01000000, /* MPMC_REG_138 0x01000000 */
+	0x01000000, /* MPMC_REG_139 0x01000000 */
+	0x01000000, /* MPMC_REG_140 0x01000000 */
+	0x01000000, /* MPMC_REG_141 0x01000000 */
+	0x01000000, /* MPMC_REG_142 0x01000000 */
+	0x01000000, /* MPMC_REG_143 0x01000000 */
+	0x01000000, /* MPMC_REG_144 0x01000000 */
+	0x06db6db6, /* MPMC_REG_145 0x06db6db6 */
+	0x06db6db6, /* MPMC_REG_146 0x06db6db6 */
+	0x06db6db6, /* MPMC_REG_147 0x06db6db6 */
+	0x06db6db6, /* MPMC_REG_148 0x06db6db6 */
+	0x06db6db6, /* MPMC_REG_149 0x06db6db6 */
+	0x00000000, /* MPMC_REG_150 0x00000000 */
+	0x00000000, /* MPMC_REG_151 0x00000000 */
+	0x00000000, /* MPMC_REG_152 0x00000000 */
+	0x00000000, /* MPMC_REG_153 0x00000000 */
+	0x00000000, /* MPMC_REG_154 0x00000000 */
+	0x2498a249, /* MPMC_REG_155 0x2498a249 */
+	0x2498a249, /* MPMC_REG_156 0x2498a249 */
+	0x2498a249, /* MPMC_REG_157 0x2498a249 */
+	0x2498a249, /* MPMC_REG_158 0x2498a249 */
+	0x2498a249, /* MPMC_REG_159 0x2498a249 */
+	0x04803219, /* MPMC_REG_160 0x04803219 */
+	0x04803219, /* MPMC_REG_161 0x04803219 */
+	0x04803219, /* MPMC_REG_162 0x04803219 */
+	0x04803219, /* MPMC_REG_163 0x04803219 */
+	0x04803219, /* MPMC_REG_164 0x04803219 */
+	0x00000000, /* MPMC_REG_165 0x00000000 */
+	0x00000000, /* MPMC_REG_166 0x00000000 */
+	0x00000000, /* MPMC_REG_167 0x00000000 */
+	0x00000000, /* MPMC_REG_168 0x00000000 */
+	0x00000000, /* MPMC_REG_169 0x00000000 */
+	0x00000000, /* MPMC_REG_170 0x00000000 */
+	0x00000000, /* MPMC_REG_171 0x00000000 */
+	0x00000000, /* MPMC_REG_172 0x00000000 */
+	0x00000000, /* MPMC_REG_173 0x00000000 */
+	0x00000000, /* MPMC_REG_174 0x00000000 */
+	0x00000000, /* MPMC_REG_175 0x00000000 */
+	0x00000000, /* MPMC_REG_176 0x00000000 */
+	0x00000000, /* MPMC_REG_177 0x00000000 */
+	0x00000000, /* MPMC_REG_178 0x00000000 */
+	0x00000000, /* MPMC_REG_179 0x00000000 */
+	0x00000000, /* MPMC_REG_180 0x00000000 */
+	0x00000000, /* MPMC_REG_181 0x00000000 */
+	0x00000c2d, /* MPMC_REG_182 0x00000c2d */
+	0x00000c2d, /* MPMC_REG_183 0x00000c2d */
+	0x00000000, /* MPMC_REG_184 0x00000000 */
+	0x00000c2d, /* MPMC_REG_185 0x00000c2d */
+	0x00013880, /* MPMC_REG_186 0x00013880 */
+	0x00000000, /* MPMC_REG_187 0x00000000 */
+	0x00000000, /* MPMC_REG_188 0x00000000 */
+	0x00000000, /* MPMC_REG_189 0x00000000 */
+	0x00000000, /* MPMC_REG_190 0x00000000 */
+	0x00000000, /* MPMC_REG_191 0x00000000 */
+	0x00000000, /* MPMC_REG_192 0x00000000 */
+	0x00000000, /* MPMC_REG_193 0x00000000 */
+	0x00000000, /* MPMC_REG_194 0x00000000 */
+	0x00000000, /* MPMC_REG_195 0x00000000 */
+	0x00000000, /* MPMC_REG_196 0x00000000 */
+	0x00000000, /* MPMC_REG_197 0x00000000 */
+	0x07000000, /* MPMC_REG_198 0x07000000 */
+	0x00000007, /* MPMC_REG_199 0x00000007 */
+	0x00000000, /* MPMC_REG_200 0x00000000 */
+	0x00006db0, /* MPMC_REG_201 0x00006db0 */
+	0x0000002c, /* MPMC_REG_202 0x00000040 */
+	0x00000000, /* MPMC_REG_203 0x00000000 */
+	0x00000000, /* MPMC_REG_204 0x00000000 */
+	0x02000000, /* MPMC_REG_205 0x02000000 */
+	0x00000000, /* MPMC_REG_206 0x00000000 */
+	0x00003ce1, /* MPMC_REG_207 0x00003ce1 */
+};
+#endif
diff --git a/board/st/spear13xx/ddr/mt41j64m16_15e_533_cl7_dqs_dq_term_en.c b/board/st/spear13xx/ddr/mt41j64m16_15e_533_cl7_dqs_dq_term_en.c
new file mode 100644
index 0000000..8ddd263
--- /dev/null
+++ b/board/st/spear13xx/ddr/mt41j64m16_15e_533_cl7_dqs_dq_term_en.c
@@ -0,0 +1,238 @@ 
+/*
+ * (C) Copyright 2000-2009
+ * Vikas Manocha, ST Microelectronics, vikas.manocha@st.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/hardware.h>
+
+#if defined(CONFIG_SPEAR_DDRFREQ533)
+const u32 mpmc_conf_vals[CONFIG_SPEAR_MPMCREGS] = {
+	0x00000100, /* MPMC_REG_00 0x00000100 */
+	0x00010100, /* MPMC_REG_01 0x00000100 */
+	0x01000000, /* MPMC_REG_02 0x01000000 */
+	0x00010100, /* MPMC_REG_03 0x00000100 */
+	0x00000000, /* MPMC_REG_04 0x00000000 */
+	0x00010100, /* MPMC_REG_05 0x00010101 */
+	0x00000001, /* MPMC_REG_06 0x00000001 */
+	0x00000000, /* MPMC_REG_07 0x00000000 */
+	0x00000000, /* MPMC_REG_08 0x00000000 */
+	0x00000000, /* MPMC_REG_09 0x00000000 */
+	0x00000000, /* MPMC_REG_10 0x00000000 */
+	0x00000101, /* MPMC_REG_11 0x00000101 */
+	0x00000101, /* MPMC_REG_12 0x00000101 */
+	0x01010000, /* MPMC_REG_13 0x01010000 */
+	0x00000000, /* MPMC_REG_14 0x00000000 */
+	0x01000000, /* MPMC_REG_15 0x01000000 */
+	0x00000000, /* MPMC_REG_16 0x00000000 */
+	0x00000000, /* MPMC_REG_17 0x00000000 */
+	0x00000201, /* MPMC_REG_18 0x00000201 */
+	0x02010102, /* MPMC_REG_19 0x02010102 */
+	0x00020000, /* MPMC_REG_20 0x00020000 */
+	0x03030002, /* MPMC_REG_21 0x07070000 */
+	0x02030301, /* MPMC_REG_22 0x00070700 */
+	0x03030303, /* MPMC_REG_23 0x07000707 */
+	0x03030403, /* MPMC_REG_24 0x00000007 */
+	0x03030305, /* MPMC_REG_25 0x03070700 */
+	0x00000400, /* MPMC_REG_26 0x00000400 */
+	0x02000100, /* MPMC_REG_27 0x02000100 */
+	0x04030402, /* MPMC_REG_28 0x04030402 */
+	0x01000104, /* MPMC_REG_29 0x01000104 */
+	0x04000000, /* MPMC_REG_30 0x04000000 */
+	0x0606060a, /* MPMC_REG_31 0x0606060a */
+	0x06060606, /* MPMC_REG_32 0x06060606 */
+	0x05050506, /* MPMC_REG_33 0x05050506 */
+	0x05050505, /* MPMC_REG_34 0x05050505 */
+	0x04040405, /* MPMC_REG_35 0x04040405 */
+	0x04040404, /* MPMC_REG_36 0x04040404 */
+	0x03030304, /* MPMC_REG_37 0x03030304 */
+	0x03030303, /* MPMC_REG_38 0x03030303 */
+	0x02020203, /* MPMC_REG_39 0x02020203 */
+	0x02020202, /* MPMC_REG_40 0x02020202 */
+	0x01010102, /* MPMC_REG_41 0x01010102 */
+	0x01010101, /* MPMC_REG_42 0x01010101 */
+	0x06000c01, /* MPMC_REG_43 0x06000c01 */
+	0x00000000, /* MPMC_REG_44 0x00000000 */
+	0x00000204, /* MPMC_REG_45 0x00000204 */
+	0x04090800, /* MPMC_REG_46 0x04090800 */
+	0x02000606, /* MPMC_REG_47 0x02000606 */
+	0x0000000e, /* MPMC_REG_48 0x0000000e */
+	0x10040407, /* MPMC_REG_49 0x10040407 */
+	0x0800000d, /* MPMC_REG_50 0x0800000d */
+	0x3f003f08, /* MPMC_REG_51 0x3f003f08 */
+	0x191b1800, /* MPMC_REG_52 0x191b1800 */
+	0x00000028, /* MPMC_REG_53 0x00000028 */
+	0x00000000, /* MPMC_REG_54 0x00000000 */
+	0x00000000, /* MPMC_REG_55 0x00000000 */
+	0x00000000, /* MPMC_REG_56 0x00000000 */
+	0x00004000, /* MPMC_REG_57 0x00004000 */
+	0x03000000, /* MPMC_REG_58 0x03000000 */
+	0x03031903, /* MPMC_REG_59 0x03031903 */
+	0x08140c04, /* MPMC_REG_60 0x08140c04 */
+	0x00006400, /* MPMC_REG_61 0x00006456 */
+	0x00640064, /* MPMC_REG_62 0x00640064 */
+	0x00640064, /* MPMC_REG_63 0x00640064 */
+	0x000f0064, /* MPMC_REG_64 0x000f0064 */
+	0x0000000a, /* MPMC_REG_65 0x0000000a */
+	0x00400100, /* MPMC_REG_66 0x00400100 */
+	0x10330200, /* MPMC_REG_67 0x10330200 */
+	0x02001033, /* MPMC_REG_68 0x02001033 */
+	0x02000200, /* MPMC_REG_69 0x02000200 */
+	0x10330200, /* MPMC_REG_70 0x10330200 */
+	0x08300830, /* MPMC_REG_71 0x08300830 */
+	0x00460046, /* MPMC_REG_72 0x00460046 */
+	0x00080008, /* MPMC_REG_73 0x00080008 */
+	0x00000000, /* MPMC_REG_74 0x00000000 */
+	0xff005555, /* MPMC_REG_75 0xff005555 */
+	0xaaaa00ff, /* MPMC_REG_76 0xaaaa00ff */
+	0xff005555, /* MPMC_REG_77 0xff005555 */
+	0x00000007, /* MPMC_REG_78 0x00000007 */
+	0x00000000, /* MPMC_REG_79 0x00000000 */
+	0x00000000, /* MPMC_REG_80 0x00000000 */
+	0x00070000, /* MPMC_REG_81 0x00070000 */
+	0x00070007, /* MPMC_REG_82 0x00070007 */
+	0x00070007, /* MPMC_REG_83 0x00070007 */
+	0x00000000, /* MPMC_REG_84 0x00000000 */
+	0x00000000, /* MPMC_REG_85 0x00000000 */
+	0x00030000, /* MPMC_REG_86 0x00030000 */
+	0x00030003, /* MPMC_REG_87 0x00030003 */
+	0x00030003, /* MPMC_REG_88 0x00030003 */
+	0xffff0010, /* MPMC_REG_89 0xffff0010 */
+	0x00000000, /* MPMC_REG_90 0x00000000 */
+	0x00000000, /* MPMC_REG_91 0x00000000 */
+	0x00000000, /* MPMC_REG_92 0x00000000 */
+	0x00000000, /* MPMC_REG_93 0x00000000 */
+	0x00000000, /* MPMC_REG_94 0x00000000 */
+	0x00000000, /* MPMC_REG_95 0x00000000 */
+	0x02000000, /* MPMC_REG_96 0x02000000 */
+	0x00000004, /* MPMC_REG_97 0x00000004 */
+	0x0040000d, /* MPMC_REG_98 0x0040000d */
+	0x00000200, /* MPMC_REG_99 0x00000200 */
+	0x00000000, /* MPMC_REG_100 0x00000000 */
+	0x00000000, /* MPMC_REG_101 0x00000000 */
+	0x00000000, /* MPMC_REG_102 0x00000000 */
+	0x00000000, /* MPMC_REG_103 0x00000000 */
+	0x00000000, /* MPMC_REG_104 0x00000000 */
+	0x00000000, /* MPMC_REG_105 0x00000000 */
+	0x00000000, /* MPMC_REG_106 0x00000000 */
+	0x00000001, /* MPMC_REG_107 0x00000001 */
+	0x00000001, /* MPMC_REG_108 0x00000001 */
+	0x00000001, /* MPMC_REG_109 0x00000001 */
+	0x00000001, /* MPMC_REG_110 0x00000001 */
+	0x00000001, /* MPMC_REG_111 0x00000001 */
+	0x00000006, /* MPMC_REG_112 0x00000006 */
+	0x00000000, /* MPMC_REG_113 0x00000000 */
+	0x00040ee6, /* MPMC_REG_114 0x00040ee6 */
+	0x00000050, /* MPMC_REG_115 0x00000050 */
+	0x00000050, /* MPMC_REG_116 0x00000050 */
+	0x00000050, /* MPMC_REG_117 0x00000050 */
+	0x00000050, /* MPMC_REG_118 0x00000050 */
+	0x00000050, /* MPMC_REG_119 0x00000050 */
+	0x00000050, /* MPMC_REG_120 0x00000050 */
+	0x00000000, /* MPMC_REG_121 0x00000000 */
+	0x00000000, /* MPMC_REG_122 0x00000000 */
+	0x000f1133, /* MPMC_REG_123 0x000f1133 */
+	0x00404000, /* MPMC_REG_124 0x00404000 */
+	0x00404000, /* MPMC_REG_125 0x00404000 */
+	0x00404000, /* MPMC_REG_126 0x00404000 */
+	0x00404000, /* MPMC_REG_127 0x00404000 */
+	0x00404000, /* MPMC_REG_128 0x00404000 */
+	0x00000002, /* MPMC_REG_129 0x00000002 */
+	0x1208a108, /* MPMC_REG_130 0x1208a108 */
+	0x1208a108, /* MPMC_REG_131 0x1208a108 */
+	0x1208a108, /* MPMC_REG_132 0x1208a108 */
+	0x1208a108, /* MPMC_REG_133 0x1208a108 */
+	0x1208a108, /* MPMC_REG_134 0x1208a108 */
+	0x01000000, /* MPMC_REG_135 0x01000000 */
+	0x01000000, /* MPMC_REG_136 0x01000000 */
+	0x01000000, /* MPMC_REG_137 0x01000000 */
+	0x01000000, /* MPMC_REG_138 0x01000000 */
+	0x01000000, /* MPMC_REG_139 0x01000000 */
+	0x01000000, /* MPMC_REG_140 0x01000000 */
+	0x01000000, /* MPMC_REG_141 0x01000000 */
+	0x01000000, /* MPMC_REG_142 0x01000000 */
+	0x01000000, /* MPMC_REG_143 0x01000000 */
+	0x01000000, /* MPMC_REG_144 0x01000000 */
+	0x06db6db6, /* MPMC_REG_145 0x06db6db6 */
+	0x06db6db6, /* MPMC_REG_146 0x06db6db6 */
+	0x06db6db6, /* MPMC_REG_147 0x06db6db6 */
+	0x06db6db6, /* MPMC_REG_148 0x06db6db6 */
+	0x06db6db6, /* MPMC_REG_149 0x06db6db6 */
+	0x00000000, /* MPMC_REG_150 0x00000000 */
+	0x00000000, /* MPMC_REG_151 0x00000000 */
+	0x00000000, /* MPMC_REG_152 0x00000000 */
+	0x00000000, /* MPMC_REG_153 0x00000000 */
+	0x00000000, /* MPMC_REG_154 0x00000000 */
+	0x2498a249, /* MPMC_REG_155 0x2498a249 */
+	0x2498a249, /* MPMC_REG_156 0x2498a249 */
+	0x2498a249, /* MPMC_REG_157 0x2498a249 */
+	0x2498a249, /* MPMC_REG_158 0x2498a249 */
+	0x2498a249, /* MPMC_REG_159 0x2498a249 */
+	0x04803219, /* MPMC_REG_160 0x04803219 */
+	0x04803219, /* MPMC_REG_161 0x04803219 */
+	0x04803219, /* MPMC_REG_162 0x04803219 */
+	0x04803219, /* MPMC_REG_163 0x04803219 */
+	0x04803219, /* MPMC_REG_164 0x04803219 */
+	0x00000000, /* MPMC_REG_165 0x00000000 */
+	0x00000000, /* MPMC_REG_166 0x00000000 */
+	0x00000000, /* MPMC_REG_167 0x00000000 */
+	0x00000000, /* MPMC_REG_168 0x00000000 */
+	0x00000000, /* MPMC_REG_169 0x00000000 */
+	0x00000000, /* MPMC_REG_170 0x00000000 */
+	0x00000000, /* MPMC_REG_171 0x00000000 */
+	0x00000000, /* MPMC_REG_172 0x00000000 */
+	0x00000000, /* MPMC_REG_173 0x00000000 */
+	0x00000000, /* MPMC_REG_174 0x00000000 */
+	0x00000000, /* MPMC_REG_175 0x00000000 */
+	0x00000000, /* MPMC_REG_176 0x00000000 */
+	0x00000000, /* MPMC_REG_177 0x00000000 */
+	0x00000000, /* MPMC_REG_178 0x00000000 */
+	0x00000000, /* MPMC_REG_179 0x00000000 */
+	0x00000000, /* MPMC_REG_180 0x00000000 */
+	0x00000000, /* MPMC_REG_181 0x00000000 */
+	0x00001033, /* MPMC_REG_182 0x00001033 */
+	0x00001033, /* MPMC_REG_183 0x00001033 */
+	0x00000000, /* MPMC_REG_184 0x00000000 */
+	0x00001033, /* MPMC_REG_185 0x00001033 */
+	0x00019f8f, /* MPMC_REG_186 0x00019f8f */
+	0x00000000, /* MPMC_REG_187 0x00000000 */
+	0x00000000, /* MPMC_REG_188 0x00000000 */
+	0x00000000, /* MPMC_REG_189 0x00000000 */
+	0x00000000, /* MPMC_REG_190 0x00000000 */
+	0x00000000, /* MPMC_REG_191 0x00000000 */
+	0x00000000, /* MPMC_REG_192 0x00000000 */
+	0x00000000, /* MPMC_REG_193 0x00000000 */
+	0x00000000, /* MPMC_REG_194 0x00000000 */
+	0x00000000, /* MPMC_REG_195 0x00000000 */
+	0x00000000, /* MPMC_REG_196 0x00000000 */
+	0x00000000, /* MPMC_REG_197 0x00000000 */
+	0x07000000, /* MPMC_REG_198 0x07000000 */
+	0x00000007, /* MPMC_REG_199 0x00000007 */
+	0x00000000, /* MPMC_REG_200 0x00000000 */
+	0x000091dd, /* MPMC_REG_201 0x000091dd */
+	0x0000003b, /* MPMC_REG_202 0x0000003b */
+	0x00000000, /* MPMC_REG_203 0x00000000 */
+	0x00000000, /* MPMC_REG_204 0x00000000 */
+	0x02000000, /* MPMC_REG_205 0x02000000 */
+	0x00000000, /* MPMC_REG_206 0x00000000 */
+	0x000050ff, /* MPMC_REG_207 0x000050ff */
+};
+#endif
diff --git a/board/st/spear13xx/ddr/mt47h128m16rt187e_400_cl6_ddr2.c b/board/st/spear13xx/ddr/mt47h128m16rt187e_400_cl6_ddr2.c
new file mode 100644
index 0000000..f986921
--- /dev/null
+++ b/board/st/spear13xx/ddr/mt47h128m16rt187e_400_cl6_ddr2.c
@@ -0,0 +1,239 @@ 
+/*
+ * (C) Copyright 2000-2009
+ * Vikas Manocha, ST Microelectronics, vikas.manocha@st.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/hardware.h>
+
+#if defined(CONFIG_DDR_MT47H128M16) && \
+	defined(CONFIG_SPEAR_DDRFREQ400)
+const u32 mpmc_conf_vals[CONFIG_SPEAR_MPMCREGS] = {
+	0x00000100, /* MPMC_REG_00 */
+	0x00010100, /* MPMC_REG_01 */
+	0x01000000, /* MPMC_REG_02 */
+	0x00010100, /* MPMC_REG_03 */
+	0x00000000, /* MPMC_REG_04 */
+	0x00010100, /* MPMC_REG_05 */
+	0x00000001, /* MPMC_REG_06 */
+	0x00000000, /* MPMC_REG_07 */
+	0x00000000, /* MPMC_REG_08 */
+	0x00000000, /* MPMC_REG_09 */
+	0x00000000, /* MPMC_REG_10 */
+	0x00000101, /* MPMC_REG_11 */
+	0x00000101, /* MPMC_REG_12 */
+	0x01010000, /* MPMC_REG_13 */
+	0x00000000, /* MPMC_REG_14 */
+	0x01000000, /* MPMC_REG_15 */
+	0x00000000, /* MPMC_REG_16 */
+	0x00000000, /* MPMC_REG_17 */
+	0x00000201, /* MPMC_REG_18 */
+	0x02010000, /* MPMC_REG_19 */
+	0x00020000, /* MPMC_REG_20 */
+	0x03030001, /* MPMC_REG_21 */
+	0x02030301, /* MPMC_REG_22 */
+	0x03030303, /* MPMC_REG_23 */
+	0x03030403, /* MPMC_REG_24 */
+	0x03030305, /* MPMC_REG_25 */
+	0x00000400, /* MPMC_REG_26 */
+	0x02000200, /* MPMC_REG_27 */
+	0x04030202, /* MPMC_REG_28 */
+	0x01000103, /* MPMC_REG_29 */
+	0x03000000, /* MPMC_REG_30 */
+	0x0606060a, /* MPMC_REG_31 */
+	0x06060606, /* MPMC_REG_32 */
+	0x05050506, /* MPMC_REG_33 */
+	0x05050505, /* MPMC_REG_34 */
+	0x04040405, /* MPMC_REG_35 */
+	0x04040404, /* MPMC_REG_36 */
+	0x03030304, /* MPMC_REG_37 */
+	0x03030303, /* MPMC_REG_38 */
+	0x02020203, /* MPMC_REG_39 */
+	0x02020202, /* MPMC_REG_40 */
+	0x01010102, /* MPMC_REG_41 */
+	0x01010101, /* MPMC_REG_42 */
+	0x04000c01, /* MPMC_REG_43 */
+	0x00000002, /* MPMC_REG_44 */
+	0x00000204, /* MPMC_REG_45 */
+	0x03070600, /* MPMC_REG_46 */
+	0x02000505, /* MPMC_REG_47 */
+	0x0000000c, /* MPMC_REG_48 */
+	0x0c030206, /* MPMC_REG_49 */
+	0x0200000c, /* MPMC_REG_50 */
+	0x3f003f06, /* MPMC_REG_51 */
+	0x19161200, /* MPMC_REG_52 */
+	0x00000028, /* MPMC_REG_53 */
+	0x00000000, /* MPMC_REG_54 */
+	0x00000000, /* MPMC_REG_55 */
+	0x00000000, /* MPMC_REG_56 */
+	0x00004000, /* MPMC_REG_57 */
+	0x03000000, /* MPMC_REG_58 */
+	0x03031703, /* MPMC_REG_59 */
+	0x06160504, /* MPMC_REG_60 */
+	0x00006400, /* MPMC_REG_61 */
+	0x00640064, /* MPMC_REG_62 */
+	0x00640064, /* MPMC_REG_63 */
+	0x000f0064, /* MPMC_REG_64 */
+	0x0000000a, /* MPMC_REG_65 */
+	0x00400100, /* MPMC_REG_66 */
+	0x0c2d0200, /* MPMC_REG_67 */
+	0x02000c2d, /* MPMC_REG_68 */
+	0x02000200, /* MPMC_REG_69 */
+	0x0c2d0200, /* MPMC_REG_70 */
+	0x0a630a63, /* MPMC_REG_71 */
+	0x00040004, /* MPMC_REG_72 */
+	0x00000000, /* MPMC_REG_73 */
+	0x00000000, /* MPMC_REG_74 */
+	0xff005555, /* MPMC_REG_75 */
+	0xaaaa00ff, /* MPMC_REG_76 */
+	0xff005555, /* MPMC_REG_77 */
+	0x00000007, /* MPMC_REG_78 */
+	0x00000000, /* MPMC_REG_79 */
+	0x00000000, /* MPMC_REG_80 */
+	0x00070000, /* MPMC_REG_81 */
+	0x00070007, /* MPMC_REG_82 */
+	0x00070007, /* MPMC_REG_83 */
+	0x00000000, /* MPMC_REG_84 */
+	0x00000000, /* MPMC_REG_85 */
+	0x00030000, /* MPMC_REG_86 */
+	0x00030003, /* MPMC_REG_87 */
+	0x00030003, /* MPMC_REG_88 */
+	0xffff0010, /* MPMC_REG_89 */
+	0x00000000, /* MPMC_REG_90 */
+	0x00000000, /* MPMC_REG_91 */
+	0x00000000, /* MPMC_REG_92 */
+	0x00000000, /* MPMC_REG_93 */
+	0x00000000, /* MPMC_REG_94 */
+	0x00000000, /* MPMC_REG_95 */
+	0x00c800a0, /* MPMC_REG_96 */
+	0x00000003, /* MPMC_REG_97 */
+	0x0053000a, /* MPMC_REG_98 */
+	0x000000c8, /* MPMC_REG_99 */
+	0x00000000, /* MPMC_REG_100 */
+	0x00000000, /* MPMC_REG_101 */
+	0x00000000, /* MPMC_REG_102 */
+	0x00000000, /* MPMC_REG_103 */
+	0x00000000, /* MPMC_REG_104 */
+	0x00000000, /* MPMC_REG_105 */
+	0x00000000, /* MPMC_REG_106 */
+	0x00000000, /* MPMC_REG_107 */
+	0x00000000, /* MPMC_REG_108 */
+	0x00000000, /* MPMC_REG_109 */
+	0x00000000, /* MPMC_REG_110 */
+	0x00000000, /* MPMC_REG_111 */
+	0x00013880, /* MPMC_REG_112 */
+	0x00000000, /* MPMC_REG_113 */
+	0x000000c8, /* MPMC_REG_114 */
+	0x00000050, /* MPMC_REG_115 */
+	0x00000050, /* MPMC_REG_116 */
+	0x00000050, /* MPMC_REG_117 */
+	0x00000050, /* MPMC_REG_118 */
+	0x00000050, /* MPMC_REG_119 */
+	0x00000050, /* MPMC_REG_120 */
+	0x00000000, /* MPMC_REG_121 */
+	0x00000000, /* MPMC_REG_122 */
+	0x000f1133, /* MPMC_REG_123 */
+	0x00386100, /* MPMC_REG_124 */
+	0x00386100, /* MPMC_REG_125 */
+	0x00386100, /* MPMC_REG_126 */
+	0x00386100, /* MPMC_REG_127 */
+	0x00386100, /* MPMC_REG_128 */
+	0x00000002, /* MPMC_REG_129 */
+	0x1208a108, /* MPMC_REG_130 */
+	0x1208a108, /* MPMC_REG_131 */
+	0x1208a108, /* MPMC_REG_132 */
+	0x1208a108, /* MPMC_REG_133 */
+	0x1208a108, /* MPMC_REG_134 */
+	0x01000000, /* MPMC_REG_135 */
+	0x01000000, /* MPMC_REG_136 */
+	0x01000000, /* MPMC_REG_137 */
+	0x01000000, /* MPMC_REG_138 */
+	0x01000000, /* MPMC_REG_139 */
+	0x01000000, /* MPMC_REG_140 */
+	0x01000000, /* MPMC_REG_141 */
+	0x01000000, /* MPMC_REG_142 */
+	0x01000000, /* MPMC_REG_143 */
+	0x01000000, /* MPMC_REG_144 */
+	0x06db6db6, /* MPMC_REG_145 */
+	0x06db6db6, /* MPMC_REG_146 */
+	0x06db6db6, /* MPMC_REG_147 */
+	0x06db6db6, /* MPMC_REG_148 */
+	0x06db6db6, /* MPMC_REG_149 */
+	0x00000000, /* MPMC_REG_150 */
+	0x00000000, /* MPMC_REG_151 */
+	0x00000000, /* MPMC_REG_152 */
+	0x00000000, /* MPMC_REG_153 */
+	0x00000000, /* MPMC_REG_154 */
+	0x2498a249, /* MPMC_REG_155 */
+	0x2498a249, /* MPMC_REG_156 */
+	0x2498a249, /* MPMC_REG_157 */
+	0x2498a249, /* MPMC_REG_158 */
+	0x2498a249, /* MPMC_REG_159 */
+	0x04803219, /* MPMC_REG_160 */
+	0x04803219, /* MPMC_REG_161 */
+	0x04803219, /* MPMC_REG_162 */
+	0x04803219, /* MPMC_REG_163 */
+	0x04803219, /* MPMC_REG_164 */
+	0x00000000, /* MPMC_REG_165 */
+	0x00000000, /* MPMC_REG_166 */
+	0x00000000, /* MPMC_REG_167 */
+	0x00000000, /* MPMC_REG_168 */
+	0x00000000, /* MPMC_REG_169 */
+	0x00000000, /* MPMC_REG_170 */
+	0x00000000, /* MPMC_REG_171 */
+	0x00000000, /* MPMC_REG_172 */
+	0x00000000, /* MPMC_REG_173 */
+	0x00000000, /* MPMC_REG_174 */
+	0x00000000, /* MPMC_REG_175 */
+	0x00000000, /* MPMC_REG_176 */
+	0x00000000, /* MPMC_REG_177 */
+	0x00000000, /* MPMC_REG_178 */
+	0x00000000, /* MPMC_REG_179 */
+	0x00000000, /* MPMC_REG_180 */
+	0x00000000, /* MPMC_REG_181 */
+	0x00000c2d, /* MPMC_REG_182 */
+	0x00000c2d, /* MPMC_REG_183 */
+	0x00000000, /* MPMC_REG_184 */
+	0x00000c2d, /* MPMC_REG_185 */
+	0x00000050, /* MPMC_REG_186 */
+	0x00000000, /* MPMC_REG_187 */
+	0x00000000, /* MPMC_REG_188 */
+	0x00000000, /* MPMC_REG_189 */
+	0x00000000, /* MPMC_REG_190 */
+	0x00000000, /* MPMC_REG_191 */
+	0x00000000, /* MPMC_REG_192 */
+	0x00000000, /* MPMC_REG_193 */
+	0x00000000, /* MPMC_REG_194 */
+	0x00000000, /* MPMC_REG_195 */
+	0x00000000, /* MPMC_REG_196 */
+	0x00000000, /* MPMC_REG_197 */
+	0x07000000, /* MPMC_REG_198 */
+	0x00000007, /* MPMC_REG_199 */
+	0x00000000, /* MPMC_REG_200 */
+	0x00006d60, /* MPMC_REG_201 */
+	0x0000004f, /* MPMC_REG_202 */
+	0x00000000, /* MPMC_REG_203 */
+	0x00000000, /* MPMC_REG_204 */
+	0x00000000, /* MPMC_REG_205 */
+	0x00000000, /* MPMC_REG_206 */
+	0x00003ce1, /* MPMC_REG_207 */
+};
+#endif
diff --git a/board/st/spear13xx/ddr/mt47h128m16rt187e_533_cl7_ddr2.c b/board/st/spear13xx/ddr/mt47h128m16rt187e_533_cl7_ddr2.c
new file mode 100644
index 0000000..3e3b2cd
--- /dev/null
+++ b/board/st/spear13xx/ddr/mt47h128m16rt187e_533_cl7_ddr2.c
@@ -0,0 +1,239 @@ 
+/*
+ * (C) Copyright 2000-2009
+ * Vikas Manocha, ST Microelectronics, vikas.manocha@st.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/hardware.h>
+
+#if defined(CONFIG_DDR_MT47H128M16) && \
+	defined(CONFIG_SPEAR_DDRFREQ533)
+const u32 mpmc_conf_vals[CONFIG_SPEAR_MPMCREGS] = {
+	0x00000100, /* MPMC_REG_00 */
+	0x00010100, /* MPMC_REG_01 */
+	0x01000000, /* MPMC_REG_02 */
+	0x00010100, /* MPMC_REG_03 */
+	0x00000000, /* MPMC_REG_04 */
+	0x00010100, /* MPMC_REG_05 */
+	0x00000001, /* MPMC_REG_06 */
+	0x00000000, /* MPMC_REG_07 */
+	0x00000000, /* MPMC_REG_08 */
+	0x00000000, /* MPMC_REG_09 */
+	0x00000000, /* MPMC_REG_10 */
+	0x00000101, /* MPMC_REG_11 */
+	0x00000101, /* MPMC_REG_12 */
+	0x01010000, /* MPMC_REG_13 */
+	0x00000000, /* MPMC_REG_14 */
+	0x01000000, /* MPMC_REG_15 */
+	0x00000000, /* MPMC_REG_16 */
+	0x00000000, /* MPMC_REG_17 */
+	0x00000201, /* MPMC_REG_18 */
+	0x02010000, /* MPMC_REG_19 */
+	0x00020000, /* MPMC_REG_20 */
+	0x03030001, /* MPMC_REG_21 */
+	0x02030301, /* MPMC_REG_22 */
+	0x03030303, /* MPMC_REG_23 */
+	0x03030403, /* MPMC_REG_24 */
+	0x03030305, /* MPMC_REG_25 */
+	0x00000400, /* MPMC_REG_26 */
+	0x02000200, /* MPMC_REG_27 */
+	0x06030202, /* MPMC_REG_28 */
+	0x01000104, /* MPMC_REG_29 */
+	0x03000000, /* MPMC_REG_30 */
+	0x0606060a, /* MPMC_REG_31 */
+	0x06060606, /* MPMC_REG_32 */
+	0x05050506, /* MPMC_REG_33 */
+	0x05050505, /* MPMC_REG_34 */
+	0x04040405, /* MPMC_REG_35 */
+	0x04040404, /* MPMC_REG_36 */
+	0x03030304, /* MPMC_REG_37 */
+	0x03030303, /* MPMC_REG_38 */
+	0x02020203, /* MPMC_REG_39 */
+	0x02020202, /* MPMC_REG_40 */
+	0x01010102, /* MPMC_REG_41 */
+	0x01010101, /* MPMC_REG_42 */
+	0x04000c01, /* MPMC_REG_43 */
+	0x00000002, /* MPMC_REG_44 */
+	0x00000204, /* MPMC_REG_45 */
+	0x04080700, /* MPMC_REG_46 */
+	0x02000606, /* MPMC_REG_47 */
+	0x0000000e, /* MPMC_REG_48 */
+	0x0f030207, /* MPMC_REG_49 */
+	0x0200000d, /* MPMC_REG_50 */
+	0x3f003f08, /* MPMC_REG_51 */
+	0x191d1800, /* MPMC_REG_52 */
+	0x00000028, /* MPMC_REG_53 */
+	0x00000000, /* MPMC_REG_54 */
+	0x00000000, /* MPMC_REG_55 */
+	0x00000000, /* MPMC_REG_56 */
+	0x00004000, /* MPMC_REG_57 */
+	0x03000000, /* MPMC_REG_58 */
+	0x03031903, /* MPMC_REG_59 */
+	0x07160704, /* MPMC_REG_60 */
+	0x00006400, /* MPMC_REG_61 */
+	0x00640064, /* MPMC_REG_62 */
+	0x00640064, /* MPMC_REG_63 */
+	0x000f0064, /* MPMC_REG_64 */
+	0x0000000a, /* MPMC_REG_65 */
+	0x00400100, /* MPMC_REG_66 */
+	0x10330200, /* MPMC_REG_67 */
+	0x02001033, /* MPMC_REG_68 */
+	0x02000200, /* MPMC_REG_69 */
+	0x10330200, /* MPMC_REG_70 */
+	0x0e730e73, /* MPMC_REG_71 */
+	0x00040004, /* MPMC_REG_72 */
+	0x00000000, /* MPMC_REG_73 */
+	0x00000000, /* MPMC_REG_74 */
+	0xff005555, /* MPMC_REG_75 */
+	0xaaaa00ff, /* MPMC_REG_76 */
+	0xff005555, /* MPMC_REG_77 */
+	0x00000007, /* MPMC_REG_78 */
+	0x00000000, /* MPMC_REG_79 */
+	0x00000000, /* MPMC_REG_80 */
+	0x00070000, /* MPMC_REG_81 */
+	0x00070007, /* MPMC_REG_82 */
+	0x00070007, /* MPMC_REG_83 */
+	0x00000000, /* MPMC_REG_84 */
+	0x00000000, /* MPMC_REG_85 */
+	0x00030000, /* MPMC_REG_86 */
+	0x00030003, /* MPMC_REG_87 */
+	0x00030003, /* MPMC_REG_88 */
+	0xffff0010, /* MPMC_REG_89 */
+	0x00000000, /* MPMC_REG_90 */
+	0x00000000, /* MPMC_REG_91 */
+	0x00000000, /* MPMC_REG_92 */
+	0x00000000, /* MPMC_REG_93 */
+	0x00000000, /* MPMC_REG_94 */
+	0x00000000, /* MPMC_REG_95 */
+	0x00c800d5, /* MPMC_REG_96 */
+	0x00000003, /* MPMC_REG_97 */
+	0x006f000d, /* MPMC_REG_98 */
+	0x000000c8, /* MPMC_REG_99 */
+	0x00000000, /* MPMC_REG_100 */
+	0x00000000, /* MPMC_REG_101 */
+	0x00000000, /* MPMC_REG_102 */
+	0x00000000, /* MPMC_REG_103 */
+	0x00000000, /* MPMC_REG_104 */
+	0x00000000, /* MPMC_REG_105 */
+	0x00000000, /* MPMC_REG_106 */
+	0x00000000, /* MPMC_REG_107 */
+	0x00000000, /* MPMC_REG_108 */
+	0x00000000, /* MPMC_REG_109 */
+	0x00000000, /* MPMC_REG_110 */
+	0x00000000, /* MPMC_REG_111 */
+	0x00019f8f, /* MPMC_REG_112 */
+	0x00000000, /* MPMC_REG_113 */
+	0x0000010a, /* MPMC_REG_114 */
+	0x00000050, /* MPMC_REG_115 */
+	0x00000050, /* MPMC_REG_116 */
+	0x00000050, /* MPMC_REG_117 */
+	0x00000050, /* MPMC_REG_118 */
+	0x00000050, /* MPMC_REG_119 */
+	0x00000050, /* MPMC_REG_120 */
+	0x00000000, /* MPMC_REG_121 */
+	0x00000000, /* MPMC_REG_122 */
+	0x000f1133, /* MPMC_REG_123 */
+	0x00486100, /* MPMC_REG_124 */
+	0x00486100, /* MPMC_REG_125 */
+	0x00486100, /* MPMC_REG_126 */
+	0x00486100, /* MPMC_REG_127 */
+	0x00486100, /* MPMC_REG_128 */
+	0x00000002, /* MPMC_REG_129 */
+	0x1208a108, /* MPMC_REG_130 */
+	0x1208a108, /* MPMC_REG_131 */
+	0x1208a108, /* MPMC_REG_132 */
+	0x1208a108, /* MPMC_REG_133 */
+	0x1208a108, /* MPMC_REG_134 */
+	0x01000000, /* MPMC_REG_135 */
+	0x01000000, /* MPMC_REG_136 */
+	0x01000000, /* MPMC_REG_137 */
+	0x01000000, /* MPMC_REG_138 */
+	0x01000000, /* MPMC_REG_139 */
+	0x01000000, /* MPMC_REG_140 */
+	0x01000000, /* MPMC_REG_141 */
+	0x01000000, /* MPMC_REG_142 */
+	0x01000000, /* MPMC_REG_143 */
+	0x01000000, /* MPMC_REG_144 */
+	0x06db6db6, /* MPMC_REG_145 */
+	0x06db6db6, /* MPMC_REG_146 */
+	0x06db6db6, /* MPMC_REG_147 */
+	0x06db6db6, /* MPMC_REG_148 */
+	0x06db6db6, /* MPMC_REG_149 */
+	0x00000000, /* MPMC_REG_150 */
+	0x00000000, /* MPMC_REG_151 */
+	0x00000000, /* MPMC_REG_152 */
+	0x00000000, /* MPMC_REG_153 */
+	0x00000000, /* MPMC_REG_154 */
+	0x2498a249, /* MPMC_REG_155 */
+	0x2498a249, /* MPMC_REG_156 */
+	0x2498a249, /* MPMC_REG_157 */
+	0x2498a249, /* MPMC_REG_158 */
+	0x2498a249, /* MPMC_REG_159 */
+	0x04803219, /* MPMC_REG_160 */
+	0x04803219, /* MPMC_REG_161 */
+	0x04803219, /* MPMC_REG_162 */
+	0x04803219, /* MPMC_REG_163 */
+	0x04803219, /* MPMC_REG_164 */
+	0x00000000, /* MPMC_REG_165 */
+	0x00000000, /* MPMC_REG_166 */
+	0x00000000, /* MPMC_REG_167 */
+	0x00000000, /* MPMC_REG_168 */
+	0x00000000, /* MPMC_REG_169 */
+	0x00000000, /* MPMC_REG_170 */
+	0x00000000, /* MPMC_REG_171 */
+	0x00000000, /* MPMC_REG_172 */
+	0x00000000, /* MPMC_REG_173 */
+	0x00000000, /* MPMC_REG_174 */
+	0x00000000, /* MPMC_REG_175 */
+	0x00000000, /* MPMC_REG_176 */
+	0x00000000, /* MPMC_REG_177 */
+	0x00000000, /* MPMC_REG_178 */
+	0x00000000, /* MPMC_REG_179 */
+	0x00000000, /* MPMC_REG_180 */
+	0x00000000, /* MPMC_REG_181 */
+	0x00001033, /* MPMC_REG_182 */
+	0x00001033, /* MPMC_REG_183 */
+	0x00000000, /* MPMC_REG_184 */
+	0x00001033, /* MPMC_REG_185 */
+	0x0000006b, /* MPMC_REG_186 */
+	0x00000000, /* MPMC_REG_187 */
+	0x00000000, /* MPMC_REG_188 */
+	0x00000000, /* MPMC_REG_189 */
+	0x00000000, /* MPMC_REG_190 */
+	0x00000000, /* MPMC_REG_191 */
+	0x00000000, /* MPMC_REG_192 */
+	0x00000000, /* MPMC_REG_193 */
+	0x00000000, /* MPMC_REG_194 */
+	0x00000000, /* MPMC_REG_195 */
+	0x00000000, /* MPMC_REG_196 */
+	0x00000000, /* MPMC_REG_197 */
+	0x07000000, /* MPMC_REG_198 */
+	0x00000007, /* MPMC_REG_199 */
+	0x00000000, /* MPMC_REG_200 */
+	0x00009173, /* MPMC_REG_201 */
+	0x0000006A, /* MPMC_REG_202 */
+	0x00000000, /* MPMC_REG_203 */
+	0x00000000, /* MPMC_REG_204 */
+	0x00000000, /* MPMC_REG_205 */
+	0x00000000, /* MPMC_REG_206 */
+	0x000050ff, /* MPMC_REG_207 */
+};
+#endif
diff --git a/board/st/spear13xx/spl-spear1340evb.c b/board/st/spear13xx/spl-spear1340evb.c
new file mode 100644
index 0000000..fb0c539
--- /dev/null
+++ b/board/st/spear13xx/spl-spear1340evb.c
@@ -0,0 +1,57 @@ 
+/*
+ * (C) Copyright 2012
+ * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/pinmux.h>
+
+void board_pre_ddrinit(void)
+{
+	/*
+	 * Several provisions are present on board for Power Management wrt DDR
+	 *
+	 * There are 4 controls with the board that it can manipulate
+	 *  - DDR_SHOFF_1V2 (PLGPIO 21): Shuts off DDR VDD 1V2
+	 *  - DDR_SHOFF_1V5 (PLGPIO 22): Shuts off DDR VDD 1V5
+	 *  - EN_DDR_CKE (PLGPIO 88): Enable DDR clock
+	 *  - EN_DDR_nRST (PLGPIO 89): Provide reset to the DDR
+	 */
+
+	/*
+	 * The selected configuration is as follows
+	 *  - DDR_SHOFF_1V2/1V5 : Enable both supply voltages (Enable pull down)
+	 *  - EN_DDR_CKE, EN_DDR_nRST : Force 0 in GPIO output mode
+	 *    (Additionally, activate pull down on both signals)
+	 */
+	spear1340_configure_pin(21, PMX_PULLDOWN);
+	spear1340_configure_pin(22, PMX_PULLDOWN);
+
+	spear1340_configure_pin(88, PMX_GPIO);
+	spear1340_configure_pin(89, PMX_GPIO);
+	spear1340_plgpio_set(88, 0);
+	spear1340_plgpio_set(89, 0);
+
+	/* Activate PULL DOWN on both EN_DDR_CKE and EN_DDR_nRST */
+	spear1340_configure_pin(88, PMX_PULLDOWN);
+	spear1340_configure_pin(89, PMX_PULLDOWN);
+}
diff --git a/include/configs/spear1340-evb.h b/include/configs/spear1340-evb.h
index 05ae8fb..a5335a3 100644
--- a/include/configs/spear1340-evb.h
+++ b/include/configs/spear1340-evb.h
@@ -87,6 +87,11 @@ 
 #define CONFIG_NAND_FSMC
 #define CONFIG_SYS_FSMC_NAND_8BIT
 
+/* SPL support */
+#define CONFIG_SPL
+#define CONFIG_DDR_MT41J256M8
+#define CONFIG_SPEAR_DDRFREQ533
+
 /* Environment Variable configs */
 #if defined(CONFIG_ENV_IS_IN_FLASH)
 	/* Environment is in serial NOR flash */
diff --git a/include/configs/spear13xx.h b/include/configs/spear13xx.h
index fc40e14..19fc04f 100644
--- a/include/configs/spear13xx.h
+++ b/include/configs/spear13xx.h
@@ -64,9 +64,58 @@ 
 #if defined(CONFIG_ARMV7_CA9LTIMER)
 #endif
 
-/* Internal memory address for spear3xx */
+/* Internal memory address for spear13xx */
 #define CONFIG_SYS_INIT_SP_ADDR			(0xB3800000 + 0x8000 - \
 						GENERATED_GBL_DATA_SIZE)
 
+/* SPL configurations */
+#if defined(CONFIG_SPL)
+	#if !defined(CONFIG_SPL_TEXT_BASE)
+		#define CONFIG_SPL_TEXT_BASE		0xB3801504
+	#endif
+	#if !defined(CONFIG_SYS_SNOR_BOOT_BASE)
+		#define CONFIG_SYS_SNOR_BOOT_BASE	0xE6010000
+	#endif
+	#if !defined(CONFIG_SYS_NAND_BOOT_BASE)
+		#define CONFIG_SYS_NAND_BOOT_BASE	0x00080000
+	#endif
+	#if !defined(CONFIG_SYS_PNOR_BOOT_BASE)
+		#define CONFIG_SYS_PNOR_BOOT_BASE	0xA0020000
+	#endif
+	#if !defined(CONFIG_SYS_MMC_BOOT_FILE)
+		#define CONFIG_SYS_MMC_BOOT_FILE	"u-boot.img"
+	#endif
+
+	#define CONFIG_SPEAR13XX_ARM2PHOLD		0xB3800600
+	#define CONFIG_SPEAR13XX_ARM2STACK		0xB3800100
+
+	#define CONFIG_SPL_NO_CPU_SUPPORT_CODE
+	#define CONFIG_SPL_LIBCOMMON_SUPPORT
+	#define CONFIG_SPL_LIBGENERIC_SUPPORT
+	#define CONFIG_SPL_MTD_SUPPORT
+	#define CONFIG_SPL_START_S_PATH	"arch/arm/cpu/armv7/spear13xx"
+	#define CONFIG_SPL_LDSCRIPT	\
+			"arch/arm/cpu/armv7/spear13xx/u-boot-spl.lds"
+
+	#if defined(CONFIG_DDR_ECC_ENABLE)
+		#define CONFIG_C3
+		#define CONFIG_SPL_MISC_SUPPORT
+	#endif
+
+	#if defined(CONFIG_DDR_MT41J64M16) || \
+		defined(CONFIG_DDR_MT41J256M8) || \
+		defined(CONFIG_DDR_H5TQ2G63BFRPBC) || \
+		defined(CONFIG_DDR_K4B2G1646CK0) || \
+		defined(CONFIG_DDR_MT41J128M16)
+
+		#define CONFIG_DDR3
+	#elif defined(CONFIG_DDR_MT47H128M16)
+
+		#define CONFIG_DDR2
+	#else
+		#error Define a supported DDR
+	#endif
+#endif
+
 #include <configs/spear.h>
 #endif /* __CONFIG_SPEAR13XX_H */
diff --git a/spl/Makefile b/spl/Makefile
index e38467a..78cb0a6 100644
--- a/spl/Makefile
+++ b/spl/Makefile
@@ -39,6 +39,7 @@  ifdef SOC
 LIBS-y += $(CPUDIR)/$(SOC)/lib$(SOC).o
 endif
 LIBS-y += board/$(BOARDDIR)/lib$(BOARD).o
+
 LIBS-$(HAVE_VENDOR_COMMON_LIB) += board/$(VENDOR)/common/lib$(VENDOR).o
 
 LIBS-$(CONFIG_SPL_FRAMEWORK) += common/spl/libspl.o
@@ -53,6 +54,7 @@  LIBS-$(CONFIG_SPL_SPI_SUPPORT) += drivers/spi/libspi.o
 LIBS-$(CONFIG_SPL_FAT_SUPPORT) += fs/fat/libfat.o
 LIBS-$(CONFIG_SPL_LIBGENERIC_SUPPORT) += lib/libgeneric.o
 LIBS-$(CONFIG_SPL_POWER_SUPPORT) += drivers/power/libpower.o
+LIBS-$(CONFIG_SPL_MTD_SUPPORT) += drivers/mtd/libmtd.o
 LIBS-$(CONFIG_SPL_NAND_SUPPORT) += drivers/mtd/nand/libnand.o
 LIBS-$(CONFIG_SPL_ONENAND_SUPPORT) += drivers/mtd/onenand/libonenand.o
 LIBS-$(CONFIG_SPL_DMA_SUPPORT) += drivers/dma/libdma.o
@@ -65,6 +67,10 @@  ifeq ($(BOARD),spear)
 LIBS-y += board/$(BOARDDIR)/ddr/lib$(BOARD)ddr.o
 endif
 
+ifeq ($(BOARD),spear13xx)
+LIBS-y += board/$(BOARDDIR)/ddr/lib$(BOARD)ddr.o
+endif
+
 ifneq ($(CONFIG_AM33XX)$(CONFIG_OMAP34XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX),)
 LIBS-y += $(CPUDIR)/omap-common/libomap-common.o
 endif