From patchwork Fri Nov 2 17:39:20 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Subject: [U-Boot,SPEAr13xx,1/7] spear1340: Add support for spear1340 SoC Date: Fri, 02 Nov 2012 07:39:20 -0000 From: Vipin Kumar X-Patchwork-Id: 196707 Message-Id: To: Cc: sr@denx.de, spear-devel@list.st.com spear1340 is a CortexA9 dual core SoC which supports multiple peripherals like GMII, USBH etc. More information can be found at http://www.st.com/internet/mcu/product/251211.jsp This patch adds support for spear1340 SoC. It also adds support for pinum for spear1340. The APIs implemented for this purpose are * _void spear1340_configure_pin(u32 plgpio, u32 mode)_ * _int spear1340_plgpio_get(u32 plgpio)_ * _void spear1340_plgpio_set(u32 plgpio, u32 val)_ Signed-off-by: Vipin Kumar --- arch/arm/cpu/armv7/spear13xx/Makefile | 50 +++ arch/arm/cpu/armv7/spear13xx/reset.c | 47 +++ arch/arm/cpu/armv7/spear13xx/spear1340-pinmux.c | 439 +++++++++++++++++++++ arch/arm/cpu/armv7/spear13xx/spear1340.c | 270 +++++++++++++ arch/arm/cpu/armv7/spear13xx/spear13xx.c | 32 ++ arch/arm/include/asm/arch-spear13xx/generic.h | 33 ++ arch/arm/include/asm/arch-spear13xx/gpio.h | 42 ++ arch/arm/include/asm/arch-spear13xx/hardware.h | 31 ++ arch/arm/include/asm/arch-spear13xx/misc.h | 31 ++ arch/arm/include/asm/arch-spear13xx/mmc.h | 29 ++ arch/arm/include/asm/arch-spear13xx/pinmux.h | 104 +++++ arch/arm/include/asm/arch-spear13xx/spear1340.h | 159 ++++++++ .../include/asm/arch-spear13xx/spear1340_misc.h | 331 ++++++++++++++++ arch/arm/include/asm/arch-spear13xx/spear13xx.h | 46 +++ drivers/usb/host/ehci-spear.c | 2 + include/linux/bitops.h | 12 + 16 files changed, 1658 insertions(+) create mode 100644 arch/arm/cpu/armv7/spear13xx/Makefile create mode 100644 arch/arm/cpu/armv7/spear13xx/reset.c create mode 100644 arch/arm/cpu/armv7/spear13xx/spear1340-pinmux.c create mode 100644 arch/arm/cpu/armv7/spear13xx/spear1340.c create mode 100644 arch/arm/cpu/armv7/spear13xx/spear13xx.c create mode 100644 arch/arm/include/asm/arch-spear13xx/generic.h create mode 100644 arch/arm/include/asm/arch-spear13xx/gpio.h create mode 100644 arch/arm/include/asm/arch-spear13xx/hardware.h create mode 100644 arch/arm/include/asm/arch-spear13xx/misc.h create mode 100644 arch/arm/include/asm/arch-spear13xx/mmc.h create mode 100644 arch/arm/include/asm/arch-spear13xx/pinmux.h create mode 100644 arch/arm/include/asm/arch-spear13xx/spear1340.h create mode 100644 arch/arm/include/asm/arch-spear13xx/spear1340_misc.h create mode 100644 arch/arm/include/asm/arch-spear13xx/spear13xx.h diff --git a/arch/arm/cpu/armv7/spear13xx/Makefile b/arch/arm/cpu/armv7/spear13xx/Makefile new file mode 100644 index 0000000..214b89b --- /dev/null +++ b/arch/arm/cpu/armv7/spear13xx/Makefile @@ -0,0 +1,50 @@ +# +# (C) Copyright 2000-2003 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# (C) Copyright 2008 +# Guennadi Liakhovetki, DENX Software Engineering, +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(SOC).o + +COBJS-$(CONFIG_ARCH_SPEAR13XX) += spear13xx.o +COBJS-$(CONFIG_SOC_SPEAR1340) += spear1340.o +COBJS-$(CONFIG_SOC_SPEAR1340) += spear1340-pinmux.o + +SRCS := $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS-y)) + +all: $(obj).depend $(LIB) + +$(LIB): $(OBJS) + $(call cmd_link_o_target, $(OBJS)) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/arch/arm/cpu/armv7/spear13xx/reset.c b/arch/arm/cpu/armv7/spear13xx/reset.c new file mode 100644 index 0000000..09fbfa9 --- /dev/null +++ b/arch/arm/cpu/armv7/spear13xx/reset.c @@ -0,0 +1,47 @@ +/* + * (C) Copyright 2012 + * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include + +void reset_cpu(ulong ignored) +{ + struct misc_regs *misc_regs_p = + (struct misc_regs *)CONFIG_SYS_MISC_BASE; + + printf("System is going to reboot ...\n"); + + /* + * This 1 second delay will allow the above message + * to be printed before reset + */ + udelay((1000 * 1000)); + + writel(0x01, &misc_regs_p->sys_sw_res); + + /* system will restart */ + while (1) + ; +} diff --git a/arch/arm/cpu/armv7/spear13xx/spear1340-pinmux.c b/arch/arm/cpu/armv7/spear13xx/spear1340-pinmux.c new file mode 100644 index 0000000..1c92beb --- /dev/null +++ b/arch/arm/cpu/armv7/spear13xx/spear1340-pinmux.c @@ -0,0 +1,439 @@ +/* + * (C) Copyright 2012 + * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include + +/* Pin multiplexing for fsmc nand 16 bit device */ +static void enable_nand16bit_pins(void) +{ + pinmux_maskval(SPEAR1340_PAD_SHARED_IP_EN_1, + KBD_ROW_COL_MASK, + 0); + pinmux_maskval(SPEAR1340_PAD_FUNCTION_EN_1, + FSMC_16_BIT_AND_KBD_ROW_COL_REG0_MASK, + FSMC_16_BIT_AND_KBD_ROW_COL_REG0_MASK); +} + +/* Pin multiplexing for fsmc nand 8 bit device */ +static void enable_nand8bit_pins(void) +{ + pinmux_maskval(SPEAR1340_PAD_FUNCTION_EN_8, + FSMC_8BIT_REG7_MASK, + FSMC_8BIT_REG7_MASK); +} + +/* Pin multiplexing for fsmc nand device */ +static void enable_nand_pins(u32 mode) +{ + switch (mode) { + case PMX_NAND_8BIT: + enable_nand8bit_pins(); + break; + case PMX_NAND_16BIT: + enable_nand16bit_pins(); + } +} + +/* Pin multiplexing for smi device */ +static void enable_smi_pins(void) +{ + pinmux_maskval(SPEAR1340_PAD_FUNCTION_EN_3, + SMI_REG2_MASK, + SMI_REG2_MASK); +} + +/* Pin multiplexing for ssp0 device */ +static void enable_ssp0cs0_pins(void) +{ + pinmux_maskval(SPEAR1340_PAD_FUNCTION_EN_3, + SSP0_REG2_MASK, + SSP0_REG2_MASK); +} + +/* Pin multiplexing for ssp0 chip select 1 */ +static void enable_ssp0cs1_pins(void) +{ + enable_ssp0cs0_pins(); + + pinmux_maskval(SPEAR1340_PAD_SHARED_IP_EN_1, + SSP0_CS1_MASK, + SSP0_CS1_MASK); + pinmux_maskval(SPEAR1340_PAD_FUNCTION_EN_1, + PWM0_AND_SSP0_CS1_REG0_MASK, + PWM0_AND_SSP0_CS1_REG0_MASK); +} + +/* Pin multiplexing for ssp0 chip select 2 */ +static void enable_ssp0cs2_pins(void) +{ + enable_ssp0cs0_pins(); + + pinmux_maskval(SPEAR1340_PAD_SHARED_IP_EN_1, + SSP0_CS2_MASK, + SSP0_CS2_MASK); + pinmux_maskval(SPEAR1340_PAD_FUNCTION_EN_3, + TS_AND_SSP0_CS2_REG2_MASK, + TS_AND_SSP0_CS2_REG2_MASK); +} + +/* Pin multiplexing for ssp0 chip select 3 */ +static void enable_ssp0cs3_pins(void) +{ + enable_ssp0cs0_pins(); + + pinmux_maskval(SPEAR1340_PAD_FUNCTION_EN_5, + SSP0_CS3_REG4_MASK, + SSP0_CS3_REG4_MASK); +} + +static void enable_ssp0_pins(u32 mode) +{ + switch (mode) { + case PMX_SSP_CS0: + enable_ssp0cs0_pins(); + break; + case PMX_SSP_CS1: + enable_ssp0cs1_pins(); + break; + case PMX_SSP_CS2: + enable_ssp0cs2_pins(); + break; + case PMX_SSP_CS3: + enable_ssp0cs3_pins(); + break; + } +} + +/* Pin multiplexing for uart0 device */ +static void enable_uart0simple_pins(void) +{ + pinmux_maskval(SPEAR1340_PAD_FUNCTION_EN_3, + UART0_REG2_MASK, + UART0_REG2_MASK); +} + +/* Pin multiplexing for uart0 enhanced (modem) device */ +static void enable_uart0_enh_pins(void) +{ + pinmux_maskval(SPEAR1340_PAD_SHARED_IP_EN_1, + GPT_MASK, + 0); + pinmux_maskval(SPEAR1340_PAD_FUNCTION_EN_1, + UART0_ENH_AND_GPT_REG0_MASK, + UART0_ENH_AND_GPT_REG0_MASK); +} + +static void enable_uart0_pins(u32 mode) +{ + switch (mode) { + case PMX_UART_SIMPLE: + enable_uart0simple_pins(); + break; + case PMX_UART_MODEM: + enable_uart0_enh_pins(); + break; + } +} + +/* Pin multiplexing for uart1 device */ +static void enable_uart1_pins(void) +{ + pinmux_maskval(SPEAR1340_PAD_FUNCTION_EN_3, + UART1_REG2_MASK, + UART1_REG2_MASK); +} + +/* Pin multiplexing for fsmc-prallel nor device */ +static void enable_fsmcpnor_pins(void) +{ + pinmux_maskval(SPEAR1340_PAD_SHARED_IP_EN_1, + MCIF_MASK, + 0); + pinmux_maskval(SPEAR1340_PAD_FUNCTION_EN_7, + FSMC_PNOR_AND_MCIF_REG6_MASK, + FSMC_PNOR_AND_MCIF_REG6_MASK); +} + +/* + * Pin multiplexing for ethernet device + * Ethernet on spear1340 can be configured as either of the below + * - GMII + * - RGMII + * - RMII + * - SGMII + */ +static void enable_miicommon_pins(void) +{ + pinmux_maskval(SPEAR1340_PAD_FUNCTION_EN_4, + GMAC_REG3_MASK, + GMAC_REG3_MASK); + pinmux_maskval(SPEAR1340_PAD_FUNCTION_EN_5, + GMAC_REG4_MASK, + GMAC_REG4_MASK); +} + +static void enable_gmii_pins(void) +{ + enable_miicommon_pins(); + + pinmux_maskval(SPEAR1340_GMAC_CLK_CFG, + GMAC_PHY_IF_SEL_MASK, + GMAC_PHY_IF_GMII_VAL); +} + +static void enable_rgmii_pins(void) +{ + enable_miicommon_pins(); + + pinmux_maskval(SPEAR1340_GMAC_CLK_CFG, + GMAC_PHY_IF_SEL_MASK, + GMAC_PHY_IF_RGMII_VAL); +} + +static void enable_rmii_pins(void) +{ + enable_miicommon_pins(); + + pinmux_maskval(SPEAR1340_GMAC_CLK_CFG, + GMAC_PHY_IF_SEL_MASK, + GMAC_PHY_IF_RMII_VAL); +} + +static void enable_sgmii_pins(void) +{ + enable_miicommon_pins(); + + pinmux_maskval(SPEAR1340_GMAC_CLK_CFG, + GMAC_PHY_IF_SEL_MASK, + GMAC_PHY_IF_SGMII_VAL); +} + +static void enable_eth0_pins(u32 mode) +{ + switch (mode) { + case PMX_ETH_GMII: + enable_gmii_pins(); + break; + case PMX_ETH_RGMII: + enable_rgmii_pins(); + break; + case PMX_ETH_RMII: + enable_rmii_pins(); + break; + case PMX_ETH_SGMII: + enable_sgmii_pins(); + break; + } +} + +/* Pin multiplexing for i2c0 device */ +static void enable_i2c0_pins(void) +{ + pinmux_maskval(SPEAR1340_PAD_FUNCTION_EN_5, + I2C0_REG4_MASK, + I2C0_REG4_MASK); +} + +/* Pin multiplexing for i2c1 device */ +static void enable_i2c1_pins(void) +{ + pinmux_maskval(SPEAR1340_PAD_FUNCTION_EN_1, + I2C1_REG0_MASK, + I2C1_REG0_MASK); +} + +/* Pin multiplexing for sdmmc device */ +static void enable_sdmmc_pins(void) +{ + pinmux_maskval(SPEAR1340_PAD_SHARED_IP_EN_1, + MCIF_MASK, + MCIF_MASK); + pinmux_maskval(SPEAR1340_PAD_FUNCTION_EN_7, + FSMC_PNOR_AND_MCIF_REG6_MASK | MCIF_REG6_MASK, + FSMC_PNOR_AND_MCIF_REG6_MASK | MCIF_REG6_MASK); + pinmux_maskval(SPEAR1340_PAD_FUNCTION_EN_8, + MCIF_REG7_MASK, + MCIF_REG7_MASK); + pinmux_maskval(SPEAR1340_PERIP_CFG, + MCIF_SEL_MASK, + MCIF_SEL_SD); +} + +/** + * spear1340_pins_default: Select a default safe mode as startup + * Generally, all pins are enabled in input mode at initialization. This can be + * done either by + * - enabling gpio's and keeping all pins in gpio inputs + * - a platform specific way. + */ +void spear1340_pins_default(void) +{ + pinmux_maskval(SPEAR1340_PAD_FUNCTION_EN_1, + PADS_AS_GPIO_REG0_MASK, + 0x0); + pinmux_maskval(SPEAR1340_PAD_FUNCTION_EN_2, + PADS_AS_GPIO_REGS_MASK, + 0x0); + pinmux_maskval(SPEAR1340_PAD_FUNCTION_EN_3, + PADS_AS_GPIO_REGS_MASK, + 0x0); + pinmux_maskval(SPEAR1340_PAD_FUNCTION_EN_4, + PADS_AS_GPIO_REGS_MASK, + 0x0); + pinmux_maskval(SPEAR1340_PAD_FUNCTION_EN_5, + PADS_AS_GPIO_REGS_MASK, + 0x0); + pinmux_maskval(SPEAR1340_PAD_FUNCTION_EN_6, + PADS_AS_GPIO_REGS_MASK, + 0x0); + pinmux_maskval(SPEAR1340_PAD_FUNCTION_EN_7, + PADS_AS_GPIO_REGS_MASK, + 0x0); + pinmux_maskval(SPEAR1340_PAD_FUNCTION_EN_8, + PADS_AS_GPIO_REG7_MASK, + 0x0); +} + +/** + * spear1340_enable_pins - enable pins for peripherals on spear1340 devices + * @ip: Peripheral index + * @mode: Mode in which peripheral has to run (16bit/8bit etc) + * + * Enable the pins for fixed peripherals on spear3xx devices. + * mode represents the mode in which the peripheral may work and may result in + * different pins being enabled. eg GMII mode and RGMII mode may need different + * pins on devices to be enabled + */ +void spear1340_enable_pins(u32 ip, u32 mode) +{ + if (PMX_SDMMC == ip) + enable_sdmmc_pins(); + else if (PMX_SMI == ip) + enable_smi_pins(); + else if (PMX_I2C0 == ip) + enable_i2c0_pins(); + else if (PMX_I2C1 == ip) + enable_i2c1_pins(); + else if (PMX_UART1 == ip) + enable_uart1_pins(); + else if (PMX_FSMCPNOR == ip) + enable_fsmcpnor_pins(); + else if (PMX_FSMCNAND == ip) + enable_nand_pins(mode); + else if (PMX_UART0 == ip) + enable_uart0_pins(mode); + else if (PMX_ETH0 == ip) + enable_eth0_pins(mode); + else if (PMX_SSP0 == ip) + enable_ssp0_pins(mode); +} + +static void configure_gpio(u32 plgpio) +{ + if (plgpio > SPEAR1340_MAX_PLGPIOS) + return; + + /* Set the pin to GPIO IN mode */ + pinmux_set_bit(plgpio, SPEAR1340_PLGPIO_EN0); + + /* Put the pin in gpio state */ + if (plgpio < 127) + pinmux_clear_bit(plgpio + 1, SPEAR1340_PAD_FUNCTION_EN_1); + else + pinmux_clear_bit(plgpio + 1, SPEAR1340_PAD_FUNCTION_EN_5); +} + +static void configure_pullup(u32 plgpio) +{ + if (plgpio > SPEAR1340_MAX_PLGPIOS) + return; + + /* Deactivate pull down */ + pinmux_set_bit(plgpio, SPEAR1340_PAD_PD_CFG_1); + + /* Activate pull up */ + pinmux_clear_bit(plgpio, SPEAR1340_PAD_PU_CFG_1); +} + +static void configure_pulldown(u32 plgpio) +{ + if (plgpio > SPEAR1340_MAX_PLGPIOS) + return; + + /* Deactivate pull up */ + pinmux_set_bit(plgpio, SPEAR1340_PAD_PU_CFG_1); + + /* Activate pull down */ + pinmux_clear_bit(plgpio, SPEAR1340_PAD_PD_CFG_1); +} + +/** + * spear1340_configure_pin - Configure pin on spear1340 devices + * @plgpio: Pin Number (plgpio number) + * @mode: Pull UP, Pull DOWN, plgpio IN, plgpio OUT etc + */ +void spear1340_configure_pin(u32 plgpio, u32 mode) +{ + if (PMX_GPIO == mode) + configure_gpio(plgpio); + else if (PMX_PULLUP == mode) + configure_pullup(plgpio); + else if (PMX_PULLDOWN == mode) + configure_pulldown(plgpio); +} + +/** + * spear1340_plgpio_get - Get the gpio input + * @plgpio: Pin Number (plgpio number) + */ +int spear1340_plgpio_get(u32 plgpio) +{ + if (plgpio > SPEAR1340_MAX_PLGPIOS) + return -1; + + /* Set the pin to GPIO IN mode */ + pinmux_set_bit(plgpio, SPEAR1340_PLGPIO_EN0); + + return pinmux_test_bit(plgpio, SPEAR1340_PLGPIO_IN0); +} + +/** + * spear1340_plgpio_set - Set the gpio value + * @plgpio: Pin Number (plgpio number) + */ +void spear1340_plgpio_set(u32 plgpio, u32 val) +{ + if (plgpio > SPEAR1340_MAX_PLGPIOS) + return; + + if (val & 0x1) + pinmux_set_bit(plgpio, SPEAR1340_PLGPIO_OUT0); + else + pinmux_clear_bit(plgpio, SPEAR1340_PLGPIO_OUT0); + + /* Set the pin to GPIO OUT mode */ + pinmux_clear_bit(plgpio, SPEAR1340_PLGPIO_EN0); +} diff --git a/arch/arm/cpu/armv7/spear13xx/spear1340.c b/arch/arm/cpu/armv7/spear13xx/spear1340.c new file mode 100644 index 0000000..ca4626e --- /dev/null +++ b/arch/arm/cpu/armv7/spear13xx/spear1340.c @@ -0,0 +1,270 @@ +/* + * (C) Copyright 2012 + * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include + +int arch_cpu_init(void) +{ + struct spear1340_misc_regs *const misc_p = + (struct spear1340_misc_regs *)CONFIG_SYS_MISC_BASE; + u32 perip1_clk_enb, perip2_clk_enb; + u32 perip_clk_cfg; +#if defined(CONFIG_SDHCI) + u32 perip_cfg; +#endif +#if defined(CONFIG_NAND_FSMC) + u32 fsmc_cfg; +#endif +#if defined(CONFIG_DESIGNWARE_ETH) + u32 gmac_clk_cfg; +#endif + + perip1_clk_enb = readl(&misc_p->perip1_clk_enb); + perip2_clk_enb = readl(&misc_p->perip2_clk_enb); + +#if defined(CONFIG_PL011_SERIAL) + /* select USB PLL 48 MHz as the src clock */ + perip_clk_cfg = readl(&misc_p->perip_clk_cfg); + perip_clk_cfg &= ~SPEAR1340_UARTCLKMSK; + perip_clk_cfg |= SPEAR1340_UART48M; + writel(perip_clk_cfg, &misc_p->perip_clk_cfg); + + perip1_clk_enb |= SPEAR1340_UART_CLKEN; +#endif + +#if defined(CONFIG_DESIGNWARE_ETH) + gmac_clk_cfg = readl(&misc_p->gmac_clk_cfg); + gmac_clk_cfg &= ~SPEAR1340_CLKSEL_MSK; + gmac_clk_cfg |= SPEAR1340_CLKSEL_PLL2; + writel(gmac_clk_cfg, &misc_p->gmac_clk_cfg); + + perip1_clk_enb |= SPEAR1340_GETH_CLKEN; +#endif + +#if defined(CONFIG_DW_UDC) + perip1_clk_enb |= SPEAR1340_UDC_UPD_CLKEN; +#endif + +#if defined(CONFIG_USB_EHCI_SPEAR) + perip1_clk_enb |= SPEAR1340_UHC1_CLKEN; +#endif + +#if defined(CONFIG_DW_I2C) + perip1_clk_enb |= SPEAR1340_I2C_CLKEN; +#endif + +#if defined(CONFIG_ST_SMI) + perip1_clk_enb |= SPEAR1340_SMI_CLKEN; +#endif + +#if defined(CONFIG_PL022_SPI) + perip1_clk_enb |= SPEAR1340_SSP_CLKEN; +#endif + +#if defined(CONFIG_SDHCI) + perip_cfg = readl(&misc_p->perip_cfg); + perip_cfg &= ~SPEAR1340_MCIF_MSK; + perip_cfg |= SPEAR1340_MCIF_SD; + writel(perip_cfg, &misc_p->perip_cfg); + + writel(SPEAR1340_SYNT_X_2 | SPEAR1340_SYNT_Y_21 | SPEAR1340_SYNT_CLKENB, + &misc_p->mcif_sd_clk_synt); + + perip1_clk_enb |= SPEAR1340_SD_CLKEN; +#endif + +#if defined(CONFIG_NAND_FSMC) + fsmc_cfg = readl(&misc_p->fsmc_cfg); + fsmc_cfg &= ~SPEAR1340_DEV_SEL_MSK; + fsmc_cfg |= SPEAR1340_DEV_SEL_NAND; +#if defined(CONFIG_SYS_FSMC_NAND_16BIT) + fsmc_cfg |= SPEAR1340_DEV_WIDTH_16; +#elif defined(CONFIG_SYS_FSMC_NAND_8BIT) + fsmc_cfg |= SPEAR1340_DEV_WIDTH_8; +#endif + writel(fsmc_cfg, &misc_p->fsmc_cfg); + + perip1_clk_enb |= SPEAR1340_FSMC_CLKEN; +#endif + + writel(perip1_clk_enb, &misc_p->perip1_clk_enb); + writel(perip2_clk_enb, &misc_p->perip2_clk_enb); + +#if defined(CONFIG_ST_SMI) + smi_init(); +#endif + return 0; +} + +#ifdef CONFIG_DISPLAY_CPUINFO +int print_cpuinfo(void) +{ + printf("CPU: SPEAr1340\n"); + return 0; +} +#endif + +#if defined(CONFIG_PL022_SPI) +int spi_cs_is_valid(unsigned int bus, unsigned int cs) +{ + struct spear1340_misc_regs *misc_regs_p = + (struct spear1340_misc_regs *)CONFIG_SYS_MISC_BASE; + u32 perip_cfg; + + perip_cfg = readl(&misc_regs_p->perip_cfg); + perip_cfg &= ~SPEAR1340_SSP_CS_EN_MSK; + perip_cfg |= cs << SPEAR1340_SSP_CS_EN_SHFT; + + perip_cfg |= SPEAR1340_HS_SSP_SW_CS; + perip_cfg |= SPEAR1340_HS_SSP_EN; + writel(perip_cfg, &misc_regs_p->perip_cfg); + + return 1; +} + +void spi_cs_activate(struct spi_slave *slave) +{ + struct spear1340_misc_regs *misc_regs_p = + (struct spear1340_misc_regs *)CONFIG_SYS_MISC_BASE; + u32 perip_cfg; + + perip_cfg = readl(&misc_regs_p->perip_cfg); + perip_cfg &= ~SPEAR1340_HS_SSP_SW_CS; + writel(perip_cfg, &misc_regs_p->perip_cfg); +} + +void spi_cs_deactivate(struct spi_slave *slave) +{ + struct spear1340_misc_regs *misc_regs_p = + (struct spear1340_misc_regs *)CONFIG_SYS_MISC_BASE; + u32 perip_cfg; + + perip_cfg = readl(&misc_regs_p->perip_cfg); + perip_cfg |= SPEAR1340_HS_SSP_SW_CS; + writel(perip_cfg, &misc_regs_p->perip_cfg); +} +#endif + +#if defined(CONFIG_USB_EHCI_SPEAR) +void spear1340_usbh_stop(void) +{ + struct spear1340_misc_regs *const misc_regs_p = + (struct spear1340_misc_regs *)CONFIG_SYS_MISC_BASE; + u32 perip1_sw_rst = readl(&misc_regs_p->perip1_sw_rst); + + perip1_sw_rst |= SPEAR1340_UHC1_SWRST; + writel(perip1_sw_rst, &misc_regs_p->perip1_sw_rst); + + udelay(1000); + perip1_sw_rst &= ~SPEAR1340_UHC1_SWRST; + writel(perip1_sw_rst, &misc_regs_p->perip1_sw_rst); +} +#endif + +#ifdef CONFIG_DW_OTG_PHYINIT +void udc_phy_init(void) +{ + struct spear1340_misc_regs *const misc_regs_p = + (struct spear1340_misc_regs *)CONFIG_SYS_MISC_BASE; + u32 temp; + ulong start; + + /* phy por assert */ + temp = readl(&misc_regs_p->usbphy_gen_cfg); + temp |= SPEAR1340_USBPHY_POR; + writel(temp, &misc_regs_p->usbphy_gen_cfg); + udelay(1); + + /* phy clock disable */ + temp = readl(&misc_regs_p->usbphy_gen_cfg); + temp &= ~SPEAR1340_USBPHY_RST; + writel(temp, &misc_regs_p->usbphy_gen_cfg); + + udelay(150); + + /* phy por deassert */ + temp = readl(&misc_regs_p->usbphy_gen_cfg); + temp &= ~SPEAR1340_USBPHY_POR; + writel(temp, &misc_regs_p->usbphy_gen_cfg); + udelay(1); + + /* phy clock enable */ + temp = readl(&misc_regs_p->usbphy_gen_cfg); + temp |= SPEAR1340_USBPHY_RST; + writel(temp, &misc_regs_p->usbphy_gen_cfg); + + start = get_timer(0); + + while (get_timer(start) < CONFIG_SYS_HZ) { + if (readl(&misc_regs_p->usbphy_gen_cfg) & + SPEAR1340_USB_PLL_LOCK) + break; + + /* Try after 10 ms */ + udelay(10); + }; + + /* wait for pll to stabilize */ + udelay(1); + + /* OTG HCLK Disable */ + temp = readl(&misc_regs_p->perip1_clk_enb); + temp &= ~SPEAR1340_UDC_UPD_CLKEN; + writel(temp, &misc_regs_p->perip1_clk_enb); + + /* OTG HRESET deassert */ + temp = readl(&misc_regs_p->perip1_sw_rst); + temp &= ~SPEAR1340_UDC_UPD_SWRST; + writel(temp, &misc_regs_p->perip1_sw_rst); + + /* OTG HCLK Enable */ + temp = readl(&misc_regs_p->perip1_clk_enb); + temp |= SPEAR1340_UDC_UPD_CLKEN; + writel(temp, &misc_regs_p->perip1_clk_enb); +} +#endif + +void reset_cpu(ulong ignored) +{ + struct spear1340_misc_regs *misc_regs_p = + (struct spear1340_misc_regs *)CONFIG_SYS_MISC_BASE; + + printf("System is going to reboot ...\n"); + + /* + * This 1 second delay will allow the above message + * to be printed before reset + */ + udelay((1000 * 1000)); + + writel(0x01, &misc_regs_p->sys_sw_res); + + /* system will restart */ + while (1) + ; +} diff --git a/arch/arm/cpu/armv7/spear13xx/spear13xx.c b/arch/arm/cpu/armv7/spear13xx/spear13xx.c new file mode 100644 index 0000000..351e8cd --- /dev/null +++ b/arch/arm/cpu/armv7/spear13xx/spear13xx.c @@ -0,0 +1,32 @@ +/* + * (C) Copyright 2012 + * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +void enable_caches(void) +{ +#ifndef CONFIG_SYS_DCACHE_OFF + /* Enable D-cache. I-cache is already enabled in start.S */ + dcache_enable(); +#endif +} diff --git a/arch/arm/include/asm/arch-spear13xx/generic.h b/arch/arm/include/asm/arch-spear13xx/generic.h new file mode 100644 index 0000000..7beb1c2 --- /dev/null +++ b/arch/arm/include/asm/arch-spear13xx/generic.h @@ -0,0 +1,33 @@ +/* + * (C) Copyright 2012 + * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __ARCH_ARM_GENERIC_H__ +#define __ARCH_ARM_GENERIC_H__ + +#if defined(CONFIG_SOC_SPEAR1310) +extern void spear1310_usbh_stop(void); +#elif defined(CONFIG_SOC_SPEAR1340) +extern void spear1340_usbh_stop(void); +#endif + +#endif diff --git a/arch/arm/include/asm/arch-spear13xx/gpio.h b/arch/arm/include/asm/arch-spear13xx/gpio.h new file mode 100644 index 0000000..59cc88f --- /dev/null +++ b/arch/arm/include/asm/arch-spear13xx/gpio.h @@ -0,0 +1,42 @@ +/* + * Copyright (C) 2012 Stefan Roese + * + * Copied from arch/arm/include/asm/arch-spear/gpio.h + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + + +#ifndef __ASM_ARCH_SPEAR_GPIO_H +#define __ASM_ARCH_SPEAR_GPIO_H + +enum gpio_direction { + GPIO_DIRECTION_IN, + GPIO_DIRECTION_OUT, +}; + +struct gpio_regs { + u32 gpiodata[0x100]; /* 0x000 ... 0x3fc */ + u32 gpiodir; /* 0x400 */ +}; + +#define SPEAR_GPIO_COUNT 8 +#define DATA_REG_ADDR(gpio) (1 << (gpio + 2)) + +#endif /* __ASM_ARCH_SPEAR_GPIO_H */ diff --git a/arch/arm/include/asm/arch-spear13xx/hardware.h b/arch/arm/include/asm/arch-spear13xx/hardware.h new file mode 100644 index 0000000..b49ef67 --- /dev/null +++ b/arch/arm/include/asm/arch-spear13xx/hardware.h @@ -0,0 +1,31 @@ +/* + * (C) Copyright 2012 + * Vipin Kumar, STMicroelectronics, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _ASM_ARCH_HARDWARE_H +#define _ASM_ARCH_HARDWARE_H + +#if defined(CONFIG_SOC_SPEAR1340) +#include +#endif + +#endif /* _ASM_ARCH_HARDWARE_H */ diff --git a/arch/arm/include/asm/arch-spear13xx/misc.h b/arch/arm/include/asm/arch-spear13xx/misc.h new file mode 100644 index 0000000..5134938 --- /dev/null +++ b/arch/arm/include/asm/arch-spear13xx/misc.h @@ -0,0 +1,31 @@ +/* + * (C) Copyright 2012 + * Vipin Kumar, ST Microelectronics, vipin.kumar@st.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _ASM_ARCH_MISC_H +#define _ASM_ARCH_MISC_H + +#ifdef CONFIG_SOC_SPEAR1340 +#include +#endif + +#endif diff --git a/arch/arm/include/asm/arch-spear13xx/mmc.h b/arch/arm/include/asm/arch-spear13xx/mmc.h new file mode 100644 index 0000000..5c01a7e --- /dev/null +++ b/arch/arm/include/asm/arch-spear13xx/mmc.h @@ -0,0 +1,29 @@ +/* + * (C) Copyright 2012 + * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _ASM_ARCH_MMC_H +#define _ASM_ARCH_MMC_H + +extern int spear_sdhci_init(u32 regbase, u32 max_clk, u32 min_clk, u32 quirks); + +#endif diff --git a/arch/arm/include/asm/arch-spear13xx/pinmux.h b/arch/arm/include/asm/arch-spear13xx/pinmux.h new file mode 100644 index 0000000..9354f21 --- /dev/null +++ b/arch/arm/include/asm/arch-spear13xx/pinmux.h @@ -0,0 +1,104 @@ +/* + * (C) Copyright 2012 + * Vipin Kumar, ST Microelectronics, vipin.kumar@st.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _ASM_ARCH_PINMUX_H +#define _ASM_ARCH_PINMUX_H + +#include +#include +#include + +static inline void pinmux_maskval(ulong reg, u32 mask, u32 val) +{ + u32 temp = readl((u32 *)reg); + temp &= ~mask; + temp |= val & mask; + writel(temp, (u32 *)reg); +} + +static inline void pinmux_set_bit(int nr, unsigned long addr) +{ + __set_bit(nr, (volatile unsigned long *)addr); +} + +static inline void pinmux_clear_bit(int nr, unsigned long addr) +{ + __clear_bit(nr, (volatile unsigned long *)addr); +} + +static inline int pinmux_test_bit(int nr, unsigned long addr) +{ + return __test_bit(nr, (volatile unsigned long *)addr); +} + +enum pinmux_ip { + PMX_UART0, + PMX_UART1, + PMX_UART2, + PMX_UART3, + PMX_UART4, + PMX_UART5, + PMX_I2C0, + PMX_I2C1, + PMX_I2C2, + PMX_SSP0, + PMX_SSP1, + PMX_SSP2, + PMX_ETH0, + PMX_ETH1, + PMX_ETH2, + PMX_FSMCNAND, + PMX_FSMCPNOR, + PMX_SDMMC, + PMX_EMI, + PMX_SMI, +}; + +/* UART0 modem modes */ +#define PMX_UART_SIMPLE 1 +#define PMX_UART_MODEM 2 + +/* SSP modes */ +#define PMX_SSP_CS0 1 +#define PMX_SSP_CS1 2 +#define PMX_SSP_CS2 3 +#define PMX_SSP_CS3 4 + +/* ETH modes */ +#define PMX_ETH_GMII 1 +#define PMX_ETH_MII 2 +#define PMX_ETH_RGMII 3 +#define PMX_ETH_RMII 4 +#define PMX_ETH_SGMII 5 +#define PMX_ETH_SMII 6 + +/* NAND modes */ +#define PMX_NAND_8BIT 1 +#define PMX_NAND_16BIT 2 + +/* PLGPIO modes */ +#define PMX_GPIO 1 +#define PMX_PULLUP 2 +#define PMX_PULLDOWN 3 + +#endif diff --git a/arch/arm/include/asm/arch-spear13xx/spear1340.h b/arch/arm/include/asm/arch-spear13xx/spear1340.h new file mode 100644 index 0000000..c595607 --- /dev/null +++ b/arch/arm/include/asm/arch-spear13xx/spear1340.h @@ -0,0 +1,159 @@ +/* + * (C) Copyright 2012 + * Vipin Kumar, ST Microelectronics, vipin.kumar@st.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _ASM_ARCH_SPEAR1340_PINMUX_H +#define _ASM_ARCH_SPEAR1340_PINMUX_H + +#include + +/* Macros to select an interface within a peripheral pins */ +#define SPEAR1340_PERIP_CFG (CONFIG_SYS_MISC_BASE + 0x42C) + /* PERIP_CFG register masks */ + #define MCIF_SEL_SD 1 + #define MCIF_SEL_CF 2 + #define MCIF_SEL_XD 3 + #define MCIF_SEL_MASK 3 + #define MCIF_SEL_SHIFT 0 + +#define SPEAR1340_GMAC_CLK_CFG (CONFIG_SYS_MISC_BASE + 0x248) + #define GMAC_PHY_IF_GMII_VAL (0 << 3) + #define GMAC_PHY_IF_RGMII_VAL (1 << 3) + #define GMAC_PHY_IF_SGMII_VAL (2 << 3) + #define GMAC_PHY_IF_RMII_VAL (4 << 3) + #define GMAC_PHY_IF_SEL_MASK (7 << 3) + +/* + * Macro's for first level of pmx - pads as gpio OR peripherals. There are 8 + * registers with 32 bits each for handling gpio pads, register 8 has only 26 + * relevant bits. + */ +#define SPEAR1340_PAD_FUNCTION_EN_1 (CONFIG_SYS_MISC_BASE + 0x668) +#define SPEAR1340_PAD_FUNCTION_EN_2 (CONFIG_SYS_MISC_BASE + 0x66C) +#define SPEAR1340_PAD_FUNCTION_EN_3 (CONFIG_SYS_MISC_BASE + 0x670) +#define SPEAR1340_PAD_FUNCTION_EN_4 (CONFIG_SYS_MISC_BASE + 0x674) +#define SPEAR1340_PAD_FUNCTION_EN_5 (CONFIG_SYS_MISC_BASE + 0x690) +#define SPEAR1340_PAD_FUNCTION_EN_6 (CONFIG_SYS_MISC_BASE + 0x694) +#define SPEAR1340_PAD_FUNCTION_EN_7 (CONFIG_SYS_MISC_BASE + 0x698) +#define SPEAR1340_PAD_FUNCTION_EN_8 (CONFIG_SYS_MISC_BASE + 0x69C) + /* macro's for making pads as gpio's */ + #define PADS_AS_GPIO_REG0_MASK 0xFFFFFFFE + #define PADS_AS_GPIO_REGS_MASK 0xFFFFFFFF + #define PADS_AS_GPIO_REG7_MASK 0x07FFFFFF + /* macro's for making pads as peripherals */ + #define FSMC_16_BIT_AND_KBD_ROW_COL_REG0_MASK 0x00000FFE + #define UART0_ENH_AND_GPT_REG0_MASK 0x0003F000 + #define PWM1_AND_KBD_COL5_REG0_MASK 0x00040000 + #define I2C1_REG0_MASK 0x01080000 + #define SPDIF_IN_REG0_MASK 0x00100000 + #define PWM2_AND_GPT0_TMR0_CPT_REG0_MASK 0x00400000 + #define PWM3_AND_GPT0_TMR1_CLK_REG0_MASK 0x00800000 + #define PWM0_AND_SSP0_CS1_REG0_MASK 0x02000000 + #define VIP_AND_CAM3_REG0_MASK 0xFC200000 + #define VIP_AND_CAM3_REG1_MASK 0x0000000F + #define VIP_REG1_MASK 0x00001EF0 + #define VIP_AND_CAM2_REG1_MASK 0x007FE100 + #define VIP_AND_CAM1_REG1_MASK 0xFF800000 + #define VIP_AND_CAM1_REG2_MASK 0x00000003 + #define VIP_AND_CAM0_REG2_MASK 0x00001FFC + #define SMI_REG2_MASK 0x0021E000 + #define SSP0_REG2_MASK 0x001E0000 + #define TS_AND_SSP0_CS2_REG2_MASK 0x00400000 + #define UART0_REG2_MASK 0x01800000 + #define UART1_REG2_MASK 0x06000000 + #define I2S_IN_REG2_MASK 0xF8000000 + #define DEVS_GRP_AND_MIPHY_DBG_REG3_MASK 0x000001FE + #define I2S_OUT_REG3_MASK 0x000001EF + #define I2S_IN_REG3_MASK 0x00000010 + #define GMAC_REG3_MASK 0xFFFFFE00 + #define GMAC_REG4_MASK 0x0000001F + #define DEVS_GRP_AND_MIPHY_DBG_REG4_MASK 0x7FFFFF20 + #define SSP0_CS3_REG4_MASK 0x00000020 + #define I2C0_REG4_MASK 0x000000C0 + #define CEC0_REG4_MASK 0x00000100 + #define CEC1_REG4_MASK 0x00000200 + #define SPDIF_OUT_REG4_MASK 0x00000400 + #define CLCD_REG4_MASK 0x7FFFF800 + #define CLCD_AND_ARM_TRACE_REG4_MASK 0x80000000 + #define CLCD_AND_ARM_TRACE_REG5_MASK 0xFFFFFFFF + #define CLCD_AND_ARM_TRACE_REG6_MASK 0x00000001 + #define FSMC_PNOR_AND_MCIF_REG6_MASK 0x073FFFFE + #define MCIF_REG6_MASK 0xF8C00000 + #define MCIF_REG7_MASK 0x000043FF + #define FSMC_8BIT_REG7_MASK 0x07FFBC00 + + + +/* - If peripherals, then primary OR alternate peripheral */ +#define SPEAR1340_PAD_SHARED_IP_EN_1 (CONFIG_SYS_MISC_BASE + 0x6A0) +#define SPEAR1340_PAD_SHARED_IP_EN_2 (CONFIG_SYS_MISC_BASE + 0x6A4) + /* + * Macro's for second level of pmx + * - pads as primary OR alternate peripheral + */ + /* Write 0 to enable FSMC_16_BIT */ + #define KBD_ROW_COL_MASK (1 << 0) + /* Write 0 to enable UART0_ENH */ + #define GPT_MASK (1 << 1) + /* Write 0 to enable PWM1 */ + #define KBD_COL5_MASK (1 << 2) + /* Write 0 to enable PWM2 */ + #define GPT0_TMR0_CPT_MASK (1 << 3) + /* Write 0 to enable PWM3 */ + #define GPT0_TMR1_CLK_MASK (1 << 4) + /* Write 0 to enable PWM0 */ + #define SSP0_CS1_MASK (1 << 5) + /* Write 0 to enable VIP */ + #define CAM3_MASK (1 << 6) + /* Write 0 to enable VIP */ + #define CAM2_MASK (1 << 7) + /* Write 0 to enable VIP */ + #define CAM1_MASK (1 << 8) + /* Write 0 to enable VIP */ + #define CAM0_MASK (1 << 9) + /* Write 0 to enable TS */ + #define SSP0_CS2_MASK (1 << 10) + /* Write 0 to enable FSMC PNOR */ + #define MCIF_MASK (1 << 11) + /* Write 0 to enable CLCD */ + #define ARM_TRACE_MASK (1 << 12) + /* Write 0 to enable I2S, SSP0_CS2, CEC0, 1, SPDIF out, CLCD */ + #define MIPHY_DBG_MASK (1 << 13) + +/* Pull DOWN and Pull UP */ +#define SPEAR1340_PAD_PU_CFG_1 (CONFIG_SYS_MISC_BASE + 0x600) +#define SPEAR1340_PAD_PD_CFG_1 (CONFIG_SYS_MISC_BASE + 0x620) + +/* Macro's to configure plgpios as Pull UP, Pull Down */ +#define CONFIG_SYS_PLGPIO_BASE 0xE2800000 + #define SPEAR1340_PLGPIO_EN0 (CONFIG_SYS_PLGPIO_BASE + 0x00) + #define SPEAR1340_PLGPIO_IN0 (CONFIG_SYS_PLGPIO_BASE + 0x20) + #define SPEAR1340_PLGPIO_OUT0 (CONFIG_SYS_PLGPIO_BASE + 0x40) + #define SPEAR1340_MAX_PLGPIOS 249 + +extern void spear1340_pins_default(void); +extern void spear1340_enable_pins(u32 ip, u32 mode); +extern void spear1340_configure_pin(u32 plgpio, u32 mode); +extern void spear1340_plgpio_set(u32 plgpio, u32 val); +extern int spear1340_plgpio_get(u32 plgpio); + +#endif diff --git a/arch/arm/include/asm/arch-spear13xx/spear1340_misc.h b/arch/arm/include/asm/arch-spear13xx/spear1340_misc.h new file mode 100644 index 0000000..090de1c --- /dev/null +++ b/arch/arm/include/asm/arch-spear13xx/spear1340_misc.h @@ -0,0 +1,331 @@ +/* + * (C) Copyright 2012 + * Vipul Kumar Samar, ST Microelectronics, vipulkumar.samar@st.com + * Vipin Kumar, ST Microelectronics, vipin.kumar@st.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __SPEAR1340_MISC_H +#define __SPEAR1340_MISC_H + +struct spear1340_misc_regs { + u32 soc_cfg; /* 0x000 */ + u32 bootstrap_cfg; /* 0x004 */ + u8 reserved_1[0x100 - 0x8]; + u32 pcm_cfg; /* 0x100 */ + u32 pcm_wkup_cfg; /* 0x104 */ + u32 switch_ctr; /* 0x108 */ + u8 reserved_2[0x200 - 0x10c]; + u32 sys_clk_ctrl; /* 0x200 */ + u32 sys_sw_res; /* 0x204 */ + u32 sys_clk_plltimer; /* 0x208 */ + u32 sys_clk_oscitimer; /* 0x20c */ + u32 pll_cfg; /* 0x210 */ + u32 pll1_ctr; /* 0x214 */ + u32 pll1_frq; /* 0x218 */ + u32 pll1_mod; /* 0x21c */ + u32 pll2_ctr; /* 0x220 */ + u32 pll2_frq; /* 0x224 */ + u32 pll2_mod; /* 0x228 */ + u32 pll3_ctr; /* 0x22c */ + u32 pll3_frq; /* 0x230 */ + u32 pll3_mod; /* 0x234 */ + u32 pll4_ctr; /* 0x238 */ + u32 pll4_frq; /* 0x23C */ + u32 pll4_mod; /* 0x240 */ + u32 perip_clk_cfg; /* 0x244 */ + u32 gmac_clk_cfg; /* 0x248 */ + u32 i2s_clk_cfg; /* 0x24c */ + u32 c3_clk_synt; /* 0x250 */ + u32 uart1_clk_synt; /* 0x254 */ + u32 uart2_clk_synt; /* 0x258 */ + u32 gmac_clk_synt; /* 0x25c */ + u32 mcif_sd_clk_synt; /* 0x260 */ + u32 mcif_cfxd_clk_synt; /* 0x264 */ + u32 cec1_clk_synt; /* 0x268 */ + u32 cec2_clk_synt; /* 0x26c */ + u32 adc_clk_synt; /* 0x270 */ + u32 amba_clk_sscg; /* 0x274 */ + u32 amba_clk_sscg_mod; /* 0x278 */ + u32 clcd_clk_sscg; /* 0x27c */ + u32 clcd_clk_sscg_mod; /* 0x280 */ + u32 cpu_clk_sscg; /* 0x284 */ + u32 cpu_clk_sscg_mod; /* 0x288 */ + u32 gen_clk_sscg0; /* 0x28C */ + u32 gen_clk_sscg0_mod; /* 0x290 */ + u32 gen_clk_sscg1; /* 0x294 */ + u32 gen_clk_sscg1_mod; /* 0x298 */ + u32 gen_clk_sscg2; /* 0x29c */ + u8 reserved_3[0x300 - 0x2A0]; + u32 gen_clk_sscg2_mod; /* 0x300 */ + u32 gen_clk_sscg3; /* 0x304 */ + u32 gen_clk_sscg3_mod; /* 0x308 */ + u32 perip1_clk_enb; /* 0x30c */ + u32 perip2_clk_enb; /* 0x310 */ + u32 perip3_clk_enb; /* 0x314 */ + u32 perip1_sw_rst; /* 0x318 */ + u32 perip2_sw_rst; /* 0x31c */ + u32 perip3_sw_rst; /* 0x320 */ + u8 reserved_4[0x400 - 0x324]; + u32 dmac_hs_sel; /* 0x400 */ + u32 dmac_sel; /* 0x404 */ + u32 dmac_flow_sel; /* 0x408 */ + u32 dmac_dir_sel; /* 0x40c */ + u32 endianess_cfg; /* 0x410 */ + u32 usbphy_gen_cfg; /* 0x414 */ + u32 usbphy_p1_cfg; /* 0x418 */ + u32 usbphy_p2_cfg; /* 0x41c */ + u32 usbphy_p3_cfg; /* 0x420 */ + u32 pcie_sata_cfg; /* 0x424 */ + u32 pcie_miphy_cfg; /* 0x428 */ + u32 perip_cfg; /* 0x42c */ + u32 fsmc_cfg; /* 0x430 */ + u32 mpmc_cfg; /* 0x434 */ + u32 mpmc_ctr_sts; /* 0x438 */ + u32 sata_core_id; /* 0x43c */ + u32 mali_gen_purpose_1; /* 0x440 */ + u32 mali_gen_purpose_2; /* 0x444 */ + u8 reserved_5[0x500 - 0x448]; + u32 prc1_lock_ctr; /* 0x500 */ + u32 prc2_lock_ctr; /* 0x504 */ + u32 prc1_irq_ctr; /* 0x508 */ + u8 reserved_6[0x51c - 0x50c]; + u32 prc2_irq_ctr; /* 0x51c */ + u8 reserved_7[0x600 - 0x520]; + u32 pad_pu_cfg_1; /* 0x600 */ + u32 pad_pu_cfg_2; /* 0x604 */ + u32 pad_pu_cfg_3; /* 0x608 */ + u32 pad_pu_cfg_4; /* 0x60c */ + u32 pad_pu_cfg_5; /* 0x610 */ + u32 pad_pu_cfg_6; /* 0x614 */ + u32 pad_pu_cfg_7; /* 0x618 */ + u32 pad_pu_cfg_8; /* 0x61c */ + u32 pad_pd_cfg_1; /* 0x620 */ + u32 pad_pd_cfg_2; /* 0x624 */ + u32 pad_pd_cfg_3; /* 0x628 */ + u32 pad_pd_cfg_4; /* 0x62c */ + u32 pad_pd_cfg_5; /* 0x630 */ + u32 pad_pd_cfg_6; /* 0x634 */ + u32 pad_pd_cfg_7; /* 0x638 */ + u32 pad_pd_cfg_8; /* 0x63c */ + u8 reserved_8[0x648 - 0x640]; + u32 pad_drv_cfg_1; /* 0x648 */ + u32 pad_drv_cfg_2; /* 0x64c */ + u32 pad_drv_cfg_3; /* 0x650 */ + u32 pad_drv_cfg_4; /* 0x654 */ + u32 pad_drv_cfg_5; /* 0x658 */ + u32 pad_slew_cfg_1; /* 0x65c */ + u32 pad_slew_cfg_2; /* 0x660 */ + u32 pad_slew_cfg_3; /* 0x664 */ + u32 pad_function_en_1; /* 0x668 */ + u32 pad_function_en_2; /* 0x66c */ + u32 pad_function_en_3; /* 0x670 */ + u32 pad_function_en_4; /* 0x674 */ + u8 reserved_9[0x690 - 0x678]; + u32 pad_function_en_5; /* 0x690 */ + u32 pad_function_en_6; /* 0x694 */ + u32 pad_function_en_7; /* 0x698 */ + u32 pad_function_en_8; /* 0x69c */ + u32 pad_shared_ip_en_1; /* 0x6A0 */ + u32 pad_shared_ip_en_2; /* 0x6A4 */ + u32 ddr_pad_cfg; /* 0x6A8 */ + u8 reserved_10[0x700 - 0x6Ac]; + u32 compensation_1v8_3v3_1_cfg; /* 0x700 */ + u32 compensation_1v8_3v3_2_cfg; /* 0x704 */ + u32 compensation_3v3_1_cfg; /* 0x708 */ + u32 compensation_3v3_2_cfg; /* 0x70c */ + u32 compensation_ddr_cfg; /* 0x710 */ + u32 compensation_2v5_3v3_1_cfg; /* 0x714 */ + u8 reserved_11[0x800 - 0x718]; + u32 otp_prog_ctr; /* 0x800 */ + u32 otp_wdata1_1; /* 0x804 */ + u32 otp_wdata1_2; /* 0x808 */ + u32 otp_wdata1_3; /* 0x80c */ + u32 otp_wdata1_4; /* 0x810 */ + u32 otp_wdata1_5; /* 0x814 */ + u32 otp_wdata1_6; /* 0x818 */ + u32 otp_wdata1_7; /* 0x81c */ + u32 otp_wdata1_8; /* 0x820 */ + u32 otp_wdata2_1; /* 0x824 */ + u32 otp_wdata2_2; /* 0x828 */ + u32 otp_wdata2_3; /* 0x82c */ + u32 otp_wdata2_4; /* 0x830 */ + u32 otp_wdata2_5; /* 0x834 */ + u32 otp_wdata2_6; /* 0x838 */ + u32 otp_wdata2_7; /* 0x83c */ + u32 otp_wdata2_8; /* 0x840 */ + u32 otp_mask_1; /* 0x844 */ + u32 otp_mask_2; /* 0x848 */ + u32 otp_mask_3; /* 0x84c */ + u32 otp_mask_4; /* 0x850 */ + u32 otp_mask_5; /* 0x854 */ + u32 otp_mask_6; /* 0x858 */ + u32 otp_mask_7; /* 0x85c */ + u32 otp_mask_8; /* 0x860 */ + u32 otp_rdata1_1; /* 0x864 */ + u32 otp_rdata1_2; /* 0x868 */ + u32 otp_rdata1_3; /* 0x86c */ + u32 otp_rdata1_4; /* 0x870 */ + u32 otp_rdata1_5; /* 0x874 */ + u32 otp_rdata1_6; /* 0x878 */ + u32 otp_rdata1_7; /* 0x87c */ + u32 otp_rdata1_8; /* 0x880 */ + u32 otp_rdata2_1; /* 0x884 */ + u32 otp_rdata2_2; /* 0x888 */ + u32 otp_rdata2_3; /* 0x88c */ + u32 otp_rdata2_4; /* 0x890 */ + u32 otp_rdata2_5; /* 0x894 */ + u32 otp_rdata2_6; /* 0x898 */ + u32 otp_rdata2_7; /* 0x89c */ + u32 otp_rdata2_8; /* 0x8a0 */ + u32 otp_rdatam_1; /* 0x8a4 */ + u32 otp_rdatam_2; /* 0x8a8 */ + u32 otp_rdatam_3; /* 0x8ac */ + u32 otp_rdatam_4; /* 0x8b0 */ + u32 otp_rdatam_5; /* 0x8b4 */ + u32 otp_rdatam_6; /* 0x8b8 */ + u32 otp_rdatam_7; /* 0x8bc */ + u32 otp_rdatam_8; /* 0x8c0 */ + u32 thsens_cfg; /* 0x8c4 */ + u8 reserved_12[0x900 - 0x8c8]; + u32 a9sm_clusterid; /* 0x900 */ + u32 a9sm_status; /* 0x904 */ + u32 a9sm_debug; /* 0x908 */ + u32 a9sm_filter; /* 0x90c */ + u32 a9sm_parity_cfg; /* 0x910 */ + u32 a9sm_parity_err; /* 0x914 */ + u8 reserved_13[0xa00 - 0x918]; + u32 die_id_1; /* 0xa00 */ + u32 die_id_2; /* 0xa04 */ + u32 die_id_3; /* 0xa08 */ + u32 die_id_4; /* 0xa0c */ + u8 reserved_14[0xc00 - 0xa10]; + u32 axi_cache_user_ctrl_0; /* 0xc00 */ + u32 axi_cache_user_ctrl_1; /* 0xc04 */ + u32 axi_cache_user_ctrl_2; /* 0xc08 */ + u32 axi_cache_user_ctrl_3; /* 0xc0c */ + u32 ahb_cache_user_ctrl_0; /* 0xc10 */ + u32 ahb_cache_user_ctrl_1; /* 0xc14 */ + u32 ahb_cache_user_ctrl_2; /* 0xc18 */ + u32 ahb_cache_user_ctrl_3; /* 0xc1c */ + u32 ahb_cache_user_ctrl_4; /* 0xc20 */ + u32 ahb_cache_user_ctrl_5; /* 0xc24 */ + u32 ahb_cache_user_ctrl_6; /* 0xc28 */ + u32 ahb_cache_user_ctrl_7; /* 0xc2c */ + u8 reserved_15[0x1000 - 0xc30]; + u32 miphy_test; /* 0x1000 */ + u32 usb_test; /* 0x1004 */ + u32 misc_cfg; /* 0x1008 */ +}; + +/* PHERIP1_CLOCK ENABLE */ +#define SPEAR1340_C3_CLKEN 0x20000000 +#define SPEAR1340_GPT1_CLKEN 0x00200000 +#define SPEAR1340_I2C_CLKEN 0x00040000 +#define SPEAR1340_SSP_CLKEN 0x00020000 +#define SPEAR1340_UART_CLKEN 0x00008000 +#define SPEAR1340_UDC_UPD_CLKEN 0x00000800 +#define SPEAR1340_UHC1_CLKEN 0x00000200 +#define SPEAR1340_GETH_CLKEN 0x00000100 +#define SPEAR1340_SD_CLKEN 0x00000040 +#define SPEAR1340_SMI_CLKEN 0x00000020 +#define SPEAR1340_FSMC_CLKEN 0x00000010 + +/* perip1_sw_rst */ +#define SPEAR1340_C3_SWRST 0x20000000 +#define SPEAR1340_UDC_UPD_SWRST 0x00000800 +#define SPEAR1340_UHC1_SWRST 0x00000200 + +#define SPEAR1340_SYS_MODE_MASK 0x00000007 +#define SPEAR1340_SYS_MODE_DOZE 0x00000001 +#define SPEAR1340_SYS_MODE_SLOW 0x00000002 +#define SPEAR1340_SYS_MODE_NORMAL 0x00000004 +#define SPEAR1340_PLL_TIMEOUT_ENB 0x00000008 +#define SPEAR1340_XTAL_TIMEOUT_ENB 0x00000010 +#define SPEAR1340_SYS_STATE_MASK 0x000F0000 +#define SPEAR1340_SYS_STATE_NORMAL 0x000F0000 + +/* sys_clk_*timer definitions */ +#define SPEAR1340_PLL_TIM 0x000007f8 +#define SPEAR1340_OSCI_TIM 0x000007f8 + +/* pll_freq definitions in MHz */ +#define SPEAR1340_FREQ_1000 0x7D000006 +#define SPEAR1340_FREQ_996 0x53000004 +#define SPEAR1340_FREQ_332 0x53000203 + +/* pll_ctr definitions */ +#define SPEAR1340_PLLLOCK 0x00000001 +#define SPEAR1340_PLLENABLE 0x00000004 + +/* perip_clk_cfg definitions */ +#define SPEAR1340_GPTCLKSRC 0x00000100 +#define SPEAR1340_UARTCLKMSK 0x00000030 +#define SPEAR1340_UART48M 0x00000000 + +/* gmac_clk_cfg definitions */ +#define SPEAR1340_PHYIF_MSK 0x00000038 +#define SPEAR1340_PHYIF_RMII 0x00000020 +#define SPEAR1340_PHYIF_SGMII 0x00000010 +#define SPEAR1340_PHYIF_RGMII 0x00000008 +#define SPEAR1340_PHYIF_GMII 0x00000000 +#define SPEAR1340_GMII_SYNT_ENB 0x00000004 +#define SPEAR1340_CLKSEL_MSK 0x00000003 +#define SPEAR1340_CLKSEL_OSCI3 0x00000002 +#define SPEAR1340_CLKSEL_PLL2 0x00000001 +#define SPEAR1340_CLKSEL_PAD 0x00000000 + +/* usbphy_gen_cfg definitions */ +#define SPEAR1340_USB_PLL_LOCK 0x01000000 +#define SPEAR1340_USBPHY_RST 0x00008000 +#define SPEAR1340_USBPHY_PRSNT 0x00002000 +#define SPEAR1340_USBPHY_POR 0x00001000 +#define SPEAR1340_COMMON_PWDN 0x00000000 + +/* perip_cfg definitions */ +#define SPEAR1340_HS_SSP_EN 0x00200000 +#define SPEAR1340_HS_SSP_SW_CS 0x00100000 +#define SPEAR1340_SSP_CS_EN_MSK 0x000C0000 +#define SPEAR1340_SSP_CS_EN_SHFT 18 +#define SPEAR1340_MCIF_MSK 0x00000003 +#define SPEAR1340_MCIF_SD 0x00000001 + +/* fsmc_cfg definitions */ +#define SPEAR1340_DEV_SEL_NOR 0x00000000 +#define SPEAR1340_DEV_SEL_NAND 0x00000001 +#define SPEAR1340_DEV_SEL_SRAM 0x00000002 +#define SPEAR1340_DEV_SEL_MSK 0x00000003 +#define SPEAR1340_NAND_BANK_0 0x00000000 +#define SPEAR1340_NAND_BANK_1 0x00000004 +#define SPEAR1340_NAND_BANK_2 0x00000008 +#define SPEAR1340_NAND_BANK_3 0x0000000C +#define SPEAR1340_DEV_WIDTH_8 0x00000000 +#define SPEAR1340_DEV_WIDTH_16 0x00000010 + +/* synth registers definitions */ +#define SPEAR1340_SYNT_CLKENB 0x80000000 +#define SPEAR1340_SYNT_FINFULL 0x04000000 +#define SPEAR1340_SYNT_X_1 0x00010000 +#define SPEAR1340_SYNT_X_2 0x00020000 +#define SPEAR1340_SYNT_Y_2 0x00000002 +#define SPEAR1340_SYNT_Y_5 0x00000005 +#define SPEAR1340_SYNT_Y_21 0x00000015 + +#endif diff --git a/arch/arm/include/asm/arch-spear13xx/spear13xx.h b/arch/arm/include/asm/arch-spear13xx/spear13xx.h new file mode 100644 index 0000000..a4fca51 --- /dev/null +++ b/arch/arm/include/asm/arch-spear13xx/spear13xx.h @@ -0,0 +1,46 @@ +/* + * (C) Copyright 2012 + * Vipin Kumar, STMicroelectronics, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _ASM_ARCH_SPEAR13XX_H +#define _ASM_ARCH_SPEAR13XX_H + +#define CONFIG_SPEAR_CORTEXBASE 0xEC800000 +#define CONFIG_ARMV7_LTIMER_BASE (CONFIG_SPEAR_CORTEXBASE + 0x600) + +#define CONFIG_SYS_C3_BASE 0xE1800000 +#define CONFIG_SYS_USBD_BASE 0xE3800000 +#define CONFIG_SYS_UHC0_EHCI_BASE 0xE4800000 +#define CONFIG_SYS_UHC1_EHCI_BASE 0xE5800000 +#define CONFIG_SYS_SMI_BASE 0xEA000000 +#define CONFIG_SYS_MISC_BASE 0xE0700000 +#define CONFIG_SYS_I2C_BASE 0xE0280000 +#define CONFIG_SYS_ETH_BASE 0xE2000000 +#define CONFIG_SYS_FSMC_BASE 0xB0000000 +#define CONFIG_SYS_MMC_BASE 0xB3000000 +#define CONFIG_SYS_SPI_BASE 0xE0100000 +#define CONFIG_GPIO_BASE 0xE0600000 + +#define CONFIG_SYS_NAND_CLE (1 << 16) +#define CONFIG_SYS_NAND_ALE (1 << 17) + +#endif /* _ASM_ARCH_SPEAR13XX_H */ diff --git a/drivers/usb/host/ehci-spear.c b/drivers/usb/host/ehci-spear.c index 71c4ea2..7a57379 100644 --- a/drivers/usb/host/ehci-spear.c +++ b/drivers/usb/host/ehci-spear.c @@ -59,6 +59,8 @@ int ehci_hcd_stop(int index) spear3xx_usbh_stop(); #elif defined(CONFIG_ARCH_SPEAR6XX) spear6xx_usbh_stop(); +#elif defined(CONFIG_SOC_SPEAR1340) + spear1340_usbh_stop(); #else #error No spear platforms defined #endif diff --git a/include/linux/bitops.h b/include/linux/bitops.h index e724310..984022c 100644 --- a/include/linux/bitops.h +++ b/include/linux/bitops.h @@ -115,6 +115,10 @@ static inline unsigned int generic_hweight8(unsigned int w) # define __set_bit generic_set_bit #endif +#ifndef PLATFORM__TEST_BIT +# define __test_bit generic_test_bit +#endif + #ifndef PLATFORM__CLEAR_BIT # define __clear_bit generic_clear_bit #endif @@ -144,6 +148,14 @@ static inline void generic_set_bit(int nr, volatile unsigned long *addr) *p |= mask; } +static inline int generic_test_bit(int nr, volatile unsigned long *addr) +{ + unsigned long mask = BIT_MASK(nr); + unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr); + + return !!(*p & mask); +} + static inline void generic_clear_bit(int nr, volatile unsigned long *addr) { unsigned long mask = BIT_MASK(nr);