From patchwork Fri Nov 2 17:39:24 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Subject: [U-Boot,SPEAr13xx,2/7] spear1310: Add support for spear1310 SoC Date: Fri, 02 Nov 2012 07:39:24 -0000 From: Vipin Kumar X-Patchwork-Id: 196692 Message-Id: To: Cc: sr@denx.de, spear-devel@list.st.com spear1310 is a CortexA9 dual core SoC which supports multiple peripherals like GMII, USBH, PCIe etc. More information can be found at http://www.st.com/internet/mcu/product/250658.jsp This patch adds support for spear1310 SoC. This patch also adds support for pinmux for spear1310 SoC. The APIs implemented are * spear1310_configure_pin: Configures a particular pin to GPIO, PULLDOWN, PULLUP. The prototype is as follows _void spear1310_configure_pin(u32 plgpio, u32 mode)_ * spear1310_plgpio_get: Configures a particular pin to GPIO IN and gets the value on that particular GPIO. The prototype is as follows _int spear1310_plgpio_get(u32 plgpio)_ * spear1310_plgpio_set: Configures a particular pin to GPIO OUT and sets a value on that particular GPIO. The prototype is as follows _void spear1310_plgpio_set(u32 plgpio, u32 val)_ Signed-off-by: Vipin Kumar --- arch/arm/cpu/armv7/spear13xx/Makefile | 2 + arch/arm/cpu/armv7/spear13xx/spear1310-pinmux.c | 860 +++++++++++++++++++++ arch/arm/cpu/armv7/spear13xx/spear1310.c | 205 +++++ arch/arm/include/asm/arch-spear13xx/hardware.h | 2 + arch/arm/include/asm/arch-spear13xx/misc.h | 3 + arch/arm/include/asm/arch-spear13xx/pinmux.h | 10 + arch/arm/include/asm/arch-spear13xx/spear1310.h | 244 ++++++ .../include/asm/arch-spear13xx/spear1310_misc.h | 300 +++++++ drivers/usb/host/ehci-spear.c | 2 + 9 files changed, 1628 insertions(+) create mode 100644 arch/arm/cpu/armv7/spear13xx/spear1310-pinmux.c create mode 100644 arch/arm/cpu/armv7/spear13xx/spear1310.c create mode 100644 arch/arm/include/asm/arch-spear13xx/spear1310.h create mode 100644 arch/arm/include/asm/arch-spear13xx/spear1310_misc.h diff --git a/arch/arm/cpu/armv7/spear13xx/Makefile b/arch/arm/cpu/armv7/spear13xx/Makefile index 214b89b..cacf268 100644 --- a/arch/arm/cpu/armv7/spear13xx/Makefile +++ b/arch/arm/cpu/armv7/spear13xx/Makefile @@ -29,6 +29,8 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(SOC).o COBJS-$(CONFIG_ARCH_SPEAR13XX) += spear13xx.o +COBJS-$(CONFIG_SOC_SPEAR1310) += spear1310.o +COBJS-$(CONFIG_SOC_SPEAR1310) += spear1310-pinmux.o COBJS-$(CONFIG_SOC_SPEAR1340) += spear1340.o COBJS-$(CONFIG_SOC_SPEAR1340) += spear1340-pinmux.o diff --git a/arch/arm/cpu/armv7/spear13xx/spear1310-pinmux.c b/arch/arm/cpu/armv7/spear13xx/spear1310-pinmux.c new file mode 100644 index 0000000..f204fda --- /dev/null +++ b/arch/arm/cpu/armv7/spear13xx/spear1310-pinmux.c @@ -0,0 +1,860 @@ +/* + * (C) Copyright 2012 + * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include + +/* Pin multiplexing for i2c0 device */ +static void enable_i2c0_pins(void) +{ + pinmux_maskval(SPEAR1310_PAD_FUNCTION_EN_1, + PMX_I2C0_MASK, + PMX_I2C0_MASK); + pinmux_maskval(SPEAR1310_PAD_DIR_SEL_1, + PMX_I2C0_MASK, + PMX_I2C0_MASK); +} + +/* Pin multiplexing for ssp cs0 device */ +static void enable_ssp0cs0_pins(void) +{ + pinmux_maskval(SPEAR1310_PAD_FUNCTION_EN_1, + PMX_SSP0_MASK, + PMX_SSP0_MASK); + pinmux_maskval(SPEAR1310_PAD_FUNCTION_EN_3, + PMX_SSP0_CS0_MASK, + PMX_SSP0_CS0_MASK); + pinmux_maskval(SPEAR1310_PAD_DIR_SEL_1, + PMX_SSP0_MASK, + PMX_SSP0_MASK); + pinmux_maskval(SPEAR1310_PAD_DIR_SEL_3, + PMX_SSP0_CS0_MASK, + PMX_SSP0_CS0_MASK); +} + +/* Pin multiplexing for ssp0 cs1 and cs2 */ +static void enable_ssp0cs1cs2_pins(void) +{ + pinmux_maskval(SPEAR1310_PAD_FUNCTION_EN_3, + PMX_SSP0_CS1_2_MASK, + PMX_SSP0_CS1_2_MASK); + pinmux_maskval(SPEAR1310_PAD_DIR_SEL_3, + PMX_SSP0_CS1_2_MASK, + PMX_SSP0_CS1_2_MASK); +} + +static void enable_ssp0_pins(u32 mode) +{ + switch (mode) { + case PMX_SSP_CS0: + enable_ssp0cs0_pins(); + case PMX_SSP_CS1_CS2: + enable_ssp0cs1cs2_pins(); + break; + } +} +/* Pin multiplexing for arm gpio device */ +static void enable_leggpio_pins(void) +{ + pinmux_maskval(SPEAR1310_PAD_FUNCTION_EN_1, + PMX_EGPIO_0_GRP_MASK, + PMX_EGPIO_0_GRP_MASK); + pinmux_maskval(SPEAR1310_PAD_FUNCTION_EN_2, + PMX_EGPIO_1_GRP_MASK, + PMX_EGPIO_1_GRP_MASK); + pinmux_maskval(SPEAR1310_PAD_DIR_SEL_1, + PMX_EGPIO_0_GRP_MASK, + PMX_EGPIO_0_GRP_MASK); + pinmux_maskval(SPEAR1310_PAD_DIR_SEL_2, + PMX_EGPIO_1_GRP_MASK, + PMX_EGPIO_1_GRP_MASK); +} + +/* Pin multiplexing for smi two chips device */ +static void enable_smi2chips_pins(void) +{ + pinmux_maskval(SPEAR1310_PAD_FUNCTION_EN_1, + PMX_SMI_MASK, + PMX_SMI_MASK); + pinmux_maskval(SPEAR1310_PAD_DIR_SEL_1, + PMX_SMI_MASK, + PMX_SMI_MASK); +} + +/* Pin multiplexing for smi four chips device */ +static void enable_smi4chips_pins(void) +{ + pinmux_maskval(SPEAR1310_PAD_FUNCTION_EN_1, + PMX_SMI_MASK, + PMX_SMI_MASK); + pinmux_maskval(SPEAR1310_PAD_FUNCTION_EN_2, + PMX_SMINCS2_MASK | PMX_SMINCS3_MASK, + PMX_SMINCS2_MASK | PMX_SMINCS3_MASK); + pinmux_maskval(SPEAR1310_PAD_DIR_SEL_1, + PMX_SMI_MASK, + PMX_SMI_MASK); + pinmux_maskval(SPEAR1310_PAD_DIR_SEL_2, + PMX_SMINCS2_MASK | PMX_SMINCS3_MASK, + PMX_SMINCS2_MASK | PMX_SMINCS3_MASK); +} + +static void enable_smi_pins(u32 mode) +{ + switch (mode) { + case PMX_SMI_2CHIPS: + enable_smi2chips_pins(); + break; + case PMX_SMI_4CHIPS: + enable_smi4chips_pins(); + break; + } +} + +/* + * Pin multiplexing for ethernet device + * Ethernet on spear1310 can be configured as either of the below + * - GMII + * - RGMII + * - RMII + * - SGMII + */ +/* Pin multiplexing for gmii device */ +static void enable_gmii_pins(void) +{ + pinmux_maskval(SPEAR1310_PAD_FUNCTION_EN_1, + PMX_GMII_MASK, + PMX_GMII_MASK); + pinmux_maskval(SPEAR1310_PAD_DIR_SEL_1, + PMX_GMII_MASK, + PMX_GMII_MASK); +} + +/* Pin multiplexing for rgmii device */ +static void enable_rgmii_pins(void) +{ + pinmux_maskval(SPEAR1310_PAD_FUNCTION_EN_1, + PMX_RGMII_REG1_MASK, + 0); + pinmux_maskval(SPEAR1310_PAD_FUNCTION_EN_2, + PMX_RGMII_REG2_MASK, + 0); + pinmux_maskval(SPEAR1310_PAD_FUNCTION_EN_3, + PMX_RGMII_REG3_MASK, + 0); + pinmux_maskval(SPEAR1310_PAD_DIR_SEL_1, + PMX_RGMII_REG1_MASK, + PMX_RGMII_REG1_MASK); + pinmux_maskval(SPEAR1310_PAD_DIR_SEL_2, + PMX_RGMII_REG2_MASK, + PMX_RGMII_REG2_MASK); + pinmux_maskval(SPEAR1310_PAD_DIR_SEL_3, + PMX_RGMII_REG3_MASK, + PMX_RGMII_REG3_MASK); +} + +static void enable_eth0_pins(u32 mode) +{ + switch (mode) { + case PMX_ETH_GMII: + enable_gmii_pins(); + break; + case PMX_ETH_RGMII: + enable_rgmii_pins(); + break; + } +} + +/* Pin multiplexing for nand 8bit device */ +static void enable_nand8bit_pins(void) +{ + pinmux_maskval(SPEAR1310_PAD_FUNCTION_EN_1, + PMX_NAND8BIT_0_MASK, + PMX_NAND8BIT_0_MASK); + pinmux_maskval(SPEAR1310_PAD_FUNCTION_EN_2, + PMX_NAND8BIT_1_MASK, + PMX_NAND8BIT_1_MASK); + pinmux_maskval(SPEAR1310_PAD_DIR_SEL_1, + PMX_NAND8BIT_0_MASK, + PMX_NAND8BIT_0_MASK); + pinmux_maskval(SPEAR1310_PAD_DIR_SEL_2, + PMX_NAND8BIT_1_MASK, + PMX_NAND8BIT_1_MASK); +} + +/* Pin multiplexing for nand 16bit device */ +static void enable_nand16bit_pins(void) +{ + pinmux_maskval(SPEAR1310_PAD_FUNCTION_EN_1, + PMX_NAND8BIT_0_MASK, + PMX_NAND8BIT_0_MASK); + pinmux_maskval(SPEAR1310_PAD_FUNCTION_EN_2, + PMX_NAND8BIT_1_MASK, + PMX_NAND8BIT_1_MASK); + pinmux_maskval(SPEAR1310_PAD_FUNCTION_EN_2, + PMX_NAND16BIT_1_MASK, + PMX_NAND16BIT_1_MASK); + pinmux_maskval(SPEAR1310_PAD_DIR_SEL_1, + PMX_NAND8BIT_0_MASK, + PMX_NAND8BIT_0_MASK); + pinmux_maskval(SPEAR1310_PAD_DIR_SEL_2, + PMX_NAND8BIT_1_MASK, + PMX_NAND8BIT_1_MASK); + pinmux_maskval(SPEAR1310_PAD_DIR_SEL_2, + PMX_NAND16BIT_1_MASK, + PMX_NAND16BIT_1_MASK); +} + +/* Pin multiplexing for nand 4chips device */ +static void enable_nand4chips_pins(void) +{ + pinmux_maskval(SPEAR1310_PAD_FUNCTION_EN_2, + PMX_NAND_4CHIPS_MASK, + PMX_NAND_4CHIPS_MASK); + pinmux_maskval(SPEAR1310_PAD_DIR_SEL_2, + PMX_NAND_4CHIPS_MASK, + PMX_NAND_4CHIPS_MASK); +} + +/* Pin multiplexing for fsmc nand device */ +static void enable_nand_pins(u32 mode) +{ + switch (mode) { + case PMX_NAND_8BIT: + enable_nand8bit_pins(); + break; + case PMX_NAND_16BIT: + enable_nand16bit_pins(); + break; + case PMX_NAND_4CHIPS: + enable_nand4chips_pins(); + } +} + +/* Pin multiplexing for uart0 device */ +static void enable_uart0simple_pins(void) +{ + pinmux_maskval(SPEAR1310_PAD_FUNCTION_EN_1, + PMX_UART0_MASK, + PMX_UART0_MASK); + pinmux_maskval(SPEAR1310_PAD_DIR_SEL_1, + PMX_UART0_MASK, + PMX_UART0_MASK); +} + +/* Pin multiplexing for uart0 modem device */ +static void enable_uart0modem_pins(void) +{ + pinmux_maskval(SPEAR1310_PAD_FUNCTION_EN_2, + PMX_UART0_MODEM_MASK, + PMX_UART0_MODEM_MASK); + pinmux_maskval(SPEAR1310_PAD_DIR_SEL_2, + PMX_UART0_MODEM_MASK, + PMX_UART0_MODEM_MASK); +} + + +static void enable_uart0_pins(u32 mode) +{ + switch (mode) { + case PMX_UART_SIMPLE: + enable_uart0simple_pins(); + break; + case PMX_UART_MODEM: + enable_uart0modem_pins(); + break; + } +} + +/* Pin multiplexing for sdmmc device */ +static void enable_sdmmc_pins(void) +{ + pinmux_maskval(SPEAR1310_PAD_FUNCTION_EN_1, + PMX_MCI_DATA8_15_MASK, + PMX_MCI_DATA8_15_MASK); + pinmux_maskval(SPEAR1310_PAD_FUNCTION_EN_2, + PMX_MCIFALL_1_MASK | PMX_NFWPRT1_MASK | + PMX_NFWPRT2_MASK, + PMX_MCIFALL_1_MASK); + pinmux_maskval(SPEAR1310_PAD_FUNCTION_EN_3, + PMX_MCIFALL_2_MASK, + PMX_MCIFALL_2_MASK); + pinmux_maskval(SPEAR1310_PERIP_CFG, + MCIF_SEL_MASK, + MCIF_SEL_SD); + pinmux_maskval(SPEAR1310_PAD_DIR_SEL_1, + PMX_MCI_DATA8_15_MASK, + PMX_MCI_DATA8_15_MASK); + pinmux_maskval(SPEAR1310_PAD_DIR_SEL_2, + PMX_MCIFALL_1_MASK | PMX_NFWPRT1_MASK | + PMX_NFWPRT2_MASK, + PMX_MCIFALL_1_MASK | PMX_NFWPRT1_MASK | + PMX_NFWPRT2_MASK); + pinmux_maskval(SPEAR1310_PAD_DIR_SEL_3, + PMX_MCIFALL_2_MASK, + PMX_MCIFALL_2_MASK); +} + +/* Pin multiplexing for uart1disi2c0 device */ +static void enable_uart1disi2c0_pins(void) +{ + pinmux_maskval(SPEAR1310_PAD_FUNCTION_EN_1, + PMX_I2C0_MASK, + 0); + pinmux_maskval(SPEAR1310_PAD_DIR_SEL_1, + PMX_I2C0_MASK, + PMX_I2C0_MASK); +} + +/* Pin multiplexing for uart1 (disables SD) device */ +static void enable_uart1dissd_pins(void) +{ + pinmux_maskval(SPEAR1310_PAD_FUNCTION_EN_2, + PMX_MCIDATA1_MASK | + PMX_MCIDATA2_MASK, + 0); + pinmux_maskval(SPEAR1310_PAD_DIR_SEL_2, + PMX_MCIDATA1_MASK | PMX_MCIDATA2_MASK, + PMX_MCIDATA1_MASK | PMX_MCIDATA2_MASK); +} + +static void enable_uart1_pins(u32 mode) +{ + switch (mode) { + case PMX_UART_DISSD: + enable_uart1dissd_pins(); + break; + case PMX_UART_DISI2C0: + enable_uart1disi2c0_pins(); + break; + } +} + +/* Pin multiplexing for uart 2 and 3 device */ +static void enable_uart23_pins(void) +{ + pinmux_maskval(SPEAR1310_PAD_FUNCTION_EN_1, + PMX_I2S0_MASK, + 0); + pinmux_maskval(SPEAR1310_PAD_DIR_SEL_1, + PMX_I2S0_MASK, + PMX_I2S0_MASK); +} + +/* Pin multiplexing for uart 4 device */ +static void enable_uart4_pins(void) +{ + pinmux_maskval(SPEAR1310_PAD_FUNCTION_EN_1, + PMX_I2S0_MASK | PMX_CLCD1_MASK, + 0); + pinmux_maskval(SPEAR1310_PAD_DIR_SEL_1, + PMX_I2S0_MASK | PMX_CLCD1_MASK, + PMX_I2S0_MASK | PMX_CLCD1_MASK); +} + +/* Pin multiplexing for uart 5 device */ +static void enable_uart5_pins(void) +{ + pinmux_maskval(SPEAR1310_PAD_FUNCTION_EN_1, + PMX_CLCD1_MASK, + 0); + pinmux_maskval(SPEAR1310_PAD_DIR_SEL_1, + PMX_CLCD1_MASK, + PMX_CLCD1_MASK); +} + +/* Pin multiplexing for i2c 1 and 2 device */ +static void enable_i2c12_pins(void) +{ + pinmux_maskval(SPEAR1310_PAD_FUNCTION_EN_1, + PMX_CLCD1_MASK, + 0); + pinmux_maskval(SPEAR1310_PAD_DIR_SEL_1, + PMX_CLCD1_MASK, + PMX_CLCD1_MASK); +} + +#if 0 +/* Pin multiplexing for i2c3 (Disables smi and clcd) device */ +static void enable_i2c3dissmiclcd_pins(void) +{ + pinmux_maskval(SPEAR1310_PAD_FUNCTION_EN_1, + PMX_CLCD1_MASK | PMX_SMI_MASK, + 0); + pinmux_maskval(SPEAR1310_PAD_DIR_SEL_1, + PMX_CLCD1_MASK | PMX_SMI_MASK, + PMX_CLCD1_MASK | PMX_SMI_MASK); +} + +/* Pin multiplexing for i2c3 (Disables sd and i2s0) device */ +static void enable_i2c3dissdi2s0_pins(void) +{ + pinmux_maskval(SPEAR1310_PAD_FUNCTION_EN_2, + PMX_I2S1_MASK | PMX_MCIDATA3_MASK, + 0); + pinmux_maskval(SPEAR1310_PAD_DIR_SEL_2, + PMX_I2S1_MASK | PMX_MCIDATA3_MASK, + PMX_I2S1_MASK | PMX_MCIDATA3_MASK); +} + +/* Pin multiplexing for i2c4 and 5 (Disables smi and clcd) device */ +static void enable_i2c3dissmiclcd_pins(void) +{ + pinmux_maskval(SPEAR1310_PAD_FUNCTION_EN_1, + PMX_SMI_MASK, + 0); + pinmux_maskval(SPEAR1310_PAD_DIR_SEL_1, + PMX_SMI_MASK, + PMX_SMI_MASK); +} + +/* Pin multiplexing for i2c4 (Disables sd) device */ +static void enable_i2c4dissd_pins(void) +{ + pinmux_maskval(SPEAR1310_PAD_FUNCTION_EN_2, + PMX_MCIDATA4_MASK, + 0); + pinmux_maskval(SPEAR1310_PAD_FUNCTION_EN_3, + PMX_MCIDATA5_MASK, + 0); + pinmux_maskval(SPEAR1310_PAD_DIR_SEL_2, + PMX_MCIDATA4_MASK, + PMX_MCIDATA4_MASK); + pinmux_maskval(SPEAR1310_PAD_DIR_SEL_3, + PMX_MCIDATA5_MASK, + PMX_MCIDATA5_MASK); +} + +/* Pin multiplexing for i2c5 (Disables sd) device */ +static void enable_i2c5dissd_pins(void) +{ + pinmux_maskval(SPEAR1310_PAD_FUNCTION_EN_3, + PMX_MCIDATA6_MASK | PMX_MCIDATA7_MASK, + 0); + pinmux_maskval(SPEAR1310_PAD_DIR_SEL_3, + PMX_MCIDATA6_MASK | PMX_MCIDATA7_MASK, + PMX_MCIDATA6_MASK | PMX_MCIDATA7_MASK); +} + +/* Pin multiplexing for i2c6 and 7 (Disables kbd) device */ +static void enable_i2c67diskbd_pins(void) +{ + pinmux_maskval(SPEAR1310_PAD_FUNCTION_EN_2, + PMX_KBD_ROWCOL25_MASK, + 0); + pinmux_maskval(SPEAR1310_PAD_DIR_SEL_2, + PMX_KBD_ROWCOL25_MASK, + PMX_KBD_ROWCOL25_MASK); +} + +/* Pin multiplexing for i2c6 (Disables sd) device */ +static void enable_i2c6dissd_pins(void) +{ + pinmux_maskval(SPEAR1310_PAD_FUNCTION_EN_3, + PMX_MCIIORDRE_MASK | PMX_MCIIOWRWE_MASK, + 0); + pinmux_maskval(SPEAR1310_PAD_DIR_SEL_3, + PMX_MCIIORDRE_MASK | PMX_MCIIOWRWE_MASK, + PMX_MCIIORDRE_MASK | PMX_MCIIOWRWE_MASK); +} + +/* Pin multiplexing for i2c7 (Disables sd) device */ +static void enable_i2c7dissd_pins(void) +{ + pinmux_maskval(SPEAR1310_PAD_FUNCTION_EN_3, + PMX_MCIRESETCF_MASK | PMX_MCICS0CE_MASK, + 0); + pinmux_maskval(SPEAR1310_PAD_DIR_SEL_3, + PMX_MCIRESETCF_MASK | PMX_MCICS0CE_MASK, + PMX_MCIRESETCF_MASK | PMX_MCICS0CE_MASK); +} + +/* Pin multiplexing for ssp1 (Disables kbd) device */ +static void enable_ssp1diskbd_pins(void) +{ + pinmux_maskval(SPEAR1310_PAD_FUNCTION_EN_2, + PMX_KBD_ROWCOL25_MASK | PMX_KBD_COL1_MASK | + PMX_KBD_COL0_MASK | PMX_NFIO8_15_MASK | PMX_NFCE1_MASK | + PMX_NFCE2_MASK, + 0); + pinmux_maskval(SPEAR1310_PAD_DIR_SEL_2, + PMX_KBD_ROWCOL25_MASK | PMX_KBD_COL1_MASK | + PMX_KBD_COL0_MASK | PMX_NFIO8_15_MASK | PMX_NFCE1_MASK | + PMX_NFCE2_MASK, + PMX_KBD_ROWCOL25_MASK | PMX_KBD_COL1_MASK | + PMX_KBD_COL0_MASK | PMX_NFIO8_15_MASK | PMX_NFCE1_MASK | + PMX_NFCE2_MASK); +} + +/* Pin multiplexing for ssp1 (Disables sd) device */ +static void enable_ssp1dissd_pins(void) +{ + pinmux_maskval(SPEAR1310_PAD_FUNCTION_EN_3, + PMX_MCIADDR0ALE_MASK | PMX_MCIADDR2_MASK | + PMX_MCICECF_MASK | PMX_MCICEXD_MASK, + 0); + pinmux_maskval(SPEAR1310_PAD_DIR_SEL_3, + PMX_MCIADDR0ALE_MASK | PMX_MCIADDR2_MASK | + PMX_MCICECF_MASK | PMX_MCICEXD_MASK, + PMX_MCIADDR0ALE_MASK | PMX_MCIADDR2_MASK | + PMX_MCICECF_MASK | PMX_MCICEXD_MASK); +} +#endif + +/** + * spear1310_pins_default: Select a default safe mode as startup + * Generally, all pins are enabled in input mode at initialization. This can be + * done either by + * - enabling gpio's and keeping all pins in gpio inputs + * - a platform specific way. + */ +void spear1310_pins_default(void) +{ +} + +/** + * spear1310_enable_pins - enable pins for peripherals on spear1310 devices + * @ip: Peripheral index + * @mode: Mode in which peripheral has to run (16bit/8bit etc) + * + * Enable the pins for fixed peripherals on spear3xx devices. + * mode represents the mode in which the peripheral may work and may result in + * different pins being enabled. eg GMII mode and RGMII mode may need different + * pins on devices to be enabled + */ +void spear1310_enable_pins(u32 ip, u32 mode) +{ + if (PMX_SDMMC == ip) + enable_sdmmc_pins(); + else if (PMX_SMI == ip) + enable_smi_pins(mode); + else if (PMX_I2C0 == ip) + enable_i2c0_pins(); + else if ((PMX_I2C1 == ip) || (PMX_I2C1 == ip)) + enable_i2c12_pins(); + else if (PMX_FSMCNAND == ip) + enable_nand_pins(mode); + else if (PMX_UART0 == ip) + enable_uart0_pins(mode); + else if (PMX_UART1 == ip) + enable_uart1_pins(mode); + else if ((PMX_UART2 == ip) || (PMX_UART3 == ip)) + enable_uart23_pins(); + else if (PMX_UART4 == ip) + enable_uart4_pins(); + else if (PMX_UART5 == ip) + enable_uart5_pins(); + else if (PMX_ETH0 == ip) + enable_eth0_pins(mode); + else if (PMX_SSP0 == ip) + enable_ssp0_pins(mode); + else if (PMX_LEGGPIO0 == ip) + enable_leggpio_pins(); +} + +static void configure_gpio(u32 plgpio) +{ + if (plgpio > SPEAR1310_MAX_PLGPIOS) + return; + + /* Set the GPIO direction to input */ + pinmux_set_bit(plgpio, SPEAR1310_GPIO_EN0); + + /* Enable PLGPIO from RAS */ + pinmux_set_bit(plgpio, SPEAR1310_GPIO_FUN_EN0); + + if (plgpio <= 3) { + pinmux_clear_bit(16, SPEAR1310_PAD_FUNCTION_EN_2); + pinmux_set_bit(16, SPEAR1310_PAD_DIR_SEL_2); + + } else if ((plgpio >= 4) && (plgpio <= 5)) { + pinmux_clear_bit(15, SPEAR1310_PAD_FUNCTION_EN_2); + pinmux_set_bit(15, SPEAR1310_PAD_DIR_SEL_2); + + } else if ((plgpio >= 6) && (plgpio <= 7)) { + pinmux_clear_bit(14, SPEAR1310_PAD_FUNCTION_EN_2); + pinmux_set_bit(14, SPEAR1310_PAD_DIR_SEL_2); + + } else if ((plgpio >= 8) && (plgpio <= 9)) { + pinmux_clear_bit(13, SPEAR1310_PAD_FUNCTION_EN_2); + pinmux_set_bit(13, SPEAR1310_PAD_DIR_SEL_2); + + } else if ((plgpio >= 10) && (plgpio <= 11)) { + pinmux_clear_bit(12, SPEAR1310_PAD_FUNCTION_EN_2); + pinmux_set_bit(12, SPEAR1310_PAD_DIR_SEL_2); + + } else if ((plgpio >= 12) && (plgpio <= 17)) { + pinmux_clear_bit(11, SPEAR1310_PAD_FUNCTION_EN_2); + pinmux_set_bit(11, SPEAR1310_PAD_DIR_SEL_2); + + } else if (plgpio == 18) { + pinmux_clear_bit(10, SPEAR1310_PAD_FUNCTION_EN_2); + pinmux_set_bit(10, SPEAR1310_PAD_DIR_SEL_2); + + } else if (plgpio == 19) { + pinmux_clear_bit(9, SPEAR1310_PAD_FUNCTION_EN_2); + pinmux_set_bit(9, SPEAR1310_PAD_DIR_SEL_2); + + } else if (plgpio == 20) { + pinmux_clear_bit(8, SPEAR1310_PAD_FUNCTION_EN_2); + pinmux_set_bit(8, SPEAR1310_PAD_DIR_SEL_2); + + } else if (plgpio == 21) { + pinmux_clear_bit(7, SPEAR1310_PAD_FUNCTION_EN_2); + pinmux_set_bit(7, SPEAR1310_PAD_DIR_SEL_2); + + } else if (plgpio == 22) { + pinmux_clear_bit(6, SPEAR1310_PAD_FUNCTION_EN_2); + pinmux_set_bit(6, SPEAR1310_PAD_DIR_SEL_2); + + } else if (plgpio == 23) { + pinmux_clear_bit(5, SPEAR1310_PAD_FUNCTION_EN_2); + pinmux_set_bit(5, SPEAR1310_PAD_DIR_SEL_2); + + } else if ((plgpio >= 24) && (plgpio <= 29)) { + pinmux_clear_bit(4, SPEAR1310_PAD_FUNCTION_EN_2); + pinmux_set_bit(4, SPEAR1310_PAD_DIR_SEL_2); + + } else if ((plgpio >= 30) && (plgpio <= 53)) { + pinmux_clear_bit(3, SPEAR1310_PAD_FUNCTION_EN_2); + pinmux_set_bit(3, SPEAR1310_PAD_DIR_SEL_2); + + } else if (plgpio == 54) { + pinmux_clear_bit(2, SPEAR1310_PAD_FUNCTION_EN_2); + pinmux_set_bit(2, SPEAR1310_PAD_DIR_SEL_2); + + } else if (plgpio == 55) { + pinmux_clear_bit(1, SPEAR1310_PAD_FUNCTION_EN_2); + pinmux_set_bit(1, SPEAR1310_PAD_DIR_SEL_2); + + } else if (plgpio == 56) { + pinmux_clear_bit(0, SPEAR1310_PAD_FUNCTION_EN_2); + pinmux_set_bit(0, SPEAR1310_PAD_DIR_SEL_2); + + } else if (plgpio == 57) { + pinmux_clear_bit(31, SPEAR1310_PAD_FUNCTION_EN_1); + pinmux_set_bit(31, SPEAR1310_PAD_DIR_SEL_1); + + } else if (plgpio == 58) { + pinmux_clear_bit(30, SPEAR1310_PAD_FUNCTION_EN_1); + pinmux_set_bit(30, SPEAR1310_PAD_DIR_SEL_1); + + } else if (plgpio == 59) { + pinmux_clear_bit(29, SPEAR1310_PAD_FUNCTION_EN_1); + pinmux_set_bit(29, SPEAR1310_PAD_DIR_SEL_1); + + } else if (plgpio == 60) { + pinmux_clear_bit(28, SPEAR1310_PAD_FUNCTION_EN_1); + pinmux_set_bit(28, SPEAR1310_PAD_DIR_SEL_1); + + } else if (plgpio == 61) { + pinmux_clear_bit(27, SPEAR1310_PAD_FUNCTION_EN_1); + pinmux_set_bit(27, SPEAR1310_PAD_DIR_SEL_1); + + } else if (plgpio == 62) { + pinmux_clear_bit(26, SPEAR1310_PAD_FUNCTION_EN_1); + pinmux_set_bit(26, SPEAR1310_PAD_DIR_SEL_1); + + } else if (plgpio == 63) { + pinmux_clear_bit(25, SPEAR1310_PAD_FUNCTION_EN_1); + pinmux_set_bit(25, SPEAR1310_PAD_DIR_SEL_1); + + } else if ((plgpio >= 64) && (plgpio <= 85)) { + pinmux_clear_bit(24, SPEAR1310_PAD_FUNCTION_EN_1); + pinmux_set_bit(24, SPEAR1310_PAD_DIR_SEL_1); + + } else if ((plgpio >= 86) && (plgpio <= 93)) { + pinmux_clear_bit(23, SPEAR1310_PAD_FUNCTION_EN_1); + pinmux_set_bit(23, SPEAR1310_PAD_DIR_SEL_1); + + } else if ((plgpio >= 94) && (plgpio <= 95)) { + pinmux_clear_bit(30, SPEAR1310_PAD_FUNCTION_EN_3); + pinmux_set_bit(30, SPEAR1310_PAD_DIR_SEL_3); + + } else if (plgpio >= 96) { + pinmux_clear_bit(29, SPEAR1310_PAD_FUNCTION_EN_3); + pinmux_set_bit(29, SPEAR1310_PAD_DIR_SEL_3); + + } else if (plgpio >= 97) { + pinmux_clear_bit(28, SPEAR1310_PAD_FUNCTION_EN_3); + pinmux_set_bit(28, SPEAR1310_PAD_DIR_SEL_3); + + } else if ((plgpio >= 98) && (plgpio <= 99)) { + pinmux_clear_bit(22, SPEAR1310_PAD_FUNCTION_EN_2); + pinmux_set_bit(22, SPEAR1310_PAD_DIR_SEL_2); + + } else if ((plgpio >= 100) && (plgpio <= 101)) { + pinmux_clear_bit(1, SPEAR1310_PAD_FUNCTION_EN_1); + pinmux_set_bit(1, SPEAR1310_PAD_DIR_SEL_1); + + } else if ((plgpio >= 102) && (plgpio <= 103)) { + pinmux_clear_bit(2, SPEAR1310_PAD_FUNCTION_EN_1); + pinmux_set_bit(2, SPEAR1310_PAD_DIR_SEL_1); + + } else if ((plgpio >= 104) && (plgpio <= 108)) { + pinmux_clear_bit(3, SPEAR1310_PAD_FUNCTION_EN_1); + pinmux_set_bit(3, SPEAR1310_PAD_DIR_SEL_1); + + } else if ((plgpio >= 109) && (plgpio <= 112)) { + pinmux_clear_bit(4, SPEAR1310_PAD_FUNCTION_EN_1); + pinmux_set_bit(4, SPEAR1310_PAD_DIR_SEL_1); + + } else if ((plgpio >= 113) && (plgpio <= 142)) { + pinmux_clear_bit(5, SPEAR1310_PAD_FUNCTION_EN_1); + pinmux_set_bit(5, SPEAR1310_PAD_DIR_SEL_1); + + } else if ((plgpio >= 143) && (plgpio <= 152)) { + pinmux_clear_bit(plgpio - 137, SPEAR1310_PAD_FUNCTION_EN_1); + pinmux_set_bit(plgpio - 137, SPEAR1310_PAD_DIR_SEL_1); + + } else if ((plgpio >= 153) && (plgpio <= 157)) { + pinmux_clear_bit(16, SPEAR1310_PAD_FUNCTION_EN_1); + pinmux_set_bit(16, SPEAR1310_PAD_DIR_SEL_1); + + } else if ((plgpio >= 158) && (plgpio <= 172)) { + pinmux_clear_bit(17, SPEAR1310_PAD_FUNCTION_EN_1); + pinmux_set_bit(17, SPEAR1310_PAD_DIR_SEL_1); + + } else if ((plgpio >= 173) && (plgpio <= 174)) { + pinmux_clear_bit(18, SPEAR1310_PAD_FUNCTION_EN_1); + pinmux_set_bit(18, SPEAR1310_PAD_DIR_SEL_1); + + } else if (plgpio == 175) { + pinmux_clear_bit(19, SPEAR1310_PAD_FUNCTION_EN_1); + pinmux_set_bit(19, SPEAR1310_PAD_DIR_SEL_1); + + } else if ((plgpio >= 176) && (plgpio <= 179)) { + pinmux_clear_bit(20, SPEAR1310_PAD_FUNCTION_EN_1); + pinmux_set_bit(20, SPEAR1310_PAD_DIR_SEL_1); + + } else if ((plgpio >= 180) && (plgpio <= 183)) { + pinmux_clear_bit(21, SPEAR1310_PAD_FUNCTION_EN_1); + pinmux_set_bit(21, SPEAR1310_PAD_DIR_SEL_1); + + } else if (plgpio == 184) { + pinmux_clear_bit(20, SPEAR1310_PAD_FUNCTION_EN_1); + pinmux_set_bit(20, SPEAR1310_PAD_DIR_SEL_1); + + } else if (plgpio == 185) { + pinmux_clear_bit(19, SPEAR1310_PAD_FUNCTION_EN_1); + pinmux_set_bit(19, SPEAR1310_PAD_DIR_SEL_1); + + } else if ((plgpio >= 186) && (plgpio <= 187)) { + pinmux_clear_bit(20, SPEAR1310_PAD_FUNCTION_EN_1); + pinmux_set_bit(20, SPEAR1310_PAD_DIR_SEL_1); + + } else if (plgpio == 188) { + pinmux_clear_bit(19, SPEAR1310_PAD_FUNCTION_EN_1); + pinmux_set_bit(19, SPEAR1310_PAD_DIR_SEL_1); + + } else if ((plgpio >= 189) && (plgpio <= 192)) { + pinmux_clear_bit(20, SPEAR1310_PAD_FUNCTION_EN_1); + pinmux_set_bit(20, SPEAR1310_PAD_DIR_SEL_1); + + } else if ((plgpio >= 193) && (plgpio <= 196)) { + pinmux_clear_bit(21, SPEAR1310_PAD_FUNCTION_EN_1); + pinmux_set_bit(21, SPEAR1310_PAD_DIR_SEL_1); + + } else if ((plgpio >= 197) && (plgpio <= 198)) { + pinmux_clear_bit(19, SPEAR1310_PAD_FUNCTION_EN_1); + pinmux_set_bit(19, SPEAR1310_PAD_DIR_SEL_1); + + } else if ((plgpio >= 199) && (plgpio <= 200)) { + pinmux_clear_bit(22, SPEAR1310_PAD_FUNCTION_EN_1); + pinmux_set_bit(22, SPEAR1310_PAD_DIR_SEL_1); + + } +} + +static void configure_pullup(u32 plgpio) +{ + if (plgpio > SPEAR1310_MAX_PLGPIOS) + return; + + /* Deactivate pull down */ + pinmux_set_bit(plgpio, SPEAR1310_PAD_PD_CFG_1); + + /* Activate pull up */ + pinmux_clear_bit(plgpio, SPEAR1310_PAD_PU_CFG_1); +} + +static void configure_pulldown(u32 plgpio) +{ + if (plgpio > SPEAR1310_MAX_PLGPIOS) + return; + + /* Deactivate pull up */ + pinmux_set_bit(plgpio, SPEAR1310_PAD_PU_CFG_1); + + /* Activate pull down */ + pinmux_clear_bit(plgpio, SPEAR1310_PAD_PD_CFG_1); +} + +/** + * spear1310_configure_pin - Configure pin on spear1310 devices + * @plgpio: Pin Number (plgpio number) + * @mode: Pull UP, Pull DOWN, plgpio IN, plgpio OUT etc + */ +void spear1310_configure_pin(u32 plgpio, u32 mode) +{ + if (PMX_GPIO == mode) + configure_gpio(plgpio); + else if (PMX_PULLUP == mode) + configure_pullup(plgpio); + else if (PMX_PULLDOWN == mode) + configure_pulldown(plgpio); +} + +/** + * spear1310_plgpio_get - Get the gpio input + * @plgpio: Pin Number (plgpio number) + */ +int spear1310_plgpio_get(u32 plgpio) +{ + if (plgpio > SPEAR1310_MAX_PLGPIOS) + return -1; + + /* Set the pin to GPIO IN mode */ + pinmux_set_bit(plgpio, SPEAR1310_GPIO_EN0); + + return pinmux_test_bit(plgpio, SPEAR1310_GPIO_IN0); +} + +/** + * spear1310_plgpio_set - Set the gpio value + * @plgpio: Pin Number (plgpio number) + */ +void spear1310_plgpio_set(u32 plgpio, u32 val) +{ + if (plgpio > SPEAR1310_MAX_PLGPIOS) + return; + + if (val & 0x1) + pinmux_set_bit(plgpio, SPEAR1310_GPIO_OUT0); + else + pinmux_clear_bit(plgpio, SPEAR1310_GPIO_OUT0); + + /* Set the pin to GPIO OUT mode */ + pinmux_clear_bit(plgpio, SPEAR1310_GPIO_EN0); +} diff --git a/arch/arm/cpu/armv7/spear13xx/spear1310.c b/arch/arm/cpu/armv7/spear13xx/spear1310.c new file mode 100644 index 0000000..9936d25 --- /dev/null +++ b/arch/arm/cpu/armv7/spear13xx/spear1310.c @@ -0,0 +1,205 @@ +/* + * (C) Copyright 2012 + * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include + +int arch_cpu_init(void) +{ + struct spear1310_misc_regs *const misc_p = + (struct spear1310_misc_regs *)CONFIG_SYS_MISC_BASE; + u32 perip1_clk_enb, perip2_clk_enb; + u32 perip_clk_cfg; +#if defined(CONFIG_SDHCI) + u32 perip_cfg; +#endif +#if defined(CONFIG_NAND_FSMC) + u32 fsmc_cfg; +#endif + perip1_clk_enb = readl(&misc_p->perip1_clk_enb); + perip2_clk_enb = readl(&misc_p->perip2_clk_enb); + +#if defined(CONFIG_PL011_SERIAL) + /* select USB PLL 48 MHz as the src clock */ + perip_clk_cfg = readl(&misc_p->perip_clk_cfg); + perip_clk_cfg &= ~SPEAR1310_UARTCLKMSK; + perip_clk_cfg |= SPEAR1310_UART48M; + writel(perip_clk_cfg, &misc_p->perip_clk_cfg); + + perip1_clk_enb |= SPEAR1310_UART_CLKEN; +#endif + +#if defined(CONFIG_DESIGNWARE_ETH) + perip1_clk_enb |= SPEAR1310_GETH_CLKEN; +#endif + +#if defined(CONFIG_DW_UDC) + perip1_clk_enb |= SPEAR1310_UDC_UPD_CLKEN; +#endif + +#if defined(CONFIG_USB_EHCI_SPEAR) + perip1_clk_enb |= SPEAR1310_UHC1_CLKEN; +#endif + +#if defined(CONFIG_DW_I2C) + perip1_clk_enb |= SPEAR1310_I2C_CLKEN; +#endif + +#if defined(CONFIG_ST_SMI) + perip1_clk_enb |= SPEAR1310_SMI_CLKEN; +#endif + +#if defined(CONFIG_PL022_SPI) + perip1_clk_enb |= SPEAR1310_SSP_CLKEN; +#endif + +#if defined(CONFIG_SDHCI) + perip_cfg = readl(&misc_p->perip_cfg); + perip_cfg &= ~SPEAR1310_MCIF_MSK; + perip_cfg |= SPEAR1310_MCIF_SD; + writel(perip_cfg, &misc_p->perip_cfg); + + writel(SPEAR1310_SYNT_X_2 | SPEAR1310_SYNT_Y_21 | + SPEAR1310_SYNT_CLKENB, &misc_p->mcif_sd_clk_synt); + + perip1_clk_enb |= SPEAR1310_SD_CLKEN; +#endif + +#if defined(CONFIG_NAND_FSMC) + fsmc_cfg = readl(&misc_p->fsmc_cfg); + fsmc_cfg &= ~SPEAR1310_NANDCS0_NORCS4; + writel(fsmc_cfg, &misc_p->fsmc_cfg); + + perip1_clk_enb |= SPEAR1310_FSMC_CLKEN; +#endif + + writel(perip1_clk_enb, &misc_p->perip1_clk_enb); + writel(perip2_clk_enb, &misc_p->perip2_clk_enb); + +#if defined(CONFIG_ST_SMI) + smi_init(); +#endif + return 0; +} + +#ifdef CONFIG_DISPLAY_CPUINFO +int print_cpuinfo(void) +{ + printf("CPU: SPEAr1310\n"); + return 0; +} +#endif + +#if defined(CONFIG_USB_EHCI_SPEAR) +void spear1310_usbh_stop(void) +{ + struct spear1310_misc_regs *const misc_regs_p = + (struct spear1310_misc_regs *)CONFIG_SYS_MISC_BASE; + u32 perip1_sw_rst = readl(&misc_regs_p->perip1_sw_rst); + + perip1_sw_rst |= SPEAR1310_UHC1_SWRST; + writel(perip1_sw_rst, &misc_regs_p->perip1_sw_rst); + + udelay(1000); + perip1_sw_rst &= ~SPEAR1310_UHC1_SWRST; + writel(perip1_sw_rst, &misc_regs_p->perip1_sw_rst); +} +#endif + +#ifdef CONFIG_DW_OTG_PHYINIT +void udc_phy_init(void) +{ + struct spear1310_misc_regs *const misc_regs_p = + (struct spear1310_misc_regs *)CONFIG_SYS_MISC_BASE; + + u32 temp; + + /* phy por assert */ + temp = readl(&misc_regs_p->usbphy_gen_cfg); + temp |= SPEAR1310_USBPHY_POR; + writel(temp, &misc_regs_p->usbphy_gen_cfg); + udelay(1); + + /* phy clock disable */ + temp = readl(&misc_regs_p->usbphy_gen_cfg); + temp &= ~SPEAR1310_USBPHY_RST; + writel(temp, &misc_regs_p->usbphy_gen_cfg); + + udelay(150); + + /* phy por deassert */ + temp = readl(&misc_regs_p->usbphy_gen_cfg); + temp &= ~SPEAR1310_USBPHY_POR; + writel(temp, &misc_regs_p->usbphy_gen_cfg); + udelay(1); + + /* phy clock enable */ + temp = readl(&misc_regs_p->usbphy_gen_cfg); + temp |= SPEAR1310_USBPHY_RST; + writel(temp, &misc_regs_p->usbphy_gen_cfg); + + /* wait for pll lock */ + while (!(readl(&misc_regs_p->usbphy_gen_cfg) & USB_PLL_LOCK)) + ; + + udelay(1); + + /* OTG HCLK Disable */ + temp = readl(&misc_regs_p->perip1_clk_enb); + temp &= ~SPEAR1310_UDC_UPD_CLKEN; + writel(temp, &misc_regs_p->perip1_clk_enb); + + /* OTG HRESET deassert */ + temp = readl(&misc_regs_p->perip1_sw_rst); + temp &= ~SPEAR1310_UDC_UPD_SWRST; + writel(temp, &misc_regs_p->perip1_sw_rst); + + /* OTG HCLK Enable */ + temp = readl(&misc_regs_p->perip1_clk_enb); + temp |= SPEAR1310_UDC_UPD_CLKEN; + writel(temp, &misc_regs_p->perip1_clk_enb); +} +#endif + +void reset_cpu(ulong ignored) +{ + struct spear1310_misc_regs *misc_regs_p = + (struct spear1310_misc_regs *)CONFIG_SYS_MISC_BASE; + + printf("System is going to reboot ...\n"); + + /* + * This 1 second delay will allow the above message + * to be printed before reset + */ + udelay((1000 * 1000)); + + writel(0x01, &misc_regs_p->sys_sw_res); + + /* system will restart */ + while (1) + ; +} diff --git a/arch/arm/include/asm/arch-spear13xx/hardware.h b/arch/arm/include/asm/arch-spear13xx/hardware.h index b49ef67..616b57d 100644 --- a/arch/arm/include/asm/arch-spear13xx/hardware.h +++ b/arch/arm/include/asm/arch-spear13xx/hardware.h @@ -26,6 +26,8 @@ #if defined(CONFIG_SOC_SPEAR1340) #include +#elif defined(CONFIG_SOC_SPEAR1310) +#include #endif #endif /* _ASM_ARCH_HARDWARE_H */ diff --git a/arch/arm/include/asm/arch-spear13xx/misc.h b/arch/arm/include/asm/arch-spear13xx/misc.h index 5134938..531862a 100644 --- a/arch/arm/include/asm/arch-spear13xx/misc.h +++ b/arch/arm/include/asm/arch-spear13xx/misc.h @@ -26,6 +26,9 @@ #ifdef CONFIG_SOC_SPEAR1340 #include + +#elif defined(CONFIG_SOC_SPEAR1310) +#include #endif #endif diff --git a/arch/arm/include/asm/arch-spear13xx/pinmux.h b/arch/arm/include/asm/arch-spear13xx/pinmux.h index 9354f21..01531f1 100644 --- a/arch/arm/include/asm/arch-spear13xx/pinmux.h +++ b/arch/arm/include/asm/arch-spear13xx/pinmux.h @@ -72,17 +72,22 @@ enum pinmux_ip { PMX_SDMMC, PMX_EMI, PMX_SMI, + PMX_LEGGPIO0, + PMX_LEGGPIO1, }; /* UART0 modem modes */ #define PMX_UART_SIMPLE 1 #define PMX_UART_MODEM 2 +#define PMX_UART_DISSD 3 +#define PMX_UART_DISI2C0 4 /* SSP modes */ #define PMX_SSP_CS0 1 #define PMX_SSP_CS1 2 #define PMX_SSP_CS2 3 #define PMX_SSP_CS3 4 +#define PMX_SSP_CS1_CS2 5 /* ETH modes */ #define PMX_ETH_GMII 1 @@ -95,6 +100,11 @@ enum pinmux_ip { /* NAND modes */ #define PMX_NAND_8BIT 1 #define PMX_NAND_16BIT 2 +#define PMX_NAND_4CHIPS 3 + +/* SMI modes */ +#define PMX_SMI_2CHIPS 1 +#define PMX_SMI_4CHIPS 2 /* PLGPIO modes */ #define PMX_GPIO 1 diff --git a/arch/arm/include/asm/arch-spear13xx/spear1310.h b/arch/arm/include/asm/arch-spear13xx/spear1310.h new file mode 100644 index 0000000..95d38aa --- /dev/null +++ b/arch/arm/include/asm/arch-spear13xx/spear1310.h @@ -0,0 +1,244 @@ +/* + * (C) Copyright 2012 + * Vipin Kumar, ST Microelectronics, vipin.kumar@st.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _ASM_ARCH_SPEAR1310_PINMUX_H +#define _ASM_ARCH_SPEAR1310_PINMUX_H + +#include + +#define SPEAR1310_PERIP_CFG (CONFIG_SYS_MISC_BASE + 0x32C) + #define MCIF_SEL_SHIFT 3 + #define MCIF_SEL_SD (0x1 << MCIF_SEL_SHIFT) + #define MCIF_SEL_CF (0x2 << MCIF_SEL_SHIFT) + #define MCIF_SEL_XD (0x3 << MCIF_SEL_SHIFT) + #define MCIF_SEL_MASK (0x3 << MCIF_SEL_SHIFT) + +#define SPEAR1310_PCIE_SATA_CFG (CONFIG_SYS_MISC_BASE + 0x3A4) + #define PCIE_SATA2_SEL_PCIE (0 << 31) + #define PCIE_SATA1_SEL_PCIE (0 << 30) + #define PCIE_SATA0_SEL_PCIE (0 << 29) + #define PCIE_SATA2_SEL_SATA (1 << 31) + #define PCIE_SATA1_SEL_SATA (1 << 30) + #define PCIE_SATA0_SEL_SATA (1 << 29) + #define SATA2_CFG_TX_CLK_EN (1 << 27) + #define SATA2_CFG_RX_CLK_EN (1 << 26) + #define SATA2_CFG_POWERUP_RESET (1 << 25) + #define SATA2_CFG_PM_CLK_EN (1 << 24) + #define SATA1_CFG_TX_CLK_EN (1 << 23) + #define SATA1_CFG_RX_CLK_EN (1 << 22) + #define SATA1_CFG_POWERUP_RESET (1 << 21) + #define SATA1_CFG_PM_CLK_EN (1 << 20) + #define SATA0_CFG_TX_CLK_EN (1 << 19) + #define SATA0_CFG_RX_CLK_EN (1 << 18) + #define SATA0_CFG_POWERUP_RESET (1 << 17) + #define SATA0_CFG_PM_CLK_EN (1 << 16) + #define PCIE2_CFG_DEVICE_PRESENT (1 << 11) + #define PCIE2_CFG_POWERUP_RESET (1 << 10) + #define PCIE2_CFG_CORE_CLK_EN (1 << 9) + #define PCIE2_CFG_AUX_CLK_EN (1 << 8) + #define PCIE1_CFG_DEVICE_PRESENT (1 << 7) + #define PCIE1_CFG_POWERUP_RESET (1 << 6) + #define PCIE1_CFG_CORE_CLK_EN (1 << 5) + #define PCIE1_CFG_AUX_CLK_EN (1 << 4) + #define PCIE0_CFG_DEVICE_PRESENT (1 << 3) + #define PCIE0_CFG_POWERUP_RESET (1 << 2) + #define PCIE0_CFG_CORE_CLK_EN (1 << 1) + #define PCIE0_CFG_AUX_CLK_EN (1 << 0) + +#define SPEAR1310_PAD_DIR_SEL_1 (CONFIG_SYS_MISC_BASE + 0x65C) +#define SPEAR1310_PAD_FUNCTION_EN_1 (CONFIG_SYS_MISC_BASE + 0x650) + #define PMX_UART0_MASK (1 << 1) + #define PMX_I2C0_MASK (1 << 2) + #define PMX_I2S0_MASK (1 << 3) + #define PMX_SSP0_MASK (1 << 4) + #define PMX_CLCD1_MASK (1 << 5) + #define PMX_EGPIO00_MASK (1 << 6) + #define PMX_EGPIO01_MASK (1 << 7) + #define PMX_EGPIO02_MASK (1 << 8) + #define PMX_EGPIO03_MASK (1 << 9) + #define PMX_EGPIO04_MASK (1 << 10) + #define PMX_EGPIO05_MASK (1 << 11) + #define PMX_EGPIO06_MASK (1 << 12) + #define PMX_EGPIO07_MASK (1 << 13) + #define PMX_EGPIO08_MASK (1 << 14) + #define PMX_EGPIO09_MASK (1 << 15) + #define PMX_SMI_MASK (1 << 16) + #define PMX_NAND8_MASK (1 << 17) + #define PMX_GMIICLK_MASK (1 << 18) + #define PMX_GMIICOL_CRS_XFERER_MIITXCLK_MASK (1 << 19) + #define PMX_RXCLK_RDV_TXEN_D03_MASK (1 << 20) + #define PMX_GMIID47_MASK (1 << 21) + #define PMX_MDC_MDIO_MASK (1 << 22) + #define PMX_MCI_DATA8_15_MASK (1 << 23) + #define PMX_NFAD23_MASK (1 << 24) + #define PMX_NFAD24_MASK (1 << 25) + #define PMX_NFAD25_MASK (1 << 26) + #define PMX_NFCE3_MASK (1 << 27) + #define PMX_NFWPRT3_MASK (1 << 28) + #define PMX_NFRSTPWDWN0_MASK (1 << 29) + #define PMX_NFRSTPWDWN1_MASK (1 << 30) + #define PMX_NFRSTPWDWN2_MASK (1 << 31) + +#define SPEAR1310_PAD_DIR_SEL_2 (CONFIG_SYS_MISC_BASE + 0x660) +#define SPEAR1310_PAD_FUNCTION_EN_2 (CONFIG_SYS_MISC_BASE + 0x654) + #define PMX_NFRSTPWDWN3_MASK (1 << 0) + #define PMX_SMINCS2_MASK (1 << 1) + #define PMX_SMINCS3_MASK (1 << 2) + #define PMX_CLCD2_MASK (1 << 3) + #define PMX_KBD_ROWCOL68_MASK (1 << 4) + #define PMX_EGPIO10_MASK (1 << 5) + #define PMX_EGPIO11_MASK (1 << 6) + #define PMX_EGPIO12_MASK (1 << 7) + #define PMX_EGPIO13_MASK (1 << 8) + #define PMX_EGPIO14_MASK (1 << 9) + #define PMX_EGPIO15_MASK (1 << 10) + #define PMX_UART0_MODEM_MASK (1 << 11) + #define PMX_GPT0_TMR0_MASK (1 << 12) + #define PMX_GPT0_TMR1_MASK (1 << 13) + #define PMX_GPT1_TMR0_MASK (1 << 14) + #define PMX_GPT1_TMR1_MASK (1 << 15) + #define PMX_I2S1_MASK (1 << 16) + #define PMX_KBD_ROWCOL25_MASK (1 << 17) + #define PMX_NFIO8_15_MASK (1 << 18) + #define PMX_KBD_COL1_MASK (1 << 19) + #define PMX_NFCE1_MASK (1 << 20) + #define PMX_KBD_COL0_MASK (1 << 21) + #define PMX_NFCE2_MASK (1 << 22) + #define PMX_KBD_ROW1_MASK (1 << 23) + #define PMX_NFWPRT1_MASK (1 << 24) + #define PMX_KBD_ROW0_MASK (1 << 25) + #define PMX_NFWPRT2_MASK (1 << 26) + #define PMX_MCIDATA0_MASK (1 << 27) + #define PMX_MCIDATA1_MASK (1 << 28) + #define PMX_MCIDATA2_MASK (1 << 29) + #define PMX_MCIDATA3_MASK (1 << 30) + #define PMX_MCIDATA4_MASK (1 << 31) + +#define SPEAR1310_PAD_DIR_SEL_3 (CONFIG_SYS_MISC_BASE + 0x664) +#define SPEAR1310_PAD_FUNCTION_EN_3 (CONFIG_SYS_MISC_BASE + 0x658) + #define PMX_MCIDATA5_MASK (1 << 0) + #define PMX_MCIDATA6_MASK (1 << 1) + #define PMX_MCIDATA7_MASK (1 << 2) + #define PMX_MCIDATA1SD_MASK (1 << 3) + #define PMX_MCIDATA2SD_MASK (1 << 4) + #define PMX_MCIDATA3SD_MASK (1 << 5) + #define PMX_MCIADDR0ALE_MASK (1 << 6) + #define PMX_MCIADDR1CLECLK_MASK (1 << 7) + #define PMX_MCIADDR2_MASK (1 << 8) + #define PMX_MCICECF_MASK (1 << 9) + #define PMX_MCICEXD_MASK (1 << 10) + #define PMX_MCICESDMMC_MASK (1 << 11) + #define PMX_MCICDCF1_MASK (1 << 12) + #define PMX_MCICDCF2_MASK (1 << 13) + #define PMX_MCICDXD_MASK (1 << 14) + #define PMX_MCICDSDMMC_MASK (1 << 15) + #define PMX_MCIDATADIR_MASK (1 << 16) + #define PMX_MCIDMARQWP_MASK (1 << 17) + #define PMX_MCIIORDRE_MASK (1 << 18) + #define PMX_MCIIOWRWE_MASK (1 << 19) + #define PMX_MCIRESETCF_MASK (1 << 20) + #define PMX_MCICS0CE_MASK (1 << 21) + #define PMX_MCICFINTR_MASK (1 << 22) + #define PMX_MCIIORDY_MASK (1 << 23) + #define PMX_MCICS1_MASK (1 << 24) + #define PMX_MCIDMAACK_MASK (1 << 25) + #define PMX_MCISDCMD_MASK (1 << 26) + #define PMX_MCILEDS_MASK (1 << 27) + #define PMX_TOUCH_XY_MASK (1 << 28) + #define PMX_SSP0_CS0_MASK (1 << 29) + #define PMX_SSP0_CS1_2_MASK (1 << 30) + +/* combined macros */ +#define PMX_GMII_MASK (PMX_GMIICLK_MASK | \ + PMX_GMIICOL_CRS_XFERER_MIITXCLK_MASK | \ + PMX_RXCLK_RDV_TXEN_D03_MASK | \ + PMX_GMIID47_MASK | PMX_MDC_MDIO_MASK) + +#define PMX_EGPIO_0_GRP_MASK (PMX_EGPIO00_MASK | PMX_EGPIO01_MASK | \ + PMX_EGPIO02_MASK | \ + PMX_EGPIO03_MASK | PMX_EGPIO04_MASK | \ + PMX_EGPIO05_MASK | PMX_EGPIO06_MASK | \ + PMX_EGPIO07_MASK | PMX_EGPIO08_MASK | \ + PMX_EGPIO09_MASK) +#define PMX_EGPIO_1_GRP_MASK (PMX_EGPIO10_MASK | PMX_EGPIO11_MASK | \ + PMX_EGPIO12_MASK | PMX_EGPIO13_MASK | \ + PMX_EGPIO14_MASK | PMX_EGPIO15_MASK) + +#define PMX_KEYBOARD_6X6_MASK (PMX_KBD_ROW0_MASK | PMX_KBD_ROW1_MASK | \ + PMX_KBD_ROWCOL25_MASK | PMX_KBD_COL0_MASK | \ + PMX_KBD_COL1_MASK) + +#define PMX_NAND8BIT_0_MASK (PMX_NAND8_MASK | PMX_NFAD23_MASK | \ + PMX_NFAD24_MASK | PMX_NFAD25_MASK | \ + PMX_NFWPRT3_MASK | PMX_NFRSTPWDWN0_MASK | \ + PMX_NFRSTPWDWN1_MASK | PMX_NFRSTPWDWN2_MASK | \ + PMX_NFCE3_MASK) +#define PMX_NAND8BIT_1_MASK PMX_NFRSTPWDWN3_MASK + +#define PMX_NAND16BIT_1_MASK (PMX_KBD_ROWCOL25_MASK | PMX_NFIO8_15_MASK) +#define PMX_NAND_4CHIPS_MASK (PMX_NFCE1_MASK | PMX_NFCE2_MASK | \ + PMX_NFWPRT1_MASK | PMX_NFWPRT2_MASK | \ + PMX_KBD_ROW0_MASK | PMX_KBD_ROW1_MASK | \ + PMX_KBD_COL0_MASK | PMX_KBD_COL1_MASK) + +#define PMX_MCIFALL_1_MASK 0xF8000000 +#define PMX_MCIFALL_2_MASK 0x0FFFFFFF + +#define PMX_PCI_REG2_MASK (PMX_SMINCS2_MASK | PMX_SMINCS3_MASK | \ + PMX_CLCD2_MASK | PMX_KBD_ROWCOL68_MASK | \ + PMX_EGPIO_1_GRP_MASK | PMX_GPT0_TMR0_MASK | \ + PMX_GPT0_TMR1_MASK | PMX_GPT1_TMR0_MASK | \ + PMX_GPT1_TMR1_MASK | PMX_I2S1_MASK | \ + PMX_NFCE2_MASK) +#define PMX_PCI_REG3_MASK (PMX_TOUCH_XY_MASK | PMX_SSP0_CS0_MASK | \ + PMX_SSP0_CS1_2_MASK) + +#define PMX_SMII_0_1_2_MASK (PMX_CLCD2_MASK | PMX_KBD_ROWCOL68_MASK) +#define PMX_RGMII_REG1_MASK (PMX_MCI_DATA8_15_MASK | \ + PMX_GMIICOL_CRS_XFERER_MIITXCLK_MASK | \ + PMX_GMIID47_MASK) +#define PMX_RGMII_REG2_MASK (PMX_KBD_ROWCOL68_MASK | PMX_EGPIO_1_GRP_MASK |\ + PMX_KBD_ROW1_MASK | PMX_NFWPRT1_MASK | \ + PMX_KBD_ROW0_MASK | PMX_NFWPRT2_MASK) +#define PMX_RGMII_REG3_MASK (PMX_TOUCH_XY_MASK | PMX_SSP0_CS0_MASK | \ + PMX_SSP0_CS1_2_MASK) + +/* Pull DOWN and Pull UP */ +#define SPEAR1310_PAD_PU_CFG_1 (CONFIG_SYS_MISC_BASE + 0x600) +#define SPEAR1310_PAD_PD_CFG_1 (CONFIG_SYS_MISC_BASE + 0x620) + +/* Macro's to configure plgpios as Pull UP, Pull Down */ +#define CONFIG_SYS_RASCFG_BASE 0xD8400000 + #define SPEAR1310_GPIO_IN0 (CONFIG_SYS_RASCFG_BASE + 0x70) + #define SPEAR1310_GPIO_OUT0 (CONFIG_SYS_RASCFG_BASE + 0x90) + #define SPEAR1310_GPIO_EN0 (CONFIG_SYS_RASCFG_BASE + 0xB0) + #define SPEAR1310_GPIO_FUN_EN0 (CONFIG_SYS_RASCFG_BASE + 0xD0) + #define SPEAR1310_MAX_PLGPIOS 200 + +extern void spear1310_pins_default(void); +extern void spear1310_enable_pins(u32 ip, u32 mode); +extern void spear1310_configure_pin(u32 plgpio, u32 mode); +extern void spear1310_plgpio_set(u32 plgpio, u32 val); +extern int spear1310_plgpio_get(u32 plgpio); + +#endif diff --git a/arch/arm/include/asm/arch-spear13xx/spear1310_misc.h b/arch/arm/include/asm/arch-spear13xx/spear1310_misc.h new file mode 100644 index 0000000..8d8278e --- /dev/null +++ b/arch/arm/include/asm/arch-spear13xx/spear1310_misc.h @@ -0,0 +1,300 @@ +/* + * (C) Copyright 2012 + * Amit Virdi, ST Microelectronics, amit.virdi@st.com + * Vipin Kumar, ST Microelectronics, vipin.kumar@st.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __SPEAR1310_REVC_MISC_H +#define __SPEAR1310_REVC_MISC_H + +struct spear1310_misc_regs { + u32 soc_cfg; /* 0x000 */ + u32 bootstrap_cfg; /* 0x004 */ + u8 reserved_1[0x100 - 0x8]; + u32 pcm_cfg; /* 0x100 */ + u32 pcm_wkup_cfg; /* 0x104 */ + u32 switch_ctr; /* 0x108 */ + u8 reserved_2[0x200 - 0x10c]; + u32 sys_clk_ctrl; /* 0x200 */ + u32 sys_sw_res; /* 0x204 */ + u32 sys_clk_plltimer; /* 0x208 */ + u32 sys_clk_oscitimer; /* 0x20c */ + u32 pll_cfg; /* 0x210 */ + u32 pll1_ctr; /* 0x214 */ + u32 pll1_frq; /* 0x218 */ + u32 pll1_mod; /* 0x21c */ + u32 pll2_ctr; /* 0x220 */ + u32 pll2_frq; /* 0x224 */ + u32 pll2_mod; /* 0x228 */ + u32 pll3_ctr; /* 0x22c */ + u32 pll3_frq; /* 0x230 */ + u32 pll3_mod; /* 0x234 */ + u32 pll4_ctr; /* 0x238 */ + u32 pll4_frq; /* 0x23C */ + u32 pll4_mod; /* 0x240 */ + u32 perip_clk_cfg; /* 0x244 */ + u32 gmac_clk_cfg; /* 0x248 */ + u32 i2s_clk_cfg; /* 0x24c */ + u32 c3_clk_synt; /* 0x250 */ + u32 uart_clk_synt; /* 0x254 */ + u32 gmac_clk_synt; /* 0x258 */ + u32 mcif_sd_clk_synt; /* 0x25c */ + u32 mcif_cfxd_clk_synt; /* 0x260 */ + u32 adc_clk_synt; /* 0x264 */ + u32 amba_clk_sscg; /* 0x268 */ + u32 amba_clk_sscg_mod; /* 0x26c */ + u32 clcd_clk_sscg; /* 0x270 */ + u32 expi_cpu_sscg_mod; /* 0x274 */ + u32 gen_clk_sscg0; /* 0x278 */ + u32 gen_clk_sscg0_mod; /* 0x27c */ + u32 gen_clk_sscg1; /* 0x280 */ + u32 gen_clk_sscg1_mod; /* 0x284 */ + u32 gen_clk_sscg2; /* 0x288 */ + u32 gen_clk_sscg2_mod; /* 0x28C */ + u32 gen_clk_sscg3; /* 0x290 */ + u32 clcd_clk_sscg_mod; /* 0x294 */ + u32 expi_cpu_sscg; /* 0x298 */ + u32 gen_clk_sscg3_mod; /* 0x29c */ + u8 reserved_3[0x300 - 0x2a0]; + u32 perip1_clk_enb; /* 0x300 */ + u32 perip2_clk_enb; /* 0x304 */ + u32 perip1_sw_rst; /* 0x308 */ + u32 perip2_sw_rst; /* 0x30c */ + u32 ras_clk_enb; /* 0x310 */ + u32 ras_sw_rst; /* 0x314 */ + u8 reserved_4[0x380 - 0x318]; + u32 dmac_hs_sel; /* 0x380 */ + u32 dmac_sel; /* 0x384 */ + u32 dmac_flow_sel; /* 0x388 */ + u32 dmac_dir_sel; /* 0x38c */ + u32 endianess_cfg; /* 0x390 */ + u32 usbphy_gen_cfg; /* 0x394 */ + u32 usbphy_p1_cfg; /* 0x398 */ + u32 usbphy_p2_cfg; /* 0x39c */ + u32 usbphy_p3_cfg; /* 0x3a0 */ + u32 pcie_sata_cfg; /* 0x3a4 */ + u32 pcie_miphy_cfg_1; /* 0x3a8 */ + u32 pcie_miphy_cfg_2; /* 0x3ac */ + u32 perip_cfg; /* 0x3b0 */ + u32 fsmc_cfg; /* 0x3b4 */ + u32 mpmc_cfg; /* 0x3b8 */ + u32 mpmc_ctr_sts; /* 0x3bc */ + u8 reserved_5[0x400 - 0x3c0]; + u32 expif_clk_cfg; /* 0x400 */ + u32 expif_cfg; /* 0x404 */ + u32 expif_dmachs_flex; /* 0x408 */ + u8 reserved_6[0x41c - 0x40c]; + u32 expif_dmachs_simple; /* 0x41c */ + u32 expif_addr_expansion_tab_0; /* 0x420 */ + u32 expif_addr_expansion_tab_1; /* 0x424 */ + u32 expif_addr_expansion_tab_2; /* 0x428 */ + u32 expif_addr_expansion_tab_3; /* 0x42c */ + u32 expif_addr_expansion_tab_4; /* 0x430 */ + u32 expif_addr_expansion_tab_5; /* 0x434 */ + u32 expif_addr_expansion_tab_6; /* 0x438 */ + u32 expif_addr_expansion_tab_7; /* 0x43c */ + u8 reserved_7[0x500 - 0x440]; + u32 prc1_lock_ctr; /* 0x500 */ + u32 prc2_lock_ctr; /* 0x504 */ + u32 prc1_irq_ctr; /* 0x508 */ + u8 reserved_8[0x51c - 0x50c]; + u32 prc2_irq_ctr; /* 0x51c */ + u8 reserved_9[0x600 - 0x520]; + u32 pad_pu_cfg_1; /* 0x600 */ + u32 pad_pu_cfg_2; /* 0x604 */ + u32 pad_pu_cfg_3; /* 0x608 */ + u32 pad_pu_cfg_4; /* 0x60c */ + u32 pad_pu_cfg_5; /* 0x610 */ + u32 pad_pu_cfg_6; /* 0x614 */ + u32 pad_pu_cfg_7; /* 0x618 */ + u32 pad_pu_cfg_8; /* 0x61c */ + u32 pad_pd_cfg_1; /* 0x620 */ + u32 pad_pd_cfg_2; /* 0x624 */ + u32 pad_pd_cfg_3; /* 0x628 */ + u32 pad_pd_cfg_4; /* 0x62c */ + u32 pad_pd_cfg_5; /* 0x630 */ + u32 pad_pd_cfg_6; /* 0x634 */ + u32 pad_pd_cfg_7; /* 0x638 */ + u32 pad_pd_cfg_8; /* 0x63c */ + u32 pad_sleep_cfg; /* 0x640 */ + u32 pad_hyst_cfg; /* 0x644 */ + u32 pad_drv_cfg; /* 0x648 */ + u32 pad_slew_cfg; /* 0x64c */ + u32 pad_function_en_1; /* 0x650 */ + u32 pad_function_en_2; /* 0x654 */ + u32 pad_function_en_3; /* 0x658 */ + u32 pad_dir_sel_1; /* 0x65c */ + u32 pad_dir_sel_2; /* 0x660 */ + u32 pad_dir_sel_3; /* 0x664 */ + u32 ddr_pad_cfg; /* 0x668 */ + u8 reserved_10[0x700 - 0x66c]; + u32 compensation_1v8_2v5_3v3_1_cfg; /* 0x700 */ + u32 compensation_1v8_2v5_3v3_2_cfg; /* 0x704 */ + u32 compensation_3v3_1_cfg; /* 0x708 */ + u32 compensation_3v3_2_cfg; /* 0x70c */ + u32 compensation_3v3_3_cfg; /* 0x710 */ + u32 compensation_ddr_cfg; /* 0x714 */ + u8 reserved_11[0x800 - 0x718]; + u32 otp_prog_ctr; /* 0x800 */ + u32 otp_wdata1_1; /* 0x804 */ + u32 otp_wdata1_2; /* 0x808 */ + u32 otp_wdata1_3; /* 0x80c */ + u32 otp_wdata1_4; /* 0x810 */ + u32 otp_wdata1_5; /* 0x814 */ + u32 otp_wdata1_6; /* 0x818 */ + u32 otp_wdata1_7; /* 0x81c */ + u32 otp_wdata1_8; /* 0x820 */ + u32 otp_wdata2_1; /* 0x824 */ + u32 otp_wdata2_2; /* 0x828 */ + u32 otp_wdata2_3; /* 0x82c */ + u32 otp_wdata2_4; /* 0x830 */ + u32 otp_wdata2_5; /* 0x834 */ + u32 otp_wdata2_6; /* 0x838 */ + u32 otp_wdata2_7; /* 0x83c */ + u32 otp_wdata2_8; /* 0x840 */ + u32 otp_mask_1; /* 0x844 */ + u32 otp_mask_2; /* 0x848 */ + u32 otp_mask_3; /* 0x84c */ + u32 otp_mask_4; /* 0x850 */ + u32 otp_mask_5; /* 0x854 */ + u32 otp_mask_6; /* 0x858 */ + u32 otp_mask_7; /* 0x85c */ + u32 otp_mask_8; /* 0x860 */ + u32 otp_rdata1_1; /* 0x864 */ + u32 otp_rdata1_2; /* 0x868 */ + u32 otp_rdata1_3; /* 0x86c */ + u32 otp_rdata1_4; /* 0x870 */ + u32 otp_rdata1_5; /* 0x874 */ + u32 otp_rdata1_6; /* 0x878 */ + u32 otp_rdata1_7; /* 0x87c */ + u32 otp_rdata1_8; /* 0x880 */ + u32 otp_rdata2_1; /* 0x884 */ + u32 otp_rdata2_2; /* 0x888 */ + u32 otp_rdata2_3; /* 0x88c */ + u32 otp_rdata2_4; /* 0x890 */ + u32 otp_rdata2_5; /* 0x894 */ + u32 otp_rdata2_6; /* 0x898 */ + u32 otp_rdata2_7; /* 0x89c */ + u32 otp_rdata2_8; /* 0x8a0 */ + u32 otp_rdatam_1; /* 0x8a4 */ + u32 otp_rdatam_2; /* 0x8a8 */ + u32 otp_rdatam_3; /* 0x8ac */ + u32 otp_rdatam_4; /* 0x8b0 */ + u32 otp_rdatam_5; /* 0x8b4 */ + u32 otp_rdatam_6; /* 0x8b8 */ + u32 otp_rdatam_7; /* 0x8bc */ + u32 otp_rdatam_8; /* 0x8c0 */ + u32 thsens_cfg; /* 0x8c4 */ + u8 reserved_12[0x900 - 0x8c8]; + u32 a9sm_clusterid; /* 0x900 */ + u32 a9sm_status; /* 0x904 */ + u32 a9sm_debug; /* 0x908 */ + u32 a9sm_filter; /* 0x90c */ + u32 a9sm_parity_cfg; /* 0x910 */ + u32 a9sm_parity_err; /* 0x914 */ + u8 reserved_13[0xa00 - 0x918]; + u32 die_id_1; /* 0xa00 */ + u32 die_id_2; /* 0xa04 */ + u32 die_id_3; /* 0xa08 */ + u32 die_id_4; /* 0xa0c */ + u8 reserved_14[0xb00 - 0xa10]; + u32 ras1_gpp_inp; /* 0xb00 */ + u32 ras2_gpp_inp; /* 0xb04 */ + u32 ras1_gpp_out; /* 0xb08 */ + u32 ras2_gpp_out; /* 0xb0c */ + u8 reserved_15[0xc00 - 0xa10]; + u32 axi_cache_user_ctrl_0; /* 0xc00 */ + u32 axi_cache_user_ctrl_1; /* 0xc04 */ + u32 axi_cache_user_ctrl_2; /* 0xc08 */ + u32 axi_cache_user_ctrl_3; /* 0xc0c */ + u32 ahb_cache_user_ctrl_0; /* 0xc10 */ + u32 ahb_cache_user_ctrl_1; /* 0xc14 */ + u32 ahb_cache_user_ctrl_2; /* 0xc18 */ + u32 ahb_cache_user_ctrl_3; /* 0xc1c */ + u32 ahb_cache_user_ctrl_4; /* 0xc20 */ + u32 ahb_cache_user_ctrl_5; /* 0xc24 */ + u32 ahb_cache_user_ctrl_6; /* 0xc28 */ + u32 ahb_cache_user_ctrl_7; /* 0xc2c */ + u8 reserved_16[0x1000 - 0xc30]; + u32 usb_test; /* 0x1000 */ + u32 misc_cfg; /* 0x1004 */ +}; + +/* PHERIP1_CLOCK ENABLE */ +#define SPEAR1310_C3_CLKEN 0x20000000 +#define SPEAR1310_GPT1_CLKEN 0x00200000 +#define SPEAR1310_I2C_CLKEN 0x00040000 +#define SPEAR1310_SSP_CLKEN 0x00020000 +#define SPEAR1310_UART_CLKEN 0x00008000 +#define SPEAR1310_UDC_UPD_CLKEN 0x00000800 +#define SPEAR1310_UHC1_CLKEN 0x00000200 +#define SPEAR1310_GETH_CLKEN 0x00000100 +#define SPEAR1310_SD_CLKEN 0x00000040 +#define SPEAR1310_SMI_CLKEN 0x00000020 +#define SPEAR1310_FSMC_CLKEN 0x00000010 + +/* perip1_sw_rst */ +#define SPEAR1310_C3_SWRST 0x20000000 +#define SPEAR1310_UDC_UPD_SWRST 0x00000800 +#define SPEAR1310_UHC1_SWRST 0x00000200 + +/* perip_clk_cfg definitions */ +#define SPEAR1310_UART48M 0x00000000 +#define SPEAR1310_UARTCLKMSK 0x00000030 + +/* gmac_clk_cfg definitions */ +#define SPEAR1310_PHYIF_MSK 0x00000070 +#define SPEAR1310_PHYIF_RMII 0x00000040 +#define SPEAR1310_PHYIF_SGMII 0x00000020 +#define SPEAR1310_PHYIF_RGMII 0x00000010 +#define SPEAR1310_PHYIF_GMII 0x00000000 +#define SPEAR1310_GMII_SYNT_ENB 0x00000008 +#define SPEAR1310_CLKSEL_OSCI3 0x00000004 +#define SPEAR1310_CLKSEL_PLL2 0x00000002 +#define SPEAR1310_CLKSEL_PAD 0x00000000 + +/* usbphy_gen_cfg definitions */ +#define SPEAR1310_USB_PLL_LOCK 0x01000000 +#define SPEAR1310_USBUTMI_RST 0x00008000 +#define SPEAR1310_USBPHY_RST 0x00002000 +#define SPEAR1310_USBPHY_POR 0x00001000 +#define SPEAR1310_COMMON_PWDN 0x00000000 + +/* perip_cfg definitions */ +#define SPEAR1310_MCIF_MSK 0x00000060 +#define SPEAR1310_MCIF_SD 0x00000020 + +/* fsmc_cfg definitions */ +#define SPEAR1310_NANDCS0_NORCS4 0x00000001 +#define SPEAR1310_NANDCS0_NORCS5 0x00000002 +#define SPEAR1310_NANDCS0_NORCS6 0x00000004 +#define SPEAR1310_NANDCS0_NORCS7 0x00000008 + +/* synth registers definitions */ +#define SPEAR1310_SYNT_CLKENB 0x80000000 +#define SPEAR1310_SYNT_FIN_FULL 0x04000000 +#define SPEAR1310_SYNT_X_1 0x00010000 +#define SPEAR1310_SYNT_X_2 0x00020000 +#define SPEAR1310_SYNT_Y_2 0x00000002 +#define SPEAR1310_SYNT_Y_5 0x00000005 +#define SPEAR1310_SYNT_Y_21 0x00000015 + +#endif diff --git a/drivers/usb/host/ehci-spear.c b/drivers/usb/host/ehci-spear.c index 7a57379..61d30f8 100644 --- a/drivers/usb/host/ehci-spear.c +++ b/drivers/usb/host/ehci-spear.c @@ -59,6 +59,8 @@ int ehci_hcd_stop(int index) spear3xx_usbh_stop(); #elif defined(CONFIG_ARCH_SPEAR6XX) spear6xx_usbh_stop(); +#elif defined(CONFIG_SOC_SPEAR1310) + spear1310_usbh_stop(); #elif defined(CONFIG_SOC_SPEAR1340) spear1340_usbh_stop(); #else