Patchwork [U-Boot,SPEAr,Enhancement,2/9] spear3xx: Add pinmux support

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Submitter Vipin Kumar
Date Nov. 2, 2012, 5:39 p.m.
Message ID <00bc4d08e4e3ed1023db9b8853be26f351dfa3b1.1351877331.git.vipin.kumar@st.com>
Download mbox | patch
Permalink /patch/196688/
State New
Delegated to: Vipin Kumar
Headers show

Comments

Vipin Kumar - Nov. 2, 2012, 5:39 p.m.
The pinmux layer for spear family of devices exports three APIs for the board.
<soc>_pins_default:
	This routine puts all the SoC pins in a default (safe) state. This API
	can be used by the respective boards to place all pins in a safe mode
	before going ahead with initializing with pinmux
<soc>_select_mode:
	This routine selects a particular SoC mode. It is particularly for those
	SoCs which have several modes one of which can be selected. spear300 and
	spear320 are such SoCs.
<soc>_enable_pins:
	This routine enables the desired pins. It accepts two arguments. First
	is 'ip' which indicates which controller pins are to be enabled and the
	second is 'mode' in which this ip has to run eg. ip can be PMX_ETH0 and
	mode can be PMX_ETH_RGMII/PMX_ETH_MII etc
<soc> spear320_configure_pin:
	Configures the selected pin in GPIO, PULLDOWN/PULLUP mode
<soc>_plgpio_get:
	Gets the value at a particular GPIO
<soc>_plgpio_set(u32 plgpio, u32 val)
	Sets the value at a particular GPIO

Additionally, this patch also defines mdio_get_control for spear3xx which also
falls in the purview of pinmux. This is defined because spear310 and spear320
devices need to control mdio lines dynamically because these are shared. Define
the mdio_get_control routine to achieve this.

Signed-off-by: Vipin Kumar <vipin.kumar@st.com>
---
 arch/arm/cpu/arm926ejs/spear/Makefile      |   6 +-
 arch/arm/cpu/arm926ejs/spear/spear300.c    | 140 +++++
 arch/arm/cpu/arm926ejs/spear/spear310.c    | 162 ++++++
 arch/arm/cpu/arm926ejs/spear/spear320.c    | 860 +++++++++++++++++++++++++++++
 arch/arm/cpu/arm926ejs/spear/spear3xx.c    |  87 +++
 arch/arm/include/asm/arch-spear/pinmux.h   | 133 +++++
 arch/arm/include/asm/arch-spear/spear300.h |  27 +
 arch/arm/include/asm/arch-spear/spear310.h |  13 +
 arch/arm/include/asm/arch-spear/spear320.h | 426 ++++++++++++++
 arch/arm/include/asm/arch-spear/spear3xx.h |  22 +
 board/st/spear/spear300evb.c               |  19 +
 board/st/spear/spear310evb.c               |  16 +
 board/st/spear/spear320plc.c               |  38 +-
 board/st/spear/spear600evb.c               |   7 +
 14 files changed, 1949 insertions(+), 7 deletions(-)
 create mode 100644 arch/arm/cpu/arm926ejs/spear/spear300.c
 create mode 100644 arch/arm/cpu/arm926ejs/spear/spear310.c
 create mode 100644 arch/arm/cpu/arm926ejs/spear/spear320.c
 create mode 100644 arch/arm/include/asm/arch-spear/pinmux.h

Patch

diff --git a/arch/arm/cpu/arm926ejs/spear/Makefile b/arch/arm/cpu/arm926ejs/spear/Makefile
index cf29ede..2e026ee 100644
--- a/arch/arm/cpu/arm926ejs/spear/Makefile
+++ b/arch/arm/cpu/arm926ejs/spear/Makefile
@@ -32,6 +32,9 @@  COBJS-y += timer.o
 
 COBJS-$(CONFIG_ST_EMI) += emi.o
 COBJS-$(CONFIG_ARCH_SPEAR3XX) += spear3xx.o
+COBJS-$(CONFIG_SOC_SPEAR300) += spear300.o
+COBJS-$(CONFIG_SOC_SPEAR310) += spear310.o
+COBJS-$(CONFIG_SOC_SPEAR320) += spear320.o
 COBJS-$(CONFIG_ARCH_SPEAR6XX) += spear6xx.o
 
 ifdef CONFIG_SPL_BUILD
@@ -39,9 +42,8 @@  COBJS-y	+= spl.o spl_boot.o
 COBJS-$(CONFIG_SOC_SPEAR600) += spl-spear600.o
 endif
 
-SRCS	:= $(START:.o=.S) $(COBJS-y:.o=.c)
+SRCS	:= $(COBJS-y:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS-y))
-START	:= $(addprefix $(obj),$(START))
 
 all:	$(obj).depend $(LIB)
 
diff --git a/arch/arm/cpu/arm926ejs/spear/spear300.c b/arch/arm/cpu/arm926ejs/spear/spear300.c
new file mode 100644
index 0000000..11c6ae7
--- /dev/null
+++ b/arch/arm/cpu/arm926ejs/spear/spear300.c
@@ -0,0 +1,140 @@ 
+/*
+ * (C) Copyright 2012
+ * Vipin Kumar, ST Microelectronics, vipin.kumar@st.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/pinmux.h>
+
+/*
+ * Pinmux support
+ *
+ * The routines are defined by the name enable_xxx_pins with xxx being the
+ * peripheral controller for which pins are to be enabled
+ *
+ * PS: In some cases, a multiple combination of pins can be enabled for the same
+ * peripheral. In those cases, the routine is defined as enable_xxx_atob_pins.
+ * Here, xxx is peripheral itself and a and b represent the pin numbers which
+ * need to be enabled for this controller
+ */
+
+/* NAND pinmux */
+static void enable_nand_2chips_pins(void)
+{
+	pinmux_maskval(SPEAR300_RAS_REG1,
+			PMX_FIRDA_MASK,
+			0);
+}
+
+static void enable_nand_4chips_pins(void)
+{
+	pinmux_maskval(SPEAR300_RAS_REG1,
+			PMX_FIRDA_MASK | PMX_UART0_MASK,
+			0);
+}
+
+static void enable_nand_pins(u32 mode)
+{
+	switch (mode) {
+	case PMX_NAND_2CHIP:
+		enable_nand_2chips_pins();
+		break;
+	case PMX_NAND_4CHIP:
+		enable_nand_4chips_pins();
+		break;
+	}
+}
+
+/* SDMMC pinmux */
+static void enable_sdmmc_4bit_pins(void)
+{
+	pinmux_maskval(SPEAR300_RAS_REG1,
+			PMX_GPIO_PIN0_MASK | PMX_GPIO_PIN1_MASK |
+			PMX_GPIO_PIN2_MASK | PMX_GPIO_PIN3_MASK |
+			PMX_GPIO_PIN4_MASK | PMX_GPIO_PIN5_MASK,
+			0);
+}
+
+static void enable_sdmmc_8bit_pins(void)
+{
+	pinmux_maskval(SPEAR300_RAS_REG1,
+			PMX_GPIO_PIN0_MASK | PMX_GPIO_PIN1_MASK |
+			PMX_GPIO_PIN2_MASK | PMX_GPIO_PIN3_MASK |
+			PMX_GPIO_PIN4_MASK | PMX_GPIO_PIN5_MASK | PMX_MII_MASK,
+			0);
+}
+
+static void enable_sdmmc_pins(u32 mode)
+{
+	switch (mode) {
+	case PMX_SDMMC_4BIT:
+		enable_sdmmc_4bit_pins();
+		break;
+	case PMX_SDMMC_8BIT:
+		enable_sdmmc_8bit_pins();
+		break;
+	}
+}
+
+/**
+ * spear300_select_mode
+ * @mode:	SoC mode to e selected
+ */
+void spear300_select_mode(u32 mode)
+{
+	pinmux_maskval(SPEAR300_RAS_REG2,
+			SPEAR300_MODE_MSK,
+			mode);
+}
+
+/**
+ * spear300_pins_default: Select a default safe mode as startup
+ * Generally, all pins are enabled in input mode at initialization. This can be
+ * done either by
+ * - enabling gpio's and keeping all pins in gpio inputs
+ * - a platform specific way.
+ */
+void spear300_pins_default(void)
+{
+}
+
+/**
+ * spear300_enable_pins - enable pins for fixed peripherals on spear3xx devices
+ * @ip:		Peripheral index
+ * @mode:	Mode in which peripheral has to run (16bit/8bit etc)
+ *
+ * Enable the pins for fixed peripherals on spear3xx devices.
+ * mode represents the mode in which the peripheral may work and may result in
+ * different pins being enabled. eg GMII mode and RGMII mode may need different
+ * pins on devices to be enabled
+ */
+void spear300_enable_pins(u32 ip, u32 mode)
+{
+	if (PMX_FSMCNAND == ip)
+		enable_nand_pins(mode);
+	else if (PMX_SDMMC == ip)
+		enable_sdmmc_pins(mode);
+	else if ((PMX_I2C0 == ip) || (PMX_SSP0 == ip) || \
+			(PMX_ETH0 == ip) || (PMX_UART0 == ip))
+		spear3xx_enable_pins(ip, mode);
+}
diff --git a/arch/arm/cpu/arm926ejs/spear/spear310.c b/arch/arm/cpu/arm926ejs/spear/spear310.c
new file mode 100644
index 0000000..d1ab43f
--- /dev/null
+++ b/arch/arm/cpu/arm926ejs/spear/spear310.c
@@ -0,0 +1,162 @@ 
+/*
+ * (C) Copyright 2012
+ * Vipin Kumar, ST Microelectronics, vipin.kumar@st.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/pinmux.h>
+
+/*
+ * Function to dnamically set control of shared mdio lines to concerned
+ * mac controller
+ */
+void arch_get_mdio_control(const char *devname)
+{
+	u32 val;
+
+	val = readl(SPEAR310_SMII_REG);
+	val &= ~SPEAR310_SMII_PHY_MASK;
+
+	if (!strcmp(devname, "macb0"))
+		val |= (0x0 << SPEAR310_SMII_PHY_SHIFT);
+	else if (!strcmp(devname, "macb1"))
+		val |= (0x1 << SPEAR310_SMII_PHY_SHIFT);
+	else if (!strcmp(devname, "macb2"))
+		val |= (0x2 << SPEAR310_SMII_PHY_SHIFT);
+	else if (!strcmp(devname, "macb3"))
+		val |= (0x3 << SPEAR310_SMII_PHY_SHIFT);
+	else
+		printf("no such device:%s\n", devname);
+
+	writel(val, SPEAR310_SMII_REG);
+}
+
+/*
+ * Pinmux support
+ *
+ * The routines are defined by the name enable_xxx_pins with xxx being the
+ * peripheral controller for which pins are to be enabled
+ *
+ * PS: In some cases, a multiple combination of pins can be enabled for the same
+ * peripheral. In those cases, the routine is defined as enable_xxx_atob_pins.
+ * Here, xxx is peripheral itself and a and b represent the pin numbers which
+ * need to be enabled for this controller
+ */
+
+/* Pinmux for EMI */
+static void enable_emi_pins(void)
+{
+	pinmux_maskval(SPEAR310_FUNCENB_REG,
+			PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK,
+			0);
+}
+
+/* Pinmux for UART1 */
+static void enable_uart1_pins(void)
+{
+	pinmux_maskval(SPEAR310_FUNCENB_REG,
+			PMX_FIRDA_MASK,
+			0);
+}
+
+/* Pinmux for UART2 */
+static void enable_uart2_pins(void)
+{
+	pinmux_maskval(SPEAR310_FUNCENB_REG,
+			PMX_TIMER_0_1_MASK,
+			0);
+}
+
+/* Pinmux for UART3 */
+static void enable_uart3_pins(void)
+{
+	pinmux_maskval(SPEAR310_FUNCENB_REG,
+			PMX_UART0_MODEM_MASK,
+			0);
+}
+
+/* Pinmux for UART4 */
+static void enable_uart4_pins(void)
+{
+	pinmux_maskval(SPEAR310_FUNCENB_REG,
+			PMX_UART0_MODEM_MASK,
+			0);
+}
+
+/* Pinmux for UART5 */
+static void enable_uart5_pins(void)
+{
+	pinmux_maskval(SPEAR310_FUNCENB_REG,
+			PMX_UART0_MODEM_MASK,
+			0);
+}
+
+/* Pinmux for NAND */
+static void enable_nand_pins(void)
+{
+	pinmux_maskval(SPEAR310_FUNCENB_REG,
+			PMX_SSP_CS_MASK,
+			0);
+}
+
+/**
+ * spear310_pins_default: Select a default safe mode as startup
+ * Generally, all pins are enabled in input mode at initialization. This can be
+ * done either by
+ * - enabling gpio's and keeping all pins in gpio inputs
+ * - a platform specific way.
+ */
+void spear310_pins_default(void)
+{
+}
+
+/**
+ * spear310_enable_pins - enable pins for fixed peripherals on spear3xx devices
+ * @ip:		Peripheral index
+ * @mode:	Mode in which peripheral has to run (16bit/8bit etc)
+ *
+ * Enable the pins for fixed peripherals on spear3xx devices.
+ * mode represents the mode in which the peripheral may work and may result in
+ * different pins being enabled. eg GMII mode and RGMII mode may need different
+ * pins on devices to be enabled
+ */
+void spear310_enable_pins(u32 ip, u32 mode)
+{
+	if (PMX_FSMCNAND == ip)
+		enable_nand_pins();
+	else if (PMX_EMI == ip)
+		enable_emi_pins();
+	else if (PMX_UART1 == ip)
+		enable_uart1_pins();
+	else if (PMX_UART2 == ip)
+		enable_uart2_pins();
+	else if (PMX_UART3 == ip)
+		enable_uart3_pins();
+	else if (PMX_UART4 == ip)
+		enable_uart4_pins();
+	else if (PMX_UART5 == ip)
+		enable_uart5_pins();
+	else if ((PMX_I2C0 == ip) || (PMX_SSP0 == ip) || \
+			(PMX_ETH0 == ip) || (PMX_UART0 == ip))
+		spear3xx_enable_pins(ip, mode);
+}
diff --git a/arch/arm/cpu/arm926ejs/spear/spear320.c b/arch/arm/cpu/arm926ejs/spear/spear320.c
new file mode 100644
index 0000000..10c921c
--- /dev/null
+++ b/arch/arm/cpu/arm926ejs/spear/spear320.c
@@ -0,0 +1,860 @@ 
+/*
+ * (C) Copyright 2012
+ * Vipin Kumar, ST Microelectronics, vipin.kumar@st.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/pinmux.h>
+
+void arch_get_mdio_control(const char *devname)
+{
+	u32 val;
+
+	val = readl(SPEAR320_CONTROL_REG);
+
+	if (!strcmp(devname, "macb0"))
+		val &= ~(0x1 << MII_ENB_SHFT);
+	else if (!strcmp(devname, "macb1"))
+		val |= (0x1 << MII_ENB_SHFT);
+	else
+		printf("no such device:%s\n", devname);
+
+	writel(val, SPEAR320_CONTROL_REG);
+}
+
+/*
+ * Pinmux support
+ *
+ * The routines are defined by the name enable_xxx_pins with xxx being the
+ * peripheral controller for which pins are to be enabled
+ *
+ * PS: In some cases, a multiple combination of pins can be enabled for the same
+ * peripheral. In those cases, the routine is defined as enable_xxx_atob_pins.
+ * Here, xxx is peripheral itself and a and b represent the pin numbers which
+ * need to be enabled for this controller
+ */
+
+/* Pinmux for EMI */
+static void enable_emi_pins(void)
+{
+	pinmux_maskval(SPEAR320_IP_SEL_PAD_40_49_REG,
+			PMX_PL_46_47_MASK | PMX_PL_48_49_MASK,
+			PMX_FSMC_EMI_PL_46_47_VAL | PMX_FSMC_EMI_PL_48_49_VAL);
+	pinmux_maskval(SPEAR320_IP_SEL_PAD_50_59_REG,
+			PMX_PL_50_51_MASK | PMX_PL_52_53_MASK |
+			PMX_PL_54_55_56_MASK | PMX_PL_58_59_MASK,
+			PMX_EMI_PL_50_51_VAL | PMX_EMI_PL_52_53_VAL |
+			PMX_FSMC_EMI_PL_54_55_56_VAL |
+			PMX_FSMC_EMI_PL_58_59_VAL);
+	pinmux_maskval(SPEAR320_IP_SEL_PAD_60_69_REG,
+			PMX_PL_69_MASK,
+			PMX_EMI_PL_69_VAL);
+	pinmux_maskval(SPEAR320_IP_SEL_PAD_70_79_REG,
+			PMX_PL_70_MASK | PMX_PL_71_72_MASK | PMX_PL_73_MASK |
+			PMX_PL_74_MASK | PMX_PL_75_76_MASK |
+			PMX_PL_77_78_79_MASK,
+			PMX_FSMC_EMI_PL_70_VAL | PMX_FSMC_EMI_PL_71_72_VAL |
+			PMX_FSMC_EMI_PL_73_VAL | PMX_EMI_PL_74_VAL |
+			PMX_EMI_PL_75_76_VAL | PMX_EMI_PL_77_78_79_VAL);
+	pinmux_maskval(SPEAR320_IP_SEL_PAD_80_89_REG,
+			PMX_PL_80_TO_85_MASK | PMX_PL_86_87_MASK |
+			PMX_PL_88_89_MASK,
+			PMX_EMI_PL_80_TO_85_VAL | PMX_EMI_PL_86_87_VAL |
+			PMX_EMI_PL_88_89_VAL);
+	pinmux_maskval(SPEAR320_IP_SEL_PAD_90_99_REG,
+			PMX_PL_90_91_MASK | PMX_PL_92_93_MASK |
+			PMX_PL_94_95_MASK | PMX_PL_96_97_MASK,
+			PMX_EMI1_PL_90_91_VAL | PMX_EMI1_PL_92_93_VAL |
+			PMX_EMI1_PL_94_95_VAL | PMX_EMI1_PL_96_97_VAL);
+	pinmux_maskval(SPEAR320_EXT_CTRL_REG,
+			EMI_FSMC_DYNAMIC_MUX_MASK,
+			EMI_FSMC_DYNAMIC_MUX_MASK);
+}
+
+/* Pinmux for 8bit NAND interface */
+static void enable_nand8bit_pins(void)
+{
+	pinmux_maskval(SPEAR320_IP_SEL_PAD_50_59_REG,
+			PMX_PL_52_53_MASK | PMX_PL_54_55_56_MASK |
+			PMX_PL_57_MASK | PMX_PL_58_59_MASK,
+			PMX_FSMC_PL_52_53_VAL | PMX_FSMC_EMI_PL_54_55_56_VAL |
+			PMX_FSMC_PL_57_VAL | PMX_FSMC_EMI_PL_58_59_VAL);
+	pinmux_maskval(SPEAR320_IP_SEL_PAD_60_69_REG,
+			PMX_PL_60_MASK | PMX_PL_61_TO_64_MASK |
+			PMX_PL_65_TO_68_MASK,
+			PMX_FSMC_PL_60_VAL | PMX_FSMC_PL_61_TO_64_VAL |
+			PMX_FSMC_PL_65_TO_68_VAL);
+	pinmux_maskval(SPEAR320_EXT_CTRL_REG,
+			EMI_FSMC_DYNAMIC_MUX_MASK,
+			EMI_FSMC_DYNAMIC_MUX_MASK);
+}
+
+/* Pinmux for 16bit NAND interface */
+static void enable_nand16bit_pins(void)
+{
+	enable_nand8bit_pins();
+
+	pinmux_maskval(SPEAR320_RASSELECT_REG,
+			PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK,
+			0);
+	pinmux_maskval(SPEAR320_IP_SEL_PAD_40_49_REG,
+			PMX_PL_46_47_MASK | PMX_PL_48_49_MASK,
+			PMX_FSMC_EMI_PL_46_47_VAL | PMX_FSMC_EMI_PL_48_49_VAL);
+	pinmux_maskval(SPEAR320_IP_SEL_PAD_70_79_REG,
+			PMX_PL_70_MASK | PMX_PL_71_72_MASK | PMX_PL_73_MASK,
+			PMX_FSMC_EMI_PL_70_VAL | PMX_FSMC_EMI_PL_71_72_VAL |
+			PMX_FSMC_EMI_PL_73_VAL);
+}
+
+static void enable_nand_pins(u32 mode)
+{
+	switch (mode) {
+	case PMX_NAND_8BIT:
+		enable_nand8bit_pins();
+		break;
+	case PMX_NAND_16BIT:
+		enable_nand16bit_pins();
+	}
+}
+
+/* Pinmux for sdmmc led */
+static void enable_sdmmc_led_pins(void)
+{
+	pinmux_maskval(SPEAR320_RASSELECT_REG,
+			PMX_SSP_CS_MASK,
+			0);
+	pinmux_maskval(SPEAR320_IP_SEL_PAD_30_39_REG,
+			PMX_PL_34_MASK,
+			PMX_PWM2_PL_34_VAL);
+}
+
+static void enable_sdmmc_common_pins(void)
+{
+	pinmux_maskval(SPEAR320_RASSELECT_REG,
+			PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK,
+			0);
+	pinmux_maskval(SPEAR320_IP_SEL_PAD_40_49_REG,
+			PMX_PL_43_MASK | PMX_PL_44_45_MASK | PMX_PL_46_47_MASK |
+			PMX_PL_48_49_MASK,
+			PMX_SDHCI_PL_43_VAL | PMX_SDHCI_PL_44_45_VAL |
+			PMX_SDHCI_PL_46_47_VAL | PMX_SDHCI_PL_48_49_VAL);
+	pinmux_maskval(SPEAR320_IP_SEL_PAD_50_59_REG,
+			PMX_PL_50_MASK,
+			PMX_SDHCI_PL_50_VAL);
+	pinmux_maskval(SPEAR320_IP_SEL_PAD_90_99_REG,
+			PMX_PL_99_MASK,
+			PMX_SDHCI_PL_99_VAL);
+	pinmux_maskval(SPEAR320_IP_SEL_MIX_PAD_REG,
+			PMX_PL_100_101_MASK,
+			PMX_SDHCI_PL_100_101_VAL);
+}
+
+static void enable_sdmmc_cd12_pins(void)
+{
+	enable_sdmmc_common_pins();
+
+	pinmux_maskval(SPEAR320_RASSELECT_REG,
+			PMX_MII_MASK,
+			0);
+	pinmux_maskval(SPEAR320_IP_SEL_PAD_10_19_REG,
+			PMX_PL_12_MASK,
+			PMX_SDHCI_CD_PL_12_VAL);
+	pinmux_maskval(SPEAR320_IP_SEL_MIX_PAD_REG,
+			PMX_SDHCI_CD_PORT_SEL_MASK,
+			PMX_SDHCI_CD_PORT_12_VAL);
+}
+
+static void enable_sdmmc_cd51_pins(void)
+{
+	enable_sdmmc_common_pins();
+
+	pinmux_maskval(SPEAR320_IP_SEL_PAD_50_59_REG,
+			PMX_PL_51_MASK,
+			PMX_SDHCI_CD_PL_51_VAL);
+	pinmux_maskval(SPEAR320_IP_SEL_MIX_PAD_REG,
+			PMX_SDHCI_CD_PORT_SEL_MASK,
+			PMX_SDHCI_CD_PORT_51_VAL);
+}
+
+static void enable_sdmmc_pins(u32 mode)
+{
+	switch (mode) {
+	case PMX_SDMMC_LED:
+		enable_sdmmc_led_pins();
+		break;
+	case PMX_SDMMC_CD12:
+		enable_sdmmc_cd12_pins();
+		break;
+	case PMX_SDMMC_CD51:
+		enable_sdmmc_cd51_pins();
+		break;
+	}
+}
+
+/* Pinmux for UART1 */
+static void enable_uart1simple_pins(void)
+{
+	pinmux_maskval(SPEAR320_RASSELECT_REG,
+			PMX_GPIO_PIN0_MASK | PMX_GPIO_PIN1_MASK,
+			0);
+	pinmux_maskval(SPEAR320_IP_SEL_PAD_20_29_REG,
+			PMX_PL_28_29_MASK,
+			PMX_UART1_PL_28_29_VAL);
+}
+
+/* Pinmux for UART1 modem */
+static void enable_uart1_modem_2to7_pins(void)
+{
+	pinmux_maskval(SPEAR320_RASSELECT_REG,
+			PMX_UART0_MASK | PMX_I2C_MASK | PMX_SSP_MASK,
+			0);
+	pinmux_maskval(SPEAR320_IP_SEL_PAD_0_9_REG,
+			PMX_PL_2_3_MASK | PMX_PL_6_7_MASK,
+			PMX_UART1_ENH_PL_2_3_VAL | PMX_UART1_ENH_PL_4_5_VAL |
+			PMX_UART1_ENH_PL_6_7_VAL);
+	pinmux_maskval(SPEAR320_IP_SEL_MIX_PAD_REG,
+			PMX_UART1_ENH_PORT_SEL_MASK,
+			PMX_UART1_ENH_PORT_3_TO_5_7_VAL);
+}
+
+static void enable_uart1_modem_31to36_pins(void)
+{
+	pinmux_maskval(SPEAR320_RASSELECT_REG,
+			PMX_GPIO_PIN3_MASK | PMX_GPIO_PIN4_MASK |
+			PMX_GPIO_PIN5_MASK | PMX_SSP_CS_MASK,
+			0);
+	pinmux_maskval(SPEAR320_IP_SEL_PAD_30_39_REG,
+			PMX_PL_31_MASK | PMX_PL_32_33_MASK | PMX_PL_34_MASK |
+			PMX_PL_35_MASK | PMX_PL_36_MASK,
+			PMX_UART1_ENH_PL_31_VAL | PMX_UART1_ENH_PL_32_33_VAL |
+			PMX_UART1_ENH_PL_34_VAL | PMX_UART1_ENH_PL_35_VAL |
+			PMX_UART1_ENH_PL_36_VAL);
+	pinmux_maskval(SPEAR320_IP_SEL_MIX_PAD_REG,
+			PMX_UART1_ENH_PORT_SEL_MASK,
+			PMX_UART1_ENH_PORT_32_TO_34_36_VAL);
+}
+
+static void enable_uart1_modem_34to45_pins(void)
+{
+	pinmux_maskval(SPEAR320_RASSELECT_REG,
+			PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK |
+			PMX_SSP_CS_MASK,
+			0);
+	pinmux_maskval(SPEAR320_IP_SEL_PAD_30_39_REG,
+			PMX_PL_34_MASK | PMX_PL_35_MASK | PMX_PL_36_MASK,
+			PMX_UART1_ENH_PL_34_VAL | PMX_UART1_ENH_PL_35_VAL |
+			PMX_UART1_ENH_PL_36_VAL);
+	pinmux_maskval(SPEAR320_IP_SEL_PAD_40_49_REG,
+			PMX_PL_43_MASK | PMX_PL_44_45_MASK,
+			PMX_UART1_ENH_PL_43_VAL | PMX_UART1_ENH_PL_44_45_VAL);
+	pinmux_maskval(SPEAR320_IP_SEL_MIX_PAD_REG,
+			PMX_UART1_ENH_PORT_SEL_MASK,
+			PMX_UART1_ENH_PORT_44_45_34_36_VAL);
+}
+
+static void enable_uart1_modem_80to85_pins(void)
+{
+	pinmux_maskval(SPEAR320_IP_SEL_PAD_80_89_REG,
+			PMX_PL_80_TO_85_MASK,
+			PMX_UART1_ENH_PL_80_TO_85_VAL);
+	pinmux_maskval(SPEAR320_IP_SEL_PAD_40_49_REG,
+			PMX_PL_43_MASK | PMX_PL_44_45_MASK,
+			PMX_UART1_ENH_PL_43_VAL | PMX_UART1_ENH_PL_44_45_VAL);
+	pinmux_maskval(SPEAR320_IP_SEL_MIX_PAD_REG,
+			PMX_UART1_ENH_PORT_SEL_MASK,
+			PMX_UART1_ENH_PORT_81_TO_85_VAL);
+}
+
+static void enable_uart1_pins(u32 mode)
+{
+	switch (mode) {
+	case PMX_UART_SIMPLE:
+		enable_uart1simple_pins();
+		break;
+	case PMX_UART_MDM_2_7:
+		enable_uart1_modem_2to7_pins();
+		break;
+	case PMX_UART_MDM_31_36:
+		enable_uart1_modem_31to36_pins();
+		break;
+	case PMX_UART_MDM_34_45:
+		enable_uart1_modem_34to45_pins();
+		break;
+	case PMX_UART_MDM_80_85:
+		enable_uart1_modem_80to85_pins();
+		break;
+	}
+}
+
+/* Pinmux for UART2 */
+static void enable_uart2_pins(void)
+{
+	pinmux_maskval(SPEAR320_RASSELECT_REG,
+			PMX_FIRDA_MASK,
+			0);
+	pinmux_maskval(SPEAR320_IP_SEL_PAD_0_9_REG,
+			PMX_PL_0_1_MASK,
+			PMX_UART2_PL_0_1_VAL);
+};
+
+/* Pinmux for SSP1 */
+static void enable_ssp1_17to20_pins(void)
+{
+	pinmux_maskval(SPEAR320_RASSELECT_REG,
+			PMX_MII_MASK,
+			0);
+	pinmux_maskval(SPEAR320_IP_SEL_PAD_10_19_REG,
+			PMX_PL_17_18_MASK | PMX_PL_19_MASK,
+			PMX_SSP1_PL_17_18_19_20_VAL);
+	pinmux_maskval(SPEAR320_IP_SEL_PAD_20_29_REG,
+			PMX_PL_20_MASK,
+			PMX_SSP1_PL_17_18_19_20_VAL);
+	pinmux_maskval(SPEAR320_IP_SEL_MIX_PAD_REG,
+			PMX_SSP1_PORT_SEL_MASK,
+			PMX_SSP1_PORT_17_TO_20_VAL);
+}
+
+static void enable_ssp1_36to39_pins(void)
+{
+	pinmux_maskval(SPEAR320_RASSELECT_REG,
+			PMX_UART0_MODEM_MASK | PMX_SSP_CS_MASK,
+			0);
+	pinmux_maskval(SPEAR320_IP_SEL_PAD_30_39_REG,
+			PMX_PL_36_MASK | PMX_PL_37_38_MASK | PMX_PL_39_MASK,
+			PMX_SSP1_PL_36_VAL | PMX_SSP1_PL_37_38_VAL |
+			PMX_SSP1_PL_39_VAL);
+	pinmux_maskval(SPEAR320_IP_SEL_MIX_PAD_REG,
+			PMX_SSP1_PORT_SEL_MASK,
+			PMX_SSP1_PORT_36_TO_39_VAL);
+}
+
+static void enable_ssp1_48to51_pins(void)
+{
+	pinmux_maskval(SPEAR320_RASSELECT_REG,
+			PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK,
+			0);
+	pinmux_maskval(SPEAR320_IP_SEL_PAD_40_49_REG,
+			PMX_PL_48_49_MASK,
+			PMX_SSP1_PL_48_49_VAL);
+	pinmux_maskval(SPEAR320_IP_SEL_PAD_50_59_REG,
+			PMX_PL_50_51_MASK,
+			PMX_SSP1_PL_50_51_VAL);
+	pinmux_maskval(SPEAR320_IP_SEL_MIX_PAD_REG,
+			PMX_SSP1_PORT_SEL_MASK,
+			PMX_SSP1_PORT_48_TO_51_VAL);
+}
+
+static void enable_ssp1_65to68_pins(void)
+{
+	pinmux_maskval(SPEAR320_IP_SEL_PAD_60_69_REG,
+			PMX_PL_65_TO_68_MASK,
+			PMX_SSP1_PL_65_TO_68_VAL);
+	pinmux_maskval(SPEAR320_IP_SEL_MIX_PAD_REG,
+			PMX_SSP1_PORT_SEL_MASK,
+			PMX_SSP1_PORT_65_TO_68_VAL);
+}
+
+static void enable_ssp1_94to97_pins(void)
+{
+	pinmux_maskval(SPEAR320_IP_SEL_PAD_90_99_REG,
+			PMX_PL_94_95_MASK | PMX_PL_96_97_MASK,
+			PMX_SSP1_PL_94_95_VAL | PMX_SSP1_PL_96_97_VAL);
+	pinmux_maskval(SPEAR320_IP_SEL_MIX_PAD_REG,
+			PMX_SSP1_PORT_SEL_MASK,
+			PMX_SSP1_PORT_94_TO_97_VAL);
+}
+
+static void enable_ssp1_pins(u32 mode)
+{
+	switch (mode) {
+	case PMX_SSP_17_20:
+		enable_ssp1_17to20_pins();
+		break;
+	case PMX_SSP_36_39:
+		enable_ssp1_36to39_pins();
+		break;
+	case PMX_SSP_48_51:
+		enable_ssp1_48to51_pins();
+		break;
+	case PMX_SSP_65_68:
+		enable_ssp1_65to68_pins();
+		break;
+	case PMX_SSP_94_97:
+		enable_ssp1_94to97_pins();
+		break;
+	}
+}
+
+/* Pinmux for SSP2 */
+static void enable_ssp2_13to16_pins(void)
+{
+	pinmux_maskval(SPEAR320_RASSELECT_REG,
+			PMX_MII_MASK,
+			0);
+	pinmux_maskval(SPEAR320_IP_SEL_PAD_10_19_REG,
+			PMX_PL_13_14_MASK | PMX_PL_15_16_MASK,
+			PMX_SSP2_PL_13_14_15_16_VAL);
+	pinmux_maskval(SPEAR320_IP_SEL_MIX_PAD_REG,
+			PMX_SSP2_PORT_SEL_MASK,
+			PMX_SSP2_PORT_13_TO_16_VAL);
+}
+
+static void enable_ssp2_32to35_pins(void)
+{
+	pinmux_maskval(SPEAR320_RASSELECT_REG,
+			PMX_SSP_CS_MASK | PMX_GPIO_PIN4_MASK |
+			PMX_GPIO_PIN5_MASK,
+			0);
+	pinmux_maskval(SPEAR320_IP_SEL_PAD_30_39_REG,
+			PMX_PL_32_33_MASK | PMX_PL_34_MASK | PMX_PL_35_MASK,
+			PMX_SSP2_PL_32_33_VAL | PMX_SSP2_PL_34_VAL |
+			PMX_SSP2_PL_35_VAL);
+	pinmux_maskval(SPEAR320_IP_SEL_MIX_PAD_REG,
+			PMX_SSP2_PORT_SEL_MASK,
+			PMX_SSP2_PORT_32_TO_35_VAL);
+}
+
+static void enable_ssp2_44to47_pins(void)
+{
+	pinmux_maskval(SPEAR320_RASSELECT_REG,
+			PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK,
+			0);
+	pinmux_maskval(SPEAR320_IP_SEL_PAD_40_49_REG,
+			PMX_PL_44_45_MASK | PMX_PL_46_47_MASK,
+			PMX_SSP2_PL_44_45_VAL | PMX_SSP2_PL_46_47_VAL);
+	pinmux_maskval(SPEAR320_IP_SEL_MIX_PAD_REG,
+			PMX_SSP2_PORT_SEL_MASK,
+			PMX_SSP2_PORT_44_TO_47_VAL);
+}
+
+static void enable_ssp2_61to64_pins(void)
+{
+	pinmux_maskval(SPEAR320_IP_SEL_PAD_60_69_REG,
+			PMX_PL_61_TO_64_MASK,
+			PMX_SSP2_PL_61_TO_64_VAL);
+	pinmux_maskval(SPEAR320_IP_SEL_MIX_PAD_REG,
+			PMX_SSP2_PORT_SEL_MASK,
+			PMX_SSP2_PORT_61_TO_64_VAL);
+}
+
+static void enable_ssp2_90to93_pins(void)
+{
+	pinmux_maskval(SPEAR320_IP_SEL_PAD_90_99_REG,
+			PMX_PL_90_91_MASK | PMX_PL_92_93_MASK,
+			PMX_SSP2_PL_90_91_VAL | PMX_SSP2_PL_92_93_VAL);
+	pinmux_maskval(SPEAR320_IP_SEL_MIX_PAD_REG,
+			PMX_SSP2_PORT_SEL_MASK,
+			PMX_SSP2_PORT_90_TO_93_VAL);
+}
+
+static void enable_ssp2_pins(u32 mode)
+{
+	switch (mode) {
+	case PMX_SSP_13_16:
+		enable_ssp2_13to16_pins();
+		break;
+	case PMX_SSP_32_35:
+		enable_ssp2_32to35_pins();
+		break;
+	case PMX_SSP_44_47:
+		enable_ssp2_44to47_pins();
+		break;
+	case PMX_SSP_61_64:
+		enable_ssp2_61to64_pins();
+		break;
+	case PMX_SSP_90_93:
+		enable_ssp2_90to93_pins();
+		break;
+	}
+}
+
+/* Pinmux for ETH2 */
+static void enable_mii2_pins(void)
+{
+	pinmux_maskval(SPEAR320_IP_SEL_PAD_80_89_REG,
+			PMX_PL_80_TO_85_MASK | PMX_PL_86_87_MASK |
+			PMX_PL_88_89_MASK,
+			PMX_MII2_PL_80_TO_85_VAL | PMX_MII2_PL_86_87_VAL |
+			PMX_MII2_PL_88_89_VAL);
+	pinmux_maskval(SPEAR320_IP_SEL_PAD_90_99_REG,
+			PMX_PL_90_91_MASK | PMX_PL_92_93_MASK |
+			PMX_PL_94_95_MASK | PMX_PL_96_97_MASK,
+			PMX_MII2_PL_90_91_VAL | PMX_MII2_PL_92_93_VAL |
+			PMX_MII2_PL_94_95_VAL | PMX_MII2_PL_96_97_VAL);
+	pinmux_maskval(SPEAR320_EXT_CTRL_REG,
+			(MAC_MODE_MASK << MAC2_MODE_SHIFT) |
+			(MAC_MODE_MASK << MAC1_MODE_SHIFT) |
+			MII_MDIO_MASK,
+			(MAC_MODE_MII << MAC2_MODE_SHIFT) |
+			(MAC_MODE_MII << MAC1_MODE_SHIFT) |
+			MII_MDIO_81_VAL);
+}
+
+static void enable_smii2_pins(void)
+{
+	pinmux_maskval(SPEAR320_RASSELECT_REG,
+			PMX_MII_MASK,
+			0);
+	pinmux_maskval(SPEAR320_IP_SEL_PAD_10_19_REG,
+			PMX_PL_10_11_MASK,
+			PMX_SMII_PL_10_11_VAL);
+	pinmux_maskval(SPEAR320_IP_SEL_PAD_20_29_REG,
+			PMX_PL_21_TO_27_MASK,
+			PMX_SMII_PL_21_TO_27_VAL);
+	pinmux_maskval(SPEAR320_EXT_CTRL_REG,
+			(MAC_MODE_MASK << MAC2_MODE_SHIFT) |
+			(MAC_MODE_MASK << MAC1_MODE_SHIFT) |
+			MII_MDIO_MASK,
+			(MAC_MODE_SMII << MAC2_MODE_SHIFT)
+			| (MAC_MODE_SMII << MAC1_MODE_SHIFT)
+			| MII_MDIO_10_11_VAL);
+}
+
+static void enable_rmii2_pins(void)
+{
+	pinmux_maskval(SPEAR320_RASSELECT_REG,
+			PMX_MII_MASK,
+			0);
+	pinmux_maskval(SPEAR320_IP_SEL_PAD_10_19_REG,
+			PMX_PL_10_11_MASK | PMX_PL_13_14_MASK |
+			PMX_PL_15_16_MASK | PMX_PL_17_18_MASK | PMX_PL_19_MASK,
+			PMX_RMII_PL_10_11_VAL | PMX_RMII_PL_13_14_VAL |
+			PMX_RMII_PL_15_16_VAL | PMX_RMII_PL_17_18_VAL |
+			PMX_RMII_PL_19_VAL);
+	pinmux_maskval(SPEAR320_IP_SEL_PAD_20_29_REG,
+			PMX_PL_20_MASK | PMX_PL_21_TO_27_MASK,
+			PMX_RMII_PL_20_VAL | PMX_RMII_PL_21_TO_27_VAL);
+	pinmux_maskval(SPEAR320_EXT_CTRL_REG,
+			(MAC_MODE_MASK << MAC2_MODE_SHIFT) |
+			(MAC_MODE_MASK << MAC1_MODE_SHIFT) |
+			MII_MDIO_MASK,
+			(MAC_MODE_RMII << MAC2_MODE_SHIFT)
+			| (MAC_MODE_RMII << MAC1_MODE_SHIFT)
+			| MII_MDIO_10_11_VAL);
+}
+
+static void enable_eth2_pins(u32 mode)
+{
+	switch (mode) {
+	case PMX_ETH_MII:
+		enable_mii2_pins();
+		break;
+	}
+}
+
+static void enable_eth1_eth2_pins(u32 mode)
+{
+	switch (mode) {
+	case PMX_ETH_SMII:
+		enable_smii2_pins();
+		break;
+	case PMX_ETH_RMII:
+		enable_rmii2_pins();
+		break;
+	}
+}
+
+/* Pinmux for I2C1 */
+static void enable_i2c1_8to9_pins(void)
+{
+	pinmux_maskval(SPEAR320_RASSELECT_REG,
+			PMX_SSP_CS_MASK,
+			0);
+	pinmux_maskval(SPEAR320_IP_SEL_PAD_0_9_REG,
+			PMX_PL_8_9_MASK,
+			PMX_I2C1_PL_8_9_VAL);
+	pinmux_maskval(SPEAR320_IP_SEL_MIX_PAD_REG,
+			PMX_I2C1_PORT_SEL_MASK,
+			PMX_I2C1_PORT_8_9_VAL);
+}
+
+static void enable_i2c1_98to99_pins(void)
+{
+	pinmux_maskval(SPEAR320_IP_SEL_PAD_90_99_REG,
+			PMX_PL_98_MASK | PMX_PL_99_MASK,
+			PMX_I2C1_PL_98_VAL | PMX_I2C1_PL_99_VAL);
+	pinmux_maskval(SPEAR320_IP_SEL_MIX_PAD_REG,
+			PMX_I2C1_PORT_SEL_MASK,
+			PMX_I2C1_PORT_98_99_VAL);
+}
+
+static void enable_i2c1_pins(u32 mode)
+{
+	switch (mode) {
+	case PMX_I2C_8_9:
+		enable_i2c1_8to9_pins();
+		break;
+	case PMX_I2C_98_99:
+		enable_i2c1_98to99_pins();
+		break;
+	}
+}
+
+/* Pinmux for I2C2 */
+static void enable_i2c2_0to1_pins(void)
+{
+	pinmux_maskval(SPEAR320_RASSELECT_REG,
+			PMX_FIRDA_MASK,
+			0);
+	pinmux_maskval(SPEAR320_IP_SEL_PAD_0_9_REG,
+			PMX_PL_0_1_MASK,
+			PMX_I2C2_PL_0_1_VAL);
+	pinmux_maskval(SPEAR320_IP_SEL_MIX_PAD_REG,
+			PMX_I2C2_PORT_SEL_MASK,
+			PMX_I2C2_PORT_0_1_VAL);
+}
+
+static void enable_i2c2_2to3_pins(void)
+{
+	pinmux_maskval(SPEAR320_RASSELECT_REG,
+			PMX_UART0_MASK,
+			0);
+	pinmux_maskval(SPEAR320_IP_SEL_PAD_0_9_REG,
+			PMX_PL_2_3_MASK,
+			PMX_I2C2_PL_2_3_VAL);
+	pinmux_maskval(SPEAR320_IP_SEL_MIX_PAD_REG,
+			PMX_I2C2_PORT_SEL_MASK,
+			PMX_I2C2_PORT_2_3_VAL);
+}
+
+static void enable_i2c2_19to20_pins(void)
+{
+	pinmux_maskval(SPEAR320_RASSELECT_REG,
+			PMX_MII_MASK,
+			0);
+	pinmux_maskval(SPEAR320_IP_SEL_PAD_10_19_REG,
+			PMX_PL_19_MASK,
+			PMX_I2C2_PL_19_VAL);
+	pinmux_maskval(SPEAR320_IP_SEL_PAD_20_29_REG,
+			PMX_PL_20_MASK,
+			PMX_I2C2_PL_20_VAL);
+	pinmux_maskval(SPEAR320_IP_SEL_MIX_PAD_REG,
+			PMX_I2C2_PORT_SEL_MASK,
+			PMX_I2C2_PORT_19_20_VAL);
+}
+
+static void enable_i2c2_75to76_pins(void)
+{
+	pinmux_maskval(SPEAR320_IP_SEL_PAD_70_79_REG,
+			PMX_PL_75_76_MASK,
+			PMX_I2C2_PL_75_76_VAL);
+	pinmux_maskval(SPEAR320_IP_SEL_MIX_PAD_REG,
+			PMX_I2C2_PORT_SEL_MASK,
+			PMX_I2C2_PORT_75_76_VAL);
+}
+
+static void enable_i2c2_96to97_pins(void)
+{
+	pinmux_maskval(SPEAR320_IP_SEL_PAD_90_99_REG,
+			PMX_PL_96_97_MASK,
+			PMX_I2C2_PL_96_97_VAL);
+	pinmux_maskval(SPEAR320_IP_SEL_MIX_PAD_REG,
+			PMX_I2C2_PORT_SEL_MASK,
+			PMX_I2C2_PORT_96_97_VAL);
+}
+
+static void enable_i2c2_pins(u32 mode)
+{
+	switch (mode) {
+	case PMX_I2C_0_1:
+		enable_i2c2_0to1_pins();
+		break;
+	case PMX_I2C_2_3:
+		enable_i2c2_2to3_pins();
+		break;
+	case PMX_I2C_19_20:
+		enable_i2c2_19to20_pins();
+		break;
+	case PMX_I2C_75_76:
+		enable_i2c2_75to76_pins();
+		break;
+	case PMX_I2C_96_97:
+		enable_i2c2_96to97_pins();
+		break;
+	}
+}
+
+/**
+ * spear320_select_mode
+ * @mode:	SoC mode to e selected
+ */
+void spear320_select_mode(u32 mode)
+{
+	if (mode == SPEAR320_EXTENDED_MODE) {
+		pinmux_maskval(SPEAR320_EXT_CTRL_REG,
+				EXT_MODE_MASK,
+				EXT_MODE_MASK);
+	} else
+		printf("deprecated: Please run device only in ext mode\n");
+}
+
+/**
+ * spear320_pins_default: Select a default safe mode as startup
+ * Generally, all pins are enabled in input mode at initialization. This can be
+ * done either by
+ * - enabling gpio's and keeping all pins in gpio inputs
+ * - a platform specific way.
+ */
+void spear320_pins_default(void)
+{
+}
+
+/**
+ * spear320_enable_pins - enable pins for fixed peripherals on spear3xx devices
+ * @ip:		Peripheral index
+ * @mode:	Mode in which peripheral has to run (16bit/8bit etc)
+ *
+ * Enable the pins for fixed peripherals on spear3xx devices.
+ * mode represents the mode in which the peripheral may work and may result in
+ * different pins being enabled. eg GMII mode and RGMII mode may need different
+ * pins on devices to be enabled
+ */
+void spear320_enable_pins(u32 ip, u32 mode)
+{
+	if (PMX_UART2 == ip)
+		enable_uart2_pins();
+	else if (PMX_EMI == ip)
+		enable_emi_pins();
+	else if (PMX_FSMCNAND == ip)
+		enable_nand_pins(mode);
+	else if (PMX_SDMMC == ip)
+		enable_sdmmc_pins(mode);
+	else if (PMX_UART1 == ip)
+		enable_uart1_pins(mode);
+	else if (PMX_I2C1 == ip)
+		enable_i2c1_pins(mode);
+	else if (PMX_I2C2 == ip)
+		enable_i2c2_pins(mode);
+	else if (PMX_SSP1 == ip)
+		enable_ssp1_pins(mode);
+	else if (PMX_SSP2 == ip)
+		enable_ssp2_pins(mode);
+	else if (PMX_ETH2 == ip)
+		enable_eth2_pins(mode);
+	else if (PMX_ETH1_ETH2 == ip)
+		enable_eth1_eth2_pins(mode);
+	else if ((PMX_I2C0 == ip) || (PMX_SSP0 == ip) || \
+			(PMX_ETH0 == ip) || (PMX_UART0 == ip))
+		spear3xx_enable_pins(ip, mode);
+}
+
+static void configure_gpio(u32 plgpio)
+{
+	if (plgpio > SPEAR3XX_MAX_PLGPIOS)
+		return;
+
+	/* Set the pin to GPIO IN mode */
+	pinmux_set_bit(plgpio, SPEAR320_GPIO_EN0);
+
+	/* Select GPIO mode */
+	pinmux_set_bit(plgpio, SPEAR320_GPIO_SELECT0);
+
+	/* Select RAS from Fixed Part / RAS */
+	if (plgpio < 2) {
+		pinmux_maskval(SPEAR3XX_FUNC_ENB_REG,
+				PMX_FIRDA_MASK, 0);
+	} else if (plgpio < 4) {
+		pinmux_maskval(SPEAR3XX_FUNC_ENB_REG,
+				PMX_UART0_MASK, 0);
+	} else if (plgpio < 6) {
+		pinmux_maskval(SPEAR3XX_FUNC_ENB_REG,
+				PMX_I2C_MASK, 0);
+	} else if (plgpio < 10) {
+		pinmux_maskval(SPEAR3XX_FUNC_ENB_REG,
+				PMX_SSP_MASK, 0);
+	} else if (plgpio < 28) {
+		pinmux_maskval(SPEAR3XX_FUNC_ENB_REG,
+				PMX_MII_MASK, 0);
+	} else if (plgpio < 29) {
+		pinmux_maskval(SPEAR3XX_FUNC_ENB_REG,
+				PMX_GPIO_PIN0_MASK, 0);
+	} else if (plgpio < 30) {
+		pinmux_maskval(SPEAR3XX_FUNC_ENB_REG,
+				PMX_GPIO_PIN1_MASK, 0);
+	} else if (plgpio < 31) {
+		pinmux_maskval(SPEAR3XX_FUNC_ENB_REG,
+				PMX_GPIO_PIN2_MASK, 0);
+	} else if (plgpio < 32) {
+		pinmux_maskval(SPEAR3XX_FUNC_ENB_REG,
+				PMX_GPIO_PIN3_MASK, 0);
+	} else if (plgpio < 33) {
+		pinmux_maskval(SPEAR3XX_FUNC_ENB_REG,
+				PMX_GPIO_PIN4_MASK, 0);
+	} else if (plgpio < 34) {
+		pinmux_maskval(SPEAR3XX_FUNC_ENB_REG,
+				PMX_GPIO_PIN5_MASK, 0);
+	} else if (plgpio < 37) {
+		pinmux_maskval(SPEAR3XX_FUNC_ENB_REG,
+				PMX_SSP_CS_MASK, 0);
+	} else if (plgpio < 43) {
+		pinmux_maskval(SPEAR3XX_FUNC_ENB_REG,
+				PMX_UART0_MODEM_MASK, 0);
+	} else if (plgpio < 51) {
+		pinmux_maskval(SPEAR3XX_FUNC_ENB_REG,
+				PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK, 0);
+	}
+}
+
+/**
+ * spear320_configure_pin - Configure pin on spear320 devices
+ * @plgpio:	Pin Number (plgpio number)
+ * @mode:	Pull UP, Pull DOWN, plgpio IN, plgpio OUT etc
+ */
+void spear320_configure_pin(u32 plgpio, u32 mode)
+{
+	if (PMX_GPIO == mode)
+		configure_gpio(plgpio);
+}
+
+/**
+ * spear320_plgpio_get - Get the gpio input
+ * @plgpio:	Pin Number (plgpio number)
+ */
+int spear320_plgpio_get(u32 plgpio)
+{
+	if (plgpio > SPEAR3XX_MAX_PLGPIOS)
+		return -1;
+
+	/* Set the pin to GPIO IN mode */
+	pinmux_set_bit(plgpio, SPEAR320_GPIO_EN0);
+
+	return pinmux_test_bit(plgpio, SPEAR320_GPIO_IN0);
+}
+
+/**
+ * spear320_plgpio_set - Set the gpio value
+ * @plgpio:	Pin Number (plgpio number)
+ */
+void spear320_plgpio_set(u32 plgpio, u32 val)
+{
+	if (plgpio > SPEAR3XX_MAX_PLGPIOS)
+		return;
+
+	if (val & 0x1)
+		pinmux_set_bit(plgpio, SPEAR320_GPIO_OUT0);
+	else
+		pinmux_clear_bit(plgpio, SPEAR320_GPIO_OUT0);
+
+	/* Set the pin to GPIO OUT mode */
+	pinmux_clear_bit(plgpio, SPEAR320_GPIO_EN0);
+}
diff --git a/arch/arm/cpu/arm926ejs/spear/spear3xx.c b/arch/arm/cpu/arm926ejs/spear/spear3xx.c
index 7a85fa9..612d237 100644
--- a/arch/arm/cpu/arm926ejs/spear/spear3xx.c
+++ b/arch/arm/cpu/arm926ejs/spear/spear3xx.c
@@ -25,6 +25,93 @@ 
 #include <asm/io.h>
 #include <asm/arch/hardware.h>
 #include <asm/arch/misc.h>
+#include <asm/arch/pinmux.h>
+
+/* Pinmux support for all fixed spear3xx devices */
+
+/* Pinmux for I2C0 */
+static void enable_i2c0_pins(void)
+{
+	pinmux_maskval(SPEAR3XX_FUNC_ENB_REG,
+			PMX_I2C_MASK,
+			PMX_I2C_MASK);
+}
+
+/* Pinmux for SSP0 */
+static void enable_ssp0_pins(void)
+{
+	pinmux_maskval(SPEAR3XX_FUNC_ENB_REG,
+			PMX_SSP_MASK,
+			PMX_SSP_MASK);
+}
+
+/* Pinmux for ETH0 */
+static void enable_eth0_pins(void)
+{
+	pinmux_maskval(SPEAR3XX_FUNC_ENB_REG,
+			PMX_MII_MASK,
+			PMX_MII_MASK);
+}
+
+/* Pinmux for UART0 ext */
+static void enable_uart0_ext_pins(void)
+{
+	pinmux_maskval(SPEAR3XX_FUNC_ENB_REG,
+			PMX_UART0_MODEM_MASK,
+			PMX_UART0_MODEM_MASK);
+
+}
+
+/* Pinmux for UART0 */
+static void enable_uart0_simple_pins(void)
+{
+	pinmux_maskval(SPEAR3XX_FUNC_ENB_REG,
+			PMX_UART0_MASK,
+			PMX_UART0_MASK);
+}
+
+static void enable_uart0_pins(u32 mode)
+{
+	switch (mode) {
+	case PMX_UART_SIMPLE:
+		enable_uart0_simple_pins();
+		break;
+	case PMX_UART_MODEM:
+		enable_uart0_ext_pins();
+		break;
+	}
+}
+
+/**
+ * spear3xx_enable_pins - enable pins for fixed peripherals on spear3xx devices
+ * @ip:		Peripheral index
+ * @mode:	Mode in which peripheral has to run (16bit/8bit etc)
+ *
+ * Enable the pins for fixed peripherals on spear3xx devices.
+ * mode represents the mode in which the peripheral may work and may result in
+ * different pins being enabled. eg GMII mode and RGMII mode may need different
+ * pins on devices to be enabled
+ */
+void spear3xx_enable_pins(u32 ip, u32 mode)
+{
+	switch (ip) {
+	case PMX_I2C0:
+		enable_i2c0_pins();
+		break;
+	case PMX_SSP0:
+		enable_ssp0_pins();
+		break;
+	case PMX_ETH0:
+		enable_eth0_pins();
+		break;
+	case PMX_UART0:
+		enable_uart0_pins(mode);
+		break;
+	default:
+		printf("Unsupported device\n");
+		break;
+	}
+}
 
 #if defined(CONFIG_USB_EHCI_SPEAR)
 void spear3xx_usbh_stop(void)
diff --git a/arch/arm/include/asm/arch-spear/pinmux.h b/arch/arm/include/asm/arch-spear/pinmux.h
new file mode 100644
index 0000000..faa46aa
--- /dev/null
+++ b/arch/arm/include/asm/arch-spear/pinmux.h
@@ -0,0 +1,133 @@ 
+/*
+ * (C) Copyright 2012
+ * Vipin Kumar, ST Microelectronics, vipin.kumar@st.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _ASM_ARCH_SPEAR_PINMUX_H
+#define _ASM_ARCH_SPEAR_PINMUX_H
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/hardware.h>
+
+static inline void pinmux_maskval(ulong reg, u32 mask, u32 val)
+{
+	u32 temp = readl((u32 *)reg);
+	temp &= ~mask;
+	temp |= val & mask;
+	writel(temp, (u32 *)reg);
+}
+
+static inline void pinmux_set_bit(int nr, unsigned long addr)
+{
+	__set_bit(nr, (volatile unsigned long *)addr);
+}
+
+static inline void pinmux_clear_bit(int nr, unsigned long addr)
+{
+	__clear_bit(nr, (volatile unsigned long *)addr);
+}
+
+static inline int pinmux_test_bit(int nr, unsigned long addr)
+{
+	return __test_bit(nr, (volatile unsigned long *)addr);
+}
+
+enum pinmux_ip {
+	PMX_UART0,
+	PMX_UART1,
+	PMX_UART2,
+	PMX_UART3,
+	PMX_UART4,
+	PMX_UART5,
+	PMX_I2C0,
+	PMX_I2C1,
+	PMX_I2C2,
+	PMX_SSP0,
+	PMX_SSP1,
+	PMX_SSP2,
+	PMX_ETH0,
+	PMX_ETH1,
+	PMX_ETH2,
+	PMX_ETH1_ETH2,
+	PMX_FSMCNAND,
+	PMX_FSMCPNOR,
+	PMX_SDMMC,
+	PMX_EMI,
+	PMX_SMI,
+};
+
+/* UART0 modem modes */
+#define PMX_UART_SIMPLE		1
+#define PMX_UART_MODEM		2
+#define PMX_UART_MDM_2_7	3
+#define PMX_UART_MDM_31_36	4
+#define PMX_UART_MDM_34_45	5
+#define PMX_UART_MDM_80_85	6
+
+/* I2C modes */
+#define PMX_I2C_8_9		1
+#define PMX_I2C_98_99		2
+#define PMX_I2C_0_1		3
+#define PMX_I2C_2_3		4
+#define PMX_I2C_19_20		5
+#define PMX_I2C_75_76		6
+#define PMX_I2C_96_97		7
+
+/* SSP modes */
+#define PMX_SSP_13_16		1
+#define PMX_SSP_17_20		2
+#define PMX_SSP_32_35		3
+#define PMX_SSP_36_39		4
+#define PMX_SSP_44_47		5
+#define PMX_SSP_48_51		6
+#define PMX_SSP_61_64		7
+#define PMX_SSP_65_68		8
+#define PMX_SSP_90_93		9
+#define PMX_SSP_94_97		10
+
+/* ETH modes */
+#define PMX_ETH_GMII		1
+#define PMX_ETH_MII		2
+#define PMX_ETH_RGMII		3
+#define PMX_ETH_RMII		4
+#define PMX_ETH_SGMII		5
+#define PMX_ETH_SMII		6
+
+/* NAND modes */
+#define PMX_NAND_8BIT		1
+#define PMX_NAND_16BIT		2
+#define PMX_NAND_2CHIP		3
+#define PMX_NAND_4CHIP		4
+
+/* SDMMC modes */
+#define PMX_SDMMC_LED		1
+#define PMX_SDMMC_CD12		2
+#define PMX_SDMMC_CD51		3
+#define PMX_SDMMC_4BIT		4
+#define PMX_SDMMC_8BIT		5
+
+/* PLGPIO modes */
+#define PMX_GPIO		1
+#define PMX_PULLUP		2
+#define PMX_PULLDOWN		3
+
+#endif
diff --git a/arch/arm/include/asm/arch-spear/spear300.h b/arch/arm/include/asm/arch-spear/spear300.h
index 24faaea..4bfa619 100644
--- a/arch/arm/include/asm/arch-spear/spear300.h
+++ b/arch/arm/include/asm/arch-spear/spear300.h
@@ -30,4 +30,31 @@ 
 #define CONFIG_SYS_NAND_CLE			(1 << 16)
 #define CONFIG_SYS_NAND_ALE			(1 << 17)
 
+/* RAS misc registers and respective bitmasks */
+#define CONFIG_SYS_RAS_BASE			0x99000000
+#define SPEAR300_RAS_REG1			CONFIG_SYS_RAS_BASE
+	/* Bitmaks for REG1 are in spear3xx.h */
+#define SPEAR300_RAS_REG2			(CONFIG_SYS_RAS_BASE + 0x04)
+	#define SPEAR300_MODE_MSK		(0xF << 0)
+	#define SPEAR300_MODE_NAND		(0x0 << 0)
+	#define SPEAR300_MODE_NOR		(0x1 << 0)
+	#define SPEAR300_MODE_PHOTOFRAME	(0x2 << 0)
+	#define SPEAR300_MODE_LENDIPFONE	(0x3 << 0)
+	#define SPEAR300_MODE_HENDIPFONE	(0x4 << 0)
+	#define SPEAR300_MODE_LENDWIFIFONE	(0x5 << 0)
+	#define SPEAR300_MODE_HENDWIFIFONE	(0x6 << 0)
+	#define SPEAR300_MODE_ATAPABXWI2S	(0x7 << 0)
+	#define SPEAR300_MODE_ATAPABXI2S	(0x8 << 0)
+	#define SPEAR300_MODE_CAM1LCDW		(0xC << 0)
+	#define SPEAR300_MODE_CAMULCD		(0xD << 0)
+	#define SPEAR300_MODE_CAMULCDW		(0xE << 0)
+	#define SPEAR300_MODE_CAM1LCD		(0xF << 0)
+
+#define SPEAR3XX_FUNC_ENB_REG		SPEAR300_RAS_REG1
+
+/* externs related to pinmux */
+extern void spear300_pins_default(void);
+extern void spear300_select_mode(u32 mode);
+extern void spear300_enable_pins(u32 ip, u32 mode);
+
 #endif
diff --git a/arch/arm/include/asm/arch-spear/spear310.h b/arch/arm/include/asm/arch-spear/spear310.h
index 0f6223e..9d20237 100644
--- a/arch/arm/include/asm/arch-spear/spear310.h
+++ b/arch/arm/include/asm/arch-spear/spear310.h
@@ -37,4 +37,17 @@ 
 #define CONFIG_SYS_MACB3_BASE			0xB1800000
 #define CONFIG_SPEAR_RASBASE			0xB4000000
 
+/* SPEAr310 RAS misc space registers and bitmasks */
+#define SPEAR310_FUNCENB_REG		(CONFIG_SPEAR_RASBASE + 0x8)
+
+#define SPEAR310_SMII_REG		(CONFIG_SPEAR_RASBASE + 0xC)
+	#define SPEAR310_SMII_PHY_SHIFT		0x0
+	#define SPEAR310_SMII_PHY_MASK		0x3
+
+#define SPEAR3XX_FUNC_ENB_REG		SPEAR310_FUNCENB_REG
+
+/* externs related to pinmux */
+extern void spear310_pins_default(void);
+extern void spear310_enable_pins(u32 ip, u32 mode);
+
 #endif
diff --git a/arch/arm/include/asm/arch-spear/spear320.h b/arch/arm/include/asm/arch-spear/spear320.h
index 110afc3..abdcda6 100644
--- a/arch/arm/include/asm/arch-spear/spear320.h
+++ b/arch/arm/include/asm/arch-spear/spear320.h
@@ -35,4 +35,430 @@ 
 #define CONFIG_SYS_MACB1_BASE			0xAB000000
 #define CONFIG_SPEAR_RASBASE			0xB3000000
 
+/* SPEAr320 SoC device modes */
+#define SPEAR320_AUTO_NET_SMII_MODE	(1 << 0)
+#define SPEAR320_AUTO_NET_MII_MODE	(1 << 1)
+#define SPEAR320_AUTO_EXP_MODE		(1 << 2)
+#define SPEAR320_SMALL_PRINTERS_MODE	(1 << 3)
+#define SPEAR320_EXTENDED_MODE		(1 << 4)
+
+/* SPEAr320 RAS misc space registers and bitmasks */
+#define SPEAR320_RASSELECT_REG		(CONFIG_SPEAR_RASBASE + 0x000C)
+
+#define SPEAR320_CONTROL_REG		(CONFIG_SPEAR_RASBASE + 0x0010)
+	#define MII_ENB_SHFT			5
+
+/* Extended mode registers and their offsets */
+#define SPEAR320_EXT_CTRL_REG		(CONFIG_SPEAR_RASBASE + 0x0018)
+	#define EXT_MODE_MASK			(1 << 0)
+	#define MII_MDIO_MASK			(1 << 4)
+	#define MII_MDIO_10_11_VAL		0
+	#define MII_MDIO_81_VAL			(1 << 4)
+	#define EMI_FSMC_DYNAMIC_MUX_MASK	(1 << 5)
+	#define MAC_MODE_MII			0
+	#define MAC_MODE_RMII			1
+	#define MAC_MODE_SMII			2
+	#define MAC_MODE_SS_SMII		3
+	#define MAC_MODE_MASK			0x3
+	#define MAC1_MODE_SHIFT			16
+	#define MAC2_MODE_SHIFT			18
+
+#define SPEAR320_GPIO_SELECT0		(CONFIG_SPEAR_RASBASE + 0x0024)
+#define SPEAR320_GPIO_OUT0		(CONFIG_SPEAR_RASBASE + 0x0034)
+#define SPEAR320_GPIO_EN0		(CONFIG_SPEAR_RASBASE + 0x0044)
+#define SPEAR320_GPIO_IN0		(CONFIG_SPEAR_RASBASE + 0x0054)
+
+#define SPEAR320_IP_SEL_PAD_0_9_REG	(CONFIG_SPEAR_RASBASE + 0x00A4)
+	#define PMX_PL_0_1_MASK			(0x3F << 0)
+	#define PMX_UART2_PL_0_1_VAL		0x0
+	#define PMX_I2C2_PL_0_1_VAL		(0x4 | (0x4 << 3))
+
+	#define PMX_PL_2_3_MASK			(0x3F << 6)
+	#define PMX_I2C2_PL_2_3_VAL		0x0
+	#define PMX_UART6_PL_2_3_VAL		((0x1 << 6) | (0x1 << 9))
+	#define PMX_UART1_ENH_PL_2_3_VAL	((0x4 << 6) | (0x4 << 9))
+
+	#define PMX_PL_4_5_MASK			(0x3F << 12)
+	#define PMX_UART5_PL_4_5_VAL		((0x1 << 12) | (0x1 << 15))
+	#define PMX_UART1_ENH_PL_4_5_VAL	((0x4 << 12) | (0x4 << 15))
+	#define PMX_PL_5_MASK			(0x7 << 15)
+	#define PMX_TOUCH_Y_PL_5_VAL		0x0
+
+	#define PMX_PL_6_7_MASK			(0x3F << 18)
+	#define PMX_PL_6_MASK			(0x7 << 18)
+	#define PMX_PL_7_MASK			(0x7 << 21)
+	#define PMX_UART4_PL_6_7_VAL		((0x1 << 18) | (0x1 << 21))
+	#define PMX_PWM_3_PL_6_VAL		(0x2 << 18)
+	#define PMX_PWM_2_PL_7_VAL		(0x2 << 21)
+	#define PMX_UART1_ENH_PL_6_7_VAL	((0x4 << 18) | (0x4 << 21))
+
+	#define PMX_PL_8_9_MASK			(0x3F << 24)
+	#define PMX_UART3_PL_8_9_VAL		((0x1 << 24) | (0x1 << 27))
+	#define PMX_PWM_0_1_PL_8_9_VAL		((0x2 << 24) | (0x2 << 27))
+	#define PMX_I2C1_PL_8_9_VAL		((0x4 << 24) | (0x4 << 27))
+
+#define SPEAR320_IP_SEL_PAD_10_19_REG	(CONFIG_SPEAR_RASBASE + 0x00A8)
+	#define PMX_PL_10_11_MASK		(0x3F << 0)
+	#define PMX_SMII_PL_10_11_VAL		0
+	#define PMX_RMII_PL_10_11_VAL		((0x4 << 0) | (0x4 << 3))
+
+	#define PMX_PL_12_MASK			(0x7 << 6)
+	#define PMX_PWM3_PL_12_VAL		0
+	#define PMX_SDHCI_CD_PL_12_VAL		(0x4 << 6)
+
+	#define PMX_PL_13_14_MASK		(0x3F << 9)
+	#define PMX_PL_13_MASK			(0x7 << 9)
+	#define PMX_PL_14_MASK			(0x7 << 12)
+	#define PMX_SSP2_PL_13_14_15_16_VAL	0
+	#define PMX_UART4_PL_13_14_VAL		((0x1 << 9) | (0x1 << 12))
+	#define PMX_RMII_PL_13_14_VAL		((0x4 << 9) | (0x4 << 12))
+	#define PMX_PWM2_PL_13_VAL		(0x2 << 9)
+	#define PMX_PWM1_PL_14_VAL		(0x2 << 12)
+
+	#define PMX_PL_15_MASK			(0x7 << 15)
+	#define PMX_PWM0_PL_15_VAL		(0x2 << 15)
+	#define PMX_PL_15_16_MASK		(0x3F << 15)
+	#define PMX_UART3_PL_15_16_VAL		((0x1 << 15) | (0x1 << 18))
+	#define PMX_RMII_PL_15_16_VAL		((0x4 << 15) | (0x4 << 18))
+
+	#define PMX_PL_17_18_MASK		(0x3F << 21)
+	#define PMX_SSP1_PL_17_18_19_20_VAL	0
+	#define PMX_RMII_PL_17_18_VAL		((0x4 << 21) | (0x4 << 24))
+
+	#define PMX_PL_19_MASK			(0x7 << 27)
+	#define PMX_I2C2_PL_19_VAL		(0x1 << 27)
+	#define PMX_RMII_PL_19_VAL		(0x4 << 27)
+
+#define SPEAR320_IP_SEL_PAD_20_29_REG	(CONFIG_SPEAR_RASBASE + 0x00AC)
+	#define PMX_PL_20_MASK			(0x7 << 0)
+	#define PMX_I2C2_PL_20_VAL		(0x1 << 0)
+	#define PMX_RMII_PL_20_VAL		(0x4 << 0)
+
+	#define PMX_PL_21_TO_27_MASK		(0x1FFFFF << 3)
+	#define PMX_SMII_PL_21_TO_27_VAL	0
+	#define PMX_RMII_PL_21_TO_27_VAL	((0x4 << 3) | (0x4 << 6) | \
+						(0x4 << 9) | (0x4 << 12) | \
+						(0x4 << 15) | (0x4 << 18) | \
+						(0x4 << 21))
+
+	#define PMX_PL_28_29_MASK		(0x3F << 24)
+	#define PMX_PL_28_MASK			(0x7 << 24)
+	#define PMX_PL_29_MASK			(0x7 << 27)
+	#define PMX_UART1_PL_28_29_VAL		0
+	#define PMX_PWM_3_PL_28_VAL		(0x4 << 24)
+	#define PMX_PWM_2_PL_29_VAL		(0x4 << 27)
+
+#define SPEAR320_IP_SEL_PAD_30_39_REG	(CONFIG_SPEAR_RASBASE + 0x00B0)
+	#define PMX_PL_30_31_MASK		(0x3F << 0)
+	#define PMX_CAN1_PL_30_31_VAL		(0)
+	#define PMX_PL_30_MASK			(0x7 << 0)
+	#define PMX_PL_31_MASK			(0x7 << 3)
+	#define PMX_PWM1_EXT_PL_30_VAL		(0x4 << 0)
+	#define PMX_PWM0_EXT_PL_31_VAL		(0x4 << 3)
+	#define PMX_UART1_ENH_PL_31_VAL		(0x3 << 3)
+
+	#define PMX_PL_32_33_MASK		(0x3F << 6)
+	#define PMX_CAN0_PL_32_33_VAL		0
+	#define PMX_UART1_ENH_PL_32_33_VAL	((0x3 << 6) | (0x3 << 9))
+	#define PMX_SSP2_PL_32_33_VAL		((0x4 << 6) | (0x4 << 9))
+
+	#define PMX_PL_34_MASK			(0x7 << 12)
+	#define PMX_PWM2_PL_34_VAL		0
+	#define PMX_UART1_ENH_PL_34_VAL		(0x2 << 12)
+	#define PMX_SSP2_PL_34_VAL		(0x4 << 12)
+
+	#define PMX_PL_35_MASK			(0x7 << 15)
+	#define PMX_I2S_REF_CLK_PL_35_VAL	0
+	#define PMX_UART1_ENH_PL_35_VAL		(0x2 << 15)
+	#define PMX_SSP2_PL_35_VAL		(0x4 << 15)
+
+	#define PMX_PL_36_MASK			(0x7 << 18)
+	#define PMX_TOUCH_X_PL_36_VAL		0
+	#define PMX_UART1_ENH_PL_36_VAL		(0x2 << 18)
+	#define PMX_SSP1_PL_36_VAL		(0x4 << 18)
+
+	#define PMX_PL_37_38_MASK		(0x3F << 21)
+	#define PMX_PWM0_1_PL_37_38_VAL		0
+	#define PMX_UART5_PL_37_38_VAL		((0x2 << 21) | (0x2 << 24))
+	#define PMX_SSP1_PL_37_38_VAL		((0x4 << 21) | (0x4 << 24))
+
+	#define PMX_PL_39_MASK			(0x7 << 27)
+	#define PMX_I2S_PL_39_VAL		0
+	#define PMX_UART4_PL_39_VAL		(0x2 << 27)
+	#define PMX_SSP1_PL_39_VAL		(0x4 << 27)
+
+#define SPEAR320_IP_SEL_PAD_40_49_REG	(CONFIG_SPEAR_RASBASE + 0x00B4)
+	#define PMX_PL_40_MASK			(0x7 << 0)
+	#define PMX_I2S_PL_40_VAL		0
+	#define PMX_UART4_PL_40_VAL		(0x2 << 0)
+	#define PMX_PWM3_PL_40_VAL		(0x4 << 0)
+
+	#define PMX_PL_41_42_MASK		(0x3F << 3)
+	#define PMX_PL_41_MASK			(0x7 << 3)
+	#define PMX_PL_42_MASK			(0x7 << 6)
+	#define PMX_I2S_PL_41_42_VAL		0
+	#define PMX_UART3_PL_41_42_VAL		((0x2 << 3) | (0x2 << 6))
+	#define PMX_PWM2_PL_41_VAL		(0x4 << 3)
+	#define PMX_PWM1_PL_42_VAL		(0x4 << 6)
+
+	#define PMX_PL_43_MASK			(0x7 << 9)
+	#define PMX_SDHCI_PL_43_VAL		0
+	#define PMX_UART1_ENH_PL_43_VAL		(0x2 << 9)
+	#define PMX_PWM0_PL_43_VAL		(0x4 << 9)
+
+	#define PMX_PL_44_45_MASK		(0x3F << 12)
+	#define PMX_SDHCI_PL_44_45_VAL	0
+	#define PMX_UART1_ENH_PL_44_45_VAL	((0x2 << 12) | (0x2 << 15))
+	#define PMX_SSP2_PL_44_45_VAL		((0x4 << 12) | (0x4 << 15))
+
+	#define PMX_PL_46_47_MASK		(0x3F << 18)
+	#define PMX_SDHCI_PL_46_47_VAL	0
+	#define PMX_FSMC_EMI_PL_46_47_VAL	((0x2 << 18) | (0x2 << 21))
+	#define PMX_SSP2_PL_46_47_VAL		((0x4 << 18) | (0x4 << 21))
+
+	#define PMX_PL_48_49_MASK		(0x3F << 24)
+	#define PMX_SDHCI_PL_48_49_VAL	0
+	#define PMX_FSMC_EMI_PL_48_49_VAL	((0x2 << 24) | (0x2 << 27))
+	#define PMX_SSP1_PL_48_49_VAL		((0x4 << 24) | (0x4 << 27))
+
+#define SPEAR320_IP_SEL_PAD_50_59_REG	(CONFIG_SPEAR_RASBASE + 0x00B8)
+	#define PMX_PL_50_51_MASK		(0x3F << 0)
+	#define PMX_EMI_PL_50_51_VAL		((0x2 << 0) | (0x2 << 3))
+	#define PMX_SSP1_PL_50_51_VAL		((0x4 << 0) | (0x4 << 3))
+	#define PMX_PL_50_MASK			(0x7 << 0)
+	#define PMX_PL_51_MASK			(0x7 << 3)
+	#define PMX_SDHCI_PL_50_VAL		0
+	#define PMX_SDHCI_CD_PL_51_VAL		0
+
+	#define PMX_PL_52_53_MASK		(0x3F << 6)
+	#define PMX_FSMC_PL_52_53_VAL		0
+	#define PMX_EMI_PL_52_53_VAL		((0x2 << 6) | (0x2 << 9))
+	#define PMX_UART3_PL_52_53_VAL		((0x4 << 6) | (0x4 << 9))
+
+	#define PMX_PL_54_55_56_MASK		(0x1FF << 12)
+	#define PMX_FSMC_EMI_PL_54_55_56_VAL	((0x2 << 12) | (0x2 << 15) | \
+						(0x2 << 18))
+
+	#define PMX_PL_57_MASK			(0x7 << 21)
+	#define PMX_FSMC_PL_57_VAL		0
+	#define PMX_PWM3_PL_57_VAL		(0x4 << 21)
+
+	#define PMX_PL_58_59_MASK		(0x3F << 24)
+	#define PMX_PL_58_MASK			(0x7 << 24)
+	#define PMX_PL_59_MASK			(0x7 << 27)
+	#define PMX_FSMC_EMI_PL_58_59_VAL	((0x2 << 24) | (0x2 << 27))
+	#define PMX_PWM2_PL_58_VAL		(0x4 << 24)
+	#define PMX_PWM1_PL_59_VAL		(0x4 << 27)
+
+#define SPEAR320_IP_SEL_PAD_60_69_REG	(CONFIG_SPEAR_RASBASE + 0x00BC)
+	#define PMX_PL_60_MASK			(0x7 << 0)
+	#define PMX_FSMC_PL_60_VAL		0
+	#define PMX_PWM0_PL_60_VAL		(0x4 << 0)
+
+	#define PMX_PL_61_TO_64_MASK		(0xFFF << 3)
+	#define PMX_FSMC_PL_61_TO_64_VAL	((0x2 << 3) | (0x2 << 6) | \
+						(0x2 << 9) | (0x2 << 12))
+	#define PMX_SSP2_PL_61_TO_64_VAL	((0x4 << 3) | (0x4 << 6) | \
+						(0x4 << 9) | (0x4 << 12))
+
+	#define PMX_PL_65_TO_68_MASK		(0xFFF << 15)
+	#define PMX_FSMC_PL_65_TO_68_VAL	((0x2 << 15) | (0x2 << 18) | \
+						(0x2 << 21) | (0x2 << 24))
+	#define PMX_SSP1_PL_65_TO_68_VAL	((0x4 << 15) | (0x4 << 18) | \
+						(0x4 << 21) | (0x4 << 24))
+
+	#define PMX_PL_69_MASK			(0x7 << 27)
+	#define PMX_CLCD_PL_69_VAL		(0)
+	#define PMX_EMI_PL_69_VAL		(0x2 << 27)
+	#define PMX_SPP_PL_69_VAL		(0x3 << 27)
+	#define PMX_UART5_PL_69_VAL		(0x4 << 27)
+
+#define SPEAR320_IP_SEL_PAD_70_79_REG	(CONFIG_SPEAR_RASBASE + 0x00C0)
+	#define PMX_PL_70_MASK			(0x7 << 0)
+	#define PMX_CLCD_PL_70_VAL		(0)
+	#define PMX_FSMC_EMI_PL_70_VAL		(0x2 << 0)
+	#define PMX_SPP_PL_70_VAL		(0x3 << 0)
+	#define PMX_UART5_PL_70_VAL		(0x4 << 0)
+
+	#define PMX_PL_71_72_MASK		(0x3F << 3)
+	#define PMX_CLCD_PL_71_72_VAL		(0)
+	#define PMX_FSMC_EMI_PL_71_72_VAL	((0x2 << 3) | (0x2 << 6))
+	#define PMX_SPP_PL_71_72_VAL		((0x3 << 3) | (0x3 << 6))
+	#define PMX_UART4_PL_71_72_VAL		((0x4 << 3) | (0x4 << 6))
+
+	#define PMX_PL_73_MASK			(0x7 << 9)
+	#define PMX_CLCD_PL_73_VAL		(0)
+	#define PMX_FSMC_EMI_PL_73_VAL		(0x2 << 9)
+	#define PMX_SPP_PL_73_VAL		(0x3 << 9)
+	#define PMX_UART3_PL_73_VAL		(0x4 << 9)
+
+	#define PMX_PL_74_MASK			(0x7 << 12)
+	#define PMX_CLCD_PL_74_VAL		(0)
+	#define PMX_EMI_PL_74_VAL		(0x2 << 12)
+	#define PMX_SPP_PL_74_VAL		(0x3 << 12)
+	#define PMX_UART3_PL_74_VAL		(0x4 << 12)
+
+	#define PMX_PL_75_76_MASK		(0x3F << 15)
+	#define PMX_CLCD_PL_75_76_VAL		(0)
+	#define PMX_EMI_PL_75_76_VAL		((0x2 << 15) | (0x2 << 18))
+	#define PMX_SPP_PL_75_76_VAL		((0x3 << 15) | (0x3 << 18))
+	#define PMX_I2C2_PL_75_76_VAL		((0x4 << 15) | (0x4 << 18))
+
+	#define PMX_PL_77_78_79_MASK		(0x1FF << 21)
+	#define PMX_CLCD_PL_77_78_79_VAL	(0)
+	#define PMX_EMI_PL_77_78_79_VAL		((0x2 << 21) | (0x2 << 24) | \
+						(0x2 << 27))
+	#define PMX_SPP_PL_77_78_79_VAL		((0x3 << 21) | (0x3 << 24) | \
+						(0x3 << 27))
+	#define PMX_RS485_PL_77_78_79_VAL	((0x4 << 21) | (0x4 << 24) | \
+						(0x4 << 27))
+
+#define SPEAR320_IP_SEL_PAD_80_89_REG	(CONFIG_SPEAR_RASBASE + 0x00C4)
+	#define PMX_PL_80_TO_85_MASK		(0x3FFFF << 0)
+	#define PMX_CLCD_PL_80_TO_85_VAL	0
+	#define PMX_MII2_PL_80_TO_85_VAL	((0x1 << 0) | (0x1 << 3) | \
+						(0x1 << 6) | (0x1 << 9) | \
+						(0x1 << 12) | (0x1 << 15))
+	#define PMX_EMI_PL_80_TO_85_VAL		((0x2 << 0) | (0x2 << 3) | \
+						(0x2 << 6) | (0x2 << 9) | \
+						(0x2 << 12) | (0x2 << 15))
+	#define PMX_SPP_PL_80_TO_85_VAL		((0x3 << 0) | (0x3 << 3) | \
+						(0x3 << 6) | (0x3 << 9) | \
+						(0x3 << 12) | (0x3 << 15))
+	#define PMX_UART1_ENH_PL_80_TO_85_VAL	((0x4 << 0) | (0x4 << 3) | \
+						(0x4 << 6) | (0x4 << 9) | \
+						(0x4 << 12) | (0x4 << 15))
+
+	#define PMX_PL_86_87_MASK		(0x3F << 18)
+	#define PMX_PL_86_MASK			(0x7 << 18)
+	#define PMX_PL_87_MASK			(0x7 << 21)
+	#define PMX_CLCD_PL_86_87_VAL		0
+	#define PMX_MII2_PL_86_87_VAL		((0x1 << 18) | (0x1 << 21))
+	#define PMX_EMI_PL_86_87_VAL		((0x2 << 18) | (0x2 << 21))
+	#define PMX_PWM3_PL_86_VAL		(0x4 << 18)
+	#define PMX_PWM2_PL_87_VAL		(0x4 << 21)
+
+	#define PMX_PL_88_89_MASK		(0x3F << 24)
+	#define PMX_CLCD_PL_88_89_VAL		0
+	#define PMX_MII2_PL_88_89_VAL		((0x1 << 24) | (0x1 << 27))
+	#define PMX_EMI_PL_88_89_VAL		((0x2 << 24) | (0x2 << 27))
+	#define PMX_UART6_PL_88_89_VAL		((0x3 << 24) | (0x3 << 27))
+	#define PMX_PWM0_1_PL_88_89_VAL		((0x4 << 24) | (0x4 << 27))
+
+#define SPEAR320_IP_SEL_PAD_90_99_REG	(CONFIG_SPEAR_RASBASE + 0x00C8)
+	#define PMX_PL_90_91_MASK		(0x3F << 0)
+	#define PMX_CLCD_PL_90_91_VAL		0
+	#define PMX_MII2_PL_90_91_VAL		((0x1 << 0) | (0x1 << 3))
+	#define PMX_EMI1_PL_90_91_VAL		((0x2 << 0) | (0x2 << 3))
+	#define PMX_UART5_PL_90_91_VAL		((0x3 << 0) | (0x3 << 3))
+	#define PMX_SSP2_PL_90_91_VAL		((0x4 << 0) | (0x4 << 3))
+
+	#define PMX_PL_92_93_MASK		(0x3F << 6)
+	#define PMX_CLCD_PL_92_93_VAL		0
+	#define PMX_MII2_PL_92_93_VAL		((0x1 << 6) | (0x1 << 9))
+	#define PMX_EMI1_PL_92_93_VAL		((0x2 << 6) | (0x2 << 9))
+	#define PMX_UART4_PL_92_93_VAL		((0x3 << 6) | (0x3 << 9))
+	#define PMX_SSP2_PL_92_93_VAL		((0x4 << 6) | (0x4 << 9))
+
+	#define PMX_PL_94_95_MASK		(0x3F << 12)
+	#define PMX_CLCD_PL_94_95_VAL		0
+	#define PMX_MII2_PL_94_95_VAL		((0x1 << 12) | (0x1 << 15))
+	#define PMX_EMI1_PL_94_95_VAL		((0x2 << 12) | (0x2 << 15))
+	#define PMX_UART3_PL_94_95_VAL		((0x3 << 12) | (0x3 << 15))
+	#define PMX_SSP1_PL_94_95_VAL		((0x4 << 12) | (0x4 << 15))
+
+	#define PMX_PL_96_97_MASK		(0x3F << 18)
+	#define PMX_CLCD_PL_96_97_VAL		0
+	#define PMX_MII2_PL_96_97_VAL		((0x1 << 18) | (0x1 << 21))
+	#define PMX_EMI1_PL_96_97_VAL		((0x2 << 18) | (0x2 << 21))
+	#define PMX_I2C2_PL_96_97_VAL		((0x3 << 18) | (0x3 << 21))
+	#define PMX_SSP1_PL_96_97_VAL		((0x4 << 18) | (0x4 << 21))
+
+	#define PMX_PL_98_MASK			(0x7 << 24)
+	#define PMX_CLCD_PL_98_VAL		0
+	#define PMX_I2C1_PL_98_VAL		(0x2 << 24)
+	#define PMX_UART3_PL_98_VAL		(0x4 << 24)
+
+	#define PMX_PL_99_MASK			(0x7 << 27)
+	#define PMX_SDHCI_PL_99_VAL		0
+	#define PMX_I2C1_PL_99_VAL		(0x2 << 27)
+	#define PMX_UART3_PL_99_VAL		(0x4 << 27)
+
+#define SPEAR320_IP_SEL_MIX_PAD_REG	(CONFIG_SPEAR_RASBASE + 0x00CC)
+	#define PMX_PL_100_101_MASK		(0x3F << 0)
+	#define PMX_SDHCI_PL_100_101_VAL	0
+	#define PMX_UART4_PL_100_101_VAL	((0x4 << 0) | (0x4 << 3))
+
+	#define PMX_SSP1_PORT_SEL_MASK		(0x7 << 8)
+	#define PMX_SSP1_PORT_94_TO_97_VAL	0
+	#define PMX_SSP1_PORT_65_TO_68_VAL	(0x1 << 8)
+	#define PMX_SSP1_PORT_48_TO_51_VAL	(0x2 << 8)
+	#define PMX_SSP1_PORT_36_TO_39_VAL	(0x3 << 8)
+	#define PMX_SSP1_PORT_17_TO_20_VAL	(0x4 << 8)
+
+	#define PMX_SSP2_PORT_SEL_MASK		(0x7 << 11)
+	#define PMX_SSP2_PORT_90_TO_93_VAL	0
+	#define PMX_SSP2_PORT_61_TO_64_VAL	(0x1 << 11)
+	#define PMX_SSP2_PORT_44_TO_47_VAL	(0x2 << 11)
+	#define PMX_SSP2_PORT_32_TO_35_VAL	(0x3 << 11)
+	#define PMX_SSP2_PORT_13_TO_16_VAL	(0x4 << 11)
+
+	#define PMX_UART1_ENH_PORT_SEL_MASK		(0x3 << 14)
+	#define PMX_UART1_ENH_PORT_81_TO_85_VAL		0
+	#define PMX_UART1_ENH_PORT_44_45_34_36_VAL	(0x1 << 14)
+	#define PMX_UART1_ENH_PORT_32_TO_34_36_VAL	(0x2 << 14)
+	#define PMX_UART1_ENH_PORT_3_TO_5_7_VAL		(0x3 << 14)
+
+	#define PMX_UART3_PORT_SEL_MASK		(0x7 << 16)
+	#define PMX_UART3_PORT_94_VAL		0
+	#define PMX_UART3_PORT_73_VAL		(0x1 << 16)
+	#define PMX_UART3_PORT_52_VAL		(0x2 << 16)
+	#define PMX_UART3_PORT_41_VAL		(0x3 << 16)
+	#define PMX_UART3_PORT_15_VAL		(0x4 << 16)
+	#define PMX_UART3_PORT_8_VAL		(0x5 << 16)
+	#define PMX_UART3_PORT_99_VAL		(0x6 << 16)
+
+	#define PMX_UART4_PORT_SEL_MASK		(0x7 << 19)
+	#define PMX_UART4_PORT_92_VAL		0
+	#define PMX_UART4_PORT_71_VAL		(0x1 << 19)
+	#define PMX_UART4_PORT_39_VAL		(0x2 << 19)
+	#define PMX_UART4_PORT_13_VAL		(0x3 << 19)
+	#define PMX_UART4_PORT_6_VAL		(0x4 << 19)
+	#define PMX_UART4_PORT_101_VAL		(0x5 << 19)
+
+	#define PMX_UART5_PORT_SEL_MASK		(0x3 << 22)
+	#define PMX_UART5_PORT_90_VAL		0
+	#define PMX_UART5_PORT_69_VAL		(0x1 << 22)
+	#define PMX_UART5_PORT_37_VAL		(0x2 << 22)
+	#define PMX_UART5_PORT_4_VAL		(0x3 << 22)
+
+	#define PMX_UART6_PORT_SEL_MASK		(0x1 << 24)
+	#define PMX_UART6_PORT_88_VAL		0
+	#define PMX_UART6_PORT_2_VAL		(0x1 << 24)
+
+	#define PMX_I2C1_PORT_SEL_MASK		(0x1 << 25)
+	#define PMX_I2C1_PORT_8_9_VAL		0
+	#define PMX_I2C1_PORT_98_99_VAL		(0x1 << 25)
+
+	#define PMX_I2C2_PORT_SEL_MASK		(0x3 << 26)
+	#define PMX_I2C2_PORT_96_97_VAL		0
+	#define PMX_I2C2_PORT_75_76_VAL		(0x1 << 26)
+	#define PMX_I2C2_PORT_19_20_VAL		(0x2 << 26)
+	#define PMX_I2C2_PORT_2_3_VAL		(0x3 << 26)
+	#define PMX_I2C2_PORT_0_1_VAL		(0x4 << 26)
+
+	#define PMX_SDHCI_CD_PORT_SEL_MASK	(0x1 << 29)
+	#define PMX_SDHCI_CD_PORT_12_VAL	0
+	#define PMX_SDHCI_CD_PORT_51_VAL	(0x1 << 29)
+
+#define SPEAR3XX_FUNC_ENB_REG		SPEAR320_RASSELECT_REG
+
+/* externs related to pinmux */
+extern void spear320_pins_default(void);
+extern void spear320_select_mode(u32 mode);
+extern void spear320_enable_pins(u32 ip, u32 mode);
+extern void spear320_configure_pin(u32 plgpio, u32 mode);
+extern void spear320_plgpio_set(u32 plgpio, u32 val);
+extern int  spear320_plgpio_get(u32 plgpio);
+
 #endif
diff --git a/arch/arm/include/asm/arch-spear/spear3xx.h b/arch/arm/include/asm/arch-spear/spear3xx.h
index e0a72f0..f0df4e6 100644
--- a/arch/arm/include/asm/arch-spear/spear3xx.h
+++ b/arch/arm/include/asm/arch-spear/spear3xx.h
@@ -37,4 +37,26 @@ 
 #define CONFIG_SPEAR_SYSCNTLBASE		0xFCA00000
 #define CONFIG_SPEAR_MISCBASE			0xFCA80000
 
+/* spear3xx pinmux register and related bit masks */
+#define PMX_FIRDA_MASK			(1 << 14)
+#define PMX_I2C_MASK			(1 << 13)
+#define PMX_SSP_CS_MASK			(1 << 12)
+#define PMX_SSP_MASK			(1 << 11)
+#define PMX_MII_MASK			(1 << 10)
+#define PMX_GPIO_PIN0_MASK		(1 << 9)
+#define PMX_GPIO_PIN1_MASK		(1 << 8)
+#define PMX_GPIO_PIN2_MASK		(1 << 7)
+#define PMX_GPIO_PIN3_MASK		(1 << 6)
+#define PMX_GPIO_PIN4_MASK		(1 << 5)
+#define PMX_GPIO_PIN5_MASK		(1 << 4)
+#define PMX_UART0_MODEM_MASK		(1 << 3)
+#define PMX_UART0_MASK			(1 << 2)
+#define PMX_TIMER_2_3_MASK		(1 << 1)
+#define PMX_TIMER_0_1_MASK		(1 << 0)
+
+#define SPEAR3XX_MAX_PLGPIOS			101
+
+/* externs related to pinmux */
+extern void spear3xx_enable_pins(u32 ip, u32 mode);
+
 #endif
diff --git a/board/st/spear/spear300evb.c b/board/st/spear/spear300evb.c
index 46a5922..2ea598a 100644
--- a/board/st/spear/spear300evb.c
+++ b/board/st/spear/spear300evb.c
@@ -30,11 +30,30 @@ 
 #include <asm/arch/hardware.h>
 #include <asm/arch/generic.h>
 #include <asm/arch/misc.h>
+#include <asm/arch/pinmux.h>
 
 #if defined(CONFIG_CMD_NAND)
 static struct nand_chip nand_chip[CONFIG_SYS_MAX_NAND_DEVICE];
 #endif
 
+#if defined(CONFIG_BOARD_EARLY_INIT_F)
+int board_early_init_f(void)
+{
+	spear300_select_mode(SPEAR300_MODE_NAND);
+
+	spear300_pins_default();
+	spear3xx_enable_pins(PMX_I2C0, 0);
+	spear3xx_enable_pins(PMX_SSP0, 0);
+	spear3xx_enable_pins(PMX_ETH0, 0);
+	spear3xx_enable_pins(PMX_UART0, PMX_UART_SIMPLE);
+
+	spear300_enable_pins(PMX_SDMMC, PMX_SDMMC_4BIT);
+	spear300_enable_pins(PMX_FSMCNAND, PMX_NAND_2CHIP);
+
+	return 0;
+}
+#endif
+
 #if defined(CONFIG_CMD_NAND)
 /*
  * board_nand_init - Board specific NAND initialization
diff --git a/board/st/spear/spear310evb.c b/board/st/spear/spear310evb.c
index 4ed8f01..7f70008 100644
--- a/board/st/spear/spear310evb.c
+++ b/board/st/spear/spear310evb.c
@@ -31,11 +31,27 @@ 
 #include <asm/arch/hardware.h>
 #include <asm/arch/generic.h>
 #include <asm/arch/misc.h>
+#include <asm/arch/pinmux.h>
 
 #if defined(CONFIG_CMD_NAND)
 static struct nand_chip nand_chip[CONFIG_SYS_MAX_NAND_DEVICE];
 #endif
 
+#if defined(CONFIG_BOARD_EARLY_INIT_F)
+int board_early_init_f(void)
+{
+	spear310_pins_default();
+	spear3xx_enable_pins(PMX_I2C0, 0);
+	spear3xx_enable_pins(PMX_SSP0, 0);
+	spear3xx_enable_pins(PMX_ETH0, 0);
+	spear3xx_enable_pins(PMX_UART0, PMX_UART_SIMPLE);
+
+	spear310_enable_pins(PMX_ETH1, 0);
+
+	return 0;
+}
+#endif
+
 #if defined(CONFIG_CMD_NAND)
 /*
  * board_nand_init - Board specific NAND initialization
diff --git a/board/st/spear/spear320plc.c b/board/st/spear/spear320plc.c
index a463998..84185a5 100644
--- a/board/st/spear/spear320plc.c
+++ b/board/st/spear/spear320plc.c
@@ -31,9 +31,8 @@ 
 #include <asm/arch/hardware.h>
 #include <asm/arch/generic.h>
 #include <asm/arch/misc.h>
-
-#define PLGPIO_SEL_36	0xb3000028
-#define PLGPIO_IO_36	0xb3000038
+#include <asm/arch/mmc.h>
+#include <asm/arch/pinmux.h>
 
 #if defined(CONFIG_CMD_NAND)
 static struct nand_chip nand_chip[CONFIG_SYS_MAX_NAND_DEVICE];
@@ -41,15 +40,44 @@  static struct nand_chip nand_chip[CONFIG_SYS_MAX_NAND_DEVICE];
 
 static void spear_phy_reset(void)
 {
-	writel(0x10, PLGPIO_IO_36);
-	writel(0x10, PLGPIO_SEL_36);
+	/* GPIO36 is used to enable oscillator */
+	spear320_configure_pin(36, PMX_GPIO);
+	spear320_plgpio_set(36, 1);
+
+	/* GPIO76 is used to reset phy */
+	spear320_configure_pin(76, PMX_GPIO);
+	spear320_plgpio_set(76, 0);
+	spear320_plgpio_set(76, 1);
 }
 
 int board_init(void)
 {
 	spear_phy_reset();
+
+	return 0;
+}
+
+#if defined(CONFIG_BOARD_EARLY_INIT_F)
+int board_early_init_f(void)
+{
+	spear320_select_mode(SPEAR320_EXTENDED_MODE);
+
+	spear320_pins_default();
+
+	spear320_enable_pins(PMX_I2C0, 0);
+	spear320_enable_pins(PMX_ETH0, 0);
+	spear320_enable_pins(PMX_SSP0, 0);
+	spear320_enable_pins(PMX_UART0, PMX_UART_SIMPLE);
+	spear320_enable_pins(PMX_ETH2, PMX_ETH_MII);
+	spear320_enable_pins(PMX_SDMMC, PMX_SDMMC_CD51);
+
+	/* GPIO61 is used for card power on */
+	spear320_configure_pin(61, PMX_GPIO);
+	spear320_plgpio_set(61, 0);
+
 	return 0;
 }
+#endif
 
 #if defined(CONFIG_CMD_NAND)
 /*
diff --git a/board/st/spear/spear600evb.c b/board/st/spear/spear600evb.c
index 17828a3..add496b 100644
--- a/board/st/spear/spear600evb.c
+++ b/board/st/spear/spear600evb.c
@@ -35,6 +35,13 @@ 
 static struct nand_chip nand_chip[CONFIG_SYS_MAX_NAND_DEVICE];
 #endif
 
+#if defined(CONFIG_BOARD_EARLY_INIT_F)
+int board_early_init_f(void)
+{
+	return 0;
+}
+#endif
+
 #if defined(CONFIG_CMD_NAND)
 /*
  * board_nand_init - Board specific NAND initialization