Index: gcc/config.gcc
===================================================================
--- gcc/config.gcc	(revision 193034)
+++ gcc/config.gcc	(working copy)
@@ -852,6 +852,39 @@
 	tm_file="${tm_file} vms/vms.h alpha/vms.h"
 	tmake_file="${tmake_file} alpha/t-vms"
 	;;
+arc-*-elf*)
+	extra_headers="arc-simd.h"
+	tm_file="dbxelf.h elfos.h newlib-stdint.h ${tm_file}"
+	tmake_file="arc/t-arc-newlib arc/t-arc"
+	case x"${with_cpu}" in
+	  xarc600|xarc601|xarc700)
+		target_cpu_default="TARGET_CPU_$with_cpu"
+		;;
+	esac
+	;;
+arc*-*-linux-uclibc*)
+	extra_headers="arc-simd.h"
+	tm_file="dbxelf.h elfos.h gnu-user.h linux.h glibc-stdint.h ${tm_file}"
+	tmake_file="${tmake_file} arc/t-arc-uClibc arc/t-arc"
+	case x"${with_cpu}" in
+	  xarc600|xarc601|xarc700)
+		target_cpu_default="TARGET_CPU_$with_cpu"
+		;;
+	esac
+	if test x${with_endian} = x; then
+		case ${target} in
+		arc*be-*-* | arc*eb-*-*)	with_endian=big ;;
+		*)				with_endian=little ;;
+		esac
+	fi
+	case ${with_endian} in
+	big|little)		;;
+	*)	echo "with_endian=${with_endian} not supported."; exit 1 ;;
+	esac
+	case ${with_endian} in
+	big*)	tm_defines="DRIVER_ENDIAN_SELF_SPECS=\\\"%{!EL:%{!mlittle-endian:-mbig-endian}}\\\" ${tm_defines}"
+	esac
+        ;;
 arm-wrs-vxworks)
 	tm_file="elfos.h arm/elf.h arm/aout.h ${tm_file} vx-common.h vxworks.h arm/vxworks.h"
 	extra_options="${extra_options} arm/vxworks.opt"
@@ -3140,6 +3173,17 @@
 		done
 		;;
 
+	arc*-*-*) # was:	arc*-*-linux-uclibc)
+		supported_defaults="cpu"
+		case $with_cpu in
+		  arc600|arc601|arc700)
+			;;
+		  *) echo "Unknown cpu type"
+			exit 1
+			;;
+		esac
+		;;
+
 	arm*-*-*)
 		supported_defaults="arch cpu float tune fpu abi mode tls"
 		for which in cpu tune; do
Index: gcc/doc/extend.texi
===================================================================
--- gcc/doc/extend.texi	(revision 193034)
+++ gcc/doc/extend.texi	(working copy)
@@ -2782,7 +2782,7 @@ least version 2.20.1), and GNU C library
 
 @item interrupt
 @cindex interrupt handler functions
-Use this attribute on the ARM, AVR, CR16, Epiphany, M32C, M32R/D, m68k, MeP, MIPS,
+Use this attribute on the ARC, ARM, AVR, CR16, Epiphany, M32C, M32R/D, m68k, MeP, MIPS,
 RL78, RX and Xstormy16 ports to indicate that the specified function is an
 interrupt handler.  The compiler will generate function entry and exit
 sequences suitable for use in an interrupt handler when this attribute
@@ -2792,6 +2792,16 @@ least version 2.20.1), and GNU C library
 Note, interrupt handlers for the Blackfin, H8/300, H8/300H, H8S, MicroBlaze,
 and SH processors can be specified via the @code{interrupt_handler} attribute.
 
+Note, on the ARC, you must specify the kind of interrupt to by handled
+in a parameter to the interrupt attribute like this:
+
+@smallexample
+void f () __attribute__ ((interrupt ("ilink1")));
+@end smallexample
+
+Permissible values for this parameter are: @w{@code{ilink1}} and
+@w{@code{ilink2}}.
+
 Note, on the AVR, the hardware globally disables interrupts when an
 interrupt is executed.  The first instruction of an interrupt handler
 declared with this attribute will be a @code{SEI} instruction to
@@ -2962,7 +2972,7 @@ handlers intended to be used with the @c
 @item long_call/short_call
 @cindex indirect calls on ARM
 This attribute specifies how a particular function is called on
-ARM and Epiphany.  Both attributes override the
+ARC, ARM and Epiphany.  Both attributes override the
 @option{-mlong-calls} (@pxref{ARM Options})
 command-line switch and @code{#pragma long_calls} settings.  The
 @code{long_call} attribute indicates that the function might be far
Index: gcc/doc/install.texi
===================================================================
--- gcc/doc/install.texi	(revision 193034)
+++ gcc/doc/install.texi	(working copy)
@@ -1179,8 +1179,8 @@ Specify that the target supports TLS (Th
 @itemx --with-cpu-64=@var{cpu}
 Specify which cpu variant the compiler should generate code for by default.
 @var{cpu} will be used as the default value of the @option{-mcpu=} switch.
-This option is only supported on some targets, including ARM, i386, M68k,
-PowerPC, and SPARC@.  The @option{--with-cpu-32} and
+This option is only supported on some targets, including ARC, ARM, i386, M68k,
+PowerPC, and SPARC@.  It is mandatory for ARC@.  The @option{--with-cpu-32} and
 @option{--with-cpu-64} options specify separate default CPUs for
 32-bit and 64-bit modes; these options are only supported for i386,
 x86-64 and PowerPC.
@@ -3147,6 +3147,22 @@ versions before @code{alpha*-dec-osf4} a
 
 @html
 <hr />
+@end html
+@heading @anchor{arc-x-elf32}arc-*-elf32
+
+Use @samp{configure --target=arc-elf32 --with-cpu=@var{cpu} --enable-languages="c,c++"}
+to configure GCC, with @var{cpu} being one of @samp{arc600}, @samp{arc601},
+or @samp{arc700}@.
+
+@html
+<hr />
+@end html
+@heading @anchor{arc-linux-uclibc}arc-linux-uclibc
+
+Use @samp{configure --target=arc-linux-uclibc --with-cpu=arc700 --enable-languages="c,c++"} to configure GCC@.
+
+@html
+<hr />
 @end html
 @heading @anchor{arm-x-eabi}arm-*-eabi
 ARM-family processors.  Subtargets that use the ELF object format
Index: gcc/doc/invoke.texi
===================================================================
--- gcc/doc/invoke.texi	(revision 193034)
+++ gcc/doc/invoke.texi	(working copy)
@@ -484,6 +484,24 @@ cpp(1), gcov(1), as(1), ld(1), gdb(1), a
 -mfp-mode=@var{mode} -mvect-double -max-vect-align=@var{num} @gol
 -msplit-vecmove-early -m1reg-@var{reg}}
 
+@emph{ARC Options}
+@gccoptlist{-mbig-endian -mlittle-endian -mno-cond-exec -mA5 -mA6 -mARC600 @gol
+-mA7 -mARC700 -mmixed-code -mvolatile-cache -mbarrel-shifter @gol
+-mnorm -mswap -mmul64 -mno-mpy -mEA -msoft-float -mlong-calls @gol
+-mno-brcc -mno-sdata -mno-millicode @gol
+-mspfp -mspfp_compact -mspfp_fast -margonaut @gol
+-mdpfp -mdpfp_compact -mdpfp_fast -mno-dpfp-lrsr @gol
+-msimd -mcpu=@var{cpu} -msize-level=@var{level} -misize @gol
+-multcost=@var{cost} -mtune=@var{cpu} -mindexed-loads @gol
+-mauto-modify-reg -mold-di-patterns -mmul32x16 -m2addr @gol
+-munalign-prob-threshold=@var{probability} -mmedium-calls @gol
+-mannotate-align -malign-call -mRcq -mRcw -mearly-cbranchsi @gol
+-mbbit-peephole @gol
+-mcase-vector-pcrel -mcompact-casesi -mq-class -mexpand-adddi @gol
+-mcrc -mdsp_packa -mdvbf -mmac_d16 -mmac_24 -mtelephony -mxy @gol
+-mlock -mswape -mrtsc @gol
+-mepilogue-cfi -EB -EL -marclinux -marclinux-prof}
+
 @emph{ARM Options}
 @gccoptlist{-mapcs-frame  -mno-apcs-frame @gol
 -mabi=@var{name} @gol
@@ -10653,6 +10671,7 @@ finds any @option{-l} options and any no
 @menu
 * AArch64 Options::
 * Adapteva Epiphany Options::
+* ARC Options::
 * ARM Options::
 * AVR Options::
 * Blackfin Options::
@@ -10980,6 +10999,394 @@ truncating (i.e.@: round towards zero) r
 @option{-march} and @option{-mcpu=}.
 @end table
 
+@node ARC Options
+@subsection ARC Options
+@cindex ARC options
+
+These @samp{-m} options are defined for Synopsys DesignWare ARC:
+
+@c architecture variants
+@table @gcctabopt
+@item -mcpu=@var{cpu}
+@opindex mcpu
+Set architecture type, register usage, and
+instruction scheduling parameters for @var{cpu}.
+There are also shortcut alias options available for backward compatibility and
+convenience.
+Supported values for @var{cpu} are
+
+@table @samp
+@item A5
+@opindex mA5
+Compile for Arctangent-A5.  Alias: @option{-mA5}.
+
+@opindex mA6
+@opindex mARC600
+@item ARC600
+Compile for ARC600.  Aliases: @option{-mA6}, @option{-mARC600}.
+
+@item ARC601
+Compile for ARC601.
+
+@item ARC700
+@opindex mA7
+@opindex mARC700
+Compile for ARC700.  Aliases: @option{-mA7}, @option{-mARC700}.
+This is the default when configured with @samp{--with-cpu=arc700}@.
+@end table
+
+@item -mbig-endian
+@opindex mbig-endian
+@item -EB
+@opindex EB
+Compile code for big endian mode
+
+@item -mlittle-endian
+@opindex mlittle-endian
+@item -EL
+@opindex EL
+Compile code for little endian mode.  This is the default.
+
+@item -mbarrel_shifter
+@opindex mbarrel_shifter
+Generate instructions supported by barrel shifter.  This is the default
+unless @samp{-mcpu=ARC601} is in effect.
+
+@item -mnorm
+@opindex mnorm
+Generate norm instruction.
+This is the default if @samp{-mcpu=ARC700} is in effect.
+
+@item -mswap
+@opindex mswap
+Generate swap instructions.
+
+@item -mmul64
+@opindex mmul64
+Generate mul64 and mulu64 instructions
+This is not valid for @samp{-mcpu=ARC700}.
+
+@item -mno-mpy
+@opindex mno-mpy
+Do not generate mpy instructions for ARC700.
+
+@item -mmul32x16
+@opindex mmul32x16
+Generate 32x16 bit multiply and mac instructions.
+
+@item -mEA
+@opindex mEA
+Generate Extended arithmetic instructions.
+Currently only @code{divaw}, @code{adds}, @code{subs}, and @code{sat16}
+supported.
+This is always enabled for @samp{-mcpu=ARC700}.
+
+@item -mspfp
+@opindex mspfp
+@item -mspfp_compact
+@opindex mspfp_compact
+FPX: Generate Single Precision FPX instructions, tuned for the compact
+implementation.
+
+@item -mspfp_fast
+@opindex mspfp_fast
+FPX: Generate Single Precision FPX instructions, tuned for the fast
+implementation.
+
+@item -margonaut
+@opindex margonaut
+FPX: Enable Argonaut ARC CPU Double Precision Floating Point extensions.
+
+@item -mdpfp
+@opindex mdpfp
+@item -mdpfp_compact
+@opindex mdpfp_compact
+FPX: Generate Double Precision FPX instructions, tuned for the compact
+implementation.
+
+@item -mdpfp_fast
+@opindex mdpfp_fast
+FPX: Generate Double Precision FPX instructions, tuned for the fast
+implementation.
+
+@item -mno-dpfp-lrsr
+@opindex mno-dpfp-lrsr
+Disable LR and SR instructions from using FPX extension aux registers.
+
+@item -msimd
+@opindex msimd
+Enable generation of ARC SIMD instructions via target-specific builtins.
+
+@item -msoft-float
+@opindex msoft-float
+This option ignored; it is provided for compatibility purposes only.
+Software floating point code is emitted by default, and this default
+can overridden by FPX options; @samp{mspfp}, @samp{mspfp_compact}, or
+@samp{mspfp_fast} for single precision, and @samp{mdpfp},
+@samp{mdpfp_compact}, or @samp{mdpfp_fast} for double precision.
+
+@c Flags used by the assembler, but for which we define preprocessor
+@c macro symbols as well.
+@item -mcrc
+@opindex mcrc
+Passed down to the assembler to
+enable the variable polynomial CRC extension.
+Also sets the preprocessor symbol @code{__Xcrc}.
+
+@item -mdsp_packa
+@opindex mdsp_packa
+Passed down to the assembler to
+enable the DSP 3.1 Pack A extensions.
+Also sets the preprocessor symbol @code{__Xdsp_packa}.
+
+@item -mdvbf
+@opindex mdvbf
+Passed down to the assembler to
+enable the dual viterbi butterfly extension.
+Also sets the preprocessor symbol @code{__Xdvbf}.
+
+@item -mmac_d16
+@opindex mmac_d16
+Passed down to the assembler.
+Also sets the preprocessor symbol @code{__Xxmac_d16}.
+
+@item -mmac_24
+@opindex mmac_24
+Passed down to the assembler.
+Also sets the preprocessor symbol @code{__Xxmac_24}.
+
+@item -mtelephony
+@opindex mtelephony
+Passed down to the assembler to
+enable dual and single operand instructions for telephony.
+Also sets the preprocessor symbol @code{__Xtelephony}.
+
+@item -mxy
+@opindex mxy
+Passed down to the assembler to
+enable the XY Memory extension (DSP version 3).
+Also sets the preprocessor symbol @code{__Xxy}.
+
+@c ARC700 4.10 extension instructions
+@item -mlock
+@opindex mlock
+Passed down to the assembler to
+enable the Locked Load/Store Conditional extension.
+Also sets the preprocessor symbol @code{__Xlock}.
+
+@item -mswape
+@opindex mswape
+Passed down to the assembler to
+enable the swap byte ordering extension instruction.
+Also sets the preprocessor symbol @code{__Xswape}.
+
+@item -mrtsc
+@opindex mrtsc
+Passed down to the assembler to
+enable the 64-bit Time-Stamp Counter extension instruction
+Also sets the preprocessor symbol @code{__Xrtsc}.
+
+
+
+@item -marclinux
+@opindex marclinux
+Pass -marclinux option through to linker.
+
+@item -marclinux_prof
+@opindex marclinux_prof
+Pass -marclinux_prof option through to linker.
+
+@c semantically relevant code generation options
+@item -mvolatile-cache
+@opindex mvolatile-cache
+Use ordinarily cached memory accesses for volatile references.  This is the
+default.
+
+@item -mno-volatile-cache
+@opindex mno-volatile-cache
+Enable cache bypass for volatile references.
+
+@item -mlong-calls
+@opindex mlong-calls
+Generate call insns as register indirect calls.
+
+@item -mmedium-calls
+@opindex mmedium-calls
+Don't use less than 25 bit addressing range for calls.
+
+@item -mno-sdata
+@opindex mno-sdata
+Do not generate sdata references
+
+@item -mno-epilogue-cfi
+@opindex mno-epilogue-cfi
+Disable generation of call frame information for epilogues.
+
+@item -mepilogue-cfi
+@opindex mepilogue-cfi
+Enable generation of call frame information for epilogues.
+
+@c code generation tuning options
+@item -mtune=@var{cpu}
+@opindex mtune
+Set instruction scheduling parameters for @var{cpu}, overriding any implied
+by @option{-mcpu=}.
+
+Supported values for @var{cpu} are
+
+@table @samp
+@item arc600
+Tune for ARC600 cpu.
+
+@item arc601
+Tune for ARC601 cpu.
+
+@item arc700
+Tune for ARC700 R4.2 Cpu with standard multiplier block.
+
+@item arc700-xmac
+@item ARC725D
+@item ARC750D
+Tune for ARC700 R4.2 Cpu with XMAC block.
+
+@end table
+
+@item -mno-cond-exec
+@opindex mno-cond-exec
+Disable ARCompact specific pass to generate conditional execution instructions.
+Due to delay slot scheduling and interactions between operand numbers,
+literal sizes, instruction lengths, and the support for conditional exection,
+the target-independent pass to generate conditional execution is often lacking,
+so the ARC port has kept a sepcial pass around that tries to find more
+conditional execution generating opportunities after register allocation,
+branch shortening, and delay slot scheduling have been done.  This pass
+generally, but not always, improves performace and code size, at the cost of
+extra compilation time, which is why there is an option to switch it off.
+If you have a problem with call instructions exceeding their allowable
+offset range because they are conditionalized, you should consider using
+@option{-mmedium-calls} instead.
+
+@item -mmixed-code
+@opindex mmixed-code
+Tweak register allocation to help 16-bit instruction generation.
+This generally has the effect of decreasing the average instruction size
+while increasing the instruction count.
+
+@item -mno-brcc
+@opindex mno-brcc
+This option disables a target-specific pass in arc_reorg to generate BRcc
+instructions.  It has no effect on BRcc generation driven by the combiner
+pass.
+
+@item -mno-millicode
+@opindex mno-millicode
+When optimizing for size (using @option{-Os}), prologues / epilogues that
+have to save / restore a lot of registers are often shortened by using call
+to a special function in libgcc; this is referred to as a millicode call.
+As these calls can pose performance issues, and/or cause linking issues
+when you link in a nonstandard way, this option is provided to turn off
+millicode call generation.
+
+@item -msize-level=@var{level}
+@ opindex msize-level
+Fine-tune size optimization with regards to instruction lengths and alignment.
+The recognized values for @var{level} are:
+@table @samp
+@item 0
+No size optimization.  This level is deprecated and treated like @samp{1}.
+@item 1
+Short instructions are used opportunistically.
+@item 2
+In addition, alignment of loops and of code after barriers are dropped.
+@item 3
+In addition, optional data alignment is dropped, and the option @option{Os} is enabled.
+
+@end table
+
+This defaults to @samp{3} when @option{-Os} is in effect.  Otherwise,
+the behaviour when this is not set is equivalent to level @samp{1}.
+
+@item -multcost=@var{num}
+@opindex multcost
+Cost to assume for a multiply instruction, with @samp{4} being equal to a
+normal instruction.
+
+@item -mindexed-loads
+@opindex mindexed-loads
+Enable the use of indexed loads.  This can be problematic because some
+optimizers will then assume the that indexed stores exist, which is not
+the case.
+
+@item -mauto-modify-reg
+@opindex mauto-modify-reg
+Enable the use of pre/post modify with register displacement.
+
+@item -mold-di-patterns
+@opindex mold-di-patterns
+Enable use of old DI patterns that have presumably been obsoleted by subreg lowering.
+
+@item -munalign-prob-threshold=@var{probability}
+@opindex munalign-prob-threshold
+Set probability threshold for unaligning branches.
+When tuning for @samp{ARC700} and optimizing for speed, branches without
+filled delay slot are preferrably emitted unaligned and long, unless
+profiling indicates that the probability for the branch to be taken
+is below @var{probability}.  @xref{Cross-profiling}.
+The default is (REG_BR_PROB_BASE/2), i.e.@: 5000.
+
+@item -malign-call
+@opindex malign-call
+Do alignment optimizations for call instructions.
+
+@item -mRcq
+@opindex mRcq
+Enable Rcq constraint handling - most short code generation depends on this.
+This is the default.
+
+@item -mRcw
+@opindex mRcw
+Enable Rcw constraint handling - ccfsm condexec mostly depends on this.
+This is the default.
+
+@item -mearly-cbranchsi
+@opindex mearly-cbranchsi
+Enable pre-reload use of the cbranchsi pattern.
+
+@item -mbbit-peephole
+@opindex mbbit-peephole
+Enable bbit peephole2.
+
+@item -mcase-vector-pcrel
+@opindex mcase-vector-pcrel
+Use pc-relative switch case tables - this enables case table shortening.
+This is the default for @option{-Os}.
+
+@item -mcompact-casesi
+@opindex mcompact-casesi
+Enable compact casesi pattern.
+This is the default for @option{-Os}.
+
+@item -mq-class
+@opindex mq-class
+Enable 'q' instruction alternatives.
+This is the default for @option{-Os}.
+
+@item -mexpand-adddi
+@opindex mexpand-adddi
+Expand adddi3 and subdi3 at rtl generation time into add.f / adc etc.
+
+@c Assembly annotation options
+@item -misize
+@opindex misize
+Annotate assembler instructions with estimated addresses.
+
+@item -mannotate-align
+@opindex mannotate-align
+Explain what alignment considerations lead to the decision to make an
+instruction short or long.
+
+@end table
+
 @node ARM Options
 @subsection ARM Options
 @cindex ARM options
Index: gcc/doc/md.texi
===================================================================
--- gcc/doc/md.texi	(revision 193034)
+++ gcc/doc/md.texi	(working copy)
@@ -1731,6 +1731,54 @@ The high part (bits 12 and upwards) of t
 @end table
 
 
+@item ARC ---@file{config/arc/constraints.md}
+@table @code
+@item q
+Registers usable in ARCompact 16-bit instructions: @code{r0}-@code{r3},
+@code{r12}-@code{r15}.  This constraint can only match when the @option{-mq}
+option is in effect.
+
+@item e
+Registers usable as base-regs of memory addresses in ARCompact 16-bit memory
+instructions: @code{r0}-@code{r3}, @code{r12}-@code{r15}, @code{sp}.
+This constraint can only match when the @option{-mq}
+option is in effect.
+@item D
+ARC FPX (dpfp) 64-bit registers. @code{D0}, @code{D1}.
+
+@item I
+A signed 12-bit integer constant.
+
+@item Cal
+constant for arithmetic/logical operations.  This might be any constant
+that can be put into a long immediate by the assmbler or linker without
+involving a PIC relocation.
+
+@item K
+A 3-bit unsigned integer constant.
+
+@item L
+A 6-bit unsigned integer constant.
+
+@item CnL
+One's complement of a 6-bit unsigned integer constant.
+
+@item CmL
+Two's complement of a 6-bit unsigned integer constant.
+
+@item M
+A 5-bit unsigned integer constant.
+
+@item O
+A 7-bit unsigned integer constant.
+
+@item P
+A 8-bit unsigned integer constant.
+
+@item H
+Any const_double value.
+@end table
+
 @item ARM family---@file{config/arm/constraints.md}
 @table @code
 @item w
Index: gcc/testsuite/gcc.c-torture/execute/20101011-1.c
===================================================================
--- gcc/testsuite/gcc.c-torture/execute/20101011-1.c	(revision 193034)
+++ gcc/testsuite/gcc.c-torture/execute/20101011-1.c	(working copy)
@@ -40,6 +40,9 @@
 #elif defined (__CRIS__)
   /* No SIGFPE for CRIS integer division.  */
 # define DO_TEST 0
+#elif defined (__arc__)
+  /* No SIGFPE for ARC integer division.  */
+# define DO_TEST 0
 #elif defined (__arm__) && defined (__ARM_EABI__)
 # ifdef __ARM_ARCH_EXT_IDIV__
   /* Hardware division instructions may not trap, and handle trapping
Index: libgcc/config.host
===================================================================
--- libgcc/config.host	(revision 193034)
+++ libgcc/config.host	(working copy)
@@ -316,6 +316,14 @@
 	extra_parts="$extra_parts vms-dwarf2.o vms-dwarf2eh.o"
 	md_unwind_header=alpha/vms-unwind.h
 	;;
+arc-*-elf*)
+	tmake_file="arc/t-arc-newlib arc/t-arc"
+	extra_parts="crti.o crtn.o crtend.o crtbegin.o crtendS.o crtbeginS.o libgmon.a crtg.o crtgend.o"
+	;;
+arc*-*-linux-uclibc*)
+	tmake_file="${tmake_file} t-slibgcc-libgcc t-slibgcc-nolc-override arc/t-arc700-uClibc arc/t-arc"
+	extra_parts="crti.o crtn.o crtend.o crtbegin.o crtendS.o crtbeginS.o libgmon.a crtg.o crtgend.o"
+	;;
 arm-wrs-vxworks)
 	tmake_file="$tmake_file arm/t-arm arm/t-vxworks t-fdpbit"
 	extra_parts="$extra_parts crti.o crtn.o"
Index: libstdc++-v3/acinclude.m4
===================================================================
--- libstdc++-v3/acinclude.m4	(revision 193034)
+++ libstdc++-v3/acinclude.m4	(working copy)
@@ -2985,6 +2985,8 @@ void foo()
     if AC_TRY_EVAL(ac_compile); then
       if grep _Unwind_SjLj_Resume conftest.s >/dev/null 2>&1 ; then
 	enable_sjlj_exceptions=yes
+      elif grep _Unwind_SjLj_Register conftest.s >/dev/null 2>&1 ; then
+	enable_sjlj_exceptions=yes
       elif grep _Unwind_Resume conftest.s >/dev/null 2>&1 ; then
 	enable_sjlj_exceptions=no
       elif grep __cxa_end_cleanup conftest.s >/dev/null 2>&1 ; then
