Patchwork [U-Boot,v1,3/8] am33xx: NAND support

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Submitter Ilya Yanok
Date Oct. 30, 2012, 10:47 p.m.
Message ID <1351637263-17464-4-git-send-email-ilya.yanok@cogentembedded.com>
Download mbox | patch
Permalink /patch/195640/
State Changes Requested
Delegated to: Tom Rini
Headers show

Comments

Ilya Yanok - Oct. 30, 2012, 10:47 p.m.
TI AM33XX has the same GPMC controller as OMAP3 so we could just use the
existing omap_gpmc driver. This patch adds adds required
definitions/intialization.

Signed-off-by: Ilya Yanok <ilya.yanok@cogentembedded.com>
---
 arch/arm/cpu/armv7/am33xx/Makefile           |    1 +
 arch/arm/cpu/armv7/am33xx/board.c            |   34 +++++
 arch/arm/cpu/armv7/am33xx/clock.c            |    5 +
 arch/arm/cpu/armv7/am33xx/mem.c              |  104 +++++++++++++++
 arch/arm/include/asm/arch-am33xx/cpu.h       |   53 ++++++++
 arch/arm/include/asm/arch-am33xx/hardware.h  |    3 +
 arch/arm/include/asm/arch-am33xx/mem.h       |  174 ++++++++++++++++++++++++++
 arch/arm/include/asm/arch-am33xx/omap_gpmc.h |  130 +++++++++++++++++++
 arch/arm/include/asm/arch-am33xx/sys_proto.h |    3 +
 9 files changed, 507 insertions(+)
 create mode 100644 arch/arm/cpu/armv7/am33xx/mem.c
 create mode 100644 arch/arm/include/asm/arch-am33xx/mem.h
 create mode 100644 arch/arm/include/asm/arch-am33xx/omap_gpmc.h
Tom Rini - Oct. 30, 2012, 11:51 p.m.
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Hash: SHA1

On 10/30/12 15:47, Ilya Yanok wrote:
> TI AM33XX has the same GPMC controller as OMAP3 so we could just
> use the existing omap_gpmc driver. This patch adds adds required 
> definitions/intialization.
[snip]
> --- a/arch/arm/cpu/armv7/am33xx/board.c +++
> b/arch/arm/cpu/armv7/am33xx/board.c
[snip]
> +U_BOOT_CMD( +	nandecc, 2, 1,	do_switch_ecc, +	"switch OMAP3 NAND
> ECC calculation algorithm", +	"[bch8/hw/sw] - Switch between NAND
> hardware (hw) or software (sw) ecc algorithm" +);

While useful for testing, I don't want to add this command to am33xx
since we don't need it like we do on omap3.  We can be consistent and
be whole chip BCH8, or later BCH16 (and use the same logic ROM does
and Linux does or will).

[snip]
> +++ b/arch/arm/cpu/armv7/am33xx/mem.c +#if defined(CONFIG_CMD_NAND)
> || defined(CONFIG_CMD_ONENAND)

There will be no ONENAND.  ANd please fixup comment style issues that
we're copying from omap3.

[snip]
> +++ b/arch/arm/include/asm/arch-am33xx/mem.h +#ifndef __ASSEMBLY__ 
> +enum { +	STACKED = 0, +	IP_DDR = 1, +	COMBO_DDR = 2, +	IP_SDR =
> 3, +}; +#endif /* __ASSEMBLY__ */ + +#define EARLY_INIT	1 +

We don't need that enum I think.  We shouldn't need EARLY_INIT either.

> +/* + * GPMC settings - + * Definitions is as per the following
> format + * #define <PART>_GPMC_CONFIG<x> <value> + * Where: + *
> PART is the part name e.g. STNOR - Intel Strata Flash + * x is GPMC
> config registers from 1 to 6 (there will be 6 macros) + * Value is
> corresponding value + * + * For every valid PRCM configuration
> there should be only one definition of + * the same. if values are
> independent of the board, this definition will be + * present in
> this file if values are dependent on the board, then this should +
> * go into corresponding mem-boardName.h file + * + * Currently
> valid part Names are (PART): + * STNOR - Intel Strata Flash + *
> SMNAND - Samsung NAND + * MPDB - H4 MPDB board + * SBNOR - Sibley
> NOR + * MNAND - Micron Large page x16 NAND + * ONNAND - Samsung One
> NAND + * + * include/configs/file.h contains the defn - for all CS
> we are interested + * #define OMAP34XX_GPMC_CSx PART + * #define
> OMAP34XX_GPMC_CSx_SIZE Size + * #define OMAP34XX_GPMC_CSx_MAP Map +
> * Where: + * x - CS number + * PART - Part Name as defined above +
> * SIZE - how big is the mapping to be + *   GPMC_SIZE_128M - 0x8 +
> *   GPMC_SIZE_64M  - 0xC + *   GPMC_SIZE_32M  - 0xE + *
> GPMC_SIZE_16M  - 0xF + * MAP  - Map this CS to which address(GPMC
> address space)- Absolute address + *   >>24 before being used. +
> */

Lets correct this comment and drop out the GPMC values for chips other
than what we have available on the GP EVM.  We can add in more later
as needed.

[snip]
> +/* GPMC CS configuration for an SMSC LAN9221 ethernet controller
> */ +#define NET_LAN9221_GPMC_CONFIG1    0x00001000 +#define
> NET_LAN9221_GPMC_CONFIG2    0x00060700 +#define
> NET_LAN9221_GPMC_CONFIG3    0x00020201 +#define
> NET_LAN9221_GPMC_CONFIG4    0x06000700 +#define
> NET_LAN9221_GPMC_CONFIG5    0x0006090A +#define
> NET_LAN9221_GPMC_CONFIG6    0x87030000 +#define
> NET_LAN9221_GPMC_CONFIG7    0x00000f6c + +#endif /*
> __ASM_ARCH_OMAP_GPMC_H */

Also don't need those, right?

- -- 
Tom
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Patch

diff --git a/arch/arm/cpu/armv7/am33xx/Makefile b/arch/arm/cpu/armv7/am33xx/Makefile
index 7768912..c93ac19 100644
--- a/arch/arm/cpu/armv7/am33xx/Makefile
+++ b/arch/arm/cpu/armv7/am33xx/Makefile
@@ -18,6 +18,7 @@  LIB	= $(obj)lib$(SOC).o
 
 COBJS	+= clock.o
 COBJS	+= sys_info.o
+COBJS	+= mem.o
 COBJS	+= ddr.o
 COBJS	+= emif4.o
 COBJS	+= board.o
diff --git a/arch/arm/cpu/armv7/am33xx/board.c b/arch/arm/cpu/armv7/am33xx/board.c
index 978b184..71f66ef 100644
--- a/arch/arm/cpu/armv7/am33xx/board.c
+++ b/arch/arm/cpu/armv7/am33xx/board.c
@@ -25,6 +25,7 @@ 
 #include <asm/arch/ddr_defs.h>
 #include <asm/arch/clock.h>
 #include <asm/arch/gpio.h>
+#include <asm/arch/mem.h>
 #include <asm/arch/mmc_host_def.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/io.h>
@@ -220,6 +221,8 @@  int board_init(void)
 
 	gd->bd->bi_boot_params = PHYS_DRAM_1 + 0x100;
 
+	gpmc_init();
+
 	return 0;
 }
 
@@ -298,3 +301,34 @@  int board_eth_init(bd_t *bis)
 	return cpsw_register(&cpsw_data);
 }
 #endif
+
+#if defined(CONFIG_NAND_OMAP_GPMC) & !defined(CONFIG_SPL_BUILD)
+/******************************************************************************
+ * AM33xx specific command to switch between NAND HW and SW ecc
+ *****************************************************************************/
+static int
+do_switch_ecc(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	if (argc != 2)
+		goto usage;
+	if (strncmp(argv[1], "hw", 2) == 0)
+		omap_nand_switch_ecc(1);
+	else if (strncmp(argv[1], "sw", 2) == 0)
+		omap_nand_switch_ecc(0);
+	else
+		goto usage;
+
+	return 0;
+
+usage:
+	printf("Usage: nandecc %s\n", cmdtp->usage);
+	return 1;
+}
+
+U_BOOT_CMD(
+	nandecc, 2, 1,	do_switch_ecc,
+	"switch OMAP3 NAND ECC calculation algorithm",
+	"[bch8/hw/sw] - Switch between NAND hardware (hw) or software (sw) ecc algorithm"
+);
+
+#endif /* CONFIG_NAND_OMAP_GPMC & !CONFIG_SPL_BUILD */
diff --git a/arch/arm/cpu/armv7/am33xx/clock.c b/arch/arm/cpu/armv7/am33xx/clock.c
index 2b19506..75ec860 100644
--- a/arch/arm/cpu/armv7/am33xx/clock.c
+++ b/arch/arm/cpu/armv7/am33xx/clock.c
@@ -114,6 +114,11 @@  static void enable_per_clocks(void)
 	while (readl(&cmwkup->wkup_uart0ctrl) != PRCM_MOD_EN)
 		;
 
+	/* GPMC */
+	writel(PRCM_MOD_EN, &cmper->gpmcclkctrl);
+	while (readl(&cmper->gpmcclkctrl) != PRCM_MOD_EN)
+		;
+
 	/* MMC0*/
 	writel(PRCM_MOD_EN, &cmper->mmc0clkctrl);
 	while (readl(&cmper->mmc0clkctrl) != PRCM_MOD_EN)
diff --git a/arch/arm/cpu/armv7/am33xx/mem.c b/arch/arm/cpu/armv7/am33xx/mem.c
new file mode 100644
index 0000000..e7f1cf7
--- /dev/null
+++ b/arch/arm/cpu/armv7/am33xx/mem.c
@@ -0,0 +1,104 @@ 
+/*
+ * (C) Copyright 2010
+ * Texas Instruments, <www.ti.com>
+ *
+ * Author :
+ *     Mansoor Ahamed <mansoor.ahamed@ti.com>
+ *
+ * Initial Code from:
+ *     Manikandan Pillai <mani.pillai@ti.com>
+ *     Richard Woodruff <r-woodruff2@ti.com>
+ *     Syed Mohammed Khasim <khasim@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/mem.h>
+#include <asm/arch/sys_proto.h>
+#include <command.h>
+
+struct gpmc *gpmc_cfg;
+
+#if defined(CONFIG_CMD_NAND)
+static const u32 gpmc_m_nand[GPMC_MAX_REG] = {
+	M_NAND_GPMC_CONFIG1,
+	M_NAND_GPMC_CONFIG2,
+	M_NAND_GPMC_CONFIG3,
+	M_NAND_GPMC_CONFIG4,
+	M_NAND_GPMC_CONFIG5,
+	M_NAND_GPMC_CONFIG6, 0
+};
+
+#define GPMC_CS 0
+
+#endif
+
+
+void enable_gpmc_cs_config(const u32 *gpmc_config, struct gpmc_cs *cs, u32 base,
+			u32 size)
+{
+	writel(0, &cs->config7);
+	sdelay(1000);
+	/* Delay for settling */
+	writel(gpmc_config[0], &cs->config1);
+	writel(gpmc_config[1], &cs->config2);
+	writel(gpmc_config[2], &cs->config3);
+	writel(gpmc_config[3], &cs->config4);
+	writel(gpmc_config[4], &cs->config5);
+	writel(gpmc_config[5], &cs->config6);
+	/* Enable the config */
+	writel((((size & 0xF) << 8) | ((base >> 24) & 0x3F) |
+		(1 << 6)), &cs->config7);
+	sdelay(2000);
+}
+
+/*****************************************************
+ * gpmc_init(): init gpmc bus
+ * Init GPMC for x16, MuxMode (SDRAM in x32).
+ * This code can only be executed from SRAM or SDRAM.
+ *****************************************************/
+void gpmc_init(void)
+{
+	/* putting a blanket check on GPMC based on ZeBu for now */
+	gpmc_cfg = (struct gpmc *)GPMC_BASE;
+
+#if defined(CONFIG_CMD_NAND) || defined(CONFIG_CMD_ONENAND)
+	const u32 *gpmc_config = NULL;
+	u32 base = 0;
+	u32 size = 0;
+#endif
+	/* global settings */
+	writel(0x00000008, &gpmc_cfg->sysconfig);
+	writel(0x00000100, &gpmc_cfg->irqstatus);
+	writel(0x00000200, &gpmc_cfg->irqenable);
+	writel(0x00000012, &gpmc_cfg->config);
+	/*
+	 * Disable the GPMC0 config set by ROM code
+	 */
+	writel(0, &gpmc_cfg->cs[0].config7);
+	sdelay(1000);
+
+#if defined(CONFIG_CMD_NAND)	/* CS 0 */
+	gpmc_config = gpmc_m_nand;
+
+	base = PISMO1_NAND_BASE;
+	size = PISMO1_NAND_SIZE;
+	enable_gpmc_cs_config(gpmc_config, &gpmc_cfg->cs[0], base, size);
+#endif
+}
diff --git a/arch/arm/include/asm/arch-am33xx/cpu.h b/arch/arm/include/asm/arch-am33xx/cpu.h
index 6cfbef7..90828e5 100644
--- a/arch/arm/include/asm/arch-am33xx/cpu.h
+++ b/arch/arm/include/asm/arch-am33xx/cpu.h
@@ -60,6 +60,59 @@ 
 
 #ifndef __KERNEL_STRICT_NAMES
 #ifndef __ASSEMBLY__
+struct gpmc_cs {
+	u32 config1;		/* 0x00 */
+	u32 config2;		/* 0x04 */
+	u32 config3;		/* 0x08 */
+	u32 config4;		/* 0x0C */
+	u32 config5;		/* 0x10 */
+	u32 config6;		/* 0x14 */
+	u32 config7;		/* 0x18 */
+	u32 nand_cmd;		/* 0x1C */
+	u32 nand_adr;		/* 0x20 */
+	u32 nand_dat;		/* 0x24 */
+	u8 res[8];		/* blow up to 0x30 byte */
+};
+
+struct bch_res_0_3 {
+	u32 bch_result_x[4];
+};
+
+struct gpmc {
+	u8 res1[0x10];
+	u32 sysconfig;		/* 0x10 */
+	u8 res2[0x4];
+	u32 irqstatus;		/* 0x18 */
+	u32 irqenable;		/* 0x1C */
+	u8 res3[0x20];
+	u32 timeout_control;	/* 0x40 */
+	u8 res4[0xC];
+	u32 config;		/* 0x50 */
+	u32 status;		/* 0x54 */
+	u8 res5[0x8];		/* 0x58 */
+	struct gpmc_cs cs[8];	/* 0x60, 0x90, .. */
+	u8 res6[0x14];		/* 0x1E0 */
+	u32 ecc_config;		/* 0x1F4 */
+	u32 ecc_control;	/* 0x1F8 */
+	u32 ecc_size_config;	/* 0x1FC */
+	u32 ecc1_result;	/* 0x200 */
+	u32 ecc2_result;	/* 0x204 */
+	u32 ecc3_result;	/* 0x208 */
+	u32 ecc4_result;	/* 0x20C */
+	u32 ecc5_result;	/* 0x210 */
+	u32 ecc6_result;	/* 0x214 */
+	u32 ecc7_result;	/* 0x218 */
+	u32 ecc8_result;	/* 0x21C */
+	u32 ecc9_result;	/* 0x220 */
+	u8 res7[12];		/* 0x224 */
+	u32 testmomde_ctrl;	/* 0x230 */
+	u8 res8[12];		/* 0x234 */
+	struct bch_res_0_3 bch_result_0_3[2];	/* 0x240 */
+};
+
+/* Used for board specific gpmc initialization */
+extern struct gpmc *gpmc_cfg;
+
 /* Encapsulating core pll registers */
 struct cm_wkuppll {
 	unsigned int wkclkstctrl;	/* offset 0x00 */
diff --git a/arch/arm/include/asm/arch-am33xx/hardware.h b/arch/arm/include/asm/arch-am33xx/hardware.h
index 62332f2..a7cf66e 100644
--- a/arch/arm/include/asm/arch-am33xx/hardware.h
+++ b/arch/arm/include/asm/arch-am33xx/hardware.h
@@ -79,6 +79,9 @@ 
 #define DDRPHY_0_CONFIG_BASE		(CTRL_BASE + 0x1400)
 #define DDRPHY_CONFIG_BASE		DDRPHY_0_CONFIG_BASE
 
+/* GPMC Base address */
+#define GPMC_BASE			0x50000000
+
 /* CPSW Config space */
 #define AM335X_CPSW_BASE		0x4A100000
 #define AM335X_CPSW_MDIO_BASE		0x4A101000
diff --git a/arch/arm/include/asm/arch-am33xx/mem.h b/arch/arm/include/asm/arch-am33xx/mem.h
new file mode 100644
index 0000000..c6aae1d
--- /dev/null
+++ b/arch/arm/include/asm/arch-am33xx/mem.h
@@ -0,0 +1,174 @@ 
+/*
+ * (C) Copyright 2006-2008
+ * Texas Instruments, <www.ti.com>
+ *
+ * Author
+ *		Mansoor Ahamed <mansoor.ahamed@ti.com>
+ *
+ * Initial Code from:
+ *		Richard Woodruff <r-woodruff2@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _MEM_H_
+#define _MEM_H_
+
+#ifndef __ASSEMBLY__
+enum {
+	STACKED = 0,
+	IP_DDR = 1,
+	COMBO_DDR = 2,
+	IP_SDR = 3,
+};
+#endif /* __ASSEMBLY__ */
+
+#define EARLY_INIT	1
+
+/*
+ * GPMC settings -
+ * Definitions is as per the following format
+ * #define <PART>_GPMC_CONFIG<x> <value>
+ * Where:
+ * PART is the part name e.g. STNOR - Intel Strata Flash
+ * x is GPMC config registers from 1 to 6 (there will be 6 macros)
+ * Value is corresponding value
+ *
+ * For every valid PRCM configuration there should be only one definition of
+ * the same. if values are independent of the board, this definition will be
+ * present in this file if values are dependent on the board, then this should
+ * go into corresponding mem-boardName.h file
+ *
+ * Currently valid part Names are (PART):
+ * STNOR - Intel Strata Flash
+ * SMNAND - Samsung NAND
+ * MPDB - H4 MPDB board
+ * SBNOR - Sibley NOR
+ * MNAND - Micron Large page x16 NAND
+ * ONNAND - Samsung One NAND
+ *
+ * include/configs/file.h contains the defn - for all CS we are interested
+ * #define OMAP34XX_GPMC_CSx PART
+ * #define OMAP34XX_GPMC_CSx_SIZE Size
+ * #define OMAP34XX_GPMC_CSx_MAP Map
+ * Where:
+ * x - CS number
+ * PART - Part Name as defined above
+ * SIZE - how big is the mapping to be
+ *   GPMC_SIZE_128M - 0x8
+ *   GPMC_SIZE_64M  - 0xC
+ *   GPMC_SIZE_32M  - 0xE
+ *   GPMC_SIZE_16M  - 0xF
+ * MAP  - Map this CS to which address(GPMC address space)- Absolute address
+ *   >>24 before being used.
+ */
+#define GPMC_SIZE_256M		0x0
+#define GPMC_SIZE_128M		0x8
+#define GPMC_SIZE_64M		0xC
+#define GPMC_SIZE_32M		0xE
+#define GPMC_SIZE_16M		0xF
+
+#define SMNAND_GPMC_CONFIG1	0x00000800
+#define SMNAND_GPMC_CONFIG2	0x00141400
+#define SMNAND_GPMC_CONFIG3	0x00141400
+#define SMNAND_GPMC_CONFIG4	0x0F010F01
+#define SMNAND_GPMC_CONFIG5	0x010C1414
+#define SMNAND_GPMC_CONFIG6	0x1F0F0A80
+#define SMNAND_GPMC_CONFIG7	0x00000C44
+
+
+#define M_NAND_GPMC_CONFIG1	0x00000800
+#define M_NAND_GPMC_CONFIG2	0x001e1e00
+#define M_NAND_GPMC_CONFIG3	0x001e1e00
+#define M_NAND_GPMC_CONFIG4	0x16051807
+#define M_NAND_GPMC_CONFIG5	0x00151e1e
+#define M_NAND_GPMC_CONFIG6	0x16000f80
+#define M_NAND_GPMC_CONFIG7	0x00000008
+
+#define STNOR_GPMC_CONFIG1	0x3
+#define STNOR_GPMC_CONFIG2	0x00151501
+#define STNOR_GPMC_CONFIG3	0x00060602
+#define STNOR_GPMC_CONFIG4	0x11091109
+#define STNOR_GPMC_CONFIG5	0x01141F1F
+#define STNOR_GPMC_CONFIG6	0x000004c4
+
+#define SIBNOR_GPMC_CONFIG1	0x1200
+#define SIBNOR_GPMC_CONFIG2	0x001f1f00
+#define SIBNOR_GPMC_CONFIG3	0x00080802
+#define SIBNOR_GPMC_CONFIG4	0x1C091C09
+#define SIBNOR_GPMC_CONFIG5	0x01131F1F
+#define SIBNOR_GPMC_CONFIG6	0x1F0F03C2
+
+#define SDPV2_MPDB_GPMC_CONFIG1	0x00611200
+#define SDPV2_MPDB_GPMC_CONFIG2	0x001F1F01
+#define SDPV2_MPDB_GPMC_CONFIG3	0x00080803
+#define SDPV2_MPDB_GPMC_CONFIG4	0x1D091D09
+#define SDPV2_MPDB_GPMC_CONFIG5	0x041D1F1F
+#define SDPV2_MPDB_GPMC_CONFIG6	0x1D0904C4
+
+#define MPDB_GPMC_CONFIG1	0x00011000
+#define MPDB_GPMC_CONFIG2	0x001f1f01
+#define MPDB_GPMC_CONFIG3	0x00080803
+#define MPDB_GPMC_CONFIG4	0x1c0b1c0a
+#define MPDB_GPMC_CONFIG5	0x041f1F1F
+#define MPDB_GPMC_CONFIG6	0x1F0F04C4
+
+#define P2_GPMC_CONFIG1	0x0
+#define P2_GPMC_CONFIG2	0x0
+#define P2_GPMC_CONFIG3	0x0
+#define P2_GPMC_CONFIG4	0x0
+#define P2_GPMC_CONFIG5	0x0
+#define P2_GPMC_CONFIG6	0x0
+
+#define ONENAND_GPMC_CONFIG1	0x00001200
+#define ONENAND_GPMC_CONFIG2	0x000F0F01
+#define ONENAND_GPMC_CONFIG3	0x00030301
+#define ONENAND_GPMC_CONFIG4	0x0F040F04
+#define ONENAND_GPMC_CONFIG5	0x010F1010
+#define ONENAND_GPMC_CONFIG6	0x1F060000
+
+#define NET_GPMC_CONFIG1	0x00001000
+#define NET_GPMC_CONFIG2	0x001e1e01
+#define NET_GPMC_CONFIG3	0x00080300
+#define NET_GPMC_CONFIG4	0x1c091c09
+#define NET_GPMC_CONFIG5	0x04181f1f
+#define NET_GPMC_CONFIG6	0x00000FCF
+#define NET_GPMC_CONFIG7	0x00000f6c
+
+/* max number of GPMC Chip Selects */
+#define GPMC_MAX_CS		8
+/* max number of GPMC regs */
+#define GPMC_MAX_REG		7
+
+#define PISMO1_NOR		1
+#define PISMO1_NAND		2
+#define PISMO2_CS0		3
+#define PISMO2_CS1		4
+#define PISMO1_ONENAND		5
+#define DBG_MPDB		6
+#define PISMO2_NAND_CS0		7
+#define PISMO2_NAND_CS1		8
+
+/* make it readable for the gpmc_init */
+#define PISMO1_NOR_BASE	FLASH_BASE
+#define PISMO1_NAND_BASE	NAND_BASE
+#define PISMO1_NAND_SIZE	GPMC_SIZE_256M
+
+#endif /* endif _MEM_H_ */
+
diff --git a/arch/arm/include/asm/arch-am33xx/omap_gpmc.h b/arch/arm/include/asm/arch-am33xx/omap_gpmc.h
new file mode 100644
index 0000000..3576984
--- /dev/null
+++ b/arch/arm/include/asm/arch-am33xx/omap_gpmc.h
@@ -0,0 +1,130 @@ 
+/*
+ * (C) Copyright 2004-2008 Texas Instruments, <www.ti.com>
+ * Rohit Choraria <rohitkc@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef __ASM_ARCH_OMAP_GPMC_H
+#define __ASM_ARCH_OMAP_GPMC_H
+
+#define GPMC_BUF_EMPTY	0
+#define GPMC_BUF_FULL	1
+
+#define ECCCLEAR	(0x1 << 8)
+#define ECCRESULTREG1	(0x1 << 0)
+#define ECCSIZE512BYTE	0xFF
+#define ECCSIZE1	(ECCSIZE512BYTE << 22)
+#define ECCSIZE0	(ECCSIZE512BYTE << 12)
+#define ECCSIZE0SEL	(0x000 << 0)
+
+/* Generic ECC Layouts */
+/* Large Page x8 NAND device Layout */
+#ifdef GPMC_NAND_ECC_LP_x8_LAYOUT
+#define GPMC_NAND_HW_ECC_LAYOUT {\
+	.eccbytes = 12,\
+	.eccpos = {1, 2, 3, 4, 5, 6, 7, 8,\
+		9, 10, 11, 12},\
+	.oobfree = {\
+		{.offset = 13,\
+		 .length = 51 } } \
+}
+#endif
+
+/* Large Page x16 NAND device Layout */
+#ifdef GPMC_NAND_ECC_LP_x16_LAYOUT
+#define GPMC_NAND_HW_ECC_LAYOUT {\
+	.eccbytes = 12,\
+	.eccpos = {2, 3, 4, 5, 6, 7, 8, 9,\
+		10, 11, 12, 13},\
+	.oobfree = {\
+		{.offset = 14,\
+		 .length = 50 } } \
+}
+#endif
+
+/* Small Page x8 NAND device Layout */
+#ifdef GPMC_NAND_ECC_SP_x8_LAYOUT
+#define GPMC_NAND_HW_ECC_LAYOUT {\
+	.eccbytes = 3,\
+	.eccpos = {1, 2, 3},\
+	.oobfree = {\
+		{.offset = 4,\
+		 .length = 12 } } \
+}
+#endif
+
+/* Small Page x16 NAND device Layout */
+#ifdef GPMC_NAND_ECC_SP_x16_LAYOUT
+#define GPMC_NAND_HW_ECC_LAYOUT {\
+	.eccbytes = 3,\
+	.eccpos = {2, 3, 4},\
+	.oobfree = {\
+		{.offset = 5,\
+		 .length = 11 } } \
+}
+#endif
+
+#define GPMC_NAND_HW_BCH4_ECC_LAYOUT {\
+	.eccbytes = 32,\
+	.eccpos = {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,\
+				16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27,\
+				28, 29, 30, 31, 32, 33},\
+	.oobfree = {\
+		{.offset = 34,\
+		 .length = 30 } } \
+}
+
+#define GPMC_NAND_HW_BCH8_ECC_LAYOUT {\
+	.eccbytes = 56,\
+	.eccpos = {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,\
+				16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27,\
+				28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39,\
+				40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51,\
+				52, 53, 54, 55, 56, 57},\
+	.oobfree = {\
+		{.offset = 58,\
+		 .length = 6 } } \
+}
+
+#define GPMC_NAND_HW_BCH16_ECC_LAYOUT {\
+	.eccbytes = 104,\
+	.eccpos = {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,\
+				16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27,\
+				28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39,\
+				40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51,\
+				52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63,\
+				64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75,\
+				76, 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87,\
+				88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99,\
+				100, 101, 102, 103, 104, 105},\
+	.oobfree = {\
+		{.offset = 106,\
+		 .length = 8 } } \
+}
+
+/* GPMC CS configuration for an SMSC LAN9221 ethernet controller */
+#define NET_LAN9221_GPMC_CONFIG1    0x00001000
+#define NET_LAN9221_GPMC_CONFIG2    0x00060700
+#define NET_LAN9221_GPMC_CONFIG3    0x00020201
+#define NET_LAN9221_GPMC_CONFIG4    0x06000700
+#define NET_LAN9221_GPMC_CONFIG5    0x0006090A
+#define NET_LAN9221_GPMC_CONFIG6    0x87030000
+#define NET_LAN9221_GPMC_CONFIG7    0x00000f6c
+
+#endif /* __ASM_ARCH_OMAP_GPMC_H */
diff --git a/arch/arm/include/asm/arch-am33xx/sys_proto.h b/arch/arm/include/asm/arch-am33xx/sys_proto.h
index 819ea65..b07ec18 100644
--- a/arch/arm/include/asm/arch-am33xx/sys_proto.h
+++ b/arch/arm/include/asm/arch-am33xx/sys_proto.h
@@ -60,4 +60,7 @@  void ddr_pll_config(unsigned int ddrpll_M);
 void enable_uart0_pin_mux(void);
 void enable_i2c0_pin_mux(void);
 void enable_board_pin_mux(struct am335x_baseboard_id *header);
+void sdelay(unsigned long);
+void gpmc_init(void);
+void omap_nand_switch_ecc(int);
 #endif