From patchwork Tue Oct 30 22:47:37 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ilya Yanok X-Patchwork-Id: 195639 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id DCE9A2C0081 for ; Wed, 31 Oct 2012 09:48:23 +1100 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 9558B4A37D; Tue, 30 Oct 2012 23:48:19 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id cj50gqp5ef0n; Tue, 30 Oct 2012 23:48:19 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id B28E04A34B; Tue, 30 Oct 2012 23:48:08 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id CA48D4A372 for ; Tue, 30 Oct 2012 23:47:56 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 8GtLj8K-GmqZ for ; Tue, 30 Oct 2012 23:47:54 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail-ea0-f172.google.com (mail-ea0-f172.google.com [209.85.215.172]) by theia.denx.de (Postfix) with ESMTPS id 9B1E34A1CF for ; Tue, 30 Oct 2012 23:47:52 +0100 (CET) Received: by mail-ea0-f172.google.com with SMTP id k13so347313eaa.3 for ; Tue, 30 Oct 2012 15:47:52 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references :x-gm-message-state; bh=Wmzrh1JYVskR7OhOvFLvBGkcMlexARy3zrMpKDocWcI=; b=A4Vofms29rPHVgnw7tGp8xmKkLT6lBZYA5ZlIijq4lTccB0KxCuuitGSXCNfkCR3+e EMmYUQTiWrI2Z3uFb6B+auql/zjxt7mUmdHa4XzH7uhpaQpLHuZF65u24hDflnjk/ChA J9yq6faOG5g2BF2pM51Iv9iDk7DLTh4uhRXp4ZHnhutMyZYpKKkLuv9PrtB5yVQbZlXu kpy7i6YgtDtfVT6JtRSQU3YSVUNGezrzQL5sn3gGjR5xMo4LXQbsDfhDmZ+BiHounK8A wbMMhgpQNRojVqJONJDqwpyG7OT3EtVXiUV2PwWDH/pdnwYc4LtcyoBtUlg0xWN4G3Ra qZpg== Received: by 10.14.193.136 with SMTP id k8mr78260608een.30.1351637272253; Tue, 30 Oct 2012 15:47:52 -0700 (PDT) Received: from chekhov.mobile.usilu.net (nat184.lu.usi.ch. [195.176.178.184]) by mx.google.com with ESMTPS id a44sm4257390eeo.7.2012.10.30.15.47.51 (version=SSLv3 cipher=OTHER); Tue, 30 Oct 2012 15:47:51 -0700 (PDT) From: Ilya Yanok To: u-boot@lists.denx.de, Tom Rini , Scott Wood Date: Tue, 30 Oct 2012 23:47:37 +0100 Message-Id: <1351637263-17464-3-git-send-email-ilya.yanok@cogentembedded.com> X-Mailer: git-send-email 1.7.10.2 (Apple Git-33) In-Reply-To: <1351637263-17464-1-git-send-email-ilya.yanok@cogentembedded.com> References: <1351637263-17464-1-git-send-email-ilya.yanok@cogentembedded.com> X-Gm-Message-State: ALoCoQkSYqcnqbAn2GQ/6EF0Ia899290L8Z1LRN1bwTuhUe0r5z+43Fli4IAUh/yp6bcXTDDAgjh Cc: Ilya Yanok Subject: [U-Boot] [PATCH v1 2/8] am335x_evm: add nand pinmux definition X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de Add NAND pins mux settings for AM335X devices. Enable NAND pins for AM335X EVM board. Signed-off-by: Ilya Yanok --- board/ti/am335x/mux.c | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/board/ti/am335x/mux.c b/board/ti/am335x/mux.c index 80becd5..a46c680 100644 --- a/board/ti/am335x/mux.c +++ b/board/ti/am335x/mux.c @@ -362,6 +362,27 @@ static struct module_pin_mux mii1_pin_mux[] = { {-1}, }; +#ifdef CONFIG_NAND_OMAP_GPMC +static struct module_pin_mux nand_pin_mux[] = { + {OFFSET(gpmc_ad0), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD0 */ + {OFFSET(gpmc_ad1), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD1 */ + {OFFSET(gpmc_ad2), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD2 */ + {OFFSET(gpmc_ad3), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD3 */ + {OFFSET(gpmc_ad4), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD4 */ + {OFFSET(gpmc_ad5), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD5 */ + {OFFSET(gpmc_ad6), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD6 */ + {OFFSET(gpmc_ad7), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD7 */ + {OFFSET(gpmc_wait0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* NAND WAIT */ + {OFFSET(gpmc_wpn), (MODE(7) | PULLUP_EN | RXACTIVE)}, /* NAND_WPN */ + {OFFSET(gpmc_csn0), (MODE(0) | PULLUDEN)}, /* NAND_CS0 */ + {OFFSET(gpmc_advn_ale), (MODE(0) | PULLUDEN)}, /* NAND_ADV_ALE */ + {OFFSET(gpmc_oen_ren), (MODE(0) | PULLUDEN)}, /* NAND_OE */ + {OFFSET(gpmc_wen), (MODE(0) | PULLUDEN)}, /* NAND_WEN */ + {OFFSET(gpmc_be0n_cle), (MODE(0) | PULLUDEN)}, /* NAND_BE_CLE */ + {-1}, +}; +#endif + /* * Configure the pin mux for the module */ @@ -435,11 +456,16 @@ void enable_board_pin_mux(struct am335x_baseboard_id *header) unsigned short profile = detect_daughter_board_profile(); configure_module_pin_mux(rgmii1_pin_mux); configure_module_pin_mux(mmc0_pin_mux); +#ifdef CONFIG_NAND_OMAP_GPMC + configure_module_pin_mux(nand_pin_mux); +#endif /* In profile #2 i2c1 and spi0 conflict. */ if (profile & ~PROFILE_2) configure_module_pin_mux(i2c1_pin_mux); else if (profile == PROFILE_2) { +#ifndef CONFIG_NAND_OMAP_GPMC configure_module_pin_mux(mmc1_pin_mux); +#endif configure_module_pin_mux(spi0_pin_mux); } } else if (!strncmp(header->name, "A335X_SK", HDR_NAME_LEN)) {