From patchwork Tue Oct 30 16:56:57 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?q?=C5=81ukasz_Majewski?= X-Patchwork-Id: 195540 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 4CBD42C007A for ; Wed, 31 Oct 2012 03:58:45 +1100 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 080ED4A24A; Tue, 30 Oct 2012 17:58:28 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id Xs1vc5lV+gz0; Tue, 30 Oct 2012 17:58:27 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 3621E4A22E; Tue, 30 Oct 2012 17:58:06 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 6F90D4A20D for ; Tue, 30 Oct 2012 17:57:49 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id TlFaVidTtbbi for ; Tue, 30 Oct 2012 17:57:47 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mailout4.samsung.com (mailout4.samsung.com [203.254.224.34]) by theia.denx.de (Postfix) with ESMTP id 595014A1FD for ; Tue, 30 Oct 2012 17:57:46 +0100 (CET) Received: from epcpsbgm1.samsung.com (epcpsbgm1 [203.254.230.26]) by mailout4.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0MCP00FZUTRCMBT0@mailout4.samsung.com> for u-boot@lists.denx.de; Wed, 31 Oct 2012 01:57:42 +0900 (KST) X-AuditID: cbfee61a-b7fa66d0000004cf-c1-509007067a9b Received: from epmmp2 ( [203.254.227.17]) by epcpsbgm1.samsung.com (EPCPMTA) with SMTP id 8C.31.01231.60700905; Wed, 31 Oct 2012 01:57:42 +0900 (KST) Received: from mcdsrvbld02.digital.local ([106.116.37.23]) by mmp2.samsung.com (Oracle Communications Messaging Server 7u4-24.01 (7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0MCP009BOTRPFA00@mmp2.samsung.com> for u-boot@lists.denx.de; Wed, 31 Oct 2012 01:57:42 +0900 (KST) From: Lukasz Majewski To: u-boot@lists.denx.de Date: Tue, 30 Oct 2012 17:56:57 +0100 Message-id: <1351616239-21079-3-git-send-email-l.majewski@samsung.com> X-Mailer: git-send-email 1.7.10 In-reply-to: <1351616239-21079-1-git-send-email-l.majewski@samsung.com> References: <1351616239-21079-1-git-send-email-l.majewski@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrIJMWRmVeSWpSXmKPExsVy+t9jQV029gkBBlNPaFu83dvJ7sDocfbO DsYAxigum5TUnMyy1CJ9uwSujBm3XrMVbJCuONL8iK2BcYFoFyMnh4SAiURH00ZGCFtM4sK9 9WxdjFwcQgLTGSW2X9rPCuEsZpK4+eYjE0gVm4CexOe7T8FsEQEJiV/9VxlBipgFdjBKNJ88 C9TOwSEsECfxdY8biMkioCpxZ4YHSDmvgJtE+6LPUMvkJZ7e7wOr5hRwl9i2Oh8kLARU8vr7 NfYJjLwLGBlWMYqmFiQXFCel5xrqFSfmFpfmpesl5+duYgR7/JnUDsaVDRaHGAU4GJV4eA3/ 9QcIsSaWFVfmHmKU4GBWEuFd8hsoxJuSWFmVWpQfX1Sak1p8iFGag0VJnLfZIyVASCA9sSQ1 OzW1ILUIJsvEwSnVwBg+afexkF81TOW/toq93rBV/uGio7aV02xE38zdoL8tVTaHqcO3O9Vg 3s7vwZ5LNbdrxc49lXLbyNPbUnzu52czAm7vjimVYHv3bHbxg2kHU3yT9t1fJ3j/0c1igafh 6zN0BVWFZifUzzy05cUfhodFXZk36lJMnTTFjermMqS9SnwQqFDne0iJpTgj0VCLuag4EQA5 /kdT9AEAAA== Cc: Tom Rini , Kyungmin Park Subject: [U-Boot] [PATCH v4 02/24] pmic:i2c: Add I2C sensor byte order (big/little) to PMIC framework X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de Since the pmic_reg_read is the u32 value, the order in which bytes are placed to form u32 value is important. Support for big and little sensor endianess is added. Moreover calls to [leXX|beXX]_to_cpu have been added to support little and big endian SoCs. Signed-off-by: Lukasz Majewski Signed-off-by: Kyungmin Park --- Changes for v2: - Move byte_order variable to struct pmic Changes for v3: - New names for sensor endianess (more readable) - Support for SoCs with different endianess Changes for v4: - None --- drivers/misc/pmic_i2c.c | 38 +++++++++++++++++++++++++++++--------- include/pmic.h | 2 ++ 2 files changed, 31 insertions(+), 9 deletions(-) diff --git a/drivers/misc/pmic_i2c.c b/drivers/misc/pmic_i2c.c index e74c372..1064bfe 100644 --- a/drivers/misc/pmic_i2c.c +++ b/drivers/misc/pmic_i2c.c @@ -30,6 +30,7 @@ #include #include #include +#include int pmic_reg_write(struct pmic *p, u32 reg, u32 val) { @@ -40,16 +41,27 @@ int pmic_reg_write(struct pmic *p, u32 reg, u32 val) switch (pmic_i2c_tx_num) { case 3: - buf[0] = (val >> 16) & 0xff; - buf[1] = (val >> 8) & 0xff; - buf[2] = val & 0xff; + if (p->sensor_byte_order == PMIC_SENSOR_BYTE_ORDER_BIG) { + buf[2] = (cpu_to_le32(val) >> 16) & 0xff; + buf[1] = (cpu_to_le32(val) >> 8) & 0xff; + buf[0] = cpu_to_le32(val) & 0xff; + } else { + buf[0] = (cpu_to_le32(val) >> 16) & 0xff; + buf[1] = (cpu_to_le32(val) >> 8) & 0xff; + buf[2] = cpu_to_le32(val) & 0xff; + } break; case 2: - buf[0] = (val >> 8) & 0xff; - buf[1] = val & 0xff; + if (p->sensor_byte_order == PMIC_SENSOR_BYTE_ORDER_BIG) { + buf[1] = (cpu_to_le32(val) >> 8) & 0xff; + buf[0] = cpu_to_le32(val) & 0xff; + } else { + buf[0] = (cpu_to_le32(val) >> 8) & 0xff; + buf[1] = cpu_to_le32(val) & 0xff; + } break; case 1: - buf[0] = val & 0xff; + buf[0] = cpu_to_le32(val) & 0xff; break; default: printf("%s: invalid tx_num: %d", __func__, pmic_i2c_tx_num); @@ -75,13 +87,21 @@ int pmic_reg_read(struct pmic *p, u32 reg, u32 *val) switch (pmic_i2c_tx_num) { case 3: - ret_val = buf[0] << 16 | buf[1] << 8 | buf[2]; + if (p->sensor_byte_order == PMIC_SENSOR_BYTE_ORDER_BIG) + ret_val = le32_to_cpu(buf[2] << 16 + | buf[1] << 8 | buf[0]); + else + ret_val = le32_to_cpu(buf[0] << 16 | + buf[1] << 8 | buf[2]); break; case 2: - ret_val = buf[0] << 8 | buf[1]; + if (p->sensor_byte_order == PMIC_SENSOR_BYTE_ORDER_BIG) + ret_val = le32_to_cpu(buf[1] << 8 | buf[0]); + else + ret_val = le32_to_cpu(buf[0] << 8 | buf[1]); break; case 1: - ret_val = buf[0]; + ret_val = le32_to_cpu(buf[0]); break; default: printf("%s: invalid tx_num: %d", __func__, pmic_i2c_tx_num); diff --git a/include/pmic.h b/include/pmic.h index 6a05b40..1a2db05 100644 --- a/include/pmic.h +++ b/include/pmic.h @@ -27,6 +27,7 @@ enum { PMIC_I2C, PMIC_SPI, }; enum { I2C_PMIC, I2C_NUM, }; enum { PMIC_READ, PMIC_WRITE, }; +enum { PMIC_SENSOR_BYTE_ORDER_LITTLE, PMIC_SENSOR_BYTE_ORDER_BIG, }; struct p_i2c { unsigned char addr; @@ -47,6 +48,7 @@ struct pmic { const char *name; unsigned char bus; unsigned char interface; + unsigned char sensor_byte_order; unsigned char number_of_regs; union hw { struct p_i2c i2c;