diff --git a/arch/powerpc/cpu/mpc85xx/start.S 
b/arch/powerpc/cpu/mpc85xx/start.S
index ac17f9d..c00db4a 100644
--- a/arch/powerpc/cpu/mpc85xx/start.S
+++ b/arch/powerpc/cpu/mpc85xx/start.S
@@ -282,7 +282,7 @@ l2_disabled:
         isync
         .endm

-#if defined(CONFIG_SYS_PPC_E500_DEBUG_TLB) && !defined(CONFIG_NAND_SPL)
+#if defined(CONFIG_SYS_PPC_E500_DEBUG_TLB) && !defined(MINIMAL_SPL)
  /*
   * TLB entry for debuggging in AS1
   * Create temporary TLB entry in AS0 to handle debug exception
@@ -309,16 +309,6 @@ l2_disabled:
                 CONFIG_SYS_MONITOR_BASE, MAS2_I|MAS2_G, \
                 CONFIG_SYS_PBI_FLASH_WINDOW, MAS3_SX|MAS3_SW|MAS3_SR, \
                 0, r6
-#else
-/*
- * TLB entry is created for IVPR + IVOR15 to map on valid OP code address
- * because "nexti" will resize TLB to 4K
- */
-       create_tlb1_entry CONFIG_SYS_PPC_E500_DEBUG_TLB, \
-               0, BOOKE_PAGESZ_256K, \
-               CONFIG_SYS_MONITOR_BASE, MAS2_I, \
-               CONFIG_SYS_MONITOR_BASE, MAS3_SX|MAS3_SW|MAS3_SR, \
-               0, r6
  #endif
  #endif

@@ -520,6 +510,24 @@ nexti:     mflr    r1              /* R1 = our PC */
         msync
         tlbwe

+#if defined(CONFIG_SYS_PPC_E500_DEBUG_TLB) && !defined(MINIMAL_SPL)\
+   && defined(CONFIG_SYS_RAMBOOT)
+/*
+ * TLB entry for debuggging in AS1
+ * Create temporary TLB entry in AS0 to handle debug exception
+ * As on debug exception MSR is cleared i.e. Address space is changed
+ * to 0. A TLB entry (in AS0) is required to handle debug exception 
generated
+ * in AS1.
+ * TLB entry is created for IVPR + IVOR15 to map on valid OP code address
+ * because "nexti" has resized  execution TLB entry to 4K
+ */
+       create_tlb1_entry CONFIG_SYS_PPC_E500_DEBUG_TLB, \
+               0, BOOKE_PAGESZ_256K, \
+               CONFIG_SYS_MONITOR_BASE & 0xfffc0000, MAS2_I, \
+               CONFIG_SYS_MONITOR_BASE & 0xfffc0000, 
MAS3_SX|MAS3_SW|MAS3_SR, \
+               0, r6
+#endif
+
  /*