From patchwork Tue Oct 30 09:26:16 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Prabhakar Kushwaha X-Patchwork-Id: 195347 X-Patchwork-Delegate: afleming@freescale.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 9E83A2C00A7 for ; Tue, 30 Oct 2012 20:28:37 +1100 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id E8D964A12F; Tue, 30 Oct 2012 10:28:35 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id ytcHubGvVVMS; Tue, 30 Oct 2012 10:28:35 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id A9BBA4A161; Tue, 30 Oct 2012 10:28:32 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 39F284A161 for ; Tue, 30 Oct 2012 10:28:31 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id GzjK5hHPswsG for ; Tue, 30 Oct 2012 10:28:30 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from am1outboundpool.messaging.microsoft.com (am1ehsobe001.messaging.microsoft.com [213.199.154.204]) by theia.denx.de (Postfix) with ESMTPS id E99FE4A12F for ; Tue, 30 Oct 2012 10:28:28 +0100 (CET) Received: from mail61-am1-R.bigfish.com (10.3.201.227) by AM1EHSOBE003.bigfish.com (10.3.204.23) with Microsoft SMTP Server id 14.1.225.23; Tue, 30 Oct 2012 09:28:27 +0000 Received: from mail61-am1 (localhost [127.0.0.1]) by mail61-am1-R.bigfish.com (Postfix) with ESMTP id 6B29460229 for ; Tue, 30 Oct 2012 09:28:27 +0000 (UTC) X-Forefront-Antispam-Report: CIP:70.37.183.190; KIP:(null); UIP:(null); IPV:NLI; H:mail.freescale.net; RD:none; EFVD:NLI X-SpamScore: -4 X-BigFish: VS-4(zzbb2dI98dI9371I1432Izz1202h1d1ah1d2ahzz8275bhz2dh2a8h668h839hd25he5bhf0ah1288h12a5h12a9h12bdh137ah13b6h1441h1504h1537h153bh1155h) Received: from mail61-am1 (localhost.localdomain [127.0.0.1]) by mail61-am1 (MessageSwitch) id 1351589304970633_379; Tue, 30 Oct 2012 09:28:24 +0000 (UTC) Received: from AM1EHSMHS007.bigfish.com (unknown [10.3.201.248]) by mail61-am1.bigfish.com (Postfix) with ESMTP id EA27A40006C for ; Tue, 30 Oct 2012 09:28:24 +0000 (UTC) Received: from mail.freescale.net (70.37.183.190) by AM1EHSMHS007.bigfish.com (10.3.207.107) with Microsoft SMTP Server (TLS) id 14.1.225.23; Tue, 30 Oct 2012 09:28:17 +0000 Received: from tx30smr01.am.freescale.net (10.81.153.31) by 039-SN1MMR1-001.039d.mgd.msft.net (10.84.1.13) with Microsoft SMTP Server (TLS) id 14.2.318.3; Tue, 30 Oct 2012 09:26:35 +0000 Received: from [10.0.2.15] (B32579-02-010232132029.ap.freescale.net [10.232.132.29]) by tx30smr01.am.freescale.net (8.14.3/8.14.0) with ESMTP id q9U9QH91000677; Tue, 30 Oct 2012 02:26:33 -0700 Message-ID: <508F9D38.5060709@freescale.com> Date: Tue, 30 Oct 2012 14:56:16 +0530 From: Prabhakar Kushwaha User-Agent: Mozilla/5.0 (X11; Linux i686; rv:16.0) Gecko/20121028 Thunderbird/16.0.2 MIME-Version: 1.0 To: Scott Wood References: <1348272087-29608-1-git-send-email-scottwood@freescale.com> <1351562710-6237-1-git-send-email-scottwood@freescale.com> <1351562710-6237-4-git-send-email-scottwood@freescale.com> In-Reply-To: <1351562710-6237-4-git-send-email-scottwood@freescale.com> X-OriginatorOrg: freescale.com Cc: u-boot@lists.denx.de, Andy Fleming Subject: Re: [U-Boot] [PATCH v2 03/22] powerpc/mpc85xx: move debug tlb entry after TLB is in known state X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de On 10/30/2012 07:34 AM, Scott Wood wrote: > Previously, in many if not all configs we were creating overlapping TLB entries > which is illegal. This caused a crash during boot when moving p2020rdb NAND SPL > into L2 SRAM. > > Signed-off-by: Scott Wood > Cc: Prabhakar Kushwaha > Cc: Andy Fleming > -- > Prabhakar, please test that debug still works. > During RAMBOOT, both "temporary debug TLB entry" and "execution TLB entry" is same. So moving "temporary debug TLB entry" creation after "execution TLB entry resizing" will make sure of debugging during NAND ramboot, SPI and SD boot. But for NOR & NAND SPL there is a problem because boot-up TLB as 0xfffff000 and temporary debug TLB as 0xEFF80000. So we require to create temporary TLB entry to support early debugging. I will suggest to split the CONFIG_SYS_PPC_E500_DEBUG_TLB define into 2 parts. 1) For NOR , NAND spl debugging 2) For RAMBoot: After resizing of execution TLB I made following changes in the patch and tested across P1010RDB for NOR, NAND-SPL, NAND Ramboot and SPI boot debugging. Please note I used only this patch after replacing MINIMAL_SPL with CONFIG_NAND_SPL. * Clear out any other TLB entries that may exist, to avoid conflicts. * Our TLB entry is in r14. @@ -534,7 +542,7 @@ nexti: mflr r1 /* R1 = our PC */ li r3, 0 mtspr MAS1, r3 1: cmpw r3, r14 -#if defined(CONFIG_SYS_PPC_E500_DEBUG_TLB) && !defined(CONFIG_NAND_SPL) +#if defined(CONFIG_SYS_PPC_E500_DEBUG_TLB) && !defined(MINIMAL_SPL) cmpwi cr1, r3, CONFIG_SYS_PPC_E500_DEBUG_TLB cror cr0*4+eq, cr0*4+eq, cr1*4+eq #endif Regards, Prabhakar diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S index ac17f9d..c00db4a 100644 --- a/arch/powerpc/cpu/mpc85xx/start.S +++ b/arch/powerpc/cpu/mpc85xx/start.S @@ -282,7 +282,7 @@ l2_disabled: isync .endm -#if defined(CONFIG_SYS_PPC_E500_DEBUG_TLB) && !defined(CONFIG_NAND_SPL) +#if defined(CONFIG_SYS_PPC_E500_DEBUG_TLB) && !defined(MINIMAL_SPL) /* * TLB entry for debuggging in AS1 * Create temporary TLB entry in AS0 to handle debug exception @@ -309,16 +309,6 @@ l2_disabled: CONFIG_SYS_MONITOR_BASE, MAS2_I|MAS2_G, \ CONFIG_SYS_PBI_FLASH_WINDOW, MAS3_SX|MAS3_SW|MAS3_SR, \ 0, r6 -#else -/* - * TLB entry is created for IVPR + IVOR15 to map on valid OP code address - * because "nexti" will resize TLB to 4K - */ - create_tlb1_entry CONFIG_SYS_PPC_E500_DEBUG_TLB, \ - 0, BOOKE_PAGESZ_256K, \ - CONFIG_SYS_MONITOR_BASE, MAS2_I, \ - CONFIG_SYS_MONITOR_BASE, MAS3_SX|MAS3_SW|MAS3_SR, \ - 0, r6 #endif #endif @@ -520,6 +510,24 @@ nexti: mflr r1 /* R1 = our PC */ msync tlbwe +#if defined(CONFIG_SYS_PPC_E500_DEBUG_TLB) && !defined(MINIMAL_SPL)\ + && defined(CONFIG_SYS_RAMBOOT) +/* + * TLB entry for debuggging in AS1 + * Create temporary TLB entry in AS0 to handle debug exception + * As on debug exception MSR is cleared i.e. Address space is changed + * to 0. A TLB entry (in AS0) is required to handle debug exception generated + * in AS1. + * TLB entry is created for IVPR + IVOR15 to map on valid OP code address + * because "nexti" has resized execution TLB entry to 4K + */ + create_tlb1_entry CONFIG_SYS_PPC_E500_DEBUG_TLB, \ + 0, BOOKE_PAGESZ_256K, \ + CONFIG_SYS_MONITOR_BASE & 0xfffc0000, MAS2_I, \ + CONFIG_SYS_MONITOR_BASE & 0xfffc0000, MAS3_SX|MAS3_SW|MAS3_SR, \ + 0, r6 +#endif + /*