From patchwork Tue Oct 30 03:25:01 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Subject: [05/16] pseries: Use #define for XICS base irq number Date: Mon, 29 Oct 2012 17:25:01 -0000 From: David Gibson X-Patchwork-Id: 195278 Message-Id: <1351567512-17278-6-git-send-email-david@gibson.dropbear.id.au> To: agraf@suse.de Cc: Michael Ellerman , qemu-ppc@nongnu.org, qemu-devel@nongnu.org, David Gibson From: Ben Herrenschmidt Currently the lowest "real" irq number for the XICS irq controller (as opposed to numbers reserved for IPIs and other special purposes) is hard coded as 16 in two places - in xics_system_init() and in spapr.c. As well as being generally bad practice, we're going to need to change this number soon to fit in with the in-kernel XICS implementation. This patch adds a #define for this number to avoid future breakage. Signed-off-by: Michael Ellerman Signed-off-by: Ben Herrenschmidt Signed-off-by: David Gibson --- hw/spapr.c | 2 +- hw/xics.c | 2 +- hw/xics.h | 1 + 3 files changed, 3 insertions(+), 2 deletions(-) diff --git a/hw/spapr.c b/hw/spapr.c index 8d0ad3c..81c49dc 100644 --- a/hw/spapr.c +++ b/hw/spapr.c @@ -799,7 +799,7 @@ static void ppc_spapr_init(QEMUMachineInitArgs *args) /* Set up Interrupt Controller */ spapr->icp = xics_system_init(XICS_IRQS); - spapr->next_irq = 16; + spapr->next_irq = XICS_IRQ_BASE; /* Set up EPOW events infrastructure */ spapr_events_init(spapr); diff --git a/hw/xics.c b/hw/xics.c index 7a899dd..db01fe3 100644 --- a/hw/xics.c +++ b/hw/xics.c @@ -548,7 +548,7 @@ struct icp_state *xics_system_init(int nr_irqs) ics = g_malloc0(sizeof(*ics)); ics->nr_irqs = nr_irqs; - ics->offset = 16; + ics->offset = XICS_IRQ_BASE; ics->irqs = g_malloc0(nr_irqs * sizeof(struct ics_irq_state)); icp->ics = ics; diff --git a/hw/xics.h b/hw/xics.h index 6817268..c3bf008 100644 --- a/hw/xics.h +++ b/hw/xics.h @@ -28,6 +28,7 @@ #define __XICS_H__ #define XICS_IPI 0x2 +#define XICS_IRQ_BASE 0x10 struct icp_state;