From patchwork Tue Oct 30 02:05:01 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Scott Wood X-Patchwork-Id: 195256 X-Patchwork-Delegate: scottwood@freescale.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id B83482C009A for ; Tue, 30 Oct 2012 13:20:57 +1100 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id DE6384A1DD; Tue, 30 Oct 2012 03:20:53 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id QYZ1jvIQlJPA; Tue, 30 Oct 2012 03:20:53 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 1795B4A1DF; Tue, 30 Oct 2012 03:20:45 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id C5C4F4A130 for ; Tue, 30 Oct 2012 03:20:42 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id aqDKi2DetDaC for ; Tue, 30 Oct 2012 03:20:41 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from ch1outboundpool.messaging.microsoft.com (ch1ehsobe003.messaging.microsoft.com [216.32.181.183]) by theia.denx.de (Postfix) with ESMTPS id A3E604A19C for ; Tue, 30 Oct 2012 03:20:36 +0100 (CET) Received: from mail60-ch1-R.bigfish.com (10.43.68.235) by CH1EHSOBE003.bigfish.com (10.43.70.53) with Microsoft SMTP Server id 14.1.225.23; Tue, 30 Oct 2012 02:05:25 +0000 Received: from mail60-ch1 (localhost [127.0.0.1]) by mail60-ch1-R.bigfish.com (Postfix) with ESMTP id BEAEF460207 for ; Tue, 30 Oct 2012 02:05:25 +0000 (UTC) X-Forefront-Antispam-Report: CIP:70.37.183.190; KIP:(null); UIP:(null); IPV:NLI; H:mail.freescale.net; RD:none; EFVD:NLI X-SpamScore: 3 X-BigFish: VS3(zzc8kzz1202h1d1ah1d2ahzz8275bhz2dh2a8h668h839hd24he5bhf0ah1288h12a5h12a9h12bdh12e5h137ah139eh13b6h1441h1504h1537h1155h) Received: from mail60-ch1 (localhost.localdomain [127.0.0.1]) by mail60-ch1 (MessageSwitch) id 1351562723886013_13215; Tue, 30 Oct 2012 02:05:23 +0000 (UTC) Received: from CH1EHSMHS020.bigfish.com (snatpool1.int.messaging.microsoft.com [10.43.68.249]) by mail60-ch1.bigfish.com (Postfix) with ESMTP id D5C583A0070 for ; Tue, 30 Oct 2012 02:05:23 +0000 (UTC) Received: from mail.freescale.net (70.37.183.190) by CH1EHSMHS020.bigfish.com (10.43.70.20) with Microsoft SMTP Server (TLS) id 14.1.225.23; Tue, 30 Oct 2012 02:05:23 +0000 Received: from tx30smr01.am.freescale.net (10.81.153.31) by 039-SN1MMR1-003.039d.mgd.msft.net (10.84.1.16) with Microsoft SMTP Server (TLS) id 14.2.318.3; Tue, 30 Oct 2012 02:05:22 +0000 Received: from snotra.am.freescale.net ([10.214.83.118]) by tx30smr01.am.freescale.net (8.14.3/8.14.0) with ESMTP id q9U25Bpl000467; Mon, 29 Oct 2012 19:05:21 -0700 From: Scott Wood To: Date: Mon, 29 Oct 2012 21:05:01 -0500 Message-ID: <1351562710-6237-14-git-send-email-scottwood@freescale.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1351562710-6237-1-git-send-email-scottwood@freescale.com> References: <1348272087-29608-1-git-send-email-scottwood@freescale.com> <1351562710-6237-1-git-send-email-scottwood@freescale.com> MIME-Version: 1.0 X-OriginatorOrg: freescale.com Cc: Scott Wood , Andy Fleming Subject: [U-Boot] [PATCH v2 13/22] spl/mpc85xx: rename cpu_init_nand.c to spl_minimal.c X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de There is nothing really NAND-specific about this file. Signed-off-by: Scott Wood Cc: Andy Fleming --- arch/powerpc/cpu/mpc85xx/cpu_init_nand.c | 59 ------------------------ arch/powerpc/cpu/mpc85xx/spl_minimal.c | 59 ++++++++++++++++++++++++ nand_spl/board/freescale/mpc8536ds/Makefile | 8 ++-- nand_spl/board/freescale/mpc8569mds/Makefile | 8 ++-- nand_spl/board/freescale/mpc8572ds/Makefile | 8 ++-- nand_spl/board/freescale/p1010rdb/Makefile | 8 ++-- nand_spl/board/freescale/p1023rds/Makefile | 8 ++-- nand_spl/board/freescale/p1_p2_rdb/Makefile | 8 ++-- nand_spl/board/freescale/p1_p2_rdb_pc/Makefile | 8 ++-- 9 files changed, 87 insertions(+), 87 deletions(-) delete mode 100644 arch/powerpc/cpu/mpc85xx/cpu_init_nand.c create mode 100644 arch/powerpc/cpu/mpc85xx/spl_minimal.c diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init_nand.c b/arch/powerpc/cpu/mpc85xx/cpu_init_nand.c deleted file mode 100644 index 0589497..0000000 --- a/arch/powerpc/cpu/mpc85xx/cpu_init_nand.c +++ /dev/null @@ -1,59 +0,0 @@ -/* - * Copyright 2009 Freescale Semiconductor, Inc. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -void cpu_init_f(void) -{ -#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR) - ccsr_l2cache_t *l2cache = (void *)CONFIG_SYS_MPC85xx_L2_ADDR; - - out_be32(&l2cache->l2srbar0, CONFIG_SYS_INIT_L2_ADDR); - - /* set MBECCDIS=1, SBECCDIS=1 */ - out_be32(&l2cache->l2errdis, - (MPC85xx_L2ERRDIS_MBECC | MPC85xx_L2ERRDIS_SBECC)); - - /* set L2E=1 & L2SRAM=001 */ - out_be32(&l2cache->l2ctl, - (MPC85xx_L2CTL_L2E | MPC85xx_L2CTL_L2SRAM_ENTIRE)); -#endif -} - -#ifndef CONFIG_SYS_FSL_TBCLK_DIV -#define CONFIG_SYS_FSL_TBCLK_DIV 8 -#endif - -void udelay(unsigned long usec) -{ - u32 ticks_per_usec = gd->bus_clk / (CONFIG_SYS_FSL_TBCLK_DIV * 1000000); - u32 ticks = ticks_per_usec * usec; - u32 s = mfspr(SPRN_TBRL); - - while ((mfspr(SPRN_TBRL) - s) < ticks); -} diff --git a/arch/powerpc/cpu/mpc85xx/spl_minimal.c b/arch/powerpc/cpu/mpc85xx/spl_minimal.c new file mode 100644 index 0000000..0589497 --- /dev/null +++ b/arch/powerpc/cpu/mpc85xx/spl_minimal.c @@ -0,0 +1,59 @@ +/* + * Copyright 2009 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +void cpu_init_f(void) +{ +#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR) + ccsr_l2cache_t *l2cache = (void *)CONFIG_SYS_MPC85xx_L2_ADDR; + + out_be32(&l2cache->l2srbar0, CONFIG_SYS_INIT_L2_ADDR); + + /* set MBECCDIS=1, SBECCDIS=1 */ + out_be32(&l2cache->l2errdis, + (MPC85xx_L2ERRDIS_MBECC | MPC85xx_L2ERRDIS_SBECC)); + + /* set L2E=1 & L2SRAM=001 */ + out_be32(&l2cache->l2ctl, + (MPC85xx_L2CTL_L2E | MPC85xx_L2CTL_L2SRAM_ENTIRE)); +#endif +} + +#ifndef CONFIG_SYS_FSL_TBCLK_DIV +#define CONFIG_SYS_FSL_TBCLK_DIV 8 +#endif + +void udelay(unsigned long usec) +{ + u32 ticks_per_usec = gd->bus_clk / (CONFIG_SYS_FSL_TBCLK_DIV * 1000000); + u32 ticks = ticks_per_usec * usec; + u32 s = mfspr(SPRN_TBRL); + + while ((mfspr(SPRN_TBRL) - s) < ticks); +} diff --git a/nand_spl/board/freescale/mpc8536ds/Makefile b/nand_spl/board/freescale/mpc8536ds/Makefile index 707273b..c923557 100644 --- a/nand_spl/board/freescale/mpc8536ds/Makefile +++ b/nand_spl/board/freescale/mpc8536ds/Makefile @@ -39,7 +39,7 @@ AFLAGS += -DCONFIG_NAND_SPL CFLAGS += -DCONFIG_NAND_SPL SOBJS = start.o resetvec.o -COBJS = cache.o cpu_init_early.o cpu_init_nand.o fsl_law.o law.o \ +COBJS = cache.o cpu_init_early.o spl_minimal.o fsl_law.o law.o \ nand_boot.o nand_boot_fsl_elbc.o ns16550.o tlb.o tlb_table.o SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c)) @@ -79,9 +79,9 @@ $(obj)cpu_init_early.c: @rm -f $(obj)cpu_init_early.c ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/cpu_init_early.c $(obj)cpu_init_early.c -$(obj)cpu_init_nand.c: - @rm -f $(obj)cpu_init_nand.c - ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/cpu_init_nand.c $(obj)cpu_init_nand.c +$(obj)spl_minimal.c: + @rm -f $(obj)spl_minimal.c + ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/spl_minimal.c $(obj)spl_minimal.c $(obj)fsl_law.c: @rm -f $(obj)fsl_law.c diff --git a/nand_spl/board/freescale/mpc8569mds/Makefile b/nand_spl/board/freescale/mpc8569mds/Makefile index 707273b..c923557 100644 --- a/nand_spl/board/freescale/mpc8569mds/Makefile +++ b/nand_spl/board/freescale/mpc8569mds/Makefile @@ -39,7 +39,7 @@ AFLAGS += -DCONFIG_NAND_SPL CFLAGS += -DCONFIG_NAND_SPL SOBJS = start.o resetvec.o -COBJS = cache.o cpu_init_early.o cpu_init_nand.o fsl_law.o law.o \ +COBJS = cache.o cpu_init_early.o spl_minimal.o fsl_law.o law.o \ nand_boot.o nand_boot_fsl_elbc.o ns16550.o tlb.o tlb_table.o SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c)) @@ -79,9 +79,9 @@ $(obj)cpu_init_early.c: @rm -f $(obj)cpu_init_early.c ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/cpu_init_early.c $(obj)cpu_init_early.c -$(obj)cpu_init_nand.c: - @rm -f $(obj)cpu_init_nand.c - ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/cpu_init_nand.c $(obj)cpu_init_nand.c +$(obj)spl_minimal.c: + @rm -f $(obj)spl_minimal.c + ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/spl_minimal.c $(obj)spl_minimal.c $(obj)fsl_law.c: @rm -f $(obj)fsl_law.c diff --git a/nand_spl/board/freescale/mpc8572ds/Makefile b/nand_spl/board/freescale/mpc8572ds/Makefile index 707273b..c923557 100644 --- a/nand_spl/board/freescale/mpc8572ds/Makefile +++ b/nand_spl/board/freescale/mpc8572ds/Makefile @@ -39,7 +39,7 @@ AFLAGS += -DCONFIG_NAND_SPL CFLAGS += -DCONFIG_NAND_SPL SOBJS = start.o resetvec.o -COBJS = cache.o cpu_init_early.o cpu_init_nand.o fsl_law.o law.o \ +COBJS = cache.o cpu_init_early.o spl_minimal.o fsl_law.o law.o \ nand_boot.o nand_boot_fsl_elbc.o ns16550.o tlb.o tlb_table.o SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c)) @@ -79,9 +79,9 @@ $(obj)cpu_init_early.c: @rm -f $(obj)cpu_init_early.c ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/cpu_init_early.c $(obj)cpu_init_early.c -$(obj)cpu_init_nand.c: - @rm -f $(obj)cpu_init_nand.c - ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/cpu_init_nand.c $(obj)cpu_init_nand.c +$(obj)spl_minimal.c: + @rm -f $(obj)spl_minimal.c + ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/spl_minimal.c $(obj)spl_minimal.c $(obj)fsl_law.c: @rm -f $(obj)fsl_law.c diff --git a/nand_spl/board/freescale/p1010rdb/Makefile b/nand_spl/board/freescale/p1010rdb/Makefile index 187ff4e..ccff1c7 100644 --- a/nand_spl/board/freescale/p1010rdb/Makefile +++ b/nand_spl/board/freescale/p1010rdb/Makefile @@ -39,7 +39,7 @@ AFLAGS += -DCONFIG_NAND_SPL CFLAGS += -DCONFIG_NAND_SPL SOBJS = start.o resetvec.o ticks.o -COBJS = cache.o cpu_init_early.o cpu_init_nand.o fsl_law.o law.o \ +COBJS = cache.o cpu_init_early.o spl_minimal.o fsl_law.o law.o \ nand_boot.o nand_boot_fsl_ifc.o ns16550.o tlb.o tlb_table.o SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c)) @@ -79,9 +79,9 @@ $(obj)cpu_init_early.c: @rm -f $(obj)cpu_init_early.c ln -sf $(SRCTREE)/$(CPUDIR)/cpu_init_early.c $(obj)cpu_init_early.c -$(obj)cpu_init_nand.c: - @rm -f $(obj)cpu_init_nand.c - ln -sf $(SRCTREE)/$(CPUDIR)/cpu_init_nand.c $(obj)cpu_init_nand.c +$(obj)spl_minimal.c: + @rm -f $(obj)spl_minimal.c + ln -sf $(SRCTREE)/$(CPUDIR)/spl_minimal.c $(obj)spl_minimal.c $(obj)fsl_law.c: @rm -f $(obj)fsl_law.c diff --git a/nand_spl/board/freescale/p1023rds/Makefile b/nand_spl/board/freescale/p1023rds/Makefile index 60fdd90..ffe29c8 100644 --- a/nand_spl/board/freescale/p1023rds/Makefile +++ b/nand_spl/board/freescale/p1023rds/Makefile @@ -34,7 +34,7 @@ AFLAGS += -DCONFIG_NAND_SPL CFLAGS += -DCONFIG_NAND_SPL SOBJS = start.o resetvec.o -COBJS = cache.o cpu_init_early.o cpu_init_nand.o fsl_law.o law.o \ +COBJS = cache.o cpu_init_early.o spl_minimal.o fsl_law.o law.o \ nand_boot.o nand_boot_fsl_elbc.o ns16550.o tlb.o tlb_table.o SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c)) @@ -74,9 +74,9 @@ $(obj)cpu_init_early.c: @rm -f $(obj)cpu_init_early.c ln -sf $(SRCTREE)/$(CPUDIR)/cpu_init_early.c $(obj)cpu_init_early.c -$(obj)cpu_init_nand.c: - @rm -f $(obj)cpu_init_nand.c - ln -sf $(SRCTREE)/$(CPUDIR)/cpu_init_nand.c $(obj)cpu_init_nand.c +$(obj)spl_minimal.c: + @rm -f $(obj)spl_minimal.c + ln -sf $(SRCTREE)/$(CPUDIR)/spl_minimal.c $(obj)spl_minimal.c $(obj)fsl_law.c: @rm -f $(obj)fsl_law.c diff --git a/nand_spl/board/freescale/p1_p2_rdb/Makefile b/nand_spl/board/freescale/p1_p2_rdb/Makefile index 707273b..c923557 100644 --- a/nand_spl/board/freescale/p1_p2_rdb/Makefile +++ b/nand_spl/board/freescale/p1_p2_rdb/Makefile @@ -39,7 +39,7 @@ AFLAGS += -DCONFIG_NAND_SPL CFLAGS += -DCONFIG_NAND_SPL SOBJS = start.o resetvec.o -COBJS = cache.o cpu_init_early.o cpu_init_nand.o fsl_law.o law.o \ +COBJS = cache.o cpu_init_early.o spl_minimal.o fsl_law.o law.o \ nand_boot.o nand_boot_fsl_elbc.o ns16550.o tlb.o tlb_table.o SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c)) @@ -79,9 +79,9 @@ $(obj)cpu_init_early.c: @rm -f $(obj)cpu_init_early.c ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/cpu_init_early.c $(obj)cpu_init_early.c -$(obj)cpu_init_nand.c: - @rm -f $(obj)cpu_init_nand.c - ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/cpu_init_nand.c $(obj)cpu_init_nand.c +$(obj)spl_minimal.c: + @rm -f $(obj)spl_minimal.c + ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/spl_minimal.c $(obj)spl_minimal.c $(obj)fsl_law.c: @rm -f $(obj)fsl_law.c diff --git a/nand_spl/board/freescale/p1_p2_rdb_pc/Makefile b/nand_spl/board/freescale/p1_p2_rdb_pc/Makefile index 98d3ad0..797a800 100644 --- a/nand_spl/board/freescale/p1_p2_rdb_pc/Makefile +++ b/nand_spl/board/freescale/p1_p2_rdb_pc/Makefile @@ -39,7 +39,7 @@ AFLAGS += -DCONFIG_NAND_SPL CFLAGS += -DCONFIG_NAND_SPL SOBJS = start.o resetvec.o -COBJS = cache.o cpu_init_early.o cpu_init_nand.o fsl_law.o law.o \ +COBJS = cache.o cpu_init_early.o spl_minimal.o fsl_law.o law.o \ nand_boot.o nand_boot_fsl_elbc.o ns16550.o tlb.o tlb_table.o SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c)) @@ -79,9 +79,9 @@ $(obj)cpu_init_early.c: @rm -f $(obj)cpu_init_early.c ln -sf $(SRCTREE)/$(CPUDIR)/cpu_init_early.c $(obj)cpu_init_early.c -$(obj)cpu_init_nand.c: - @rm -f $(obj)cpu_init_nand.c - ln -sf $(SRCTREE)/$(CPUDIR)/cpu_init_nand.c $(obj)cpu_init_nand.c +$(obj)spl_minimal.c: + @rm -f $(obj)spl_minimal.c + ln -sf $(SRCTREE)/$(CPUDIR)/spl_minimal.c $(obj)spl_minimal.c $(obj)fsl_law.c: @rm -f $(obj)fsl_law.c