From patchwork Tue Oct 30 02:05:10 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Scott Wood X-Patchwork-Id: 195245 X-Patchwork-Delegate: scottwood@freescale.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id AE5F72C008B for ; Tue, 30 Oct 2012 13:08:50 +1100 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 516444A448; Tue, 30 Oct 2012 03:07:57 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id BVvt2Ay1Lw+d; Tue, 30 Oct 2012 03:07:57 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id C2DF84A3E8; Tue, 30 Oct 2012 03:07:45 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 082FD4A097 for ; Tue, 30 Oct 2012 03:06:12 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id VXYW6kDyv2zL for ; Tue, 30 Oct 2012 03:06:10 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from db3outboundpool.messaging.microsoft.com (db3ehsobe001.messaging.microsoft.com [213.199.154.139]) by theia.denx.de (Postfix) with ESMTPS id A32394A119 for ; Tue, 30 Oct 2012 03:05:34 +0100 (CET) Received: from mail113-db3-R.bigfish.com (10.3.81.232) by DB3EHSOBE010.bigfish.com (10.3.84.30) with Microsoft SMTP Server id 14.1.225.23; Tue, 30 Oct 2012 02:05:33 +0000 Received: from mail113-db3 (localhost [127.0.0.1]) by mail113-db3-R.bigfish.com (Postfix) with ESMTP id 784E144032E for ; Tue, 30 Oct 2012 02:05:33 +0000 (UTC) X-Forefront-Antispam-Report: CIP:70.37.183.190; KIP:(null); UIP:(null); IPV:NLI; H:mail.freescale.net; RD:none; EFVD:NLI X-SpamScore: 0 X-BigFish: VS0(zzzz1202h1d1ah1d2ahzz8275bhz2dh2a8h668h839hd24he5bhf0ah1288h12a5h12a9h12bdh12e5h137ah139eh13b6h1441h1504h1537h1155h) Received: from mail113-db3 (localhost.localdomain [127.0.0.1]) by mail113-db3 (MessageSwitch) id 1351562731412636_2455; Tue, 30 Oct 2012 02:05:31 +0000 (UTC) Received: from DB3EHSMHS009.bigfish.com (unknown [10.3.81.234]) by mail113-db3.bigfish.com (Postfix) with ESMTP id 62409200083 for ; Tue, 30 Oct 2012 02:05:31 +0000 (UTC) Received: from mail.freescale.net (70.37.183.190) by DB3EHSMHS009.bigfish.com (10.3.87.109) with Microsoft SMTP Server (TLS) id 14.1.225.23; Tue, 30 Oct 2012 02:05:30 +0000 Received: from tx30smr01.am.freescale.net (10.81.153.31) by 039-SN1MMR1-002.039d.mgd.msft.net (10.84.1.15) with Microsoft SMTP Server (TLS) id 14.2.318.3; Tue, 30 Oct 2012 02:05:29 +0000 Received: from snotra.am.freescale.net ([10.214.83.118]) by tx30smr01.am.freescale.net (8.14.3/8.14.0) with ESMTP id q9U25Bpu000467; Mon, 29 Oct 2012 19:05:28 -0700 From: Scott Wood To: Date: Mon, 29 Oct 2012 21:05:10 -0500 Message-ID: <1351562710-6237-23-git-send-email-scottwood@freescale.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1351562710-6237-1-git-send-email-scottwood@freescale.com> References: <1348272087-29608-1-git-send-email-scottwood@freescale.com> <1351562710-6237-1-git-send-email-scottwood@freescale.com> MIME-Version: 1.0 X-OriginatorOrg: freescale.com Cc: Scott Wood , Andy Fleming Subject: [U-Boot] [PATCH v2 22/22] powerpc/mpc85xx/p2020rdb-pca: Use L2 SRAM for SPL boot X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de This allows DDR configuration to be deferred to the final U-Boot image, which is able to make use of SPD data. The SPL itself cannot use SPD due to code size constraints. It previously used fixed register values for DDR configuration, and those values did not work on the p2020rdb-pca board I tested with. It's possible that different revisions of the board require different settings. Using SPD eliminates that problem. Signed-off-by: Scott Wood Cc: Andy Fleming --- board/freescale/p1_p2_rdb_pc/spl_minimal.c | 5 ++- board/freescale/p1_p2_rdb_pc/tlb.c | 15 ++++++- include/configs/p1_p2_rdb_pc.h | 65 +++++++++++++--------------- 3 files changed, 46 insertions(+), 39 deletions(-) diff --git a/board/freescale/p1_p2_rdb_pc/spl_minimal.c b/board/freescale/p1_p2_rdb_pc/spl_minimal.c index 5c893ee..8e2725f 100644 --- a/board/freescale/p1_p2_rdb_pc/spl_minimal.c +++ b/board/freescale/p1_p2_rdb_pc/spl_minimal.c @@ -23,6 +23,7 @@ #include #include #include +#include #include #include #include @@ -32,7 +33,7 @@ DECLARE_GLOBAL_DATA_PTR; /* * Fixed sdram init -- doesn't use serial presence detect. */ -void sdram_init(void) +static void __maybe_unused sdram_init(void) { ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC85xx_DDR_ADDR; @@ -101,8 +102,10 @@ void board_init_f(ulong bootflag) __raw_writel(0x00000000, &pgpio->gpdir); #endif +#ifndef CONFIG_SYS_INIT_L2_ADDR /* Initialize the DDR3 */ sdram_init(); +#endif /* copy code to RAM and jump to it - this should not return */ /* NOTE - code has to be copied out of NAND buffer before diff --git a/board/freescale/p1_p2_rdb_pc/tlb.c b/board/freescale/p1_p2_rdb_pc/tlb.c index 0873dd7..3e4dffd 100644 --- a/board/freescale/p1_p2_rdb_pc/tlb.c +++ b/board/freescale/p1_p2_rdb_pc/tlb.c @@ -95,6 +95,16 @@ struct fsl_e_tlb_entry tlb_table[] = { #endif #if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_SPL) +#ifdef CONFIG_SYS_INIT_L2_ADDR + /* L2SRAM */ + SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR, CONFIG_SYS_INIT_L2_ADDR_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 8, BOOKE_PAGESZ_256K, 1), + SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR + 0x40000, + CONFIG_SYS_INIT_L2_ADDR_PHYS + 0x40000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 12, BOOKE_PAGESZ_256K, 1), +#else /* *I*G - eSDHC/eSPI/NAND boot */ SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, MAS3_SX|MAS3_SW|MAS3_SR, 0, @@ -106,8 +116,9 @@ struct fsl_e_tlb_entry tlb_table[] = { CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 9, BOOKE_PAGESZ_1G, 1), -#endif -#endif +#endif /* P1020MBG */ +#endif /* not L2 SRAM */ +#endif /* RAMBOOT/SPL */ }; int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h index ba7a364..f02ba2b 100644 --- a/include/configs/p1_p2_rdb_pc.h +++ b/include/configs/p1_p2_rdb_pc.h @@ -38,6 +38,7 @@ #define __SW_BOOT_MASK 0x03 #define __SW_BOOT_NOR 0xe4 #define __SW_BOOT_SD 0x54 +#define CONFIG_SYS_L2_SIZE (256 << 10) #endif #if defined(CONFIG_P1020UTM) @@ -46,6 +47,7 @@ #define __SW_BOOT_MASK 0x03 #define __SW_BOOT_NOR 0xe0 #define __SW_BOOT_SD 0x50 +#define CONFIG_SYS_L2_SIZE (256 << 10) #endif #if defined(CONFIG_P1020RDB) @@ -61,6 +63,7 @@ #define __SW_BOOT_SD 0x9c #define __SW_BOOT_NAND 0xec #define __SW_BOOT_PCIE 0x6c +#define CONFIG_SYS_L2_SIZE (256 << 10) #endif #if defined(CONFIG_P1021RDB) @@ -78,6 +81,7 @@ #define __SW_BOOT_SD 0x9c #define __SW_BOOT_NAND 0xec #define __SW_BOOT_PCIE 0x6c +#define CONFIG_SYS_L2_SIZE (256 << 10) #endif #if defined(CONFIG_P1024RDB) @@ -91,6 +95,7 @@ #define __SW_BOOT_SPI 0x08 #define __SW_BOOT_SD 0x04 #define __SW_BOOT_NAND 0x0c +#define CONFIG_SYS_L2_SIZE (256 << 10) #endif #if defined(CONFIG_P1025RDB) @@ -108,6 +113,7 @@ #define __SW_BOOT_SPI 0x08 #define __SW_BOOT_SD 0x04 #define __SW_BOOT_NAND 0x0c +#define CONFIG_SYS_L2_SIZE (256 << 10) #endif #if defined(CONFIG_P2020RDB) @@ -122,6 +128,13 @@ #define __SW_BOOT_SD 0x68 /* or 0x18 */ #define __SW_BOOT_NAND 0xe8 #define __SW_BOOT_PCIE 0xa8 +#define CONFIG_SYS_L2_SIZE (512 << 10) +#endif + +#if CONFIG_SYS_L2_SIZE >= (512 << 10) +#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 +#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR /* must be 32-bit */ +#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) #endif #ifdef CONFIG_SDCARD @@ -149,14 +162,25 @@ #define CONFIG_SPL_FLUSH_IMAGE #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" -#define CONFIG_SYS_TEXT_BASE 0x00201000 #define CONFIG_SPL_TEXT_BASE 0xfffff000 #define CONFIG_SPL_MAX_SIZE (4 * 1024) + +#ifdef CONFIG_SYS_INIT_L2_ADDR +/* We multiply CONFIG_SPL_MAX_SIZE by two to leave some room for BSS. */ +#define CONFIG_SYS_TEXT_BASE 0xf8f82000 +#define CONFIG_SPL_RELOC_TEXT_BASE (CONFIG_SYS_INIT_L2_END - CONFIG_SPL_MAX_SIZE * 2) +#define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_END - CONFIG_SPL_MAX_SIZE * 2) +#define CONFIG_SYS_NAND_U_BOOT_DST (CONFIG_SYS_INIT_L2_ADDR) +#define CONFIG_SYS_NAND_U_BOOT_START (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SPL_MAX_SIZE) +#else +#define CONFIG_SYS_TEXT_BASE 0x00201000 #define CONFIG_SPL_RELOC_TEXT_BASE 0x00100000 #define CONFIG_SPL_RELOC_STACK 0x00100000 -#define CONFIG_SYS_NAND_U_BOOT_SIZE ((512 << 10) + CONFIG_SPL_MAX_SIZE) #define CONFIG_SYS_NAND_U_BOOT_DST (0x00200000 - CONFIG_SPL_MAX_SIZE) #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 +#endif + +#define CONFIG_SYS_NAND_U_BOOT_SIZE ((512 << 10) - 0x2000) #define CONFIG_SYS_NAND_U_BOOT_OFFS 0 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" #endif @@ -261,39 +285,7 @@ #define CONFIG_DIMM_SLOTS_PER_CTLR 1 /* Default settings for DDR3 */ -#ifdef CONFIG_P2020RDB -#define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f -#define CONFIG_SYS_DDR_CS0_CONFIG 0x80014202 -#define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000 -#define CONFIG_SYS_DDR_CS1_BNDS 0x00000000 -#define CONFIG_SYS_DDR_CS1_CONFIG 0x00000000 -#define CONFIG_SYS_DDR_CS1_CONFIG_2 0x00000000 - -#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef -#define CONFIG_SYS_DDR_INIT_ADDR 0x00000000 -#define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000 -#define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000 - -#define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600 -#define CONFIG_SYS_DDR_WRLVL_CONTROL 0x8645F607 -#define CONFIG_SYS_DDR_SR_CNTR 0x00000000 -#define CONFIG_SYS_DDR_RCW_1 0x00000000 -#define CONFIG_SYS_DDR_RCW_2 0x00000000 -#define CONFIG_SYS_DDR_CONTROL 0xC7000000 /* Type = DDR3 */ -#define CONFIG_SYS_DDR_CONTROL_2 0x24401000 -#define CONFIG_SYS_DDR_TIMING_4 0x00220001 -#define CONFIG_SYS_DDR_TIMING_5 0x02401400 - -#define CONFIG_SYS_DDR_TIMING_3 0x00020000 -#define CONFIG_SYS_DDR_TIMING_0 0x00330104 -#define CONFIG_SYS_DDR_TIMING_1 0x6f6B4644 -#define CONFIG_SYS_DDR_TIMING_2 0x0FA88CCF -#define CONFIG_SYS_DDR_CLK_CTRL 0x02000000 -#define CONFIG_SYS_DDR_MODE_1 0x00421422 -#define CONFIG_SYS_DDR_MODE_2 0x04000000 -#define CONFIG_SYS_DDR_INTERVAL 0x0C300100 - -#else +#ifndef CONFIG_P2020RDB #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302 #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000 @@ -334,13 +326,14 @@ * 0x0000_0000 0x7fff_ffff DDR Up to 2GB cacheable * 0x8000_0000 0xdfff_ffff PCI Express Mem 1.5G non-cacheable(PCIe * 3) * 0xec00_0000 0xefff_ffff NOR flash Up to 64M non-cacheable CS0/1 + * 0xf8f8_0000 0xf8ff_ffff L2 SRAM Up to 512K cacheable + * (early boot only) * 0xff80_0000 0xff80_7fff NAND flash 32K non-cacheable CS1/0 * 0xff98_0000 0xff98_ffff PMC 64K non-cacheable CS2 * 0xffa0_0000 0xffaf_ffff CPLD 1M non-cacheable CS3 * 0xffb0_0000 0xffbf_ffff VSC7385 switch 1M non-cacheable CS2 * 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable * 0xffd0_0000 0xffd0_3fff L1 for stack 16K cacheable - * 0xffd8_0000 0xffdf_ffff L2 SRAM Up to 512K cacheable * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable */