Patchwork [v2,14/19] target-mips: don't use local temps for store conditional

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Submitter Aurelien Jarno
Date Oct. 30, 2012, 12:12 a.m.
Message ID <1351555932-19695-15-git-send-email-aurelien@aurel32.net>
Download mbox | patch
Permalink /patch/195204/
State New
Headers show

Comments

Aurelien Jarno - Oct. 30, 2012, 12:12 a.m.
Store conditional operations only need local temps in user mode. Fix
the code to use temp local only in user mode, this spares two memory
stores in system mode.

At the same time remove a wrong a wrong copied & pasted comment,
store operations don't have a register destination.

Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
---
 target-mips/translate.c |   11 ++++++-----
 1 file changed, 6 insertions(+), 5 deletions(-)

Patch

diff --git a/target-mips/translate.c b/target-mips/translate.c
index b385923..54f309f 100644
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -1359,13 +1359,14 @@  static void gen_st_cond (DisasContext *ctx, uint32_t opc, int rt,
     const char *opn = "st_cond";
     TCGv t0, t1;
 
+#ifdef CONFIG_USER_ONLY
     t0 = tcg_temp_local_new();
-
-    gen_base_offset_addr(ctx, t0, base, offset);
-    /* Don't do NOP if destination is zero: we must perform the actual
-       memory access. */
-
     t1 = tcg_temp_local_new();
+#else
+    t0 = tcg_temp_new();
+    t1 = tcg_temp_new();
+#endif
+    gen_base_offset_addr(ctx, t0, base, offset);
     gen_load_gpr(t1, rt);
     switch (opc) {
 #if defined(TARGET_MIPS64)