Patchwork [v2,02/19] target-mips: do not save CPU state when using retranslation

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Submitter Aurelien Jarno
Date Oct. 30, 2012, 12:11 a.m.
Message ID <1351555932-19695-3-git-send-email-aurelien@aurel32.net>
Download mbox | patch
Permalink /patch/195176/
State New
Headers show

Comments

Aurelien Jarno - Oct. 30, 2012, 12:11 a.m.
When the CPU state after a possible retranslation is going to be handled
through code retranslation, we don't need to save the CPU state before.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
---
 target-mips/translate.c |   19 -------------------
 1 file changed, 19 deletions(-)

Patch

diff --git a/target-mips/translate.c b/target-mips/translate.c
index 3cf4ca1..97a63ea 100644
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -1171,13 +1171,11 @@  static void gen_ld (CPUMIPSState *env, DisasContext *ctx, uint32_t opc,
     switch (opc) {
 #if defined(TARGET_MIPS64)
     case OPC_LWU:
-        save_cpu_state(ctx, 0);
         op_ld_lwu(t0, t0, ctx);
         gen_store_gpr(t0, rt);
         opn = "lwu";
         break;
     case OPC_LD:
-        save_cpu_state(ctx, 0);
         op_ld_ld(t0, t0, ctx);
         gen_store_gpr(t0, rt);
         opn = "ld";
@@ -1203,7 +1201,6 @@  static void gen_ld (CPUMIPSState *env, DisasContext *ctx, uint32_t opc,
         opn = "ldr";
         break;
     case OPC_LDPC:
-        save_cpu_state(ctx, 0);
         tcg_gen_movi_tl(t1, pc_relative_pc(ctx));
         gen_op_addr_add(ctx, t0, t0, t1);
         op_ld_ld(t0, t0, ctx);
@@ -1212,7 +1209,6 @@  static void gen_ld (CPUMIPSState *env, DisasContext *ctx, uint32_t opc,
         break;
 #endif
     case OPC_LWPC:
-        save_cpu_state(ctx, 0);
         tcg_gen_movi_tl(t1, pc_relative_pc(ctx));
         gen_op_addr_add(ctx, t0, t0, t1);
         op_ld_lw(t0, t0, ctx);
@@ -1220,31 +1216,26 @@  static void gen_ld (CPUMIPSState *env, DisasContext *ctx, uint32_t opc,
         opn = "lwpc";
         break;
     case OPC_LW:
-        save_cpu_state(ctx, 0);
         op_ld_lw(t0, t0, ctx);
         gen_store_gpr(t0, rt);
         opn = "lw";
         break;
     case OPC_LH:
-        save_cpu_state(ctx, 0);
         op_ld_lh(t0, t0, ctx);
         gen_store_gpr(t0, rt);
         opn = "lh";
         break;
     case OPC_LHU:
-        save_cpu_state(ctx, 0);
         op_ld_lhu(t0, t0, ctx);
         gen_store_gpr(t0, rt);
         opn = "lhu";
         break;
     case OPC_LB:
-        save_cpu_state(ctx, 0);
         op_ld_lb(t0, t0, ctx);
         gen_store_gpr(t0, rt);
         opn = "lb";
         break;
     case OPC_LBU:
-        save_cpu_state(ctx, 0);
         op_ld_lbu(t0, t0, ctx);
         gen_store_gpr(t0, rt);
         opn = "lbu";
@@ -1289,7 +1280,6 @@  static void gen_st (DisasContext *ctx, uint32_t opc, int rt,
     switch (opc) {
 #if defined(TARGET_MIPS64)
     case OPC_SD:
-        save_cpu_state(ctx, 0);
         op_st_sd(t1, t0, ctx);
         opn = "sd";
         break;
@@ -1305,17 +1295,14 @@  static void gen_st (DisasContext *ctx, uint32_t opc, int rt,
         break;
 #endif
     case OPC_SW:
-        save_cpu_state(ctx, 0);
         op_st_sw(t1, t0, ctx);
         opn = "sw";
         break;
     case OPC_SH:
-        save_cpu_state(ctx, 0);
         op_st_sh(t1, t0, ctx);
         opn = "sh";
         break;
     case OPC_SB:
-        save_cpu_state(ctx, 0);
         op_st_sb(t1, t0, ctx);
         opn = "sb";
         break;
@@ -8149,7 +8136,6 @@  static void gen_flt3_ldst (DisasContext *ctx, uint32_t opc,
     }
     /* Don't do NOP if destination is zero: we must perform the actual
        memory access. */
-    save_cpu_state(ctx, 0);
     switch (opc) {
     case OPC_LWXC1:
         check_cop1x(ctx);
@@ -10422,7 +10408,6 @@  static void gen_ldxs (DisasContext *ctx, int base, int index, int rd)
         gen_op_addr_add(ctx, t0, t1, t0);
     }
 
-    save_cpu_state(ctx, 0);
     op_ld_lw(t1, t0, ctx);
     gen_store_gpr(t1, rd);
 
@@ -10452,7 +10437,6 @@  static void gen_ldst_pair (DisasContext *ctx, uint32_t opc, int rd,
             generate_exception(ctx, EXCP_RI);
             return;
         }
-        save_cpu_state(ctx, 0);
         op_ld_lw(t1, t0, ctx);
         gen_store_gpr(t1, rd);
         tcg_gen_movi_tl(t1, 4);
@@ -10462,7 +10446,6 @@  static void gen_ldst_pair (DisasContext *ctx, uint32_t opc, int rd,
         opn = "lwp";
         break;
     case SWP:
-        save_cpu_state(ctx, 0);
         gen_load_gpr(t1, rd);
         op_st_sw(t1, t0, ctx);
         tcg_gen_movi_tl(t1, 4);
@@ -10477,7 +10460,6 @@  static void gen_ldst_pair (DisasContext *ctx, uint32_t opc, int rd,
             generate_exception(ctx, EXCP_RI);
             return;
         }
-        save_cpu_state(ctx, 0);
         op_ld_ld(t1, t0, ctx);
         gen_store_gpr(t1, rd);
         tcg_gen_movi_tl(t1, 8);
@@ -10487,7 +10469,6 @@  static void gen_ldst_pair (DisasContext *ctx, uint32_t opc, int rd,
         opn = "ldp";
         break;
     case SDP:
-        save_cpu_state(ctx, 0);
         gen_load_gpr(t1, rd);
         op_st_sd(t1, t0, ctx);
         tcg_gen_movi_tl(t1, 8);