From patchwork Mon Oct 29 19:51:27 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christopher Harvey X-Patchwork-Id: 195135 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from merlin.infradead.org (merlin.infradead.org [IPv6:2001:4978:20e::2]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id EC42D2C009B for ; Tue, 30 Oct 2012 07:09:52 +1100 (EST) Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1TSvci-0002j5-Pw; Mon, 29 Oct 2012 20:07:49 +0000 Received: from mtxmxout5.matrox.com ([138.11.2.95]) by merlin.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1TSvce-0002iS-M6 for linux-mtd@lists.infradead.org; Mon, 29 Oct 2012 20:07:46 +0000 Received: from mars.matrox.com (mars.matrox.com [192.168.1.29]) by mtxmxout5.matrox.com (Postfix) with ESMTP id 9D9891C6BFD; Mon, 29 Oct 2012 15:47:42 -0400 (EDT) Received: (from ssmsp@localhost) by mars.matrox.com (8.14.4/8.13.2) id q9TJlgAf026945; Mon, 29 Oct 2012 15:47:42 -0400 Received: from localhost (localhost.localdomain [127.0.0.1]) by mars.matrox.com (Postfix) with ESMTP id 5D2C1951F9; Mon, 29 Oct 2012 15:47:42 -0400 (EDT) X-Virus-MTX-Scanned: by Matrox Virus scanner at mars.matrox.com Received: from pluton.matrox.com (pluton.matrox.com [192.168.8.7]) by mars.matrox.com (Postfix) with ESMTP id 3E610951F8; Mon, 29 Oct 2012 15:47:42 -0400 (EDT) Received: from harvey-pc.matrox.com (dyn-152-224.matrox.com [192.168.152.224]) by pluton.matrox.com (Postfix) with ESMTP id 2EC477F45F; Mon, 29 Oct 2012 15:47:42 -0400 (EDT) Date: Mon, 29 Oct 2012 15:51:27 -0400 From: Christopher Harvey To: linux-mtd@lists.infradead.org Subject: [PATCH v3] mtd: omap: nand: Remove 0xFF's that prefixed 16bit NAND addresses Message-ID: <20121029195127.GA32749@harvey-pc.matrox.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20121026193410.GA21474@harvey-pc.matrox.com> User-Agent: Mutt/1.5.21 (2010-09-15) X-Spam-Note: CRM114 invocation failed X-Spam-Score: -2.6 (--) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-2.6 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 SPF_PASS SPF: sender matches SPF record -0.7 RP_MATCHES_RCVD Envelope sender domain matches handover relay domain -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] Cc: Ivan Djelic , linux-omap@vger.kernel.org X-BeenThere: linux-mtd@lists.infradead.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: Linux MTD discussion mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: linux-mtd-bounces@lists.infradead.org Errors-To: linux-mtd-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org In 16bit NAND mode the GPMC would send the address 0xNN as 0xFFNN instead of 0x00NN on the bus. The 0xFFs were actually uninitialized bits that were left unset in the GPMC command output register. The reason they weren't initialized in 16bit mode is that if the same code that writes to this register was used in 8bit mode then 2 commands would be output in 8bit mode. One for the low byte, and an extra 0x0 command for the high byte. This commit uses writew if we're using 16bit NAND. This commit also changes the high byte in the command output register, but they are ignored by NAND chips anyway. Most chips seem fine with the extra 0xFFs, but the ONFI spec says otherwise. Signed-off-by: Christopher Harvey --- drivers/mtd/nand/omap2.c | 14 +++++++++----- 1 files changed, 9 insertions(+), 5 deletions(-) diff --git a/drivers/mtd/nand/omap2.c b/drivers/mtd/nand/omap2.c index 5b31386..ae6738f 100644 --- a/drivers/mtd/nand/omap2.c +++ b/drivers/mtd/nand/omap2.c @@ -225,16 +225,20 @@ static void omap_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl) { struct omap_nand_info *info = container_of(mtd, struct omap_nand_info, mtd); + void __iomem *reg; if (cmd != NAND_CMD_NONE) { if (ctrl & NAND_CLE) - writeb(cmd, info->reg.gpmc_nand_command); - + reg = info->reg.gpmc_nand_command; else if (ctrl & NAND_ALE) - writeb(cmd, info->reg.gpmc_nand_address); - + reg = info->reg.gpmc_nand_address; else /* NAND_NCE */ - writeb(cmd, info->reg.gpmc_nand_data); + reg = info->reg.gpmc_nand_data; + + if (info->nand.options & NAND_BUSWIDTH_16) + writew(cmd, reg); + else + writeb(cmd, reg); } }