Patchwork [10/15] SPEAr13xx: DTS: Add auxiliary data for PCIe host

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Submitter Pratyush ANAND
Date Oct. 29, 2012, 7:01 a.m.
Message ID <91c2505d23f161ce535b220dea497e2c3abfd7f6.1351492562.git.pratyush.anand@st.com>
Download mbox | patch
Permalink /patch/194854/
State Not Applicable
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Comments

Pratyush ANAND - Oct. 29, 2012, 7:01 a.m.
Signed-off-by: Pratyush Anand <pratyush.anand@st.com>
---
 arch/arm/boot/dts/spear13xx.dtsi |   24 ++++++++++++++++++++++++
 1 files changed, 24 insertions(+), 0 deletions(-)
viresh kumar - Oct. 29, 2012, 1:24 p.m.
On Mon, Oct 29, 2012 at 12:31 PM, Pratyush Anand <pratyush.anand@st.com> wrote:
> Signed-off-by: Pratyush Anand <pratyush.anand@st.com>
> ---

Please add commit log in each and every message.

What do you mean by auxiliary data in subject?
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Pratyush ANAND - Oct. 30, 2012, 3:24 a.m.
On 10/29/2012 6:54 PM, viresh kumar wrote:
> On Mon, Oct 29, 2012 at 12:31 PM, Pratyush Anand <pratyush.anand@st.com> wrote:
>> Signed-off-by: Pratyush Anand <pratyush.anand@st.com>
>> ---
>
> Please add commit log in each and every message.
>
> What do you mean by auxiliary data in subject?

It used to be plat data earlier, which is being passed from DT now.

> .
>



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viresh kumar - Oct. 30, 2012, 5:47 a.m.
On 30 October 2012 08:54, Pratyush Anand <pratyush.anand@st.com> wrote:
>> What do you mean by auxiliary data in subject?
>
> It used to be plat data earlier, which is being passed from DT now.

Yes. But how did you conclude that it should be called auxiliary data?

I would change subject of this patch to:
ARM: SPEAr13xx: Pass configuration information of PCIe via DT

But i believe you wouldn't need any of above messages and the new message
will also add basic DT support for PCIe.

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viresh
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Patch

diff --git a/arch/arm/boot/dts/spear13xx.dtsi b/arch/arm/boot/dts/spear13xx.dtsi
index b7990754..fe55d21 100644
--- a/arch/arm/boot/dts/spear13xx.dtsi
+++ b/arch/arm/boot/dts/spear13xx.dtsi
@@ -199,6 +199,14 @@ 
 				0xeb800000 0x1000 >;
 			interrupts = <0 68 0x4>;
 			status = "disabled";
+			pcie-host,is_host = <1>;
+			pcie-host,is_gen1 = <0>;
+			pcie-host,cfg0_size = <0x100000>;
+			pcie-host,cfg1_size = <0x100000>;
+			pcie-host,mem_size = <0xFC00000>;
+			pcie-host,msg_size = <0x100000>;
+			/* Entire DDR Area */
+			pcie-host,in_mem_size = <0x80000000>;
 		};
 
 		pcie1@b1800000 {
@@ -208,6 +216,14 @@ 
 				0xeb804000 0x1000 >;
 			interrupts = <0 69 0x4>;
 			status = "disabled";
+			pcie-host,is_host = <1>;
+			pcie-host,is_gen1 = <0>;
+			pcie-host,cfg0_size = <0x100000>;
+			pcie-host,cfg1_size = <0x100000>;
+			pcie-host,mem_size = <0xFC00000>;
+			pcie-host,msg_size = <0x100000>;
+			/* Entire DDR Area */
+			pcie-host,in_mem_size = <0x80000000>;
 		};
 
 		pcie2@b4000000 {
@@ -217,6 +233,14 @@ 
 				0xeb808000 0x1000 >;
 			interrupts = <0 70 0x4>;
 			status = "disabled";
+			pcie-host,is_host = <1>;
+			pcie-host,is_gen1 = <0>;
+			pcie-host,cfg0_size = <0x100000>;
+			pcie-host,cfg1_size = <0x100000>;
+			pcie-host,mem_size = <0xFC00000>;
+			pcie-host,msg_size = <0x100000>;
+			/* Entire DDR Area */
+			pcie-host,in_mem_size = <0x80000000>;
 		};
 
 		c3@e1800000 {