From patchwork Mon Oct 29 06:45:00 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Crosthwaite X-Patchwork-Id: 194842 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 1D3D22C009A for ; Mon, 29 Oct 2012 17:46:00 +1100 (EST) Received: from localhost ([::1]:47919 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TSj6k-0002nk-B0 for incoming@patchwork.ozlabs.org; Mon, 29 Oct 2012 02:45:58 -0400 Received: from eggs.gnu.org ([208.118.235.92]:42201) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TSj68-0001BA-BI for qemu-devel@nongnu.org; Mon, 29 Oct 2012 02:45:21 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1TSj66-00041s-Mv for qemu-devel@nongnu.org; Mon, 29 Oct 2012 02:45:20 -0400 Received: from mail-pa0-f45.google.com ([209.85.220.45]:59685) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TSj66-0003q7-GY for qemu-devel@nongnu.org; Mon, 29 Oct 2012 02:45:18 -0400 Received: by mail-pa0-f45.google.com with SMTP id fb10so3026760pad.4 for ; Sun, 28 Oct 2012 23:45:18 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=sender:from:to:cc:subject:date:message-id:x-mailer:in-reply-to :references:x-gm-message-state; bh=yE32GvLWWiUB8gQvHoY9FypLExXio8XIrGgDi/t6u/E=; b=S51kdR41ZG8DjpwFFlPIi8LpoqVhW+xmRfbR3pXw270HwNd7nmf51aQM2RgDUU+xqm Vz8LObCBK8uddBZ0p5d8kYzcd+yQj6YqEm7aEr030mRscTp//vD1npfX/N624ZuZ+Wmi soxApjHAE5vrTrpmArWDaVrW0TouDDj+PUPKmGNbA92f6FkMQOeVeg6z+x29exlDcpdQ kVz9aFaLHlHmRUF4PW/EGZqSmZ2qQ3M+D35oTIMBosuWVOk0WDfaBsEiHo2CByZCSxVc zbNuAPE6HSTiT6jxoA8cbBBSJo+1nsYvDav9rnRmF1+8/zdwGHBTXul9iVyhmsT4G8g+ bd1g== Received: by 10.68.195.195 with SMTP id ig3mr91202002pbc.108.1351493117812; Sun, 28 Oct 2012 23:45:17 -0700 (PDT) Received: from localhost ([124.148.20.9]) by mx.google.com with ESMTPS id mn5sm5511116pbc.12.2012.10.28.23.45.15 (version=TLSv1/SSLv3 cipher=OTHER); Sun, 28 Oct 2012 23:45:17 -0700 (PDT) From: Peter Crosthwaite To: qemu-devel@nongnu.org Date: Mon, 29 Oct 2012 16:45:00 +1000 Message-Id: <1351493100-5850-4-git-send-email-peter.crosthwaite@xilinx.com> X-Mailer: git-send-email 1.7.0.4 In-Reply-To: <1351493100-5850-1-git-send-email-peter.crosthwaite@xilinx.com> References: <1351493100-5850-1-git-send-email-peter.crosthwaite@xilinx.com> X-Gm-Message-State: ALoCoQmEYHT/eKVZDTPXJdcRD12IAdMXBWgtwsiqVGIcNXz+nCEdMa8Gv8Uynw1hzxFQPe3es88S X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 209.85.220.45 Cc: blauwirbel@gmail.com, edgar.iglesias@gmail.com, aliguori@us.ibm.com Subject: [Qemu-devel] [PATCH 3/3] xilinx_zynq: added QSPI controller X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Added the QSPI controller to the Zynq. 4 SPI devices are attached to allow modelling of the different geometries. E.G. Dual parallel and dual stacked mode can both be tested with this one arrangement. Signed-off-by: Peter Crosthwaite --- hw/xilinx_zynq.c | 40 ++++++++++++++++++++++++++++------------ 1 files changed, 28 insertions(+), 12 deletions(-) diff --git a/hw/xilinx_zynq.c b/hw/xilinx_zynq.c index c55dafb..0026235 100644 --- a/hw/xilinx_zynq.c +++ b/hw/xilinx_zynq.c @@ -27,6 +27,8 @@ #include "ssi.h" #define NUM_SPI_FLASHES 4 +#define NUM_QSPI_FLASHES 2 +#define NUM_QSPI_BUSSES 2 #define FLASH_SIZE (64 * 1024 * 1024) #define FLASH_SECTOR_SIZE (128 * 1024) @@ -49,30 +51,43 @@ static void gem_init(NICInfo *nd, uint32_t base, qemu_irq irq) sysbus_connect_irq(s, 0, irq); } -static inline void zynq_init_spi_flashes(uint32_t base_addr, qemu_irq irq) +static inline void zynq_init_spi_flashes(uint32_t base_addr, qemu_irq irq, + bool is_qspi) { DeviceState *dev; SysBusDevice *busdev; SSIBus *spi; - int i; + int i, j; + int num_busses = is_qspi ? NUM_QSPI_BUSSES : 1; + int num_ss = is_qspi ? NUM_QSPI_FLASHES : NUM_SPI_FLASHES; dev = qdev_create(NULL, "xilinx,spips"); + qdev_prop_set_uint8(dev, "num-txrx-bytes", is_qspi ? 4 : 1); + qdev_prop_set_uint8(dev, "num-ss-bits", num_ss); + qdev_prop_set_uint8(dev, "num-busses", num_busses); qdev_init_nofail(dev); busdev = sysbus_from_qdev(dev); sysbus_mmio_map(busdev, 0, base_addr); + if (is_qspi) { + sysbus_mmio_map(busdev, 1, 0xFC000000); + } sysbus_connect_irq(busdev, 0, irq); - spi = (SSIBus *)qdev_get_child_bus(dev, "spi"); - - for (i = 0; i < NUM_SPI_FLASHES; ++i) { + for (i = 0; i < num_busses; ++i) { + char bus_name[16]; qemu_irq cs_line; - dev = ssi_create_slave_no_init(spi, "m25p80"); - qdev_prop_set_string(dev, "partname", "n25q128"); - qdev_init_nofail(dev); + snprintf(bus_name, 16, "spi%d", i); + spi = (SSIBus *)qdev_get_child_bus(dev, bus_name); - cs_line = qdev_get_gpio_in(dev, 0); - sysbus_connect_irq(busdev, i+1, cs_line); + for (j = 0; j < num_ss; ++j) { + dev = ssi_create_slave_no_init(spi, "m25p80"); + qdev_prop_set_string(dev, "partname", "n25q128"); + qdev_init_nofail(dev); + + cs_line = qdev_get_gpio_in(dev, 0); + sysbus_connect_irq(busdev, i * num_ss + j + 1, cs_line); + } } } @@ -147,8 +162,9 @@ static void zynq_init(QEMUMachineInitArgs *args) pic[n] = qdev_get_gpio_in(dev, n); } - zynq_init_spi_flashes(0xE0006000, pic[58-IRQ_OFFSET]); - zynq_init_spi_flashes(0xE0007000, pic[81-IRQ_OFFSET]); + zynq_init_spi_flashes(0xE0006000, pic[58-IRQ_OFFSET], false); + zynq_init_spi_flashes(0xE0007000, pic[81-IRQ_OFFSET], false); + zynq_init_spi_flashes(0xE000D000, pic[51-IRQ_OFFSET], true); sysbus_create_simple("cadence_uart", 0xE0000000, pic[59-IRQ_OFFSET]); sysbus_create_simple("cadence_uart", 0xE0001000, pic[82-IRQ_OFFSET]);