From patchwork Sat Oct 27 02:40:14 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Subject: [U-Boot] powerpc/corenet_ds: Update DDR timing for single-rank DIMMs Date: Fri, 26 Oct 2012 16:40:14 -0000 From: York Sun X-Patchwork-Id: 194597 Message-Id: <1351305615-19107-1-git-send-email-yorksun@freescale.com> To: Cc: afleming@gmail.com Single rank UDIMM timing has been verified with HMT325U7BFR8C-H9 for speed 800, 900, 1000, 1200, 1300MT/s. Signed-off-by: York Sun --- board/freescale/corenet_ds/ddr.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/board/freescale/corenet_ds/ddr.c b/board/freescale/corenet_ds/ddr.c index 4a53b8d..da284cd 100644 --- a/board/freescale/corenet_ds/ddr.c +++ b/board/freescale/corenet_ds/ddr.c @@ -139,8 +139,8 @@ static const struct board_specific_parameters udimm0[] = { {2, 1250, 4, 6, 0xff, 2, 0}, {2, 1350, 5, 7, 0xff, 2, 0}, {2, 1666, 5, 8, 0xff, 2, 0}, - {1, 850, 4, 5, 0xff, 2, 0}, - {1, 950, 4, 7, 0xff, 2, 0}, + {1, 1250, 4, 6, 0xff, 2, 0}, + {1, 1335, 4, 7, 0xff, 2, 0}, {1, 1666, 4, 8, 0xff, 2, 0}, {} };