Patchwork [U-Boot] powerpc/corenet_ds: Update DDR timing for single-rank DIMMs

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Submitter York Sun
Date Oct. 27, 2012, 2:40 a.m.
Message ID <1351305615-19107-1-git-send-email-yorksun@freescale.com>
Download mbox | patch
Permalink /patch/194597/
State Accepted, archived
Delegated to: Andy Fleming
Headers show

Comments

York Sun - Oct. 27, 2012, 2:40 a.m.
Single rank UDIMM timing has been verified with HMT325U7BFR8C-H9 for speed
800, 900, 1000, 1200, 1300MT/s.

Signed-off-by: York Sun <yorksun@freescale.com>
---
 board/freescale/corenet_ds/ddr.c |    4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

Patch

diff --git a/board/freescale/corenet_ds/ddr.c b/board/freescale/corenet_ds/ddr.c
index 4a53b8d..da284cd 100644
--- a/board/freescale/corenet_ds/ddr.c
+++ b/board/freescale/corenet_ds/ddr.c
@@ -139,8 +139,8 @@  static const struct board_specific_parameters udimm0[] = {
 	{2,  1250,    4,     6,   0xff,    2,  0},
 	{2,  1350,    5,     7,   0xff,    2,  0},
 	{2,  1666,    5,     8,   0xff,    2,  0},
-	{1,   850,    4,     5,   0xff,    2,  0},
-	{1,   950,    4,     7,   0xff,    2,  0},
+	{1,  1250,    4,     6,   0xff,    2,  0},
+	{1,  1335,    4,     7,   0xff,    2,  0},
 	{1,  1666,    4,     8,   0xff,    2,  0},
 	{}
 };