From patchwork Fri Oct 26 05:47:43 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Crosthwaite X-Patchwork-Id: 194376 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 56D4D2C00A4 for ; Fri, 26 Oct 2012 17:13:07 +1100 (EST) Received: from localhost ([::1]:36143 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TRcmj-0003Pz-31 for incoming@patchwork.ozlabs.org; Fri, 26 Oct 2012 01:48:45 -0400 Received: from eggs.gnu.org ([208.118.235.92]:59219) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TRcmG-0002pa-7h for qemu-devel@nongnu.org; Fri, 26 Oct 2012 01:48:17 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1TRcmD-0000z8-KC for qemu-devel@nongnu.org; Fri, 26 Oct 2012 01:48:16 -0400 Received: from mail-da0-f45.google.com ([209.85.210.45]:49828) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TRcmD-0000xV-Er for qemu-devel@nongnu.org; Fri, 26 Oct 2012 01:48:13 -0400 Received: by mail-da0-f45.google.com with SMTP id n15so1090001dad.4 for ; Thu, 25 Oct 2012 22:48:13 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=sender:from:to:cc:subject:date:message-id:x-mailer:in-reply-to :references:in-reply-to:references:x-gm-message-state; bh=u9RrYaP5TCqICtMkrslVjw1Pjp4/ZGOfwux6Fr6zdHY=; b=l+e8i5PzB+1svh4bIILAZdVW16wx75T4OwuSddTpDZSeEj+al8qqV5guS2ppv7/wNJ 3D7KNUGzW+2X2XLiOPQONmBTJ34lfnb+0gnpGz4FHs/ZyMI+naTZjoMb2crDmcTeJsRu MFBRCnxUBYafVG2WFiamqnd8slGvDVaClu7tKYL0qzhRPqIRb/JQhTPWK/ICVSzwig1M dSTZKslLI2DqIAikjLdoxcClnD6AsLgLKHVRmsugK9IOPfy+tsz9yUO17/SBlsSH8Cjd GfnViLsk801awvU3GFqXrpljDL9y+RkIWQtE7g1d13guECvDxHBr2ITCOynVGckHJSFw RJjg== Received: by 10.66.90.36 with SMTP id bt4mr59165861pab.54.1351230492977; Thu, 25 Oct 2012 22:48:12 -0700 (PDT) Received: from localhost ([124.148.20.9]) by mx.google.com with ESMTPS id ka4sm615451pbc.61.2012.10.25.22.48.09 (version=TLSv1/SSLv3 cipher=OTHER); Thu, 25 Oct 2012 22:48:12 -0700 (PDT) From: Peter Crosthwaite To: qemu-devel@nongnu.org Date: Fri, 26 Oct 2012 15:47:43 +1000 Message-Id: <18f7a25daf0799874694d0caea4730f110c60112.1351229557.git.peter.crosthwaite@xilinx.com> X-Mailer: git-send-email 1.7.0.4 In-Reply-To: References: In-Reply-To: References: X-Gm-Message-State: ALoCoQnUBlG8COOxvd6N8Flz1iHqgZcy81f2/yZUdz4hjEP7yzY5wNDYZ8zJK+MWBFUrSgjKlWks X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 209.85.210.45 Cc: vineshp@xilinx.com, peter.maydell@linaro.org, Peter Crosthwaite , john.williams@xilinx.com, kraxel@redhat.com, edgar.iglesias@gmail.com, afaerber@suse.de Subject: [Qemu-devel] [PATCH v2 03/11] usb/ehci: parameterise the register region offsets X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org The capabilities register and operational register offsets can vary from one EHCI implementation to the next. Parameterise accordingly. Signed-off-by: Peter Crosthwaite --- changed from v1: Moved opregbase and capregbase to class_data (Gerd Review) Fixed capa regs to 16 bytes in length (Gerd Review) Removed C++ comments touched by this patch (Checkpatch) hw/usb/hcd-ehci.c | 80 ++++++++++++++++++++++++++++++---------------------- 1 files changed, 46 insertions(+), 34 deletions(-) diff --git a/hw/usb/hcd-ehci.c b/hw/usb/hcd-ehci.c index 625ec2a..1d99f5b 100644 --- a/hw/usb/hcd-ehci.c +++ b/hw/usb/hcd-ehci.c @@ -48,20 +48,18 @@ #define USB_RET_PROCERR (-99) #define MMIO_SIZE 0x1000 +#define CAPA_SIZE 0x10 /* Capability Registers Base Address - section 2.2 */ -#define CAPREGBASE 0x0000 -#define CAPLENGTH CAPREGBASE + 0x0000 // 1-byte, 0x0001 reserved -#define HCIVERSION CAPREGBASE + 0x0002 // 2-bytes, i/f version # -#define HCSPARAMS CAPREGBASE + 0x0004 // 4-bytes, structural params -#define HCCPARAMS CAPREGBASE + 0x0008 // 4-bytes, capability params +#define CAPLENGTH 0x0000 /* 1-byte, 0x0001 reserved */ +#define HCIVERSION 0x0002 /* 2-bytes, i/f version # */ +#define HCSPARAMS 0x0004 /* 4-bytes, structural params */ +#define HCCPARAMS 0x0008 /* 4-bytes, capability params */ #define EECP HCCPARAMS + 1 -#define HCSPPORTROUTE1 CAPREGBASE + 0x000c -#define HCSPPORTROUTE2 CAPREGBASE + 0x0010 +#define HCSPPORTROUTE1 0x000c +#define HCSPPORTROUTE2 0x0010 -#define OPREGBASE 0x0020 // Operational Registers Base Address - -#define USBCMD OPREGBASE + 0x0000 +#define USBCMD 0x0000 #define USBCMD_RUNSTOP (1 << 0) // run / Stop #define USBCMD_HCRESET (1 << 1) // HC Reset #define USBCMD_FLS (3 << 2) // Frame List Size @@ -75,7 +73,7 @@ #define USBCMD_ITC (0x7f << 16) // Int Threshold Control #define USBCMD_ITC_SH 16 // Int Threshold Control Shift -#define USBSTS OPREGBASE + 0x0004 +#define USBSTS 0x0004 #define USBSTS_RO_MASK 0x0000003f #define USBSTS_INT (1 << 0) // USB Interrupt #define USBSTS_ERRINT (1 << 1) // Error Interrupt @@ -92,18 +90,18 @@ * Interrupt enable bits correspond to the interrupt active bits in USBSTS * so no need to redefine here. */ -#define USBINTR OPREGBASE + 0x0008 +#define USBINTR 0x0008 #define USBINTR_MASK 0x0000003f -#define FRINDEX OPREGBASE + 0x000c -#define CTRLDSSEGMENT OPREGBASE + 0x0010 -#define PERIODICLISTBASE OPREGBASE + 0x0014 -#define ASYNCLISTADDR OPREGBASE + 0x0018 +#define FRINDEX 0x000c +#define CTRLDSSEGMENT 0x0010 +#define PERIODICLISTBASE 0x0014 +#define ASYNCLISTADDR 0x0018 #define ASYNCLISTADDR_MASK 0xffffffe0 -#define CONFIGFLAG OPREGBASE + 0x0040 +#define CONFIGFLAG 0x0040 -#define PORTSC (OPREGBASE + 0x0044) +#define PORTSC 0x0044 #define PORTSC_BEGIN PORTSC #define PORTSC_END (PORTSC + 4 * NB_PORTS) /* @@ -399,14 +397,15 @@ struct EHCIState { /* properties */ uint32_t maxframes; + uint16_t opregbase; /* * EHCI spec version 1.0 Section 2.3 * Host Controller Operational Registers */ - uint8_t caps[OPREGBASE]; + uint8_t caps[CAPA_SIZE]; union { - uint32_t opreg[(PORTSC_BEGIN-OPREGBASE)/sizeof(uint32_t)]; + uint32_t opreg[PORTSC_BEGIN/sizeof(uint32_t)]; struct { uint32_t usbcmd; uint32_t usbsts; @@ -505,8 +504,7 @@ static const char *state2str(uint32_t state) static const char *addr2str(hwaddr addr) { - return nr2str(ehci_mmio_names, ARRAY_SIZE(ehci_mmio_names), - addr + OPREGBASE); + return nr2str(ehci_mmio_names, ARRAY_SIZE(ehci_mmio_names), addr); } static void ehci_trace_usbsts(uint32_t mask, int state) @@ -1114,7 +1112,7 @@ static uint64_t ehci_opreg_read(void *ptr, hwaddr addr, uint32_t val; val = s->opreg[addr >> 2]; - trace_usb_ehci_opreg_read(addr + OPREGBASE, addr2str(addr), val); + trace_usb_ehci_opreg_read(addr + s->opregbase, addr2str(addr), val); return val; } @@ -1210,9 +1208,9 @@ static void ehci_opreg_write(void *ptr, hwaddr addr, uint32_t old = *mmio; int i; - trace_usb_ehci_opreg_write(addr + OPREGBASE, addr2str(addr), val); + trace_usb_ehci_opreg_write(addr + s->opregbase, addr2str(addr), val); - switch (addr + OPREGBASE) { + switch (addr) { case USBCMD: if (val & USBCMD_HCRESET) { ehci_reset(s); @@ -1290,7 +1288,8 @@ static void ehci_opreg_write(void *ptr, hwaddr addr, } *mmio = val; - trace_usb_ehci_opreg_change(addr + OPREGBASE, addr2str(addr), *mmio, old); + trace_usb_ehci_opreg_change(addr + s->opregbase, addr2str(addr), + *mmio, old); } @@ -2645,6 +2644,9 @@ typedef struct EHCIClass { union { PCIDeviceClass pci; }; + + uint16_t capabase; + uint16_t opregbase; } EHCIClass; static void ehci_class_init(ObjectClass *klass, void *data) @@ -2659,6 +2661,8 @@ static void ehci_class_init(ObjectClass *klass, void *data) k->pci.device_id = template->pci.device_id; /* ich4 */ k->pci.revision = template->pci.revision; k->pci.class_id = PCI_CLASS_SERIAL_USB; + k->opregbase = template->opregbase; + k->capabase = template->capabase; dc->vmsd = &vmstate_ehci; dc->props = ehci_properties; } @@ -2674,7 +2678,9 @@ static TypeInfo ehci_info[] = { .pci.vendor_id = PCI_VENDOR_ID_INTEL, .pci.device_id = PCI_DEVICE_ID_INTEL_82801D, .pci.revision = 0x10, - } + }, + 0x00, + 0x20, } } }, { .name = "ich9-usb-ehci1", @@ -2686,7 +2692,9 @@ static TypeInfo ehci_info[] = { .pci.vendor_id = PCI_VENDOR_ID_INTEL, .pci.device_id = PCI_DEVICE_ID_INTEL_82801I_EHCI1, .pci.revision = 0x03, - } + }, + 0x00, + 0x20, } } }, { .name = NULL } }; @@ -2694,6 +2702,7 @@ static TypeInfo ehci_info[] = { static int usb_ehci_initfn(PCIDevice *dev) { EHCIState *s = DO_UPCAST(EHCIState, dev, dev); + EHCIClass *c = (EHCIClass *)object_get_class(OBJECT(dev)); uint8_t *pci_conf = s->dev.config; int i; @@ -2726,8 +2735,10 @@ static int usb_ehci_initfn(PCIDevice *dev) pci_conf[0x6e] = 0x00; pci_conf[0x6f] = 0xc0; // USBLEFCTLSTS + s->opregbase = c->opregbase; + /* 2.2 host controller interface version */ - s->caps[0x00] = (uint8_t) OPREGBASE; + s->caps[0x00] = (uint8_t)(s->opregbase - c->capabase); s->caps[0x01] = 0x00; s->caps[0x02] = 0x00; s->caps[0x03] = 0x01; /* HC version */ @@ -2760,15 +2771,16 @@ static int usb_ehci_initfn(PCIDevice *dev) memory_region_init(&s->mem, "ehci", MMIO_SIZE); memory_region_init_io(&s->mem_caps, &ehci_mmio_caps_ops, s, - "capabilities", OPREGBASE); + "capabilities", CAPA_SIZE); memory_region_init_io(&s->mem_opreg, &ehci_mmio_opreg_ops, s, - "operational", PORTSC_BEGIN - OPREGBASE); + "operational", PORTSC_BEGIN); memory_region_init_io(&s->mem_ports, &ehci_mmio_port_ops, s, "ports", PORTSC_END - PORTSC_BEGIN); - memory_region_add_subregion(&s->mem, 0, &s->mem_caps); - memory_region_add_subregion(&s->mem, OPREGBASE, &s->mem_opreg); - memory_region_add_subregion(&s->mem, PORTSC_BEGIN, &s->mem_ports); + memory_region_add_subregion(&s->mem, c->capabase, &s->mem_caps); + memory_region_add_subregion(&s->mem, s->opregbase, &s->mem_opreg); + memory_region_add_subregion(&s->mem, s->opregbase + PORTSC_BEGIN, + &s->mem_ports); pci_register_bar(&s->dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->mem);