From patchwork Fri Oct 26 05:47:45 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Crosthwaite X-Patchwork-Id: 194364 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 351332C0094 for ; Fri, 26 Oct 2012 16:49:01 +1100 (EST) Received: from localhost ([::1]:37889 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TRcmx-0004LI-CX for incoming@patchwork.ozlabs.org; Fri, 26 Oct 2012 01:48:59 -0400 Received: from eggs.gnu.org ([208.118.235.92]:59301) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TRcmT-0003Xy-SZ for qemu-devel@nongnu.org; Fri, 26 Oct 2012 01:48:31 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1TRcmQ-00011P-QZ for qemu-devel@nongnu.org; Fri, 26 Oct 2012 01:48:29 -0400 Received: from mail-da0-f45.google.com ([209.85.210.45]:49828) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TRcmQ-0000xV-Jl for qemu-devel@nongnu.org; Fri, 26 Oct 2012 01:48:26 -0400 Received: by mail-da0-f45.google.com with SMTP id n15so1090001dad.4 for ; Thu, 25 Oct 2012 22:48:26 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=sender:from:to:cc:subject:date:message-id:x-mailer:in-reply-to :references:in-reply-to:references:x-gm-message-state; bh=iOszDzNdPnpxc8aDT43QzPswJHOcGTBGLsvVxnomsNs=; b=YNCxymuwhkF/KWn6R9Busu6QM7Z/eZClrF2s1DVnGa6amPUUrVGXapMX1wCNkF5n89 mHps4C+vA5ZZr1bdMXeILRhHfaCAiDK/CzN+2Ujg+q00vEvfeiKj902l2BiR98BQwKg/ Itxu33yr1qhikibHFMOFsUPvirysdlNym7S7AYfqrnBEhpJqadvZFwFg/OW0fSF69pzN aIjM+qnx90xJGurW2B0+xxQInhT2ZMEbFSwWCk57Airv2HJg1tFwaGwkPZwfcxz+b/cx gBD34O+mYyYnI4AgtGFCDZ11aQr8HDtDpz/dqZrupZiBgkYQubLqPlZA8mVLvBpHHfhV thTQ== Received: by 10.68.226.71 with SMTP id rq7mr25079604pbc.65.1351230506166; Thu, 25 Oct 2012 22:48:26 -0700 (PDT) Received: from localhost ([124.148.20.9]) by mx.google.com with ESMTPS id c1sm445795pav.23.2012.10.25.22.48.22 (version=TLSv1/SSLv3 cipher=OTHER); Thu, 25 Oct 2012 22:48:25 -0700 (PDT) From: Peter Crosthwaite To: qemu-devel@nongnu.org Date: Fri, 26 Oct 2012 15:47:45 +1000 Message-Id: <16ccd8856bbc63649b8d5bed1123213ac0a05edc.1351229557.git.peter.crosthwaite@xilinx.com> X-Mailer: git-send-email 1.7.0.4 In-Reply-To: References: In-Reply-To: References: X-Gm-Message-State: ALoCoQmt0XMLraztYM/372hrYzyU7Lm46hvv5XPt3BYtCjzO2spLmtB3RR8ccPBBzSn7JFQK1SXX X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 209.85.210.45 Cc: vineshp@xilinx.com, peter.maydell@linaro.org, Peter Crosthwaite , john.williams@xilinx.com, kraxel@redhat.com, edgar.iglesias@gmail.com, afaerber@suse.de Subject: [Qemu-devel] [PATCH v2 05/11] usb/ehci: seperate out PCIisms X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Seperate the PCI stuff from the EHCI components. Extracted the PCIDevice out into a new wrapper struct to make EHCIState non-PCI-specific. Seperated tho non PCI init component out into a seperate "common" init function. Signed-off-by: Peter Crosthwaite --- Changed from v1: renamed VMSD defintions to preserve backwards compatibility (Gerd Review) hw/usb/hcd-ehci.c | 136 ++++++++++++++++++++++++++++++++-------------------- 1 files changed, 84 insertions(+), 52 deletions(-) diff --git a/hw/usb/hcd-ehci.c b/hw/usb/hcd-ehci.c index 28bd7e9..1c5e5ed 100644 --- a/hw/usb/hcd-ehci.c +++ b/hw/usb/hcd-ehci.c @@ -386,7 +386,6 @@ struct EHCIQueue { typedef QTAILQ_HEAD(EHCIQueueHead, EHCIQueue) EHCIQueueHead; struct EHCIState { - PCIDevice dev; USBBus bus; qemu_irq irq; MemoryRegion mem; @@ -446,6 +445,13 @@ struct EHCIState { uint32_t async_stepdown; }; +typedef struct EHCItfState { + union { + PCIDevice pcidev; + }; + struct EHCIState ehci; +} EHCIItfState; + #define SET_LAST_RUN_CLOCK(s) \ (s)->last_run_ns = qemu_get_clock_ns(vm_clock); @@ -2539,7 +2545,7 @@ static const MemoryRegionOps ehci_mmio_port_ops = { .endianness = DEVICE_LITTLE_ENDIAN, }; -static int usb_ehci_initfn(PCIDevice *dev); +static int usb_ehci_pci_initfn(PCIDevice *dev); static USBPortOps ehci_port_ops = { .attach = ehci_attach, @@ -2600,12 +2606,11 @@ static void usb_ehci_vm_state_change(void *opaque, int running, RunState state) } static const VMStateDescription vmstate_ehci = { - .name = "ehci", + .name = "ehci-core", .version_id = 2, .minimum_version_id = 1, .post_load = usb_ehci_post_load, .fields = (VMStateField[]) { - VMSTATE_PCI_DEVICE(dev, EHCIState), /* mmio registers */ VMSTATE_UINT32(usbcmd, EHCIState), VMSTATE_UINT32(usbsts, EHCIState), @@ -2636,8 +2641,19 @@ static const VMStateDescription vmstate_ehci = { } }; +static const VMStateDescription vmstate_ehci_pci = { + .name = "ehci", + .version_id = 2, + .minimum_version_id = 1, + .post_load = usb_ehci_post_load, + .fields = (VMStateField[]) { + VMSTATE_PCI_DEVICE(pcidev, EHCIItfState), + VMSTATE_STRUCT(ehci, EHCIItfState, 2, vmstate_ehci, EHCIState), + } +}; + static Property ehci_properties[] = { - DEFINE_PROP_UINT32("maxframes", EHCIState, maxframes, 128), + DEFINE_PROP_UINT32("maxframes", EHCIItfState, ehci.maxframes, 128), DEFINE_PROP_END_OF_LIST(), }; @@ -2657,23 +2673,33 @@ static void ehci_class_init(ObjectClass *klass, void *data) EHCIClass *k = (EHCIClass *)klass; EHCIClass *template = data; - k->pci.init = usb_ehci_initfn; - k->pci.vendor_id = template->pci.vendor_id; - k->pci.device_id = template->pci.device_id; /* ich4 */ - k->pci.revision = template->pci.revision; - k->pci.class_id = PCI_CLASS_SERIAL_USB; k->opregbase = template->opregbase; k->capabase = template->capabase; dc->vmsd = &vmstate_ehci; dc->props = ehci_properties; } +static void ehci_pci_class_init(ObjectClass *klass, void *data) +{ + /* FIXME: how do you do object check for a dynamic class? */ + PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); + EHCIClass *template = data; + + k->init = usb_ehci_pci_initfn; + k->vendor_id = template->pci.vendor_id; + k->device_id = template->pci.device_id; /* ich4 */ + k->revision = template->pci.revision; + k->class_id = PCI_CLASS_SERIAL_USB; + + ehci_class_init(klass, data); +} + static TypeInfo ehci_info[] = { { .name = "usb-ehci", .parent = TYPE_PCI_DEVICE, - .instance_size = sizeof(EHCIState), - .class_init = ehci_class_init, + .instance_size = sizeof(EHCIItfState), + .class_init = ehci_pci_class_init, .class_size = sizeof(EHCIClass), .class_data = (EHCIClass[]) {{{ .pci.vendor_id = PCI_VENDOR_ID_INTEL, @@ -2686,8 +2712,8 @@ static TypeInfo ehci_info[] = { }, { .name = "ich9-usb-ehci1", .parent = TYPE_PCI_DEVICE, - .instance_size = sizeof(EHCIState), - .class_init = ehci_class_init, + .instance_size = sizeof(EHCIItfState), + .class_init = ehci_pci_class_init, .class_size = sizeof(EHCIClass), .class_data = (EHCIClass[]) {{{ .pci.vendor_id = PCI_VENDOR_ID_INTEL, @@ -2700,42 +2726,12 @@ static TypeInfo ehci_info[] = { }, { .name = NULL } }; -static int usb_ehci_initfn(PCIDevice *dev) + +static void usb_ehci_initfn(EHCIState *s, DeviceState *dev) { - EHCIState *s = DO_UPCAST(EHCIState, dev, dev); EHCIClass *c = (EHCIClass *)object_get_class(OBJECT(dev)); - uint8_t *pci_conf = s->dev.config; int i; - pci_set_byte(&pci_conf[PCI_CLASS_PROG], 0x20); - - /* capabilities pointer */ - pci_set_byte(&pci_conf[PCI_CAPABILITY_LIST], 0x00); - //pci_set_byte(&pci_conf[PCI_CAPABILITY_LIST], 0x50); - - pci_set_byte(&pci_conf[PCI_INTERRUPT_PIN], 4); /* interrupt pin D */ - pci_set_byte(&pci_conf[PCI_MIN_GNT], 0); - pci_set_byte(&pci_conf[PCI_MAX_LAT], 0); - - // pci_conf[0x50] = 0x01; // power management caps - - pci_set_byte(&pci_conf[USB_SBRN], USB_RELEASE_2); // release number (2.1.4) - pci_set_byte(&pci_conf[0x61], 0x20); // frame length adjustment (2.1.5) - pci_set_word(&pci_conf[0x62], 0x00); // port wake up capability (2.1.6) - - pci_conf[0x64] = 0x00; - pci_conf[0x65] = 0x00; - pci_conf[0x66] = 0x00; - pci_conf[0x67] = 0x00; - pci_conf[0x68] = 0x01; - pci_conf[0x69] = 0x00; - pci_conf[0x6a] = 0x00; - pci_conf[0x6b] = 0x00; // USBLEGSUP - pci_conf[0x6c] = 0x00; - pci_conf[0x6d] = 0x00; - pci_conf[0x6e] = 0x00; - pci_conf[0x6f] = 0xc0; // USBLEFCTLSTS - s->opregbase = c->opregbase; /* 2.2 host controller interface version */ @@ -2752,11 +2748,7 @@ static int usb_ehci_initfn(PCIDevice *dev) s->caps[0x0a] = 0x00; s->caps[0x0b] = 0x00; - s->irq = s->dev.irq[3]; - - s->dma = pci_dma_context(dev); - - usb_bus_new(&s->bus, &ehci_bus_ops, &s->dev.qdev); + usb_bus_new(&s->bus, &ehci_bus_ops, dev); for(i = 0; i < NB_PORTS; i++) { usb_register_port(&s->bus, &s->ports[i], s, i, &ehci_port_ops, USB_SPEED_MASK_HIGH); @@ -2784,8 +2776,48 @@ static int usb_ehci_initfn(PCIDevice *dev) memory_region_add_subregion(&s->mem, s->opregbase, &s->mem_opreg); memory_region_add_subregion(&s->mem, s->opregbase + PORTSC_BEGIN, &s->mem_ports); +} + +static int usb_ehci_pci_initfn(PCIDevice *dev) +{ + EHCIItfState *i = DO_UPCAST(EHCIItfState, pcidev, dev); + EHCIState *s = &i->ehci; + uint8_t *pci_conf = dev->config; + + pci_set_byte(&pci_conf[PCI_CLASS_PROG], 0x20); + + /* capabilities pointer */ + pci_set_byte(&pci_conf[PCI_CAPABILITY_LIST], 0x00); + /* pci_set_byte(&pci_conf[PCI_CAPABILITY_LIST], 0x50); */ + + pci_set_byte(&pci_conf[PCI_INTERRUPT_PIN], 4); /* interrupt pin D */ + pci_set_byte(&pci_conf[PCI_MIN_GNT], 0); + pci_set_byte(&pci_conf[PCI_MAX_LAT], 0); + + /* pci_conf[0x50] = 0x01; *//* power management caps */ + + pci_set_byte(&pci_conf[USB_SBRN], USB_RELEASE_2); /* release # (2.1.4) */ + pci_set_byte(&pci_conf[0x61], 0x20); /* frame length adjustment (2.1.5) */ + pci_set_word(&pci_conf[0x62], 0x00); /* port wake up capability (2.1.6) */ + + pci_conf[0x64] = 0x00; + pci_conf[0x65] = 0x00; + pci_conf[0x66] = 0x00; + pci_conf[0x67] = 0x00; + pci_conf[0x68] = 0x01; + pci_conf[0x69] = 0x00; + pci_conf[0x6a] = 0x00; + pci_conf[0x6b] = 0x00; /* USBLEGSUP */ + pci_conf[0x6c] = 0x00; + pci_conf[0x6d] = 0x00; + pci_conf[0x6e] = 0x00; + pci_conf[0x6f] = 0xc0; /* USBLEFCTLSTS */ + + s->irq = dev->irq[3]; + s->dma = pci_dma_context(dev); - pci_register_bar(&s->dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->mem); + usb_ehci_initfn(s, DEVICE(dev)); + pci_register_bar(dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->mem); return 0; }