From patchwork Thu Oct 25 12:57:43 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 194160 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 1711A2C009B for ; Fri, 26 Oct 2012 00:43:05 +1100 (EST) Received: from localhost ([::1]:41282 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TRN1L-0007hP-7s for incoming@patchwork.ozlabs.org; Thu, 25 Oct 2012 08:58:47 -0400 Received: from eggs.gnu.org ([208.118.235.92]:44106) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TRN0d-00069i-7j for qemu-devel@nongnu.org; Thu, 25 Oct 2012 08:58:09 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1TRN0Y-0005I9-Rm for qemu-devel@nongnu.org; Thu, 25 Oct 2012 08:58:03 -0400 Received: from 38.0.169.217.in-addr.arpa ([217.169.0.38]:40618 helo=mnementh.archaic.org.uk) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TRN0Y-0005Ds-Kj for qemu-devel@nongnu.org; Thu, 25 Oct 2012 08:57:58 -0400 Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.72) (envelope-from ) id 1TRN0N-0001Qr-ST; Thu, 25 Oct 2012 13:57:47 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Date: Thu, 25 Oct 2012 13:57:43 +0100 Message-Id: <1351169867-5466-9-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.2.5 In-Reply-To: <1351169867-5466-1-git-send-email-peter.maydell@linaro.org> References: <1351169867-5466-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6 (newer, 2) X-Received-From: 217.169.0.38 Cc: patches@linaro.org Subject: [Qemu-devel] [PATCH 08/12] hw/arm_timer: Use LOG_GUEST_ERROR and LOG_UNIMP X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Use LOG_GUEST_ERROR to report guest accesses to bad register offsets, and LOG_UNIMP for access to the unimplemented test registers. Signed-off-by: Peter Maydell --- hw/arm_timer.c | 19 +++++++++++++------ 1 file changed, 13 insertions(+), 6 deletions(-) diff --git a/hw/arm_timer.c b/hw/arm_timer.c index 2e13621..af339d3 100644 --- a/hw/arm_timer.c +++ b/hw/arm_timer.c @@ -64,7 +64,8 @@ static uint32_t arm_timer_read(void *opaque, hwaddr offset) return 0; return s->int_level; default: - hw_error("%s: Bad offset %x\n", __func__, (int)offset); + qemu_log_mask(LOG_GUEST_ERROR, + "%s: Bad offset %x\n", __func__, (int)offset); return 0; } } @@ -131,7 +132,8 @@ static void arm_timer_write(void *opaque, hwaddr offset, arm_timer_recalibrate(s, 0); break; default: - hw_error("%s: Bad offset %x\n", __func__, (int)offset); + qemu_log_mask(LOG_GUEST_ERROR, + "%s: Bad offset %x\n", __func__, (int)offset); } arm_timer_update(s); } @@ -223,10 +225,14 @@ static uint64_t sp804_read(void *opaque, hwaddr offset, /* Integration Test control registers, which we won't support */ case 0xf00: /* TimerITCR */ case 0xf04: /* TimerITOP (strictly write only but..) */ + qemu_log_mask(LOG_UNIMP, + "%s: integration test registers unimplemented\n", + __func__); return 0; } - hw_error("%s: Bad offset %x\n", __func__, (int)offset); + qemu_log_mask(LOG_GUEST_ERROR, + "%s: Bad offset %x\n", __func__, (int)offset); return 0; } @@ -246,7 +252,8 @@ static void sp804_write(void *opaque, hwaddr offset, } /* Technically we could be writing to the Test Registers, but not likely */ - hw_error("%s: Bad offset %x\n", __func__, (int)offset); + qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset %x\n", + __func__, (int)offset); } static const MemoryRegionOps sp804_ops = { @@ -300,7 +307,7 @@ static uint64_t icp_pit_read(void *opaque, hwaddr offset, /* ??? Don't know the PrimeCell ID for this device. */ n = offset >> 8; if (n > 2) { - hw_error("%s: Bad timer %d\n", __func__, n); + qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad timer %d\n", __func__, n); } return arm_timer_read(s->timer[n], offset & 0xff); @@ -314,7 +321,7 @@ static void icp_pit_write(void *opaque, hwaddr offset, n = offset >> 8; if (n > 2) { - hw_error("%s: Bad timer %d\n", __func__, n); + qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad timer %d\n", __func__, n); } arm_timer_write(s->timer[n], offset & 0xff, value);