Patchwork [U-Boot,1/3] PPC: remove dead boards (AMX860, c2mon, ETX094, IAD210, LANTEC, SCM)

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Submitter Wolfgang Denk
Date Oct. 24, 2012, 12:36 p.m.
Message ID <1351082177-28351-2-git-send-email-wd@denx.de>
Download mbox | patch
Permalink /patch/193762/
State Accepted
Delegated to: Tom Rini
Headers show

Comments

Wolfgang Denk - Oct. 24, 2012, 12:36 p.m.
These boards have long reached EOL, and there has been no indication
of any active users of such hardware for years.  Get rid of the dead
weight.

Signed-off-by: Wolfgang Denk <wd@denx.de>
Cc: Wolfgang Grandegger <wg@denx.de>
---
 MAINTAINERS                          |    6 -
 README                               |    4 +-
 arch/powerpc/cpu/mpc8xx/fec.c        |    2 +-
 arch/powerpc/cpu/mpc8xx/scc.c        |   16 +-
 board/c2mon/Makefile                 |   44 ---
 board/c2mon/c2mon.c                  |  236 -----------
 board/c2mon/flash.c                  |  570 ---------------------------
 board/c2mon/pcmcia.c                 |  282 --------------
 board/c2mon/u-boot.lds               |  106 -----
 board/c2mon/u-boot.lds.debug         |  137 -------
 board/etx094/Makefile                |   44 ---
 board/etx094/etx094.c                |  384 ------------------
 board/etx094/flash.c                 |  687 --------------------------------
 board/etx094/u-boot.lds              |  107 -----
 board/lantec/Makefile                |   44 ---
 board/lantec/flash.c                 |  625 ------------------------------
 board/lantec/lantec.c                |  208 ----------
 board/lantec/u-boot.lds              |  107 -----
 board/lantec/u-boot.lds.debug        |  137 -------
 board/siemens/IAD210/IAD210.c        |  299 --------------
 board/siemens/IAD210/Makefile        |   44 ---
 board/siemens/IAD210/atm.c           |  652 -------------------------------
 board/siemens/IAD210/atm.h           |  287 --------------
 board/siemens/IAD210/flash.c         |  502 ------------------------
 board/siemens/IAD210/u-boot.lds      |  107 -----
 board/siemens/SCM/Makefile           |   49 ---
 board/siemens/SCM/flash.c            |  488 -----------------------
 board/siemens/SCM/fpga_scm.c         |  104 -----
 board/siemens/SCM/scm.c              |  541 --------------------------
 board/siemens/SCM/scm.h              |   89 -----
 board/siemens/common/README          |   27 --
 board/siemens/common/fpga.c          |  369 ------------------
 board/siemens/common/fpga.h          |   53 ---
 board/westel/amx860/Makefile         |   44 ---
 board/westel/amx860/amx860.c         |   93 -----
 board/westel/amx860/flash.c          |  637 ------------------------------
 board/westel/amx860/u-boot.lds       |  107 -----
 board/westel/amx860/u-boot.lds.debug |  138 -------
 boards.cfg                           |    7 -
 doc/README.scrapyard                 |    8 +-
 include/commproc.h                   |  131 +------
 include/configs/AMX860.h             |  299 --------------
 include/configs/ETX094.h             |  357 -----------------
 include/configs/IAD210.h             |  381 ------------------
 include/configs/LANTEC.h             |  358 -----------------
 include/configs/SCM.h                |  710 ----------------------------------
 include/configs/c2mon.h              |  417 --------------------
 include/pcmcia.h                     |    2 -
 include/status_led.h                 |   36 --
 post/cpu/mpc8xx/ether.c              |   45 +---
 50 files changed, 17 insertions(+), 11110 deletions(-)
 delete mode 100644 board/c2mon/Makefile
 delete mode 100644 board/c2mon/c2mon.c
 delete mode 100644 board/c2mon/flash.c
 delete mode 100644 board/c2mon/pcmcia.c
 delete mode 100644 board/c2mon/u-boot.lds
 delete mode 100644 board/c2mon/u-boot.lds.debug
 delete mode 100644 board/etx094/Makefile
 delete mode 100644 board/etx094/etx094.c
 delete mode 100644 board/etx094/flash.c
 delete mode 100644 board/etx094/u-boot.lds
 delete mode 100644 board/lantec/Makefile
 delete mode 100644 board/lantec/flash.c
 delete mode 100644 board/lantec/lantec.c
 delete mode 100644 board/lantec/u-boot.lds
 delete mode 100644 board/lantec/u-boot.lds.debug
 delete mode 100644 board/siemens/IAD210/IAD210.c
 delete mode 100644 board/siemens/IAD210/Makefile
 delete mode 100644 board/siemens/IAD210/atm.c
 delete mode 100644 board/siemens/IAD210/atm.h
 delete mode 100644 board/siemens/IAD210/flash.c
 delete mode 100644 board/siemens/IAD210/u-boot.lds
 delete mode 100644 board/siemens/SCM/Makefile
 delete mode 100644 board/siemens/SCM/flash.c
 delete mode 100644 board/siemens/SCM/fpga_scm.c
 delete mode 100644 board/siemens/SCM/scm.c
 delete mode 100644 board/siemens/SCM/scm.h
 delete mode 100644 board/siemens/common/README
 delete mode 100644 board/siemens/common/fpga.c
 delete mode 100644 board/siemens/common/fpga.h
 delete mode 100644 board/westel/amx860/Makefile
 delete mode 100644 board/westel/amx860/amx860.c
 delete mode 100644 board/westel/amx860/flash.c
 delete mode 100644 board/westel/amx860/u-boot.lds
 delete mode 100644 board/westel/amx860/u-boot.lds.debug
 delete mode 100644 include/configs/AMX860.h
 delete mode 100644 include/configs/ETX094.h
 delete mode 100644 include/configs/IAD210.h
 delete mode 100644 include/configs/LANTEC.h
 delete mode 100644 include/configs/SCM.h
 delete mode 100644 include/configs/c2mon.h

Patch

diff --git a/MAINTAINERS b/MAINTAINERS
index 1b2da94..2daee7d 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -104,8 +104,6 @@  Wolfgang Denk <wd@denx.de>
 
 	ARIA		MPC5121e
 
-	AMX860		MPC860
-	ETX094		MPC850
 	FPS850L		MPC850
 	FPS860L		MPC860
 	ICU862		MPC862
@@ -116,7 +114,6 @@  Wolfgang Denk <wd@denx.de>
 	IVMS8		MPC860
 	IVMS8_128	MPC860
 	IVMS8_256	MPC860
-	LANTEC		MPC850
 	LWMON		MPC823
 	R360MPI		MPC823
 	RRvision	MPC823
@@ -128,7 +125,6 @@  Wolfgang Denk <wd@denx.de>
 	TQM855L		MPC855
 	TQM860L		MPC860
 	TQM860L_FEC	MPC860
-	c2mon		MPC855
 	hermes		MPC860
 	lwmon		MPC823
 
@@ -227,7 +223,6 @@  Wolfgang Grandegger <wg@denx.de>
 
 	PN62		MPC8240
 	IPHASE4539	MPC8260
-	SCM		MPC8260
 
 Anatolij Gustschin <agust@denx.de>
 
@@ -543,7 +538,6 @@  Unknown / orphaned boards:
 	FADS850SAR	MPC8xx
 	FADS860T	MPC8xx
 	GENIETV		MPC8xx
-	IAD210		MPC8xx
 	MBX		MPC8xx
 	MBX860T		MPC8xx
 	NX823		MPC8xx
diff --git a/README b/README
index 69da2b8..4f16240 100644
--- a/README
+++ b/README
@@ -2182,8 +2182,8 @@  CBFS (Coreboot Filesystem) support
 		following board configurations are known to be
 		"pRAM-clean":
 
-			ETX094, IVMS8, IVML24, SPD8xx, TQM8xxL,
-			HERMES, IP860, RPXlite, LWMON, LANTEC,
+			IVMS8, IVML24, SPD8xx, TQM8xxL,
+			HERMES, IP860, RPXlite, LWMON,
 			FLAGADM, TQM8260
 
 - Error Recovery:
diff --git a/arch/powerpc/cpu/mpc8xx/fec.c b/arch/powerpc/cpu/mpc8xx/fec.c
index b348a98..d7c9090 100644
--- a/arch/powerpc/cpu/mpc8xx/fec.c
+++ b/arch/powerpc/cpu/mpc8xx/fec.c
@@ -460,7 +460,7 @@  static void fec_pin_init(int fecidx)
 
 #endif /* !CONFIG_RMII */
 
-#elif !defined(CONFIG_ICU862) && !defined(CONFIG_IAD210)
+#elif !defined(CONFIG_ICU862)
 		/*
 		 * Configure all of port D for MII.
 		 */
diff --git a/arch/powerpc/cpu/mpc8xx/scc.c b/arch/powerpc/cpu/mpc8xx/scc.c
index 2c93e24..2ef77b4 100644
--- a/arch/powerpc/cpu/mpc8xx/scc.c
+++ b/arch/powerpc/cpu/mpc8xx/scc.c
@@ -473,20 +473,6 @@  static int scc_init (struct eth_device *dev, bd_t * bis)
 	*((uint *) BCSR1) &= ~BCSR1_ETHEN;
 #endif /* MPC860ADS */
 
-#if defined(CONFIG_AMX860)
-	/*
-	 * Port B is used to control the PHY,MC68160.
-	 */
-	immr->im_cpm.cp_pbdir |=
-		(PB_ENET_ETHLOOP | PB_ENET_TPFLDL | PB_ENET_TPSQEL);
-
-	immr->im_cpm.cp_pbdat |= PB_ENET_TPFLDL;
-	immr->im_cpm.cp_pbdat &= ~(PB_ENET_ETHLOOP | PB_ENET_TPSQEL);
-
-	immr->im_ioport.iop_pddir |= PD_ENET_ETH_EN;
-	immr->im_ioport.iop_pddat &= ~PD_ENET_ETH_EN;
-#endif /* AMX860 */
-
 #ifdef CONFIG_RPXCLASSIC
 	*((uchar *) BCSR0) &= ~BCSR0_ETHLPBK;
 	*((uchar *) BCSR0) |= (BCSR0_ETHEN | BCSR0_COLTEST | BCSR0_FULLDPLX);
@@ -542,7 +528,7 @@  static int scc_init (struct eth_device *dev, bd_t * bis)
 	 */
 #if defined (CONFIG_FADS)
 	udelay (10000);		/* wait 10 ms */
-#elif defined (CONFIG_AMX860) || defined(CONFIG_RPXCLASSIC)
+#elif defined(CONFIG_RPXCLASSIC)
 	udelay (100000);	/* wait 100 ms */
 #endif
 
diff --git a/board/c2mon/Makefile b/board/c2mon/Makefile
deleted file mode 100644
index b49f26d..0000000
--- a/board/c2mon/Makefile
+++ /dev/null
@@ -1,44 +0,0 @@ 
-#
-# (C) Copyright 2001-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	= $(BOARD).o flash.o pcmcia.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
diff --git a/board/c2mon/c2mon.c b/board/c2mon/c2mon.c
deleted file mode 100644
index 348dfa0..0000000
--- a/board/c2mon/c2mon.c
+++ /dev/null
@@ -1,236 +0,0 @@ 
-/*
- * (C) Copyright 2001
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <mpc8xx.h>
-
-/* ------------------------------------------------------------------------- */
-
-static long int dram_size (long int, long int *, long int);
-
-/* ------------------------------------------------------------------------- */
-
-#define	_NOT_USED_	0xFFFFFFFF
-
-const uint sdram_table[] =
-{
-	/*
-	 * Single Read. (Offset 0 in UPMA RAM)
-	 */
-	0x1F07FC04, 0xEEAEFC04, 0x11ADFC04, 0xEFBBBC00,
-	0x1FF77C47, /* last */
-	/*
-	 * SDRAM Initialization (offset 5 in UPMA RAM)
-	 *
-	 * This is no UPM entry point. The following definition uses
-	 * the remaining space to establish an initialization
-	 * sequence, which is executed by a RUN command.
-	 *
-	 */
-		    0x1FF77C34, 0xEFEABC34, 0x1FB57C35, /* last */
-	/*
-	 * Burst Read. (Offset 8 in UPMA RAM)
-	 */
-	0x1F07FC04, 0xEEAEFC04, 0x10ADFC04, 0xF0AFFC00,
-	0xF0AFFC00, 0xF1AFFC00, 0xEFBBBC00, 0x1FF77C47, /* last */
-	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
-	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
-	/*
-	 * Single Write. (Offset 18 in UPMA RAM)
-	 */
-	0x1F07FC04, 0xEEAEBC00, 0x01B93C04, 0x1FF77C47, /* last */
-	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
-	/*
-	 * Burst Write. (Offset 20 in UPMA RAM)
-	 */
-	0x1F07FC04, 0xEEAEBC00, 0x10AD7C00, 0xF0AFFC00,
-	0xF0AFFC00, 0xE1BBBC04, 0x1FF77C47, /* last */
-					    _NOT_USED_,
-	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
-	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
-	/*
-	 * Refresh  (Offset 30 in UPMA RAM)
-	 */
-	0x1FF5FC84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
-	0xFFFFFC84, 0xFFFFFC07, /* last */
-				_NOT_USED_, _NOT_USED_,
-	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
-	/*
-	 * Exception. (Offset 3c in UPMA RAM)
-	 */
-	0x7FFFFC07, /* last */
-		    _NOT_USED_, _NOT_USED_, _NOT_USED_,
-};
-
-/* ------------------------------------------------------------------------- */
-
-
-/*
- * Check Board Identity:
- */
-
-int checkboard (void)
-{
-	char buf[64];
-	int i;
-	int l = getenv_f("serial#", buf, sizeof(buf));
-
-	puts ("Board: TTTech C2MON ");
-
-	for (i = 0; i < l;  ++i) {
-		if (buf[i] == ' ')
-			break;
-		putc (buf[i]);
-	}
-
-	putc ('\n');
-
-	return (0);
-}
-
-/* ------------------------------------------------------------------------- */
-
-phys_size_t initdram (int board_type)
-{
-	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
-	volatile memctl8xx_t *memctl = &immap->im_memctl;
-	unsigned long reg;
-	long int size8, size9;
-	long int size = 0;
-
-	upmconfig (UPMA, (uint *)sdram_table, sizeof(sdram_table) / sizeof(uint));
-
-	/*
-	 * Preliminary prescaler for refresh (depends on number of
-	 * banks): This value is selected for four cycles every 62.4 us
-	 * with two SDRAM banks or four cycles every 31.2 us with one
-	 * bank. It will be adjusted after memory sizing.
-	 */
-	memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_8K;
-
-	memctl->memc_mar = 0x00000088;
-
-	/*
-	 * Map controller bank 2 the SDRAM bank 2 at physical address 0.
-	 */
-	memctl->memc_or2 = CONFIG_SYS_OR2_PRELIM;
-	memctl->memc_br2 = CONFIG_SYS_BR2_PRELIM;
-
-	memctl->memc_mamr = CONFIG_SYS_MAMR_8COL & (~(MAMR_PTAE));	/* no refresh yet */
-
-	udelay (200);
-
-	/* perform SDRAM initializsation sequence */
-
-	memctl->memc_mcr = 0x80004105;	/* SDRAM bank 0 */
-	udelay (1);
-	memctl->memc_mcr = 0x80004230;	/* SDRAM bank 0 - execute twice */
-	udelay (1);
-
-	memctl->memc_mamr |= MAMR_PTAE;	/* enable refresh */
-
-	udelay (1000);
-
-	/*
-	 * Check Bank 0 Memory Size
-	 *
-	 * try 8 column mode
-	 */
-	size8 = dram_size (CONFIG_SYS_MAMR_8COL,
-			   SDRAM_BASE2_PRELIM,
-			   SDRAM_MAX_SIZE);
-
-	udelay (1000);
-
-	/*
-	 * try 9 column mode
-	 */
-	size9 = dram_size (CONFIG_SYS_MAMR_9COL,
-			   SDRAM_BASE2_PRELIM,
-			   SDRAM_MAX_SIZE);
-
-	if (size8 < size9) {		/* leave configuration at 9 columns */
-		size = size9;
-/*		debug ("SDRAM Bank 0 in 9 column mode: %ld MB\n", size >> 20);	*/
-	} else {			/* back to 8 columns            */
-		size = size8;
-		memctl->memc_mamr = CONFIG_SYS_MAMR_8COL;
-		udelay (500);
-/*		debug ("SDRAM Bank 0 in 8 column mode: %ld MB\n", size >> 20);	*/
-	}
-
-	udelay (1000);
-
-	/*
-	 * Adjust refresh rate depending on SDRAM type
-	 * For types > 128 MBit leave it at the current (fast) rate
-	 */
-	if (size < 0x02000000) {
-		/* reduce to 15.6 us (62.4 us / quad) */
-		memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_4K;
-		udelay (1000);
-	}
-
-	/*
-	 * Final mapping
-	 */
-	memctl->memc_or2 = ((-size) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM;
-	memctl->memc_br2 = (CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
-
-	/*
-	 * No bank 1
-	 *
-	 * invalidate bank
-	 */
-	memctl->memc_br3 = 0;
-
-	/* adjust refresh rate depending on SDRAM type, one bank */
-	reg = memctl->memc_mptpr;
-	reg >>= 1;			/* reduce to CONFIG_SYS_MPTPR_1BK_8K / _4K */
-	memctl->memc_mptpr = reg;
-
-	udelay (10000);
-
-	return (size);
-}
-
-/* ------------------------------------------------------------------------- */
-
-/*
- * Check memory range for valid RAM. A simple memory test determines
- * the actually available RAM size between addresses `base' and
- * `base + maxsize'. Some (not all) hardware errors are detected:
- * - short between address lines
- * - short between data lines
- */
-
-static long int dram_size (long int mamr_value, long int *base,
-						   long int maxsize)
-{
-	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
-	volatile memctl8xx_t *memctl = &immap->im_memctl;
-
-	memctl->memc_mamr = mamr_value;
-
-	return (get_ram_size(base, maxsize));
-}
diff --git a/board/c2mon/flash.c b/board/c2mon/flash.c
deleted file mode 100644
index d33cb6c..0000000
--- a/board/c2mon/flash.c
+++ /dev/null
@@ -1,570 +0,0 @@ 
-/*
- * (C) Copyright 2001
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <mpc8xx.h>
-
-#ifndef	CONFIG_ENV_ADDR
-#define CONFIG_ENV_ADDR	(CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
-#endif
-
-flash_info_t	flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
-
-/*-----------------------------------------------------------------------
- * Functions
- */
-static ulong flash_get_size (vu_long *addr, flash_info_t *info);
-static int write_word (flash_info_t *info, ulong dest, ulong data);
-static void flash_get_offsets (ulong base, flash_info_t *info);
-
-/*-----------------------------------------------------------------------
- */
-
-unsigned long flash_init (void)
-{
-	volatile immap_t     *immap  = (immap_t *)CONFIG_SYS_IMMR;
-	volatile memctl8xx_t *memctl = &immap->im_memctl;
-	unsigned long size_b0, size_b1;
-	int i;
-
-	/* Init: no FLASHes known */
-	for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
-		flash_info[i].flash_id = FLASH_UNKNOWN;
-	}
-
-	/* Static FLASH Bank configuration here - FIXME XXX */
-
-	size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
-
-	if (flash_info[0].flash_id == FLASH_UNKNOWN) {
-		printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
-			size_b0, size_b0<<20);
-	}
-
-	size_b1 = flash_get_size((vu_long *)FLASH_BASE1_PRELIM, &flash_info[1]);
-
-	if (size_b1 > size_b0) {
-		printf ("## ERROR: "
-			"Bank 1 (0x%08lx = %ld MB) > Bank 0 (0x%08lx = %ld MB)\n",
-			size_b1, size_b1<<20,
-			size_b0, size_b0<<20
-		);
-		flash_info[0].flash_id	= FLASH_UNKNOWN;
-		flash_info[1].flash_id	= FLASH_UNKNOWN;
-		flash_info[0].sector_count	= -1;
-		flash_info[1].sector_count	= -1;
-		flash_info[0].size		= 0;
-		flash_info[1].size		= 0;
-		return (0);
-	}
-
-	/* Remap FLASH according to real size */
-	memctl->memc_or0 = CONFIG_SYS_OR_TIMING_FLASH | (-size_b0 & OR_AM_MSK);
-	memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_V;
-
-	/* Re-do sizing to get full correct info */
-	size_b0 = flash_get_size((vu_long *)CONFIG_SYS_FLASH_BASE, &flash_info[0]);
-
-	flash_get_offsets (CONFIG_SYS_FLASH_BASE, &flash_info[0]);
-
-#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
-	/* monitor protection ON by default */
-	flash_protect(FLAG_PROTECT_SET,
-		      CONFIG_SYS_MONITOR_BASE,
-		      CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1,
-		      &flash_info[0]);
-#endif
-
-#ifdef	CONFIG_ENV_IS_IN_FLASH
-	/* ENV protection ON by default */
-	flash_protect(FLAG_PROTECT_SET,
-		      CONFIG_ENV_ADDR,
-		      CONFIG_ENV_ADDR+CONFIG_ENV_SIZE-1,
-		      &flash_info[0]);
-#endif
-
-	if (size_b1) {
-		memctl->memc_or1 = CONFIG_SYS_OR_TIMING_FLASH | (-size_b1 & 0xFFFF8000);
-		memctl->memc_br1 = ((CONFIG_SYS_FLASH_BASE + size_b0) & BR_BA_MSK) |
-				    BR_MS_GPCM | BR_V;
-
-		/* Re-do sizing to get full correct info */
-		size_b1 = flash_get_size((vu_long *)(CONFIG_SYS_FLASH_BASE + size_b0),
-					  &flash_info[1]);
-
-		flash_get_offsets (CONFIG_SYS_FLASH_BASE + size_b0, &flash_info[1]);
-
-#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
-		/* monitor protection ON by default */
-		flash_protect(FLAG_PROTECT_SET,
-			      CONFIG_SYS_MONITOR_BASE,
-			      CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1,
-			      &flash_info[1]);
-#endif
-
-#ifdef	CONFIG_ENV_IS_IN_FLASH
-		/* ENV protection ON by default */
-		flash_protect(FLAG_PROTECT_SET,
-			      CONFIG_ENV_ADDR,
-			      CONFIG_ENV_ADDR+CONFIG_ENV_SIZE-1,
-			      &flash_info[1]);
-#endif
-	} else {
-		memctl->memc_br1 = 0;		/* invalidate bank */
-
-		flash_info[1].flash_id = FLASH_UNKNOWN;
-		flash_info[1].sector_count = -1;
-	}
-
-	flash_info[0].size = size_b0;
-	flash_info[1].size = size_b1;
-
-	return (size_b0 + size_b1);
-}
-
-/*-----------------------------------------------------------------------
- */
-static void flash_get_offsets (ulong base, flash_info_t *info)
-{
-	int i;
-
-	/* set up sector start address table */
-	if (info->flash_id & FLASH_BTYPE) {
-		/* set sector offsets for bottom boot block type	*/
-		info->start[0] = base + 0x00000000;
-		info->start[1] = base + 0x00008000;
-		info->start[2] = base + 0x0000C000;
-		info->start[3] = base + 0x00010000;
-		for (i = 4; i < info->sector_count; i++) {
-			info->start[i] = base + (i * 0x00020000) - 0x00060000;
-		}
-	} else {
-		/* set sector offsets for top boot block type		*/
-		i = info->sector_count - 1;
-		info->start[i--] = base + info->size - 0x00008000;
-		info->start[i--] = base + info->size - 0x0000C000;
-		info->start[i--] = base + info->size - 0x00010000;
-		for (; i >= 0; i--) {
-			info->start[i] = base + i * 0x00020000;
-		}
-	}
-}
-
-/*-----------------------------------------------------------------------
- */
-void flash_print_info  (flash_info_t *info)
-{
-	int i;
-
-	if (info->flash_id == FLASH_UNKNOWN) {
-		printf ("missing or unknown FLASH type\n");
-		return;
-	}
-
-	switch (info->flash_id & FLASH_VENDMASK) {
-	case FLASH_MAN_AMD:	printf ("AMD ");		break;
-	case FLASH_MAN_FUJ:	printf ("FUJITSU ");		break;
-	default:		printf ("Unknown Vendor ");	break;
-	}
-
-	switch (info->flash_id & FLASH_TYPEMASK) {
-	case FLASH_AM400B:	printf ("AM29LV400B (4 Mbit, bottom boot sect)\n");
-				break;
-	case FLASH_AM400T:	printf ("AM29LV400T (4 Mbit, top boot sector)\n");
-				break;
-	case FLASH_AM800B:	printf ("AM29LV800B (8 Mbit, bottom boot sect)\n");
-				break;
-	case FLASH_AM800T:	printf ("AM29LV800T (8 Mbit, top boot sector)\n");
-				break;
-	case FLASH_AM160B:	printf ("AM29LV160B (16 Mbit, bottom boot sect)\n");
-				break;
-	case FLASH_AM160T:	printf ("AM29LV160T (16 Mbit, top boot sector)\n");
-				break;
-	case FLASH_AM320B:	printf ("AM29LV320B (32 Mbit, bottom boot sect)\n");
-				break;
-	case FLASH_AM320T:	printf ("AM29LV320T (32 Mbit, top boot sector)\n");
-				break;
-	default:		printf ("Unknown Chip Type\n");
-				break;
-	}
-
-	printf ("  Size: %ld MB in %d Sectors\n",
-		info->size >> 20, info->sector_count);
-
-	printf ("  Sector Start Addresses:");
-	for (i=0; i<info->sector_count; ++i) {
-		if ((i % 5) == 0)
-			printf ("\n   ");
-		printf (" %08lX%s",
-			info->start[i],
-			info->protect[i] ? " (RO)" : "     "
-		);
-	}
-	printf ("\n");
-	return;
-}
-
-/*-----------------------------------------------------------------------
- */
-
-
-/*-----------------------------------------------------------------------
- */
-
-/*
- * The following code cannot be run from FLASH!
- */
-
-static ulong flash_get_size (vu_long *addr, flash_info_t *info)
-{
-	short i;
-	ulong value;
-	ulong base = (ulong)addr;
-
-	/* Write auto select command: read Manufacturer ID */
-	addr[0x0555] = 0x00AA00AA;
-	addr[0x02AA] = 0x00550055;
-	addr[0x0555] = 0x00900090;
-
-	value = addr[0];
-
-	switch (value) {
-	case AMD_MANUFACT:
-		info->flash_id = FLASH_MAN_AMD;
-		break;
-	case FUJ_MANUFACT:
-		info->flash_id = FLASH_MAN_FUJ;
-		break;
-	default:
-		info->flash_id = FLASH_UNKNOWN;
-		info->sector_count = 0;
-		info->size = 0;
-		return (0);			/* no or unknown flash	*/
-	}
-
-	value = addr[1];			/* device ID		*/
-
-	switch (value) {
-	case AMD_ID_LV400T:
-		info->flash_id += FLASH_AM400T;
-		info->sector_count = 11;
-		info->size = 0x00100000;
-		break;				/* => 1 MB		*/
-
-	case AMD_ID_LV400B:
-		info->flash_id += FLASH_AM400B;
-		info->sector_count = 11;
-		info->size = 0x00100000;
-		break;				/* => 1 MB		*/
-
-	case AMD_ID_LV800T:
-		info->flash_id += FLASH_AM800T;
-		info->sector_count = 19;
-		info->size = 0x00200000;
-		break;				/* => 2 MB		*/
-
-	case AMD_ID_LV800B:
-		info->flash_id += FLASH_AM800B;
-		info->sector_count = 19;
-		info->size = 0x00200000;
-		break;				/* => 2 MB		*/
-
-	case AMD_ID_LV160T:
-		info->flash_id += FLASH_AM160T;
-		info->sector_count = 35;
-		info->size = 0x00400000;
-		break;				/* => 4 MB		*/
-
-	case AMD_ID_LV160B:
-		info->flash_id += FLASH_AM160B;
-		info->sector_count = 35;
-		info->size = 0x00400000;
-		break;				/* => 4 MB		*/
-#if 0	/* enable when device IDs are available */
-	case AMD_ID_LV320T:
-		info->flash_id += FLASH_AM320T;
-		info->sector_count = 67;
-		info->size = 0x00800000;
-		break;				/* => 8 MB		*/
-
-	case AMD_ID_LV320B:
-		info->flash_id += FLASH_AM320B;
-		info->sector_count = 67;
-		info->size = 0x00800000;
-		break;				/* => 8 MB		*/
-#endif
-	default:
-		info->flash_id = FLASH_UNKNOWN;
-		return (0);			/* => no or unknown flash */
-	}
-
-	/* set up sector start address table */
-	if (info->flash_id & FLASH_BTYPE) {
-		/* set sector offsets for bottom boot block type	*/
-		info->start[0] = base + 0x00000000;
-		info->start[1] = base + 0x00008000;
-		info->start[2] = base + 0x0000C000;
-		info->start[3] = base + 0x00010000;
-		for (i = 4; i < info->sector_count; i++) {
-			info->start[i] = base + (i * 0x00020000) - 0x00060000;
-		}
-	} else {
-		/* set sector offsets for top boot block type		*/
-		i = info->sector_count - 1;
-		info->start[i--] = base + info->size - 0x00008000;
-		info->start[i--] = base + info->size - 0x0000C000;
-		info->start[i--] = base + info->size - 0x00010000;
-		for (; i >= 0; i--) {
-			info->start[i] = base + i * 0x00020000;
-		}
-	}
-
-	/* check for protected sectors */
-	for (i = 0; i < info->sector_count; i++) {
-		/* read sector protection at sector address, (A7 .. A0) = 0x02 */
-		/* D0 = 1 if protected */
-		addr = (volatile unsigned long *)(info->start[i]);
-		info->protect[i] = addr[2] & 1;
-	}
-
-	/*
-	 * Prevent writes to uninitialized FLASH.
-	 */
-	if (info->flash_id != FLASH_UNKNOWN) {
-		addr = (volatile unsigned long *)info->start[0];
-
-		*addr = 0x00F000F0;	/* reset bank */
-	}
-
-	return (info->size);
-}
-
-
-/*-----------------------------------------------------------------------
- */
-
-int	flash_erase (flash_info_t *info, int s_first, int s_last)
-{
-	vu_long *addr = (vu_long*)(info->start[0]);
-	int flag, prot, sect, l_sect;
-	ulong start, now, last;
-
-	if ((s_first < 0) || (s_first > s_last)) {
-		if (info->flash_id == FLASH_UNKNOWN) {
-			printf ("- missing\n");
-		} else {
-			printf ("- no sectors to erase\n");
-		}
-		return 1;
-	}
-
-	if ((info->flash_id == FLASH_UNKNOWN) ||
-	    (info->flash_id > FLASH_AMD_COMP)) {
-		printf ("Can't erase unknown flash type %08lx - aborted\n",
-			info->flash_id);
-		return 1;
-	}
-
-	prot = 0;
-	for (sect=s_first; sect<=s_last; ++sect) {
-		if (info->protect[sect]) {
-			prot++;
-		}
-	}
-
-	if (prot) {
-		printf ("- Warning: %d protected sectors will not be erased!\n",
-			prot);
-	} else {
-		printf ("\n");
-	}
-
-	l_sect = -1;
-
-	/* Disable interrupts which might cause a timeout here */
-	flag = disable_interrupts();
-
-	addr[0x0555] = 0x00AA00AA;
-	addr[0x02AA] = 0x00550055;
-	addr[0x0555] = 0x00800080;
-	addr[0x0555] = 0x00AA00AA;
-	addr[0x02AA] = 0x00550055;
-
-	/* Start erase on unprotected sectors */
-	for (sect = s_first; sect<=s_last; sect++) {
-		if (info->protect[sect] == 0) {	/* not protected */
-			addr = (vu_long*)(info->start[sect]);
-			addr[0] = 0x00300030;
-			l_sect = sect;
-		}
-	}
-
-	/* re-enable interrupts if necessary */
-	if (flag)
-		enable_interrupts();
-
-	/* wait at least 80us - let's wait 1 ms */
-	udelay (1000);
-
-	/*
-	 * We wait for the last triggered sector
-	 */
-	if (l_sect < 0)
-		goto DONE;
-
-	start = get_timer (0);
-	last  = start;
-	addr = (vu_long*)(info->start[l_sect]);
-	while ((addr[0] & 0x00800080) != 0x00800080) {
-		if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
-			printf ("Timeout\n");
-			return 1;
-		}
-		/* show that we're waiting */
-		if ((now - last) > 1000) {	/* every second */
-			putc ('.');
-			last = now;
-		}
-	}
-
-DONE:
-	/* reset to read mode */
-	addr = (volatile unsigned long *)info->start[0];
-	addr[0] = 0x00F000F0;	/* reset bank */
-
-	printf (" done\n");
-	return 0;
-}
-
-/*-----------------------------------------------------------------------
- * Copy memory to flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-
-int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
-{
-	ulong cp, wp, data;
-	int i, l, rc;
-
-	wp = (addr & ~3);	/* get lower word aligned address */
-
-	/*
-	 * handle unaligned start bytes
-	 */
-	if ((l = addr - wp) != 0) {
-		data = 0;
-		for (i=0, cp=wp; i<l; ++i, ++cp) {
-			data = (data << 8) | (*(uchar *)cp);
-		}
-		for (; i<4 && cnt>0; ++i) {
-			data = (data << 8) | *src++;
-			--cnt;
-			++cp;
-		}
-		for (; cnt==0 && i<4; ++i, ++cp) {
-			data = (data << 8) | (*(uchar *)cp);
-		}
-
-		if ((rc = write_word(info, wp, data)) != 0) {
-			return (rc);
-		}
-		wp += 4;
-	}
-
-	/*
-	 * handle word aligned part
-	 */
-	while (cnt >= 4) {
-		data = 0;
-		for (i=0; i<4; ++i) {
-			data = (data << 8) | *src++;
-		}
-		if ((rc = write_word(info, wp, data)) != 0) {
-			return (rc);
-		}
-		wp  += 4;
-		cnt -= 4;
-	}
-
-	if (cnt == 0) {
-		return (0);
-	}
-
-	/*
-	 * handle unaligned tail bytes
-	 */
-	data = 0;
-	for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
-		data = (data << 8) | *src++;
-		--cnt;
-	}
-	for (; i<4; ++i, ++cp) {
-		data = (data << 8) | (*(uchar *)cp);
-	}
-
-	return (write_word(info, wp, data));
-}
-
-/*-----------------------------------------------------------------------
- * Write a word to Flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-static int write_word (flash_info_t *info, ulong dest, ulong data)
-{
-	vu_long *addr = (vu_long*)(info->start[0]);
-	ulong start;
-	int flag;
-
-	/* Check if Flash is (sufficiently) erased */
-	if ((*((vu_long *)dest) & data) != data) {
-		return (2);
-	}
-	/* Disable interrupts which might cause a timeout here */
-	flag = disable_interrupts();
-
-	addr[0x0555] = 0x00AA00AA;
-	addr[0x02AA] = 0x00550055;
-	addr[0x0555] = 0x00A000A0;
-
-	*((vu_long *)dest) = data;
-
-	/* re-enable interrupts if necessary */
-	if (flag)
-		enable_interrupts();
-
-	/* data polling for D7 */
-	start = get_timer (0);
-	while ((*((vu_long *)dest) & 0x00800080) != (data & 0x00800080)) {
-		if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
-			return (1);
-		}
-	}
-	return (0);
-}
-
-/*-----------------------------------------------------------------------
- */
diff --git a/board/c2mon/pcmcia.c b/board/c2mon/pcmcia.c
deleted file mode 100644
index 2267829..0000000
--- a/board/c2mon/pcmcia.c
+++ /dev/null
@@ -1,282 +0,0 @@ 
-#include <common.h>
-#include <mpc8xx.h>
-#include <pcmcia.h>
-
-#undef	CONFIG_PCMCIA
-
-#if	defined(CONFIG_CMD_PCMCIA)
-#define	CONFIG_PCMCIA
-#endif
-
-#if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_8xx_PCCARD)
-#define	CONFIG_PCMCIA
-#endif
-
-#ifdef	CONFIG_PCMCIA
-
-#define PCMCIA_BOARD_MSG "C2MON"
-
-static void cfg_ports (void)
-{
-	volatile immap_t	*immap;
-	volatile cpm8xx_t	*cp;
-	ushort sreg;
-
-	immap = (immap_t *)CONFIG_SYS_IMMR;
-	cp    = (cpm8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_cpm));
-
-	/*
-	* Configure Port C for TPS2211 PC-Card Power-Interface Switch
-	*
-	* Switch off all voltages, assert shutdown
-	*/
-	sreg = immap->im_ioport.iop_pcdat;
-	sreg |=  (TPS2211_VPPD0 | TPS2211_VPPD1);	/* VAVPP => Hi-Z */
-	sreg &= ~(TPS2211_VCCD0 | TPS2211_VCCD1);	/* 3V and 5V off */
-	immap->im_ioport.iop_pcdat = sreg;
-
-	immap->im_ioport.iop_pcpar &= ~(TPS2211_OUTPUTS);
-	immap->im_ioport.iop_pcdir |=   TPS2211_OUTPUTS;
-
-	debug ("Set Port C: PAR:     %04x DIR:     %04x DAT:     %04x\n",
-	       immap->im_ioport.iop_pcpar,
-	       immap->im_ioport.iop_pcdir,
-	       immap->im_ioport.iop_pcdat);
-
-	/*
-	* Configure Port B for TPS2211 PC-Card Power-Interface Switch
-	*
-	* Over-Current Input only
-	*/
-	cp->cp_pbpar &= ~(TPS2211_INPUTS);
-	cp->cp_pbdir &= ~(TPS2211_INPUTS);
-
-	debug ("Set Port B: PAR: %08x DIR: %08x DAT: %08x\n",
-	       cp->cp_pbpar, cp->cp_pbdir, cp->cp_pbdat);
-}
-
-int pcmcia_hardware_enable(int slot)
-{
-	volatile immap_t	*immap;
-	volatile cpm8xx_t	*cp;
-	volatile pcmconf8xx_t	*pcmp;
-	volatile sysconf8xx_t	*sysp;
-	uint reg, pipr, mask;
-	ushort sreg;
-	int i;
-
-	debug ("hardware_enable: " PCMCIA_BOARD_MSG " Slot %c\n", 'A'+slot);
-
-	udelay(10000);
-
-	immap = (immap_t *)CONFIG_SYS_IMMR;
-	sysp  = (sysconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_siu_conf));
-	pcmp  = (pcmconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia));
-	cp    = (cpm8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_cpm));
-
-	/* Configure Ports for TPS2211A PC-Card Power-Interface Switch */
-	cfg_ports ();
-
-	/*
-	* Configure SIUMCR to enable PCMCIA port B
-	* (VFLS[0:1] are not used for debugging, we connect FRZ# instead)
-	*/
-	sysp->sc_siumcr &= ~SIUMCR_DBGC11;	/* set DBGC to 00 */
-
-	/* clear interrupt state, and disable interrupts */
-	pcmp->pcmc_pscr =  PCMCIA_MASK(_slot_);
-	pcmp->pcmc_per &= ~PCMCIA_MASK(_slot_);
-
-	/*
-	* Disable interrupts, DMA, and PCMCIA buffers
-	* (isolate the interface) and assert RESET signal
-	*/
-	debug ("Disable PCMCIA buffers and assert RESET\n");
-	reg  = 0;
-	reg |= __MY_PCMCIA_GCRX_CXRESET;	/* active high */
-	reg |= __MY_PCMCIA_GCRX_CXOE;		/* active low  */
-	PCMCIA_PGCRX(_slot_) = reg;
-	udelay(500);
-
-	/*
-	* Make sure there is a card in the slot, then configure the interface.
-	*/
-	udelay(10000);
-	debug ("[%d] %s: PIPR(%p)=0x%x\n",
-	       __LINE__,__FUNCTION__,
-	       &(pcmp->pcmc_pipr),pcmp->pcmc_pipr);
-	if (pcmp->pcmc_pipr & (0x18000000 >> (slot << 4))) {
-		printf ("   No Card found\n");
-		return (1);
-	}
-
-	/*
-	* Power On: Set VAVCC to 3.3V or 5V, set VAVPP to Hi-Z
-	*/
-	mask = PCMCIA_VS1(slot) | PCMCIA_VS2(slot);
-	pipr = pcmp->pcmc_pipr;
-	debug ("PIPR: 0x%x ==> VS1=o%s, VS2=o%s\n",
-	       pipr,
-	       (reg&PCMCIA_VS1(slot))?"n":"ff",
-	       (reg&PCMCIA_VS2(slot))?"n":"ff");
-
-	sreg = immap->im_ioport.iop_pcdat;
-	if ((pipr & mask) == mask) {
-		sreg |=  (TPS2211_VPPD0 | TPS2211_VPPD1 |	/* VAVPP => Hi-Z */
-				TPS2211_VCCD1);			/* 5V on	*/
-		sreg &= ~(TPS2211_VCCD0);			/* 3V off	*/
-		puts (" 5.0V card found: ");
-	} else {
-		sreg |=  (TPS2211_VPPD0 | TPS2211_VPPD1 |	/* VAVPP => Hi-Z */
-				TPS2211_VCCD0);			/* 3V on	*/
-		sreg &= ~(TPS2211_VCCD1);			/* 5V off	*/
-		puts (" 3.3V card found: ");
-	}
-
-	debug ("\nPC DAT: %04x -> 3.3V %s 5.0V %s\n",
-	       sreg,
-	       ( (sreg & TPS2211_VCCD0) && !(sreg & TPS2211_VCCD1)) ? "on" : "off",
-	       (!(sreg & TPS2211_VCCD0) &&  (sreg & TPS2211_VCCD1)) ? "on" : "off"
-	      );
-
-	immap->im_ioport.iop_pcdat = sreg;
-
-	/*  Wait 500 ms; use this to check for over-current */
-	for (i=0; i<5000; ++i) {
-		if ((cp->cp_pbdat & TPS2211_OC) == 0) {
-			printf ("   *** Overcurrent - Safety shutdown ***\n");
-			immap->im_ioport.iop_pcdat &= ~(TPS2211_VCCD0|TPS2211_VCCD1);
-			return (1);
-		}
-		udelay (100);
-	}
-
-	debug ("Enable PCMCIA buffers and stop RESET\n");
-	reg  =  PCMCIA_PGCRX(_slot_);
-	reg &= ~__MY_PCMCIA_GCRX_CXRESET;	/* active high */
-	reg &= ~__MY_PCMCIA_GCRX_CXOE;		/* active low  */
-	PCMCIA_PGCRX(_slot_) = reg;
-
-	udelay(250000);	/* some cards need >150 ms to come up :-( */
-
-	debug ("# hardware_enable done\n");
-
-	return (0);
-}
-
-
-#if defined(CONFIG_CMD_PCMCIA)
-int pcmcia_hardware_disable(int slot)
-{
-	volatile immap_t	*immap;
-	volatile cpm8xx_t	*cp;
-	volatile pcmconf8xx_t	*pcmp;
-	u_long reg;
-
-	debug ("hardware_disable: " PCMCIA_BOARD_MSG " Slot %c\n", 'A'+slot);
-
-	immap = (immap_t *)CONFIG_SYS_IMMR;
-	pcmp  = (pcmconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia));
-
-	/* Configure PCMCIA General Control Register */
-	debug ("Disable PCMCIA buffers and assert RESET\n");
-	reg  = 0;
-	reg |= __MY_PCMCIA_GCRX_CXRESET;	/* active high */
-	reg |= __MY_PCMCIA_GCRX_CXOE;		/* active low  */
-	PCMCIA_PGCRX(_slot_) = reg;
-
-	/* ALl voltages off / Hi-Z */
-	immap->im_ioport.iop_pcdat |= (TPS2211_VPPD0 | TPS2211_VPPD1 |
-			TPS2211_VCCD0 | TPS2211_VCCD1 );
-
-	udelay(10000);
-
-	return (0);
-}
-#endif
-
-
-int pcmcia_voltage_set(int slot, int vcc, int vpp)
-{
-	volatile immap_t	*immap;
-	volatile pcmconf8xx_t	*pcmp;
-	u_long reg;
-	ushort sreg;
-
-	debug ("voltage_set: "
-			PCMCIA_BOARD_MSG
-			" Slot %c, Vcc=%d.%d, Vpp=%d.%d\n",
-	'A'+slot, vcc/10, vcc%10, vpp/10, vcc%10);
-
-	immap = (immap_t *)CONFIG_SYS_IMMR;
-	pcmp  = (pcmconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia));
-	/*
-	 * Disable PCMCIA buffers (isolate the interface)
-	 * and assert RESET signal
-	 */
-	debug ("Disable PCMCIA buffers and assert RESET\n");
-	reg  = PCMCIA_PGCRX(_slot_);
-	reg |= __MY_PCMCIA_GCRX_CXRESET;	/* active high */
-	reg |= __MY_PCMCIA_GCRX_CXOE;		/* active low  */
-	PCMCIA_PGCRX(_slot_) = reg;
-	udelay(500);
-
-	/*
-	* Configure Port C pins for
-	* 5 Volts Enable and 3 Volts enable,
-	* Turn all power pins to Hi-Z
-	*/
-	debug ("PCMCIA power OFF\n");
-	cfg_ports ();	/* Enables switch, but all in Hi-Z */
-
-	sreg  = immap->im_ioport.iop_pcdat;
-	sreg |= TPS2211_VPPD0 | TPS2211_VPPD1;		/* VAVPP always Hi-Z */
-
-	switch(vcc) {
-		case  0:			break;	/* Switch off		*/
-		case 33: sreg |=  TPS2211_VCCD0;	/* Switch on 3.3V	*/
-		sreg &= ~TPS2211_VCCD1;
-		break;
-		case 50: sreg &= ~TPS2211_VCCD0;	/* Switch on 5.0V	*/
-		sreg |=  TPS2211_VCCD1;
-		break;
-		default:			goto done;
-	}
-
-	/* Checking supported voltages */
-
-	debug ("PIPR: 0x%x --> %s\n",
-	       pcmp->pcmc_pipr,
-	       (pcmp->pcmc_pipr & 0x00008000) ? "only 5 V" : "can do 3.3V");
-
-	immap->im_ioport.iop_pcdat = sreg;
-
-#ifdef DEBUG
-{
-	char *s;
-
-	if ((sreg & TPS2211_VCCD0) && !(sreg & TPS2211_VCCD1)) {
-		s = "at 3.3V";
-	} else if (!(sreg & TPS2211_VCCD0) &&  (sreg & TPS2211_VCCD1)) {
-		s = "at 5.0V";
-	} else {
-		s = "down";
-	}
-	printf ("PCMCIA powered %s\n", s);
-}
-#endif
-
-done:
-	debug ("Enable PCMCIA buffers and stop RESET\n");
-	reg  =  PCMCIA_PGCRX(_slot_);
-	reg &= ~__MY_PCMCIA_GCRX_CXRESET;	/* active high */
-	reg &= ~__MY_PCMCIA_GCRX_CXOE;		/* active low  */
-	PCMCIA_PGCRX(_slot_) = reg;
-	udelay(500);
-
-	debug ("voltage_set: " PCMCIA_BOARD_MSG " Slot %c, DONE\n",
-	       slot+'A');
-	return (0);
-}
-
-#endif	/* CONFIG_PCMCIA */
diff --git a/board/c2mon/u-boot.lds b/board/c2mon/u-boot.lds
deleted file mode 100644
index b854c18..0000000
--- a/board/c2mon/u-boot.lds
+++ /dev/null
@@ -1,106 +0,0 @@ 
-/*
- * (C) Copyright 2001-2010
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_ARCH(powerpc)
-
-SECTIONS
-{
-  /* Read-only sections, merged into text segment: */
-  . = + SIZEOF_HEADERS;
-  .text      :
-  {
-    /* WARNING - the following is hand-optimized to fit within	*/
-    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
-
-    arch/powerpc/cpu/mpc8xx/start.o	(.text*)
-    arch/powerpc/cpu/mpc8xx/traps.o	(.text*)
-    arch/powerpc/cpu/mpc8xx/libmpc8xx.o	(.text*)
-    net/libnet.o			(.text*)
-
-    . = env_offset;
-    common/env_embedded.o		(.text*)
-
-    *(.text*)
-  }
-  _etext = .;
-  PROVIDE (etext = .);
-  .rodata    :
-  {
-    *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
-  }
-
-  /* Read-write section, merged into data segment: */
-  . = (. + 0x00FF) & 0xFFFFFF00;
-  _erotext = .;
-  PROVIDE (erotext = .);
-  .reloc   :
-  {
-    _GOT2_TABLE_ = .;
-    KEEP(*(.got2))
-    KEEP(*(.got))
-    PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4);
-    _FIXUP_TABLE_ = .;
-    KEEP(*(.fixup))
-  }
-  __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1;
-  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
-  .data    :
-  {
-    *(.data*)
-    *(.sdata*)
-  }
-  _edata  =  .;
-  PROVIDE (edata = .);
-
-  . = .;
-
-  . = ALIGN(4);
-  .u_boot_list : {
-	#include <u-boot.lst>
-  }
-
-
-  . = .;
-  __start___ex_table = .;
-  __ex_table : { *(__ex_table) }
-  __stop___ex_table = .;
-
-  . = ALIGN(256);
-  __init_begin = .;
-  .text.init : { *(.text.init) }
-  .data.init : { *(.data.init) }
-  . = ALIGN(256);
-  __init_end = .;
-
-  __bss_start = .;
-  .bss (NOLOAD)       :
-  {
-   *(.bss*)
-   *(.sbss*)
-   *(COMMON)
-   . = ALIGN(4);
-  }
-  __bss_end__ = . ;
-  PROVIDE (end = .);
-}
diff --git a/board/c2mon/u-boot.lds.debug b/board/c2mon/u-boot.lds.debug
deleted file mode 100644
index 92796e6..0000000
--- a/board/c2mon/u-boot.lds.debug
+++ /dev/null
@@ -1,137 +0,0 @@ 
-/*
- * (C) Copyright 2001
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_ARCH(powerpc)
-/* Do we need any of these for elf?
-   __DYNAMIC = 0;    */
-SECTIONS
-{
-  /* Read-only sections, merged into text segment: */
-  . = + SIZEOF_HEADERS;
-  .interp : { *(.interp) }
-  .hash          : { *(.hash)		}
-  .dynsym        : { *(.dynsym)		}
-  .dynstr        : { *(.dynstr)		}
-  .rel.text      : { *(.rel.text)		}
-  .rela.text     : { *(.rela.text)	}
-  .rel.data      : { *(.rel.data)		}
-  .rela.data     : { *(.rela.data)	}
-  .rel.rodata    : { *(.rel.rodata)	}
-  .rela.rodata   : { *(.rela.rodata)	}
-  .rel.got       : { *(.rel.got)		}
-  .rela.got      : { *(.rela.got)		}
-  .rel.ctors     : { *(.rel.ctors)	}
-  .rela.ctors    : { *(.rela.ctors)	}
-  .rel.dtors     : { *(.rel.dtors)	}
-  .rela.dtors    : { *(.rela.dtors)	}
-  .rel.bss       : { *(.rel.bss)		}
-  .rela.bss      : { *(.rela.bss)		}
-  .rel.plt       : { *(.rel.plt)		}
-  .rela.plt      : { *(.rela.plt)		}
-  .init          : { *(.init)	}
-  .plt : { *(.plt) }
-  .text      :
-  {
-    /* WARNING - the following is hand-optimized to fit within	*/
-    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
-
-    arch/powerpc/cpu/mpc8xx/start.o	(.text)
-    common/dlmalloc.o	(.text)
-    lib/vsprintf.o	(.text)
-    lib/crc32.o		(.text)
-
-    . = env_offset;
-    common/env_embedded.o(.text)
-
-    *(.text)
-    *(.got1)
-  }
-  _etext = .;
-  PROVIDE (etext = .);
-  .rodata    :
-  {
-    *(.rodata)
-    *(.rodata1)
-    *(.rodata.str1.4)
-    *(.eh_frame)
-  }
-  .fini      : { *(.fini)    } =0
-  .ctors     : { *(.ctors)   }
-  .dtors     : { *(.dtors)   }
-
-  /* Read-write section, merged into data segment: */
-  . = (. + 0x0FFF) & 0xFFFFF000;
-  _erotext = .;
-  PROVIDE (erotext = .);
-  .reloc   :
-  {
-    *(.got)
-    _GOT2_TABLE_ = .;
-    *(.got2)
-    _FIXUP_TABLE_ = .;
-    *(.fixup)
-  }
-  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
-  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
-  .data    :
-  {
-    *(.data)
-    *(.data1)
-    *(.sdata)
-    *(.sdata2)
-    *(.dynamic)
-    CONSTRUCTORS
-  }
-  _edata  =  .;
-  PROVIDE (edata = .);
-
-
-  . = ALIGN(4);
-  .u_boot_list : {
-	#include <u-boot.lst>
-  }
-
-
-  __start___ex_table = .;
-  __ex_table : { *(__ex_table) }
-  __stop___ex_table = .;
-
-  . = ALIGN(4096);
-  __init_begin = .;
-  .text.init : { *(.text.init) }
-  .data.init : { *(.data.init) }
-  . = ALIGN(4096);
-  __init_end = .;
-
-  __bss_start = .;
-  .bss       :
-  {
-   *(.sbss) *(.scommon)
-   *(.dynbss)
-   *(.bss)
-   *(COMMON)
-  }
-  __bss_end__ = . ;
-  PROVIDE (end = .);
-}
diff --git a/board/etx094/Makefile b/board/etx094/Makefile
deleted file mode 100644
index 6dc495c..0000000
--- a/board/etx094/Makefile
+++ /dev/null
@@ -1,44 +0,0 @@ 
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	= $(BOARD).o flash.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
diff --git a/board/etx094/etx094.c b/board/etx094/etx094.c
deleted file mode 100644
index abefe4a..0000000
--- a/board/etx094/etx094.c
+++ /dev/null
@@ -1,384 +0,0 @@ 
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <mpc8xx.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/* ------------------------------------------------------------------------- */
-
-static long int dram_size (long int, long int *, long int);
-static void read_hw_vers (void);
-
-/* ------------------------------------------------------------------------- */
-
-#define _NOT_USED_	0xFFFFFFFF
-
-const uint sdram_table[] = {
-
-	/* single read   (offset 0x00 in upm ram) */
-
-	0xEECEFC24, 0x100DFC24, 0xE02FBC04, 0x01AA7C04,
-	0x1FB5FC00, 0xFFFFFC05, _NOT_USED_, _NOT_USED_,
-
-	/* burst read    (offset 0x08 in upm ram) */
-
-	0xEECEFC24, 0x100DFC24, 0xE0FFBC04, 0x10FF7C04,
-	0xF0FFFC00, 0xF0FFFC00, 0xF0FFFC00, 0xFFFFFC00,
-	0xFFFFFC05, _NOT_USED_, _NOT_USED_, _NOT_USED_,
-	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
-
-	/* single write  (offset 0x18 in upm ram) */
-
-	0xEECEFC24, 0x100DFC24, 0xE02BBC04, 0x01A27C00,
-	0xEFAAFC04, 0x1FB5FC05, _NOT_USED_, _NOT_USED_,
-
-	/* burst write   (offset 0x20 in upm ram) */
-
-	0xEECEFC24, 0x103DFC24, 0xE0FBBC00, 0x10F77C00,
-	0xF0FFFC00, 0xF0FFFC00, 0xF0FFFC04, 0xFFFFFC05,
-
-	/* init part1      (offset 0x28 in upm ram) */
-
-	0xEFFAFC3C, 0x1FF4FC34, 0xEFFCBC34, 0x1FFC3C34,
-	0xFFFC3C35, _NOT_USED_, _NOT_USED_, _NOT_USED_,
-
-	/* refresh   (offset 0x30 in upm ram) */
-
-	0xEFFEBC0C, 0x1FFD7C04, 0xFFFFFC04, 0xFFFFFC05,
-
-	/* init part2     (offset 0x34 in upm ram) */
-
-	0xFFFEBC04, 0xEFFC3CB4, 0x1FFC3C34, 0xFFFC3C34,
-	0xFFFC3C34, 0xEFE83CB4, 0x1FB57C35, _NOT_USED_,
-
-	/* exception     (offset 0x3C in upm ram) */
-
-	0xFFFFFC05, _NOT_USED_, _NOT_USED_, _NOT_USED_,
-
-};
-
-/* ------------------------------------------------------------------------- */
-
-
-/*
- * Check Board Identity:
- *
- * Test ETX ID string (ETX_xxx...)
- *
- * Return 1 always.
- */
-
-int checkboard (void)
-{
-	char buf[64];
-	int i;
-	int l = getenv_f("serial#", buf, sizeof(buf));
-
-	puts ("Board: ");
-
-#ifdef SB_ETX094
-	gd->board_type = 0; /* 0 = 2SDRAM-Device */
-#else
-	gd->board_type = 1; /* 1 = 1SDRAM-Device */
-#endif
-
-	if (l < 0 || strncmp(buf, "ETX_", 4)) {
-		puts ("### No HW ID - assuming ETX_094\n");
-		read_hw_vers ();
-		return (0);
-	}
-
-	for (i = 0; i < l; ++i) {
-		if (buf[i] == ' ')
-			break;
-		putc(buf[i]);
-	}
-	putc ('\n');
-
-	read_hw_vers ();
-	return (0);
-}
-
-/* ------------------------------------------------------------------------- */
-
-phys_size_t initdram (int board_type)
-{
-	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
-	volatile memctl8xx_t *memctl = &immap->im_memctl;
-	long int size_b0, size_b1, size8, size9;
-
-	upmconfig (UPMA, (uint *) sdram_table,
-			   sizeof (sdram_table) / sizeof (uint));
-
-	/*
-	 * Preliminary prescaler for refresh (depends on number of
-	 * banks): This value is selected for four cycles every 62.4 us
-	 * with two SDRAM banks or four cycles every 31.2 us with one
-	 * bank. It will be adjusted after memory sizing.
-	 */
-	memctl->memc_mptpr = CONFIG_SYS_MPTPR_1BK_4K;	/* MPTPR_PTP_DIV32 0x0200 */
-
-	/* A3(SDRAM)=0      => Bursttype = Sequential
-	 * A2-A0(SDRAM)=010 => Burst length = 4
-	 * A4-A6(SDRAM)=010 => CasLat=2
-	 */
-	memctl->memc_mar = 0x00000088;
-
-	/*
-	 * Map controller banks 2 and 3 to the SDRAM banks 2 and 3 at
-	 * preliminary addresses - these have to be modified after the
-	 * SDRAM size has been determined.
-	 */
-	memctl->memc_or2 = CONFIG_SYS_OR2_PRELIM;
-	memctl->memc_br2 = CONFIG_SYS_BR2_PRELIM;
-
-	if (board_type == 0) {	/* "L" type boards have only one bank SDRAM */
-		memctl->memc_or3 = CONFIG_SYS_OR3_PRELIM;
-		memctl->memc_br3 = CONFIG_SYS_BR3_PRELIM;
-	}
-
-	memctl->memc_mamr = CONFIG_SYS_MAMR_8COL & (~(MAMR_PTAE));	/* no refresh yet */
-
-	udelay (200);
-
-	/* perform SDRAM initializsation sequence */
-
-	memctl->memc_mcr = 0x80004128;	/* SDRAM bank 0 (CS2) - Init Part 1 */
-	memctl->memc_mcr = 0x80004734;	/* SDRAM bank 0 (CS2) - Init Part 2 */
-	udelay (1);
-
-	if (board_type == 0) {		/* "L" type boards have only one bank SDRAM */
-		memctl->memc_mcr = 0x80006128;	/* SDRAM bank 1 (CS3) - Init Part 1 */
-		memctl->memc_mcr = 0x80006734;	/* SDRAM bank 1 (CS3) - Init Part 2 */
-		udelay (1);
-	}
-
-	memctl->memc_mamr |= MAMR_PTAE;	/* enable refresh */
-
-	udelay (1000);
-
-	/*
-	 * Check Bank 0 Memory Size for re-configuration
-	 *
-	 * try 8 column mode
-	 */
-	size8 = dram_size (CONFIG_SYS_MAMR_8COL, (long *) SDRAM_BASE2_PRELIM,
-					   SDRAM_MAX_SIZE);
-
-	udelay (1000);
-
-	/*
-	 * try 9 column mode
-	 */
-	size9 = dram_size (CONFIG_SYS_MAMR_9COL, (long *) SDRAM_BASE2_PRELIM,
-					   SDRAM_MAX_SIZE);
-
-	if (size8 < size9) {		/* leave configuration at 9 columns */
-		size_b0 = size9;
-/*	debug ("SDRAM Bank 0 in 9 column mode: %ld MB\n", size >> 20);	*/
-	} else {					/* back to 8 columns            */
-		size_b0 = size8;
-		memctl->memc_mamr = CONFIG_SYS_MAMR_8COL;
-		udelay (500);
-/*	debug ("SDRAM Bank 0 in 8 column mode: %ld MB\n", size >> 20);	*/
-	}
-
-	if (board_type == 0) {		/* "L" type boards have only one bank SDRAM */
-		/*
-		 * Check Bank 1 Memory Size
-		 * use current column settings
-		 * [9 column SDRAM may also be used in 8 column mode,
-		 *  but then only half the real size will be used.]
-		 */
-		size_b1 =
-				dram_size (memctl->memc_mamr, (long *) SDRAM_BASE3_PRELIM,
-						   SDRAM_MAX_SIZE);
-/*	debug ("SDRAM Bank 1: %ld MB\n", size8 >> 20);	*/
-	} else {
-		size_b1 = 0;
-	}
-
-	udelay (1000);
-
-	/*
-	 * Adjust refresh rate depending on SDRAM type, both banks
-	 * For types > 128 MBit leave it at the current (fast) rate
-	 */
-	if ((size_b0 < 0x02000000) && (size_b1 < 0x02000000)) {
-		/* reduce to 15.6 us (62.4 us / quad) */
-		memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_4K;	/*DIV16 */
-		udelay (1000);
-	}
-
-	/*
-	 * Final mapping: map bigger bank first
-	 */
-	if (size_b1 > size_b0) {	/* SDRAM Bank 1 is bigger - map first   */
-
-		memctl->memc_or3 = ((-size_b1) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM;
-		memctl->memc_br3 =
-			(CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
-
-		if (size_b0 > 0) {
-			/*
-			 * Position Bank 0 immediately above Bank 1
-			 */
-			memctl->memc_or2 =
-				((-size_b0) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM;
-			memctl->memc_br2 =
-				((CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V)
-				+ size_b1;
-		} else {
-			unsigned long reg;
-
-			/*
-			 * No bank 0
-			 *
-			 * invalidate bank
-			 */
-			memctl->memc_br2 = 0;
-
-			/* adjust refresh rate depending on SDRAM type, one bank */
-			reg = memctl->memc_mptpr;
-			reg >>= 1;	/* reduce to CONFIG_SYS_MPTPR_1BK_8K / _4K */
-			memctl->memc_mptpr = reg;
-		}
-
-	} else {			/* SDRAM Bank 0 is bigger - map first   */
-
-		memctl->memc_or2 = ((-size_b0) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM;
-		memctl->memc_br2 =
-				(CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
-
-		if (size_b1 > 0) {
-			/*
-			 * Position Bank 1 immediately above Bank 0
-			 */
-			memctl->memc_or3 =
-					((-size_b1) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM;
-			memctl->memc_br3 =
-					((CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V)
-					+ size_b0;
-		} else {
-			unsigned long reg;
-
-			/*
-			 * No bank 1
-			 *
-			 * invalidate bank
-			 */
-			memctl->memc_br3 = 0;
-
-			/* adjust refresh rate depending on SDRAM type, one bank */
-			reg = memctl->memc_mptpr;
-			reg >>= 1;	/* reduce to CONFIG_SYS_MPTPR_1BK_8K / _4K */
-			memctl->memc_mptpr = reg;
-		}
-	}
-
-	udelay (10000);
-
-	return (size_b0 + size_b1);
-}
-
-/* ------------------------------------------------------------------------- */
-
-/*
- * Check memory range for valid RAM. A simple memory test determines
- * the actually available RAM size between addresses `base' and
- * `base + maxsize'. Some (not all) hardware errors are detected:
- * - short between address lines
- * - short between data lines
- */
-
-static long int dram_size (long int mamr_value, long int *base,
-						   long int maxsize)
-{
-	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
-	volatile memctl8xx_t *memctl = &immap->im_memctl;
-
-	memctl->memc_mamr = mamr_value;
-
-	return (get_ram_size(base, maxsize));
-}
-
-/* ------------------------------------------------------------------------- */
-
-/* HW-ID Table (Bits: 2^9;2^7;2^5) */
-#define HW_ID_0 0x0000
-#define HW_ID_1 0x0020
-#define HW_ID_2 0x0080
-#define HW_ID_3 0x00a0
-#define HW_ID_4 0x0200
-#define HW_ID_5 0x0220
-#define HW_ID_6 0x0280
-#define HW_ID_7 0x02a0
-
-void read_hw_vers ()
-{
-	unsigned short rd_msk = 0x02A0;
-
-	/* HW-ID pin-definition */
-	volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
-
-	immr->im_ioport.iop_pddir &= ~(rd_msk);
-	immr->im_ioport.iop_pdpar &= ~(rd_msk);
-
-	/* debug printf("State of PD: %x\n",immr->im_ioport.iop_pddat); */
-
-	/* Check the HW-ID */
-	printf ("HW-Version: ");
-	switch (immr->im_ioport.iop_pddat & rd_msk) {
-	case HW_ID_0:
-		printf ("V0.1 - V0.3 / W97238-Q3162-A1-1-2\n");
-		break;
-	case HW_ID_1:
-		printf ("V0.9 / W50037-Q1-D6-1\n");
-		break;
-	case HW_ID_2:
-		printf ("NOT USED - assuming ID#2\n");
-		break;
-	case HW_ID_3:
-		printf ("NOT USED - assuming ID#3\n");
-		break;
-	case HW_ID_4:
-		printf ("NOT USED - assuming ID#4\n");
-		break;
-	case HW_ID_5:
-		printf ("NOT USED - assuming ID#5\n");
-		break;
-	case HW_ID_6:
-		printf ("NOT USED - assuming ID#6\n");
-		break;
-	case HW_ID_7:
-		printf ("NOT USED - assuming ID#7\n");
-		break;
-	default:
-		printf ("###Error###\n");
-		break;
-	}
-}
-
-/* ------------------------------------------------------------------------- */
diff --git a/board/etx094/flash.c b/board/etx094/flash.c
deleted file mode 100644
index 0958e73..0000000
--- a/board/etx094/flash.c
+++ /dev/null
@@ -1,687 +0,0 @@ 
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <mpc8xx.h>
-
-flash_info_t	flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
-
-/*-----------------------------------------------------------------------
- * Functions
- */
-static ulong flash_get_size(vu_long *addr, flash_info_t *info);
-static int write_word(flash_info_t *info, ulong dest, ulong data);
-static void flash_get_offsets(ulong base, flash_info_t *info);
-
-/*-----------------------------------------------------------------------
- */
-
-unsigned long flash_init(void)
-{
-	volatile immap_t     *immap  = (immap_t *)CONFIG_SYS_IMMR;
-	volatile memctl8xx_t *memctl = &immap->im_memctl;
-	unsigned long size_b0;
-	int i;
-
-	/* Init: no FLASHes known */
-	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i)
-		flash_info[i].flash_id = FLASH_UNKNOWN;
-
-	/* Static FLASH Bank configuration here - FIXME XXX */
-
-	size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
-
-	if (flash_info[0].flash_id == FLASH_UNKNOWN) {
-		printf("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
-			size_b0, size_b0<<20);
-	}
-
-	/* Remap FLASH according to real size */
-	memctl->memc_or0 = CONFIG_SYS_OR_TIMING_FLASH | (-size_b0 & 0xFFFF8000);
-#ifdef CONFIG_FLASH_16BIT
-	memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) |
-		BR_MS_GPCM | BR_V | BR_PS_16; /* 16 Bit data port */
-#else
-	memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) |
-		BR_MS_GPCM | BR_V;
-#endif
-
-	/* Re-do sizing to get full correct info */
-	size_b0 = flash_get_size((vu_long *)CONFIG_SYS_FLASH_BASE,
-			&flash_info[0]);
-
-	flash_get_offsets(CONFIG_SYS_FLASH_BASE, &flash_info[0]);
-
-#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
-	/* monitor protection ON by default */
-	flash_protect(FLAG_PROTECT_SET,
-		      CONFIG_SYS_MONITOR_BASE,
-		      CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1,
-		      &flash_info[0]);
-#endif
-
-	memctl->memc_br1 = 0;		/* invalidate bank 1 */
-
-	flash_info[0].size = size_b0;
-
-	return size_b0;
-}
-
-/*-----------------------------------------------------------------------
- */
-static void flash_get_offsets(ulong base, flash_info_t *info)
-{
-	int i;
-
-	if (info->flash_id == FLASH_UNKNOWN)
-		return;
-
-	if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) {
-		for (i = 0; i < info->sector_count; i++)
-			info->start[i] = base + (i * 0x00002000);
-
-		return;
-	}
-
-	/* set up sector start address table */
-	if (info->flash_id & FLASH_BTYPE) {
-		/* set sector offsets for bottom boot block type	*/
-#ifdef CONFIG_FLASH_16BIT
-		info->start[0] = base + 0x00000000;
-		info->start[1] = base + 0x00004000;
-		info->start[2] = base + 0x00006000;
-		info->start[3] = base + 0x00008000;
-		for (i = 4; i < info->sector_count; i++)
-			info->start[i] = base + (i * 0x00010000) - 0x00030000;
-#else
-		info->start[0] = base + 0x00000000;
-		info->start[1] = base + 0x00008000;
-		info->start[2] = base + 0x0000C000;
-		info->start[3] = base + 0x00010000;
-		for (i = 4; i < info->sector_count; i++)
-			info->start[i] = base + (i * 0x00020000) - 0x00060000;
-#endif
-	} else {
-		/* set sector offsets for top boot block type		*/
-		i = info->sector_count - 1;
-		info->start[i--] = base + info->size - 0x00008000;
-		info->start[i--] = base + info->size - 0x0000C000;
-		info->start[i--] = base + info->size - 0x00010000;
-		for (; i >= 0; i--)
-			info->start[i] = base + i * 0x00020000;
-	}
-}
-
-/*-----------------------------------------------------------------------
- */
-void flash_print_info(flash_info_t *info)
-{
-	int i;
-
-	if (info->flash_id == FLASH_UNKNOWN) {
-		printf("missing or unknown FLASH type\n");
-		return;
-	}
-
-	switch (info->flash_id & FLASH_VENDMASK) {
-	case FLASH_MAN_AMD:
-		printf("AMD ");
-		break;
-	case FLASH_MAN_FUJ:
-		printf("FUJITSU ");
-		break;
-	case FLASH_MAN_SST:
-		printf("SST ");
-		break;
-	case FLASH_MAN_STM:
-		printf("STM ");
-		break;
-	default:
-		printf("Unknown Vendor ");
-		break;
-	}
-
-	switch (info->flash_id & FLASH_TYPEMASK) {
-	case FLASH_AM400B:
-		printf("AM29LV400B (4 Mbit, bottom boot sect)\n");
-		break;
-	case FLASH_AM400T:
-		printf("AM29LV400T (4 Mbit, top boot sector)\n");
-		break;
-	case FLASH_AM800B:
-		printf("AM29LV800B (8 Mbit, bottom boot sect)\n");
-		break;
-	case FLASH_AM800T:
-		printf("AM29LV800T (8 Mbit, top boot sector)\n");
-		break;
-	case FLASH_AM160B:
-		printf("AM29LV160B (16 Mbit, bottom boot sect)\n");
-		break;
-	case FLASH_AM160T:
-		printf("AM29LV160T (16 Mbit, top boot sector)\n");
-		break;
-	case FLASH_AM320B:
-		printf("AM29LV320B (32 Mbit, bottom boot sect)\n");
-		break;
-	case FLASH_AM320T:
-		printf("AM29LV320T (32 Mbit, top boot sector)\n");
-		break;
-	case FLASH_SST200A:
-		printf("39xF200A (2M = 128K x 16)\n");
-		break;
-	case FLASH_SST400A:
-		printf("39xF400A (4M = 256K x 16)\n");
-		break;
-	case FLASH_SST800A:
-		printf("39xF800A (8M = 512K x 16)\n");
-		break;
-	case FLASH_STM800AB:
-		printf("M29W800AB (8M = 512K x 16)\n");
-		break;
-	default:
-		printf("Unknown Chip Type\n");
-		break;
-	}
-
-	printf("  Size: %ld MB in %d Sectors\n",
-		info->size >> 20, info->sector_count);
-
-	printf("  Sector Start Addresses:");
-	for (i = 0; i < info->sector_count; ++i) {
-		if ((i % 5) == 0)
-			printf("\n   ");
-		printf(" %08lX%s",
-			info->start[i],
-			info->protect[i] ? " (RO)" : "     "
-		);
-	}
-	printf("\n");
-	return;
-}
-
-/*
- * The following code cannot be run from FLASH!
- */
-
-static ulong flash_get_size(vu_long *addr, flash_info_t *info)
-{
-	short i;
-	ulong value;
-	ulong base = (ulong)addr;
-
-	/* Write auto select command: read Manufacturer ID */
-#ifdef CONFIG_FLASH_16BIT
-	vu_short *s_addr = (vu_short *)addr;
-	s_addr[0x5555] = 0x00AA;
-	s_addr[0x2AAA] = 0x0055;
-	s_addr[0x5555] = 0x0090;
-	value = s_addr[0];
-	value = value|(value<<16);
-#else
-	addr[0x5555] = 0x00AA00AA;
-	addr[0x2AAA] = 0x00550055;
-	addr[0x5555] = 0x00900090;
-	value = addr[0];
-#endif
-
-	switch (value) {
-	case AMD_MANUFACT:
-		info->flash_id = FLASH_MAN_AMD;
-		break;
-	case FUJ_MANUFACT:
-		info->flash_id = FLASH_MAN_FUJ;
-		break;
-	case SST_MANUFACT:
-		info->flash_id = FLASH_MAN_SST;
-		break;
-	case STM_MANUFACT:
-		info->flash_id = FLASH_MAN_STM;
-		break;
-	default:
-		info->flash_id = FLASH_UNKNOWN;
-		info->sector_count = 0;
-		info->size = 0;
-		return 0;			/* no or unknown flash	*/
-	}
-#ifdef CONFIG_FLASH_16BIT
-	value = s_addr[1];
-	value = value|(value<<16);
-#else
-	value = addr[1];			/* device ID		*/
-#endif
-
-	switch (value) {
-	case AMD_ID_LV400T:
-		info->flash_id += FLASH_AM400T;
-		info->sector_count = 11;
-		info->size = 0x00100000;
-		break;				/* => 1 MB		*/
-
-	case AMD_ID_LV400B:
-		info->flash_id += FLASH_AM400B;
-		info->sector_count = 11;
-		info->size = 0x00100000;
-		break;				/* => 1 MB		*/
-
-	case AMD_ID_LV800T:
-		info->flash_id += FLASH_AM800T;
-		info->sector_count = 19;
-		info->size = 0x00200000;
-		break;				/* => 2 MB		*/
-
-	case AMD_ID_LV800B:
-		info->flash_id += FLASH_AM800B;
-#ifdef CONFIG_FLASH_16BIT
-		info->sector_count = 19;
-		info->size = 0x00100000;	/* => 1 MB */
-#else
-		info->sector_count = 19;
-		info->size = 0x00200000;	/* => 2 MB	*/
-#endif
-		break;
-
-	case AMD_ID_LV160T:
-		info->flash_id += FLASH_AM160T;
-		info->sector_count = 35;
-		info->size = 0x00400000;
-		break;				/* => 4 MB		*/
-
-	case AMD_ID_LV160B:
-		info->flash_id += FLASH_AM160B;
-#ifdef CONFIG_FLASH_16BIT
-		info->sector_count = 35;
-		info->size = 0x00200000;	/* => 2 MB	*/
-#else
-		info->sector_count = 35;
-		info->size = 0x00400000;	/* => 4 MB	*/
-#endif
-
-		break;
-	case SST_ID_xF200A:
-		info->flash_id += FLASH_SST200A;
-		info->sector_count = 64;	/* 39xF200A (2M = 128K x 16) */
-		info->size = 0x00080000;
-		break;
-	case SST_ID_xF400A:
-		info->flash_id += FLASH_SST400A;
-		info->sector_count = 128;	/* 39xF400A (4M = 256K x 16) */
-		info->size = 0x00100000;
-		break;
-	case SST_ID_xF800A:
-		info->flash_id += FLASH_SST800A;
-		info->sector_count = 256;	/* 39xF800A (8M = 512K x 16) */
-		info->size = 0x00200000;
-		break;				/* => 2 MB		*/
-	case STM_ID_x800AB:
-		info->flash_id += FLASH_STM800AB;
-		info->sector_count = 19;
-		info->size = 0x00200000;
-		break;				/* => 2 MB		*/
-	default:
-		info->flash_id = FLASH_UNKNOWN;
-		return 0;			/* => no or unknown flash */
-
-	}
-
-	if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) {
-		printf("** ERROR: sector count %d > max (%d) **\n",
-			info->sector_count, CONFIG_SYS_MAX_FLASH_SECT);
-		info->sector_count = CONFIG_SYS_MAX_FLASH_SECT;
-	}
-
-	if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) {
-		for (i = 0; i < info->sector_count; i++)
-			info->start[i] = base + (i * 0x00002000);
-	} else {	/* AMD and Fujitsu types */
-		/* set up sector start address table */
-		if (info->flash_id & FLASH_BTYPE) {
-			/* set sector offsets for bottom boot block type */
-#ifdef CONFIG_FLASH_16BIT
-
-			info->start[0] = base + 0x00000000;
-			info->start[1] = base + 0x00004000;
-			info->start[2] = base + 0x00006000;
-			info->start[3] = base + 0x00008000;
-			for (i = 4; i < info->sector_count; i++)
-				info->start[i] = base +
-					(i * 0x00010000) - 0x00030000;
-#else
-			info->start[0] = base + 0x00000000;
-			info->start[1] = base + 0x00008000;
-			info->start[2] = base + 0x0000C000;
-			info->start[3] = base + 0x00010000;
-			for (i = 4; i < info->sector_count; i++)
-				info->start[i] = base +
-					(i * 0x00020000) - 0x00060000;
-#endif
-		} else {
-			/* set sector offsets for top boot block type	*/
-			i = info->sector_count - 1;
-			info->start[i--] = base + info->size - 0x00008000;
-			info->start[i--] = base + info->size - 0x0000C000;
-			info->start[i--] = base + info->size - 0x00010000;
-			for (; i >= 0; i--)
-				info->start[i] = base + i * 0x00020000;
-		}
-
-		/* check for protected sectors */
-		for (i = 0; i < info->sector_count; i++) {
-			/*
-			 * read sector protection at sector address:
-			 * (A7 .. A0) = 0x02
-			 * D0 = 1 if protected
-			 */
-#ifdef CONFIG_FLASH_16BIT
-			s_addr = (volatile unsigned short *)(info->start[i]);
-			info->protect[i] = s_addr[2] & 1;
-#else
-			addr = (volatile unsigned long *)(info->start[i]);
-			info->protect[i] = addr[2] & 1;
-#endif
-		}
-	}
-
-	/*
-	 * Prevent writes to uninitialized FLASH.
-	 */
-	if (info->flash_id != FLASH_UNKNOWN) {
-#ifdef CONFIG_FLASH_16BIT
-		s_addr = (volatile unsigned short *)(info->start[0]);
-		*s_addr = 0x00F0;	/* reset bank */
-#else
-		addr = (volatile unsigned long *)info->start[0];
-		*addr = 0x00F000F0;	/* reset bank */
-#endif
-
-	}
-	return info->size;
-}
-
-int	flash_erase(flash_info_t *info, int s_first, int s_last)
-{
-	vu_long *addr = (vu_long *)(info->start[0]);
-	int flag, prot, sect;
-	ulong start, now, last;
-#ifdef CONFIG_FLASH_16BIT
-	vu_short *s_addr = (vu_short *)addr;
-#endif
-
-	if ((s_first < 0) || (s_first > s_last)) {
-		if (info->flash_id == FLASH_UNKNOWN)
-			printf("- missing\n");
-		else
-			printf("- no sectors to erase\n");
-		return 1;
-	}
-/*#ifndef CONFIG_FLASH_16BIT
-	ulong type;
-	type = (info->flash_id & FLASH_VENDMASK);
-	if ((type != FLASH_MAN_SST) && (type != FLASH_MAN_STM)) {
-		printf ("Can't erase unknown flash type %08lx - aborted\n",
-			info->flash_id);
-		return;
-	}
-#endif*/
-	prot = 0;
-	for (sect = s_first; sect <= s_last; ++sect) {
-		if (info->protect[sect])
-			prot++;
-	}
-
-	if (prot) {
-		printf("- Warning: %d protected sectors will not be erased!\n",
-			prot);
-	} else {
-		printf("\n");
-	}
-
-	start = get_timer(0);
-	last  = start;
-	/* Start erase on unprotected sectors */
-	for (sect = s_first; sect <= s_last; sect++) {
-		if (info->protect[sect] == 0) {	/* not protected */
-#ifdef CONFIG_FLASH_16BIT
-			vu_short *s_sect_addr = (vu_short *)(info->start[sect]);
-#else
-			vu_long	*sect_addr = (vu_long *)(info->start[sect]);
-#endif
-			/* Disable interrupts which might cause a timeout */
-			flag = disable_interrupts();
-
-#ifdef CONFIG_FLASH_16BIT
-
-			/*printf("\ns_sect_addr=%x",s_sect_addr);*/
-			s_addr[0x5555] = 0x00AA;
-			s_addr[0x2AAA] = 0x0055;
-			s_addr[0x5555] = 0x0080;
-			s_addr[0x5555] = 0x00AA;
-			s_addr[0x2AAA] = 0x0055;
-			s_sect_addr[0] = 0x0030;
-#else
-			addr[0x5555] = 0x00AA00AA;
-			addr[0x2AAA] = 0x00550055;
-			addr[0x5555] = 0x00800080;
-			addr[0x5555] = 0x00AA00AA;
-			addr[0x2AAA] = 0x00550055;
-			sect_addr[0] = 0x00300030;
-#endif
-			/* re-enable interrupts if necessary */
-			if (flag)
-				enable_interrupts();
-
-			/* wait at least 80us - let's wait 1 ms */
-			udelay(1000);
-
-#ifdef CONFIG_FLASH_16BIT
-			while ((s_sect_addr[0] & 0x0080) != 0x0080) {
-#else
-			while ((sect_addr[0] & 0x00800080) != 0x00800080) {
-#endif
-				now = get_timer(start);
-				if (now > CONFIG_SYS_FLASH_ERASE_TOUT) {
-					printf("Timeout\n");
-					return 1;
-				}
-				/* show every second that we're waiting */
-				if ((now - last) > 1000) {
-					putc('.');
-					last = now;
-				}
-			}
-		}
-	}
-
-	/* reset to read mode */
-	addr = (volatile unsigned long *)info->start[0];
-#ifdef CONFIG_FLASH_16BIT
-	s_addr[0] = 0x00F0;	/* reset bank */
-#else
-	addr[0] = 0x00F000F0;	/* reset bank */
-#endif
-
-	printf(" done\n");
-	return 0;
-}
-
-/*-----------------------------------------------------------------------
- * Copy memory to flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- * 4 - Flash not identified
- */
-
-int write_buff(flash_info_t *info, uchar *src, ulong addr, ulong cnt)
-{
-	ulong cp, wp, data;
-	int i, l, rc;
-
-	if (info->flash_id == FLASH_UNKNOWN)
-		return 4;
-
-	wp = (addr & ~3);	/* get lower word aligned address */
-
-	/*
-	 * handle unaligned start bytes
-	 */
-	l = addr - wp;
-
-	if (l != 0) {
-		data = 0;
-		for (i = 0, cp = wp; i < l; ++i, ++cp)
-			data = (data << 8) | (*(uchar *)cp);
-
-		for (; i < 4 && cnt > 0; ++i) {
-			data = (data << 8) | *src++;
-			--cnt;
-			++cp;
-		}
-		for (; cnt == 0 && i < 4; ++i, ++cp)
-			data = (data << 8) | (*(uchar *)cp);
-
-		rc = write_word(info, wp, data);
-
-		if (rc != 0)
-			return rc;
-
-		wp += 4;
-	}
-
-	/*
-	 * handle word aligned part
-	 */
-	while (cnt >= 4) {
-		data = 0;
-		for (i = 0; i < 4; ++i)
-			data = (data << 8) | *src++;
-
-		rc = write_word(info, wp, data);
-		if (rc != 0)
-			return rc;
-
-		wp  += 4;
-		cnt -= 4;
-	}
-
-	if (cnt == 0)
-		return 0;
-
-	/*
-	 * handle unaligned tail bytes
-	 */
-	data = 0;
-	for (i = 0, cp = wp; i < 4 && cnt > 0; ++i, ++cp) {
-		data = (data << 8) | *src++;
-		--cnt;
-	}
-	for (; i < 4; ++i, ++cp)
-		data = (data << 8) | (*(uchar *)cp);
-
-	return write_word(info, wp, data);
-}
-
-/*-----------------------------------------------------------------------
- * Write a word to Flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-static int write_word(flash_info_t *info, ulong dest, ulong data)
-{
-	vu_long *addr = (vu_long *)(info->start[0]);
-
-#ifdef CONFIG_FLASH_16BIT
-	vu_short high_data;
-	vu_short low_data;
-	vu_short *s_addr = (vu_short *)addr;
-#endif
-	ulong start;
-	int flag;
-
-	/* Check if Flash is (sufficiently) erased */
-	if ((*((vu_long *)dest) & data) != data)
-		return 2;
-
-#ifdef CONFIG_FLASH_16BIT
-	/* Write the 16 higher-bits */
-	/* Disable interrupts which might cause a timeout here */
-	flag = disable_interrupts();
-
-	high_data = ((data>>16) & 0x0000ffff);
-
-	s_addr[0x5555] = 0x00AA;
-	s_addr[0x2AAA] = 0x0055;
-	s_addr[0x5555] = 0x00A0;
-
-	*((vu_short *)dest) = high_data;
-
-	/* re-enable interrupts if necessary */
-	if (flag)
-		enable_interrupts();
-
-	/* data polling for D7 */
-	start = get_timer(0);
-	while ((*((vu_short *)dest) & 0x0080) != (high_data & 0x0080)) {
-		if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT)
-			return 1;
-	}
-
-	/* Write the 16 lower-bits */
-#endif
-
-	/* Disable interrupts which might cause a timeout here */
-	flag = disable_interrupts();
-#ifdef CONFIG_FLASH_16BIT
-	dest += 0x2;
-	low_data = (data & 0x0000ffff);
-
-	s_addr[0x5555] = 0x00AA;
-	s_addr[0x2AAA] = 0x0055;
-	s_addr[0x5555] = 0x00A0;
-	*((vu_short *)dest) = low_data;
-
-#else
-	addr[0x5555] = 0x00AA00AA;
-	addr[0x2AAA] = 0x00550055;
-	addr[0x5555] = 0x00A000A0;
-	*((vu_long *)dest) = data;
-#endif
-
-	/* re-enable interrupts if necessary */
-	if (flag)
-		enable_interrupts();
-
-	/* data polling for D7 */
-	start = get_timer(0);
-
-#ifdef CONFIG_FLASH_16BIT
-	while ((*((vu_short *)dest) & 0x0080) != (low_data & 0x0080)) {
-#else
-	while ((*((vu_long *)dest) & 0x00800080) != (data & 0x00800080)) {
-#endif
-
-		if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT)
-			return 1;
-	}
-	return 0;
-}
diff --git a/board/etx094/u-boot.lds b/board/etx094/u-boot.lds
deleted file mode 100644
index 56c3470..0000000
--- a/board/etx094/u-boot.lds
+++ /dev/null
@@ -1,107 +0,0 @@ 
-/*
- * (C) Copyright 2000-2010
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_ARCH(powerpc)
-
-SECTIONS
-{
-  /* Read-only sections, merged into text segment: */
-  . = + SIZEOF_HEADERS;
-  .text      :
-  {
-    /* WARNING - the following is hand-optimized to fit within	*/
-    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
-
-    arch/powerpc/cpu/mpc8xx/start.o	(.text*)
-    arch/powerpc/cpu/mpc8xx/traps.o	(.text*)
-    net/libnet.o			(.text*)
-    arch/powerpc/cpu/mpc8xx/libmpc8xx.o	(.text*)
-    *(.text.vsprintf)
-
-    . = env_offset;
-    common/env_embedded.o		(.text*)
-
-    *(.text*)
-  }
-  _etext = .;
-  PROVIDE (etext = .);
-  .rodata    :
-  {
-    *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
-  }
-
-  /* Read-write section, merged into data segment: */
-  . = (. + 0x00FF) & 0xFFFFFF00;
-  _erotext = .;
-  PROVIDE (erotext = .);
-  .reloc   :
-  {
-    _GOT2_TABLE_ = .;
-    KEEP(*(.got2))
-    KEEP(*(.got))
-    PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4);
-    _FIXUP_TABLE_ = .;
-    KEEP(*(.fixup))
-  }
-  __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1;
-  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
-  .data    :
-  {
-    *(.data*)
-    *(.sdata*)
-  }
-  _edata  =  .;
-  PROVIDE (edata = .);
-
-  . = .;
-
-  . = ALIGN(4);
-  .u_boot_list : {
-	#include <u-boot.lst>
-  }
-
-
-  . = .;
-  __start___ex_table = .;
-  __ex_table : { *(__ex_table) }
-  __stop___ex_table = .;
-
-  . = ALIGN(256);
-  __init_begin = .;
-  .text.init : { *(.text.init) }
-  .data.init : { *(.data.init) }
-  . = ALIGN(256);
-  __init_end = .;
-
-  __bss_start = .;
-  .bss (NOLOAD)       :
-  {
-   *(.bss*)
-   *(.sbss*)
-   *(COMMON)
-   . = ALIGN(4);
-  }
-  __bss_end__ = . ;
-  PROVIDE (end = .);
-}
diff --git a/board/lantec/Makefile b/board/lantec/Makefile
deleted file mode 100644
index 12e4aa6..0000000
--- a/board/lantec/Makefile
+++ /dev/null
@@ -1,44 +0,0 @@ 
-#
-# (C) Copyright 2001-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	= $(BOARD).o flash.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
diff --git a/board/lantec/flash.c b/board/lantec/flash.c
deleted file mode 100644
index 97ed054..0000000
--- a/board/lantec/flash.c
+++ /dev/null
@@ -1,625 +0,0 @@ 
-/*
- * (C) Copyright 2000, 2001
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * Derived from ../tqm8xx/flash.c
- * [Torsten Stevens, FHG IMS; Bruno Achauer, Exet AG]
- */
-
-#include <common.h>
-#include <mpc8xx.h>
-
-#if defined(CONFIG_ENV_IS_IN_FLASH)
-# ifndef  CONFIG_ENV_ADDR
-#  define CONFIG_ENV_ADDR	(CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
-# endif
-# ifndef  CONFIG_ENV_SIZE
-#  define CONFIG_ENV_SIZE	CONFIG_ENV_SECT_SIZE
-# endif
-# ifndef  CONFIG_ENV_SECT_SIZE
-#  define CONFIG_ENV_SECT_SIZE  CONFIG_ENV_SIZE
-# endif
-#endif
-
-/*---------------------------------------------------------------------*/
-#undef DEBUG_FLASH
-
-#ifdef DEBUG_FLASH
-#define DEBUGF(fmt,args...) printf(fmt ,##args)
-#else
-#define DEBUGF(fmt,args...)
-#endif
-/*---------------------------------------------------------------------*/
-
-flash_info_t	flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
-
-/*-----------------------------------------------------------------------
- * Functions
- */
-static ulong flash_get_size (vu_long *addr, flash_info_t *info);
-static int write_word (flash_info_t *info, ulong dest, ulong data);
-static void flash_get_offsets (ulong base, flash_info_t *info);
-
-/*-----------------------------------------------------------------------
- */
-
-unsigned long flash_init (void)
-{
-	volatile immap_t     *immap  = (immap_t *)CONFIG_SYS_IMMR;
-	volatile memctl8xx_t *memctl = &immap->im_memctl;
-	unsigned long size_b0, size_b1;
-	int i;
-
-	/* Init: no FLASHes known */
-	for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
-		flash_info[i].flash_id = FLASH_UNKNOWN;
-	}
-
-	/* Static FLASH Bank configuration here - FIXME XXX */
-
-	DEBUGF("\n## Get flash bank 1 size @ 0x%08x\n",FLASH_BASE0_PRELIM);
-
-	size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
-
-	if (flash_info[0].flash_id == FLASH_UNKNOWN) {
-		printf ("## Unknown FLASH on Bank 0: "
-			"ID 0x%lx, Size = 0x%08lx = %ld MB\n",
-			flash_info[0].flash_id,
-			size_b0, size_b0<<20);
-	}
-
-	DEBUGF("## Get flash bank 2 size @ 0x%08x\n",FLASH_BASE5_PRELIM);
-
-	size_b1 = flash_get_size((vu_long *)FLASH_BASE5_PRELIM, &flash_info[1]);
-
-	DEBUGF("## Prelim. Flash bank sizes: %08lx + 0x%08lx\n",size_b0,size_b1);
-
-	if (size_b1 > size_b0) {
-		printf ("## ERROR: "
-			"Bank 1 (0x%08lx = %ld MB) > Bank 0 (0x%08lx = %ld MB)\n",
-			size_b1, size_b1<<20,
-			size_b0, size_b0<<20
-		);
-		flash_info[0].flash_id	= FLASH_UNKNOWN;
-		flash_info[1].flash_id	= FLASH_UNKNOWN;
-		flash_info[0].sector_count	= -1;
-		flash_info[1].sector_count	= -1;
-		flash_info[0].size		= 0;
-		flash_info[1].size		= 0;
-		return (0);
-	}
-
-	DEBUGF ("## Before remap: "
-		"BR0: 0x%08x    OR0: 0x%08x    "
-		"BR1: 0x%08x    OR1: 0x%08x\n",
-		memctl->memc_br0, memctl->memc_or0,
-		memctl->memc_br1, memctl->memc_or1);
-
-	/* Remap FLASH according to real size */
-	memctl->memc_or0 = CONFIG_SYS_OR_TIMING_FLASH | (-size_b0 & 0xFFFF8000);
-	memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | \
-				BR_MS_GPCM | BR_PS_32 | BR_V;
-
-	DEBUGF("## BR0: 0x%08x    OR0: 0x%08x\n",
-		memctl->memc_br0, memctl->memc_or0);
-
-	/* Re-do sizing to get full correct info */
-	size_b0 = flash_get_size((vu_long *)CONFIG_SYS_FLASH_BASE, &flash_info[0]);
-
-	flash_get_offsets (CONFIG_SYS_FLASH_BASE, &flash_info[0]);
-
-	flash_info[0].size = size_b0;
-
-#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
-	/* monitor protection ON by default */
-	flash_protect(FLAG_PROTECT_SET,
-		      CONFIG_SYS_MONITOR_BASE,
-		      CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1,
-		      &flash_info[0]);
-#endif
-
-#ifdef	CONFIG_ENV_IS_IN_FLASH
-	/* ENV protection ON by default */
-	flash_protect(FLAG_PROTECT_SET,
-		      CONFIG_ENV_ADDR,
-		      CONFIG_ENV_ADDR+CONFIG_ENV_SECT_SIZE-1,
-		      &flash_info[0]);
-#endif
-
-	if (size_b1) {
-		memctl->memc_or5 = CONFIG_SYS_OR_TIMING_FLASH | (-size_b1 & 0xFFFF8000);
-		memctl->memc_br5 = ((CONFIG_SYS_FLASH_BASE + size_b0) & BR_BA_MSK) |
-				    BR_MS_GPCM | BR_PS_32 | BR_V;
-
-		DEBUGF("## BR5: 0x%08x    OR5: 0x%08x\n",
-			memctl->memc_br5, memctl->memc_or5);
-
-		/* Re-do sizing to get full correct info */
-		size_b1 = flash_get_size((vu_long *)(CONFIG_SYS_FLASH_BASE + size_b0),
-					  &flash_info[1]);
-
-		flash_info[1].size = size_b1;
-
-		flash_get_offsets (CONFIG_SYS_FLASH_BASE + size_b0, &flash_info[1]);
-
-#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
-		/* monitor protection ON by default */
-		flash_protect(FLAG_PROTECT_SET,
-			      CONFIG_SYS_MONITOR_BASE,
-			      CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1,
-			      &flash_info[1]);
-#endif
-
-#ifdef	CONFIG_ENV_IS_IN_FLASH
-		/* ENV protection ON by default */
-		flash_protect(FLAG_PROTECT_SET,
-			      CONFIG_ENV_ADDR,
-			      CONFIG_ENV_ADDR+CONFIG_ENV_SECT_SIZE-1,
-			      &flash_info[1]);
-#endif
-	} else {
-		memctl->memc_br5 = 0;		/* invalidate bank */
-		memctl->memc_or5 = 0;		/* invalidate bank */
-
-		DEBUGF("## DISABLE BR5: 0x%08x    OR5: 0x%08x\n",
-			memctl->memc_br5, memctl->memc_or5);
-
-		flash_info[1].flash_id = FLASH_UNKNOWN;
-		flash_info[1].sector_count = -1;
-		flash_info[1].size = 0;
-	}
-
-	DEBUGF("## Final Flash bank sizes: %08lx + 0x%08lx\n",size_b0,size_b1);
-
-	return (size_b0 + size_b1);
-}
-
-/*-----------------------------------------------------------------------
- */
-static void flash_get_offsets (ulong base, flash_info_t *info)
-{
-	int i;
-
-	/* set up sector start address table */
-	if (info->flash_id & FLASH_BTYPE) {
-		/* set sector offsets for bottom boot block type	*/
-		info->start[0] = base + 0x00000000;
-		info->start[1] = base + 0x00008000;
-		info->start[2] = base + 0x0000C000;
-		info->start[3] = base + 0x00010000;
-		for (i = 4; i < info->sector_count; i++) {
-			info->start[i] = base + (i * 0x00020000) - 0x00060000;
-		}
-	} else {
-		/* set sector offsets for top boot block type		*/
-		i = info->sector_count - 1;
-		info->start[i--] = base + info->size - 0x00008000;
-		info->start[i--] = base + info->size - 0x0000C000;
-		info->start[i--] = base + info->size - 0x00010000;
-		for (; i >= 0; i--) {
-			info->start[i] = base + i * 0x00020000;
-		}
-	}
-
-}
-
-/*-----------------------------------------------------------------------
- */
-void flash_print_info  (flash_info_t *info)
-{
-	int i;
-
-	if (info->flash_id == FLASH_UNKNOWN) {
-		printf ("missing or unknown FLASH type\n");
-		return;
-	}
-
-	switch (info->flash_id & FLASH_VENDMASK) {
-	case FLASH_MAN_AMD:	printf ("AMD ");		break;
-	case FLASH_MAN_FUJ:	printf ("FUJITSU ");		break;
-	default:		printf ("Unknown Vendor ");	break;
-	}
-
-	switch (info->flash_id & FLASH_TYPEMASK) {
-	case FLASH_AM400B:	printf ("AM29LV400B (4 Mbit, bottom boot sect)\n");
-				break;
-	case FLASH_AM400T:	printf ("AM29LV400T (4 Mbit, top boot sector)\n");
-				break;
-	case FLASH_AM800B:	printf ("AM29LV800B (8 Mbit, bottom boot sect)\n");
-				break;
-	case FLASH_AM800T:	printf ("AM29LV800T (8 Mbit, top boot sector)\n");
-				break;
-	case FLASH_AM160B:	printf ("AM29LV160B (16 Mbit, bottom boot sect)\n");
-				break;
-	case FLASH_AM160T:	printf ("AM29LV160T (16 Mbit, top boot sector)\n");
-				break;
-	case FLASH_AM320B:	printf ("AM29LV320B (32 Mbit, bottom boot sect)\n");
-				break;
-	case FLASH_AM320T:	printf ("AM29LV320T (32 Mbit, top boot sector)\n");
-				break;
-	default:		printf ("Unknown Chip Type\n");
-				break;
-	}
-
-	printf ("  Size: %ld MB in %d Sectors\n",
-		info->size >> 20, info->sector_count);
-
-	printf ("  Sector Start Addresses:");
-	for (i=0; i<info->sector_count; ++i) {
-		if ((i % 5) == 0)
-			printf ("\n   ");
-		printf (" %08lX%s",
-			info->start[i],
-			info->protect[i] ? " (RO)" : "     "
-		);
-	}
-	printf ("\n");
-	return;
-}
-
-/*-----------------------------------------------------------------------
- */
-
-
-/*-----------------------------------------------------------------------
- */
-
-/*
- * The following code cannot be run from FLASH!
- */
-
-static ulong flash_get_size (vu_long *addr, flash_info_t *info)
-{
-	short i;
-	ulong value;
-	ulong base = (ulong)addr;
-
-
-	/* Write auto select command: read Manufacturer ID */
-	addr[0x0555] = 0x00AA00AA;
-	addr[0x02AA] = 0x00550055;
-	addr[0x0555] = 0x00900090;
-
-	value = addr[0];
-
-	switch (value) {
-	case AMD_MANUFACT:
-		info->flash_id = FLASH_MAN_AMD;
-		break;
-	case FUJ_MANUFACT:
-		info->flash_id = FLASH_MAN_FUJ;
-		break;
-	default:
-		info->flash_id = FLASH_UNKNOWN;
-		info->sector_count = 0;
-		info->size = 0;
-		return (0);			/* no or unknown flash	*/
-	}
-
-	value = addr[1];			/* device ID		*/
-
-	switch (value) {
-	case AMD_ID_LV400T:
-		info->flash_id += FLASH_AM400T;
-		info->sector_count = 11;
-		info->size = 0x00100000;
-		break;				/* => 1 MB		*/
-
-	case AMD_ID_LV400B:
-		info->flash_id += FLASH_AM400B;
-		info->sector_count = 11;
-		info->size = 0x00100000;
-		break;				/* => 1 MB		*/
-
-	case AMD_ID_LV800T:
-		info->flash_id += FLASH_AM800T;
-		info->sector_count = 19;
-		info->size = 0x00200000;
-		break;				/* => 2 MB		*/
-
-	case AMD_ID_LV800B:
-		info->flash_id += FLASH_AM800B;
-		info->sector_count = 19;
-		info->size = 0x00200000;
-		break;				/* => 2 MB		*/
-
-	case AMD_ID_LV160T:
-		info->flash_id += FLASH_AM160T;
-		info->sector_count = 35;
-		info->size = 0x00400000;
-		break;				/* => 4 MB		*/
-
-	case AMD_ID_LV160B:
-		info->flash_id += FLASH_AM160B;
-		info->sector_count = 35;
-		info->size = 0x00400000;
-		break;				/* => 4 MB		*/
-#if 0	/* enable when device IDs are available */
-	case AMD_ID_LV320T:
-		info->flash_id += FLASH_AM320T;
-		info->sector_count = 67;
-		info->size = 0x00800000;
-		break;				/* => 8 MB		*/
-
-	case AMD_ID_LV320B:
-		info->flash_id += FLASH_AM320B;
-		info->sector_count = 67;
-		info->size = 0x00800000;
-		break;				/* => 8 MB		*/
-#endif
-	default:
-		info->flash_id = FLASH_UNKNOWN;
-		return (0);			/* => no or unknown flash */
-
-	}
-
-	/* set up sector start address table */
-	if (info->flash_id & FLASH_BTYPE) {
-		/* set sector offsets for bottom boot block type	*/
-		info->start[0] = base + 0x00000000;
-		info->start[1] = base + 0x00008000;
-		info->start[2] = base + 0x0000C000;
-		info->start[3] = base + 0x00010000;
-		for (i = 4; i < info->sector_count; i++) {
-			info->start[i] = base + (i * 0x00020000) - 0x00060000;
-		}
-	} else {
-		/* set sector offsets for top boot block type		*/
-		i = info->sector_count - 1;
-		info->start[i--] = base + info->size - 0x00008000;
-		info->start[i--] = base + info->size - 0x0000C000;
-		info->start[i--] = base + info->size - 0x00010000;
-		for (; i >= 0; i--) {
-			info->start[i] = base + i * 0x00020000;
-		}
-	}
-
-	/* check for protected sectors */
-	for (i = 0; i < info->sector_count; i++) {
-		/* read sector protection at sector address, (A7 .. A0) = 0x02 */
-		/* D0 = 1 if protected */
-		addr = (volatile unsigned long *)(info->start[i]);
-		info->protect[i] = addr[2] & 1;
-	}
-
-	/*
-	 * Prevent writes to uninitialized FLASH.
-	 */
-	if (info->flash_id != FLASH_UNKNOWN) {
-		addr = (volatile unsigned long *)info->start[0];
-
-		*addr = 0x00F000F0;	/* reset bank */
-	}
-
-	return (info->size);
-}
-
-
-/*-----------------------------------------------------------------------
- */
-
-int	flash_erase (flash_info_t *info, int s_first, int s_last)
-{
-	vu_long *addr = (vu_long*)(info->start[0]);
-	int flag, prot, sect, l_sect;
-	ulong start, now, last;
-
-	if ((s_first < 0) || (s_first > s_last)) {
-		if (info->flash_id == FLASH_UNKNOWN) {
-			printf ("- missing\n");
-		} else {
-			printf ("- no sectors to erase\n");
-		}
-		return 1;
-	}
-
-	if ((info->flash_id == FLASH_UNKNOWN) ||
-	    (info->flash_id > FLASH_AMD_COMP)) {
-		printf ("Can't erase unknown flash type %08lx - aborted\n",
-			info->flash_id);
-		return 1;
-	}
-
-	prot = 0;
-	for (sect=s_first; sect<=s_last; ++sect) {
-		if (info->protect[sect]) {
-			prot++;
-		}
-	}
-
-	if (prot) {
-		printf ("- Warning: %d protected sectors will not be erased!\n",
-			prot);
-	} else {
-		printf ("\n");
-	}
-
-	l_sect = -1;
-
-	/* Disable interrupts which might cause a timeout here */
-	flag = disable_interrupts();
-
-	addr[0x0555] = 0x00AA00AA;
-	addr[0x02AA] = 0x00550055;
-	addr[0x0555] = 0x00800080;
-	addr[0x0555] = 0x00AA00AA;
-	addr[0x02AA] = 0x00550055;
-
-	/* Start erase on unprotected sectors */
-	for (sect = s_first; sect<=s_last; sect++) {
-		if (info->protect[sect] == 0) {	/* not protected */
-			addr = (vu_long*)(info->start[sect]);
-			addr[0] = 0x00300030;
-			l_sect = sect;
-		}
-	}
-
-	/* re-enable interrupts if necessary */
-	if (flag)
-		enable_interrupts();
-
-	/* wait at least 80us - let's wait 1 ms */
-	udelay (1000);
-
-	/*
-	 * We wait for the last triggered sector
-	 */
-	if (l_sect < 0)
-		goto DONE;
-
-	start = get_timer (0);
-	last  = start;
-	addr = (vu_long*)(info->start[l_sect]);
-	while ((addr[0] & 0x00800080) != 0x00800080) {
-		if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
-			printf ("Timeout\n");
-			return 1;
-		}
-		/* show that we're waiting */
-		if ((now - last) > 1000) {	/* every second */
-			putc ('.');
-			last = now;
-		}
-	}
-
-DONE:
-	/* reset to read mode */
-	addr = (volatile unsigned long *)info->start[0];
-	addr[0] = 0x00F000F0;	/* reset bank */
-
-	printf (" done\n");
-	return 0;
-}
-
-/*-----------------------------------------------------------------------
- * Copy memory to flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-
-int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
-{
-	ulong cp, wp, data;
-	int i, l, rc;
-
-	wp = (addr & ~3);	/* get lower word aligned address */
-
-	/*
-	 * handle unaligned start bytes
-	 */
-	if ((l = addr - wp) != 0) {
-		data = 0;
-		for (i=0, cp=wp; i<l; ++i, ++cp) {
-			data = (data << 8) | (*(uchar *)cp);
-		}
-		for (; i<4 && cnt>0; ++i) {
-			data = (data << 8) | *src++;
-			--cnt;
-			++cp;
-		}
-		for (; cnt==0 && i<4; ++i, ++cp) {
-			data = (data << 8) | (*(uchar *)cp);
-		}
-
-		if ((rc = write_word(info, wp, data)) != 0) {
-			return (rc);
-		}
-		wp += 4;
-	}
-
-	/*
-	 * handle word aligned part
-	 */
-	while (cnt >= 4) {
-		data = 0;
-		for (i=0; i<4; ++i) {
-			data = (data << 8) | *src++;
-		}
-		if ((rc = write_word(info, wp, data)) != 0) {
-			return (rc);
-		}
-		wp  += 4;
-		cnt -= 4;
-	}
-
-	if (cnt == 0) {
-		return (0);
-	}
-
-	/*
-	 * handle unaligned tail bytes
-	 */
-	data = 0;
-	for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
-		data = (data << 8) | *src++;
-		--cnt;
-	}
-	for (; i<4; ++i, ++cp) {
-		data = (data << 8) | (*(uchar *)cp);
-	}
-
-	return (write_word(info, wp, data));
-}
-
-/*-----------------------------------------------------------------------
- * Write a word to Flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-static int write_word (flash_info_t *info, ulong dest, ulong data)
-{
-	vu_long *addr = (vu_long*)(info->start[0]);
-	ulong start;
-	int flag;
-
-	/* Check if Flash is (sufficiently) erased */
-	if ((*((vu_long *)dest) & data) != data) {
-		return (2);
-	}
-	/* Disable interrupts which might cause a timeout here */
-	flag = disable_interrupts();
-
-	addr[0x0555] = 0x00AA00AA;
-	addr[0x02AA] = 0x00550055;
-	addr[0x0555] = 0x00A000A0;
-
-	*((vu_long *)dest) = data;
-
-	/* re-enable interrupts if necessary */
-	if (flag)
-		enable_interrupts();
-
-	/* data polling for D7 */
-	start = get_timer (0);
-	while ((*((vu_long *)dest) & 0x00800080) != (data & 0x00800080)) {
-		if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
-			return (1);
-		}
-	}
-	return (0);
-}
-
-/*-----------------------------------------------------------------------
- */
diff --git a/board/lantec/lantec.c b/board/lantec/lantec.c
deleted file mode 100644
index 6d3486c..0000000
--- a/board/lantec/lantec.c
+++ /dev/null
@@ -1,208 +0,0 @@ 
-/*
- * (C) Copyright 2000, 2001
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- * (C) Copyright 2001
- * Torsten Stevens, FHG IMS, stevens@ims.fhg.de
- * Bruno Achauer, Exet AG, bruno@exet-ag.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * Derived from ../tqm8xx/tqm8xx.c
- */
-
-#include <common.h>
-#include <mpc8xx.h>
-
-/* ------------------------------------------------------------------------- */
-
-static long int dram_size (long int, long int *, long int);
-
-/* ------------------------------------------------------------------------- */
-
-#define	_NOT_USED_	0xFFFFFFFF
-
-const uint sdram_table[] = {
-	/*
-	 * Single Read. (Offset 0 in UPMA RAM)
-	 */
-	0x1f07fc04, 0xeeaefc04, 0x11adfc04, 0xefbbbc00,
-	0x1ff77c47,		/* last */
-	/*
-	 * SDRAM Initialization (offset 5 in UPMA RAM)
-	 *
-	 * This is no UPM entry point. The following definition uses
-	 * the remaining space to establish an initialization
-	 * sequence, which is executed by a RUN command.
-	 *
-	 */
-	0x1ff77c35, 0xefeabc34, 0x1fb57c35,	/* last */
-	/*
-	 * Burst Read. (Offset 8 in UPMA RAM)
-	 */
-	0x1f07fc04, 0xeeaefc04, 0x10adfc04, 0xf0affc00,
-	0xf0affc00, 0xf1affc00, 0xefbbbc00, 0x1ff77c47,	/* last */
-	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
-	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
-	/*
-	 * Single Write. (Offset 18 in UPMA RAM)
-	 */
-	0x1f27fc04, 0xeeaebc00, 0x01b93c04, 0x1ff77c47,	/* last */
-	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
-	/*
-	 * Burst Write. (Offset 20 in UPMA RAM)
-	 */
-	0x1f07fc04, 0xeeaebc00, 0x10ad7c00, 0xf0affc00,
-	0xf0affc00, 0xe1bbbc04, 0x1ff77c47,	/* last */
-	_NOT_USED_,
-	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
-	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
-	/*
-	 * Refresh  (Offset 30 in UPMA RAM)
-	 */
-	0x1ff5fc84, 0xfffffc04, 0xfffffc04, 0xfffffc04,
-	0xfffffc84, 0xfffffc07, 0xfffffc07,	/* last */
-	_NOT_USED_,
-	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
-	/*
-	 * Exception. (Offset 3c in UPMA RAM)
-	 */
-	0x7ffffc07,		/* last */
-	_NOT_USED_, _NOT_USED_, _NOT_USED_,
-};
-
-/* ------------------------------------------------------------------------- */
-
-
-/*
- * Check Board Identity:
- *
- * Test TQ ID string (TQM8xx...)
- * If present, check for "L" type (no second DRAM bank),
- * otherwise "L" type is assumed as default.
- *
- * Return 1 for "L" type, 0 else.
- */
-
-int checkboard (void)
-{
-	printf ("Board: Lantec special edition rev.%d\n", CONFIG_LANTEC);
-	return 0;
-}
-
-/* ------------------------------------------------------------------------- */
-
-phys_size_t initdram (int board_type)
-{
-	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
-	volatile memctl8xx_t *memctl = &immap->im_memctl;
-	long int size_b0;
-	int i;
-
-	/*
-	 * Configure UPMA for SDRAM
-	 */
-	upmconfig (UPMA, (uint *) sdram_table,
-		   sizeof (sdram_table) / sizeof (uint));
-
-	memctl->memc_mptpr = CONFIG_SYS_MPTPR_1BK_8K /* XXX CONFIG_SYS_MPTPR XXX */ ;
-
-	/* burst length=4, burst type=sequential, CAS latency=2 */
-	memctl->memc_mar = 0x00000088;
-
-	/*
-	 * Map controller bank 3 to the SDRAM bank at preliminary address.
-	 */
-	memctl->memc_or3 = CONFIG_SYS_OR3_PRELIM;
-	memctl->memc_br3 = CONFIG_SYS_BR3_PRELIM;
-
-	/* initialize memory address register */
-	memctl->memc_mamr = CONFIG_SYS_MAMR_8COL;	/* refresh not enabled yet */
-
-	/* mode initialization (offset 5) */
-	udelay (200);		/* 0x80006105 */
-	memctl->memc_mcr =
-		MCR_OP_RUN | MCR_MB_CS3 | MCR_MLCF (1) | MCR_MAD (0x05);
-
-	/* run 2 refresh sequence with 4-beat refresh burst (offset 0x30) */
-	udelay (1);		/* 0x80006130 */
-	memctl->memc_mcr =
-		MCR_OP_RUN | MCR_MB_CS3 | MCR_MLCF (1) | MCR_MAD (0x30);
-	udelay (1);		/* 0x80006130 */
-	memctl->memc_mcr =
-		MCR_OP_RUN | MCR_MB_CS3 | MCR_MLCF (1) | MCR_MAD (0x30);
-
-	udelay (1);		/* 0x80006106 */
-	memctl->memc_mcr =
-		MCR_OP_RUN | MCR_MB_CS3 | MCR_MLCF (1) | MCR_MAD (0x06);
-
-	memctl->memc_mamr |= MAMR_PTAE;	/* refresh enabled */
-
-	udelay (200);
-
-	/* Need at least 10 DRAM accesses to stabilize */
-	for (i = 0; i < 10; ++i) {
-		volatile unsigned long *addr =
-			(volatile unsigned long *) SDRAM_BASE3_PRELIM;
-		unsigned long val;
-
-		val = *(addr + i);
-		*(addr + i) = val;
-	}
-
-	/*
-	 * Check Bank 0 Memory Size for re-configuration
-	 */
-	size_b0 = dram_size (CONFIG_SYS_MAMR_8COL,
-			     (long *) SDRAM_BASE3_PRELIM, SDRAM_MAX_SIZE);
-
-	memctl->memc_mamr = CONFIG_SYS_MAMR_8COL | MAMR_PTAE;
-
-	/*
-	 * Final mapping:
-	 */
-
-	memctl->memc_or3 = ((-size_b0) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM;
-	memctl->memc_br3 = (CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
-	udelay (1000);
-
-	return (size_b0);
-}
-
-/* ------------------------------------------------------------------------- */
-
-/*
- * Check memory range for valid RAM. A simple memory test determines
- * the actually available RAM size between addresses `base' and
- * `base + maxsize'. Some (not all) hardware errors are detected:
- * - short between address lines
- * - short between data lines
- */
-
-static long int dram_size (long int mamr_value, long int *base,
-			   long int maxsize)
-{
-	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
-	volatile memctl8xx_t *memctl = &immap->im_memctl;
-
-	memctl->memc_mamr = mamr_value;
-
-	return (get_ram_size (base, maxsize));
-}
diff --git a/board/lantec/u-boot.lds b/board/lantec/u-boot.lds
deleted file mode 100644
index 9411802..0000000
--- a/board/lantec/u-boot.lds
+++ /dev/null
@@ -1,107 +0,0 @@ 
-/*
- * (C) Copyright 2000-2010
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_ARCH(powerpc)
-
-SECTIONS
-{
-  /* Read-only sections, merged into text segment: */
-  . = + SIZEOF_HEADERS;
-  .text      :
-  {
-    /* WARNING - the following is hand-optimized to fit within	*/
-    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
-
-    arch/powerpc/cpu/mpc8xx/start.o	(.text*)
-    arch/powerpc/cpu/mpc8xx/traps.o	(.text*)
-    net/libnet.o			(.text*)
-    arch/powerpc/lib/libpowerpc.o	(.text*)
-    drivers/rtc/librtc.o		(.text*)
-
-    . = env_offset;
-    common/env_embedded.o		(.text*)
-
-    *(.text*)
-  }
-  _etext = .;
-  PROVIDE (etext = .);
-  .rodata    :
-  {
-    *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
-  }
-
-  /* Read-write section, merged into data segment: */
-  . = (. + 0x00FF) & 0xFFFFFF00;
-  _erotext = .;
-  PROVIDE (erotext = .);
-  .reloc   :
-  {
-    _GOT2_TABLE_ = .;
-    KEEP(*(.got2))
-    KEEP(*(.got))
-    PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4);
-    _FIXUP_TABLE_ = .;
-    KEEP(*(.fixup))
-  }
-  __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1;
-  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
-  .data    :
-  {
-    *(.data*)
-    *(.sdata*)
-  }
-  _edata  =  .;
-  PROVIDE (edata = .);
-
-  . = .;
-
-  . = ALIGN(4);
-  .u_boot_list : {
-	#include <u-boot.lst>
-  }
-
-
-  . = .;
-  __start___ex_table = .;
-  __ex_table : { *(__ex_table) }
-  __stop___ex_table = .;
-
-  . = ALIGN(256);
-  __init_begin = .;
-  .text.init : { *(.text.init) }
-  .data.init : { *(.data.init) }
-  . = ALIGN(256);
-  __init_end = .;
-
-  __bss_start = .;
-  .bss (NOLOAD)       :
-  {
-   *(.bss*)
-   *(.sbss*)
-   *(COMMON)
-   . = ALIGN(4);
-  }
-  __bss_end__ = . ;
-  PROVIDE (end = .);
-}
diff --git a/board/lantec/u-boot.lds.debug b/board/lantec/u-boot.lds.debug
deleted file mode 100644
index e788f5c..0000000
--- a/board/lantec/u-boot.lds.debug
+++ /dev/null
@@ -1,137 +0,0 @@ 
-/*
- * (C) Copyright 2000, 2001
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_ARCH(powerpc)
-/* Do we need any of these for elf?
-   __DYNAMIC = 0;    */
-SECTIONS
-{
-  /* Read-only sections, merged into text segment: */
-  . = + SIZEOF_HEADERS;
-  .interp : { *(.interp) }
-  .hash          : { *(.hash)		}
-  .dynsym        : { *(.dynsym)		}
-  .dynstr        : { *(.dynstr)		}
-  .rel.text      : { *(.rel.text)		}
-  .rela.text     : { *(.rela.text)	}
-  .rel.data      : { *(.rel.data)		}
-  .rela.data     : { *(.rela.data)	}
-  .rel.rodata    : { *(.rel.rodata)	}
-  .rela.rodata   : { *(.rela.rodata)	}
-  .rel.got       : { *(.rel.got)		}
-  .rela.got      : { *(.rela.got)		}
-  .rel.ctors     : { *(.rel.ctors)	}
-  .rela.ctors    : { *(.rela.ctors)	}
-  .rel.dtors     : { *(.rel.dtors)	}
-  .rela.dtors    : { *(.rela.dtors)	}
-  .rel.bss       : { *(.rel.bss)		}
-  .rela.bss      : { *(.rela.bss)		}
-  .rel.plt       : { *(.rel.plt)		}
-  .rela.plt      : { *(.rela.plt)		}
-  .init          : { *(.init)	}
-  .plt : { *(.plt) }
-  .text      :
-  {
-    /* WARNING - the following is hand-optimized to fit within	*/
-    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
-
-    arch/powerpc/cpu/mpc8xx/start.o	(.text)
-    common/dlmalloc.o	(.text)
-    lib/vsprintf.o	(.text)
-    lib/crc32.o		(.text)
-
-    . = env_offset;
-    common/env_embedded.o(.text)
-
-    *(.text)
-    *(.got1)
-  }
-  _etext = .;
-  PROVIDE (etext = .);
-  .rodata    :
-  {
-    *(.rodata)
-    *(.rodata1)
-    *(.rodata.str1.4)
-    *(.eh_frame)
-  }
-  .fini      : { *(.fini)    } =0
-  .ctors     : { *(.ctors)   }
-  .dtors     : { *(.dtors)   }
-
-  /* Read-write section, merged into data segment: */
-  . = (. + 0x0FFF) & 0xFFFFF000;
-  _erotext = .;
-  PROVIDE (erotext = .);
-  .reloc   :
-  {
-    *(.got)
-    _GOT2_TABLE_ = .;
-    *(.got2)
-    _FIXUP_TABLE_ = .;
-    *(.fixup)
-  }
-  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
-  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
-  .data    :
-  {
-    *(.data)
-    *(.data1)
-    *(.sdata)
-    *(.sdata2)
-    *(.dynamic)
-    CONSTRUCTORS
-  }
-  _edata  =  .;
-  PROVIDE (edata = .);
-
-
-  . = ALIGN(4);
-  .u_boot_list : {
-	#include <u-boot.lst>
-  }
-
-
-  __start___ex_table = .;
-  __ex_table : { *(__ex_table) }
-  __stop___ex_table = .;
-
-  . = ALIGN(4096);
-  __init_begin = .;
-  .text.init : { *(.text.init) }
-  .data.init : { *(.data.init) }
-  . = ALIGN(4096);
-  __init_end = .;
-
-  __bss_start = .;
-  .bss       :
-  {
-   *(.sbss) *(.scommon)
-   *(.dynbss)
-   *(.bss)
-   *(COMMON)
-  }
-  __bss_end__ = . ;
-  PROVIDE (end = .);
-}
diff --git a/board/siemens/IAD210/IAD210.c b/board/siemens/IAD210/IAD210.c
deleted file mode 100644
index 7325a93..0000000
--- a/board/siemens/IAD210/IAD210.c
+++ /dev/null
@@ -1,299 +0,0 @@ 
-/*
- * (C) Copyright 2001
- * Paul Geerinckx
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <mpc8xx.h>
-#include <net.h>
-#include "atm.h"
-#include <i2c.h>
-
-/* ------------------------------------------------------------------------- */
-
-static long int dram_size (long int, long int *, long int);
-
-/* ------------------------------------------------------------------------- */
-
-/* used PLD registers */
-#  define PLD_GCR1_REG (unsigned char *) (0x10000000 + 0)
-#  define PLD_EXT_RES  (unsigned char *) (0x10000000 + 10)
-#  define PLD_EXT_FETH (unsigned char *) (0x10000000 + 11)
-#  define PLD_EXT_LED  (unsigned char *) (0x10000000 + 12)
-#  define PLD_EXT_X21  (unsigned char *) (0x10000000 + 13)
-
-#define	_NOT_USED_	0xFFFFFFFF
-
-const uint sdram_table[] = {
-	/*
-	 * Single Read. (Offset 0 in UPMA RAM)
-	 */
-	0xFE2DB004, 0xF0AA7004, 0xF0A5F400, 0xF3AFFC47,	/* last */
-	_NOT_USED_,
-	/*
-	 * SDRAM Initialization (offset 5 in UPMA RAM)
-	 *
-	 * This is no UPM entry point. The following definition uses
-	 * the remaining space to establish an initialization
-	 * sequence, which is executed by a RUN command.
-	 *
-	 */
-	0xFFFAF834, 0xFFE5B435,	/* last */
-	_NOT_USED_,
-	/*
-	 * Burst Read. (Offset 8 in UPMA RAM)
-	 */
-	0xFE2DB004, 0xF0AF7404, 0xF0AFFC00, 0xF0AFFC00,
-	0xF0AFFC00, 0xF0AAF800, 0xF1A5E447,	/* last */
-	_NOT_USED_,
-	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
-	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
-	/*
-	 * Single Write. (Offset 18 in UPMA RAM)
-	 */
-	0xFE29B300, 0xF1A27304, 0xFFA5F747,	/* last */
-	_NOT_USED_,
-	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
-	/*
-	 * Burst Write. (Offset 20 in UPMA RAM)
-	 */
-	0x1F0DFC04, 0xEEABBC00, 0x10A77C00, 0xF0AFFC00,
-	0xF1AAF804, 0xFFA5F447,	/* last */
-	_NOT_USED_, _NOT_USED_,
-	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
-	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
-	/*
-	 * Refresh  (Offset 30 in UPMA RAM)
-	 */
-	0xFFAC3884, 0xFFAC3404, 0xFFAFFC04, 0xFFAFFC84,
-	0xFFAFFC07,		/* last */
-	_NOT_USED_, _NOT_USED_, _NOT_USED_,
-	/*
-	 * MRS sequence  (Offset 38 in UPMA RAM)
-	 */
-	0xFFAAB834, 0xFFA57434, 0xFFAFFC05,	/* last */
-	_NOT_USED_,
-	/*
-	 * Exception. (Offset 3c in UPMA RAM)
-	 */
-	0xFFAFFC04, 0xFFAFFC05,	/* last */
-	_NOT_USED_, _NOT_USED_,
-};
-
-/* ------------------------------------------------------------------------- */
-
-
-phys_size_t initdram (int board_type)
-{
-	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
-	volatile memctl8xx_t *memctl = &immap->im_memctl;
-	volatile iop8xx_t *iop = &immap->im_ioport;
-	volatile fec_t *fecp = &immap->im_cpm.cp_fec;
-	long int size;
-
-	upmconfig (UPMA, (uint *) sdram_table,
-		   sizeof (sdram_table) / sizeof (uint));
-
-	/*
-	 * Preliminary prescaler for refresh (depends on number of
-	 * banks): This value is selected for four cycles every 62.4 us
-	 * with two SDRAM banks or four cycles every 31.2 us with one
-	 * bank. It will be adjusted after memory sizing.
-	 */
-	memctl->memc_mptpr = CONFIG_SYS_MPTPR;
-
-	memctl->memc_mar = 0x00000088;
-
-	/*
-	 * Map controller banks 2 and 3 to the SDRAM banks 2 and 3 at
-	 * preliminary addresses - these have to be modified after the
-	 * SDRAM size has been determined.
-	 */
-	memctl->memc_or2 = CONFIG_SYS_OR2_PRELIM;
-	memctl->memc_br2 = CONFIG_SYS_BR2_PRELIM;
-
-	memctl->memc_mamr = CONFIG_SYS_MAMR & (~(MAMR_PTAE));	/* no refresh yet */
-
-	udelay (200);
-
-	/* perform SDRAM initializsation sequence */
-
-	memctl->memc_mcr = 0x80004105;	/* SDRAM bank 0 */
-	udelay (1);
-	memctl->memc_mcr = 0x80004230;	/* SDRAM bank 0 - execute twice */
-	udelay (1);
-
-	memctl->memc_mcr = 0x80004105;	/* SDRAM precharge */
-	udelay (1);
-	memctl->memc_mcr = 0x80004030;	/* SDRAM 16x autorefresh */
-	udelay (1);
-	memctl->memc_mcr = 0x80004138;	/* SDRAM upload parameters */
-	udelay (1);
-
-	memctl->memc_mamr |= MAMR_PTAE;	/* enable refresh */
-
-	udelay (1000);
-
-	/*
-	 * Check Bank 0 Memory Size for re-configuration
-	 *
-	 */
-	size = dram_size (CONFIG_SYS_MAMR, (long *) SDRAM_BASE_PRELIM,
-			  SDRAM_MAX_SIZE);
-
-	udelay (1000);
-
-
-	memctl->memc_mamr = CONFIG_SYS_MAMR;
-	udelay (1000);
-
-	/*
-	 * Final mapping
-	 */
-	memctl->memc_or2 = ((-size) & 0xFFFF0000) | CONFIG_SYS_OR2_PRELIM;
-	memctl->memc_br2 = ((CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V);
-
-	udelay (10000);
-
-	/* prepare pin multiplexing for fast ethernet */
-
-	atmLoad ();
-	fecp->fec_ecntrl = 0x00000004;	/* rev D3 pinmux SET */
-	iop->iop_pdpar |= 0x0080;	/* set pin as MII_clock */
-
-
-	return (size);
-}
-
-/* ------------------------------------------------------------------------- */
-
-/*
- * Check memory range for valid RAM. A simple memory test determines
- * the actually available RAM size between addresses `base' and
- * `base + maxsize'. Some (not all) hardware errors are detected:
- * - short between address lines
- * - short between data lines
- */
-
-static long int dram_size (long int mamr_value, long int *base,
-			   long int maxsize)
-{
-	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
-	volatile memctl8xx_t *memctl = &immap->im_memctl;
-
-	memctl->memc_mamr = mamr_value;
-
-	return (get_ram_size (base, maxsize));
-}
-
-/*
- * Check Board Identity:
- */
-
-int checkboard (void)
-{
-	return (0);
-}
-
-void board_serial_init (void)
-{
-	;			/* nothing to do here */
-}
-
-void board_ether_init (void)
-{
-	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
-	volatile iop8xx_t *iop = &immap->im_ioport;
-	volatile fec_t *fecp = &immap->im_cpm.cp_fec;
-
-	atmLoad ();
-	fecp->fec_ecntrl = 0x00000004;	/* rev D3 pinmux SET */
-	iop->iop_pdpar |= 0x0080;	/* set pin as MII_clock */
-}
-
-int board_early_init_f (void)
-{
-	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
-	volatile cpmtimer8xx_t *timers = &immap->im_cpmtimer;
-	volatile memctl8xx_t *memctl = &immap->im_memctl;
-	volatile iop8xx_t *iop = &immap->im_ioport;
-
-	/* configure the LED timing output pins - port A pin 4 */
-	iop->iop_papar = 0x0800;
-	iop->iop_padir = 0x0800;
-
-	/* start timer 2 for the 4hz LED blink rate */
-	timers->cpmt_tmr2 = 0xff2c;	/* 4HZ for 64MHz */
-	timers->cpmt_trr2 = 0x000003d0;	/* clk/16 , prescale=256 */
-	timers->cpmt_tgcr = 0x00000810;	/* run timer 2 */
-
-	/* chip select for PLD access */
-	memctl->memc_br6 = 0x10000401;
-	memctl->memc_or6 = 0xFC000908;
-
-	/* PLD initial values ( set LEDs, remove reset on LXT) */
-
-	*PLD_GCR1_REG = 0x06;
-	*PLD_EXT_RES = 0xC0;
-	*PLD_EXT_FETH = 0x40;
-	*PLD_EXT_LED = 0xFF;
-	*PLD_EXT_X21 = 0x04;
-	return 0;
-}
-
-static void board_get_enetaddr(uchar *addr)
-{
-	int i;
-	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
-	volatile cpm8xx_t *cpm = &immap->im_cpm;
-	unsigned int rccrtmp;
-
-	char default_mac_addr[] = { 0x00, 0x08, 0x01, 0x02, 0x03, 0x04 };
-
-	for (i = 0; i < 6; i++)
-		addr[i] = default_mac_addr[i];
-
-	printf ("There is an error in the i2c driver .. /n");
-	printf ("You need to fix it first....../n");
-
-	rccrtmp = cpm->cp_rccr;
-	cpm->cp_rccr |= 0x0020;
-
-	i2c_reg_read (0xa0, 0);
-	printf ("seep = '-%c-%c-%c-%c-%c-%c-'\n",
-		i2c_reg_read (0xa0, 0), i2c_reg_read (0xa0, 0),
-		i2c_reg_read (0xa0, 0), i2c_reg_read (0xa0, 0),
-		i2c_reg_read (0xa0, 0), i2c_reg_read (0xa0, 0));
-
-	cpm->cp_rccr = rccrtmp;
-}
-
-int misc_init_r(void)
-{
-	uchar enetaddr[6];
-
-	if (!eth_getenv_enetaddr("ethaddr", enetaddr)) {
-		board_get_enetaddr(enetaddr);
-		eth_setenv_enetaddr("ethaddr", enetaddr);
-	}
-
-	return 0;
-}
diff --git a/board/siemens/IAD210/Makefile b/board/siemens/IAD210/Makefile
deleted file mode 100644
index bb81507..0000000
--- a/board/siemens/IAD210/Makefile
+++ /dev/null
@@ -1,44 +0,0 @@ 
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	= $(BOARD).o flash.o atm.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
diff --git a/board/siemens/IAD210/atm.c b/board/siemens/IAD210/atm.c
deleted file mode 100644
index 40aad0a..0000000
--- a/board/siemens/IAD210/atm.c
+++ /dev/null
@@ -1,652 +0,0 @@ 
-#include <common.h>
-#include <mpc8xx.h>
-#include <commproc.h>
-
-#include "atm.h"
-#include <linux/stddef.h>
-
-#define SYNC __asm__("sync")
-#define MY_ALIGN(p, a) ((char *)(((uint32)(p)+(a)-1) & ~((uint32)(a)-1)))
-
-#define FALSE  1
-#define TRUE   0
-#define OK     0
-#define ERROR -1
-
-struct atm_connection_t g_conn[NUM_CONNECTIONS] =
-{
-  { NULL, 10, NULL, 10,  NULL, NULL, NULL, NULL }, /* OAM  */
-};
-
-struct atm_driver_t g_atm =
-{
-  FALSE,   /* loaded */
-  FALSE,   /* started */
-  NULL,    /* csram */
-  0,       /* csram_size */
-  NULL,    /* am_top */
-  NULL,    /* ap_top */
-  NULL,    /* int_reload_ptr */
-  NULL,    /* int_serv_ptr */
-  NULL,    /* rbd_base_ptr */
-  NULL,    /* tbd_base_ptr */
-  0        /* linerate */
-};
-
-char csram[1024]; /* more than enough for doing nothing*/
-
-int    atmLoad(void);
-void   atmUnload(void);
-int    atmMemInit(void);
-void   atmIntInit(void);
-void   atmApcInit(void);
-void   atmAmtInit(void);
-void   atmCpmInit(void);
-void   atmUtpInit(void);
-
-/*****************************************************************************
- *
- * FUNCTION NAME: atmLoad
- *
- * DESCRIPTION: Basic ATM initialization.
- *
- * PARAMETERS: none
- *
- * RETURNS: OK or ERROR
- *
- ****************************************************************************/
-int atmLoad()
-{
-  volatile immap_t       *immap  = (immap_t *)CONFIG_SYS_IMMR;
-  volatile cpmtimer8xx_t *timers = &immap->im_cpmtimer;
-  volatile iop8xx_t      *iop    = &immap->im_ioport;
-
-  timers->cpmt_tgcr &=  0x0FFF; SYNC;             /* Disable Timer 4 */
-  immap->im_cpm.cp_scc[3].scc_gsmrl = 0x0; SYNC; /* Disable SCC4 */
-  iop->iop_pdpar &= 0x3FFF; SYNC;                 /* Disable SAR and UTOPIA */
-
-  if ( atmMemInit() != OK ) return ERROR;
-
-  atmIntInit();
-  atmApcInit();
-  atmAmtInit();
-  atmCpmInit();
-  atmUtpInit();
-
-  g_atm.loaded = TRUE;
-
-  return OK;
-}
-
-/*****************************************************************************
- *
- * FUNCTION NAME: atmUnload
- *
- * DESCRIPTION: Disables ATM and UTOPIA.
- *
- * PARAMETERS: none
- *
- * RETURNS: void
- *
- ****************************************************************************/
-void atmUnload()
-{
-  volatile immap_t       *immap  = (immap_t *)CONFIG_SYS_IMMR;
-  volatile cpmtimer8xx_t *timers = &immap->im_cpmtimer;
-  volatile iop8xx_t      *iop    = &immap->im_ioport;
-
-  timers->cpmt_tgcr &=  0x0FFF; SYNC;             /* Disable Timer 4 */
-  immap->im_cpm.cp_scc[3].scc_gsmrl = 0x0; SYNC;  /* Disable SCC4 */
-  iop->iop_pdpar &= 0x3FFF; SYNC;                 /* Disable SAR and UTOPIA */
-  g_atm.loaded = FALSE;
-}
-
-/*****************************************************************************
- *
- * FUNCTION NAME: atmMemInit
- *
- * DESCRIPTION:
- *
- * The ATM driver uses the following resources:
- *
- * A. Memory in DPRAM to hold
- *
- *     1/ CT          = Connection Table ( RCT & TCT )
- *     2/ TCTE        = Transmit Connection Table Extension
- *     3/ MPHYPT      = Multi-PHY Pointing Table
- *     4/ APCP        = APC Parameter Table
- *     5/ APCT_PRIO_1 = APC Table ( priority 1 for AAL1/2 )
- *     6/ APCT_PRIO_2 = APC Table ( priority 2 for VBR )
- *     7/ APCT_PRIO_3 = APC Table ( priority 3 for UBR )
- *     8/ TQ          = Transmit Queue
- *     9/ AM          = Address Matching Table
- *    10/ AP          = Address Pointing Table
- *
- * B. Memory in cache safe RAM to hold
- *
- *     1/ INT         = Interrupt Queue
- *     2/ RBD         = Receive Buffer Descriptors
- *     3/ TBD         = Transmit Buffer Descriptors
- *
- * This function
- * 1. clears the ATM DPRAM area,
- * 2. Allocates and clears cache safe memory,
- * 3. Initializes 'g_conn'.
- *
- * PARAMETERS: none
- *
- * RETURNS: OK or ERROR
- *
- ****************************************************************************/
-int atmMemInit()
-{
-  int i;
-  unsigned immr = CONFIG_SYS_IMMR;
-  int total_num_rbd = 0;
-  int total_num_tbd = 0;
-
-  memset((char *)CONFIG_SYS_IMMR + 0x2000 + ATM_DPRAM_BEGIN, 0x00, ATM_DPRAM_SIZE);
-
-  g_atm.csram_size = NUM_INT_ENTRIES * SIZE_OF_INT_ENTRY;
-
-  for ( i = 0; i < NUM_CONNECTIONS; ++i ) {
-    total_num_rbd += g_conn[i].num_rbd;
-    total_num_tbd += g_conn[i].num_tbd;
-  }
-
-  g_atm.csram_size += total_num_rbd * SIZE_OF_RBD + total_num_tbd * SIZE_OF_TBD + 4;
-
-  g_atm.csram = &csram[0];
-  memset(&(g_atm.csram), 0x00, g_atm.csram_size);
-
-  g_atm.int_reload_ptr = (uint32 *)MY_ALIGN(g_atm.csram, 4);
-  g_atm.rbd_base_ptr = (struct atm_bd_t *)(g_atm.int_reload_ptr + NUM_INT_ENTRIES);
-  g_atm.tbd_base_ptr = (struct atm_bd_t *)(g_atm.rbd_base_ptr + total_num_rbd);
-
-  g_conn[0].rbd_ptr = g_atm.rbd_base_ptr;
-  g_conn[0].tbd_ptr = g_atm.tbd_base_ptr;
-  g_conn[0].ct_ptr = CT_PTR(immr);
-  g_conn[0].tcte_ptr = TCTE_PTR(immr);
-
-  return OK;
-}
-
-/*****************************************************************************
- *
- * FUNCTION NAME: atmIntInit
- *
- * DESCRIPTION:
- *
- * Initialization of the MPC860 ESAR Interrupt Queue.
- * This function
- * - clears all entries in the INT,
- * - sets the WRAP bit of the last INT entry,
- * - initializes the 'int_serv_ptr' attribuut of the AtmDriver structure
- *   to the first INT entry.
- *
- * PARAMETERS: none
- *
- * RETURNS: void
- *
- * REMARKS:
- *
- * - The INT resides in external cache safe memory.
- * - The base address of the INT is stored in g_atm.int_reload_ptr.
- * - The number of entries in the INT is given by NUM_INT_ENTRIES.
- * - The INTBASE field in SAR Parameter RAM is set by atmCpmInit().
- *
- ****************************************************************************/
-void atmIntInit()
-{
-  int i;
-  for ( i = 0; i < NUM_INT_ENTRIES - 1; ++i) g_atm.int_reload_ptr[i] = 0;
-  g_atm.int_reload_ptr[i] = INT_WRAP;
-  g_atm.int_serv_ptr = g_atm.int_reload_ptr;
-}
-
-/*****************************************************************************
- *
- * FUNCTION NAME: atmApcInit
- *
- * DESCRIPTION:
- *
- * This function initializes the following ATM Pace Controller related
- * data structures:
- *
- * - 1 MPHY Pointing Table (contains only one entry)
- * - 3 APC Parameter Tables (one PHY with 3 priorities)
- * - 3 APC Tables (one table for each priority)
- * - 1 Transmit Queue (one transmit queue per PHY)
- *
- * PARAMETERS: none
- *
- * RETURNS: void
- *
- ****************************************************************************/
-void atmApcInit()
-{
-  int i;
-  /* unsigned immr = CONFIG_SYS_IMMR; */
-  uint16 * mphypt_ptr = MPHYPT_PTR(CONFIG_SYS_IMMR);
-  struct apc_params_t * apcp_ptr = APCP_PTR(CONFIG_SYS_IMMR);
-  uint16 * apct_prio1_ptr = APCT1_PTR(CONFIG_SYS_IMMR);
-  uint16 * tq_ptr = TQ_PTR(CONFIG_SYS_IMMR);
-  /***************************************************/
-  /* Initialize MPHY Pointing Table (only one entry) */
-  /***************************************************/
-  *mphypt_ptr = APCP_BASE;
-
-  /********************************************/
-  /* Initialize APC parameters for priority 1 */
-  /********************************************/
-  apcp_ptr->apct_base1 = APCT_PRIO_1_BASE;
-  apcp_ptr->apct_end1  =  APCT_PRIO_1_BASE + NUM_APCT_PRIO_1_ENTRIES * 2;
-  apcp_ptr->apct_ptr1  =  APCT_PRIO_1_BASE;
-  apcp_ptr->apct_sptr1 = APCT_PRIO_1_BASE;
-  apcp_ptr->etqbase    = TQ_BASE;
-  apcp_ptr->etqend     =  TQ_BASE + ( NUM_TQ_ENTRIES - 1 ) * 2;
-  apcp_ptr->etqaptr    = TQ_BASE;
-  apcp_ptr->etqtptr    = TQ_BASE;
-  apcp_ptr->apc_mi     = 8;
-  apcp_ptr->ncits      = 0x0100;   /* NCITS = 1 */
-  apcp_ptr->apcnt      = 0;
-  apcp_ptr->reserved1  = 0;
-  apcp_ptr->eapcst     = 0x2009;  /* LAST, ESAR, MPHY */
-  apcp_ptr->ptp_counter = 0;
-  apcp_ptr->ptp_txch   = 0;
-  apcp_ptr->reserved2  = 0;
-
-
-  /***************************************************/
-  /* Initialize APC Tables with empty slots (0xFFFF) */
-  /***************************************************/
-  for ( i = 0; i < NUM_APCT_PRIO_1_ENTRIES; ++i ) *(apct_prio1_ptr++) = 0xFFFF;
-
-  /************************/
-  /* Clear Transmit Queue */
-  /************************/
-  for ( i = 0; i < NUM_TQ_ENTRIES; ++i ) *(tq_ptr++) = 0;
-}
-
-/*****************************************************************************
- *
- * FUNCTION NAME: atmAmtInit
- *
- * DESCRIPTION:
- *
- * This function clears the first entry in the Address Matching Table and
- * lets the first entry in the Address Pointing table point to the first
- * entry in the TCT table (i.e. the raw cell channel).
- *
- * PARAMETERS: none
- *
- * RETURNS: void
- *
- * REMARKS:
- *
- * The values for the AMBASE, AMEND and APBASE registers in SAR parameter
- * RAM are initialized by atmCpmInit().
- *
- ****************************************************************************/
-void atmAmtInit()
-{
-  unsigned immr = CONFIG_SYS_IMMR;
-
-  g_atm.am_top = AM_PTR(immr);
-  g_atm.ap_top = AP_PTR(immr);
-
-  *(g_atm.ap_top--) = CT_BASE;
-  *(g_atm.am_top--) = 0;
-}
-
-/*****************************************************************************
- *
- * FUNCTION NAME: atmCpmInit
- *
- * DESCRIPTION:
- *
- * This function initializes the Utopia Interface Parameter RAM Map
- * (SCC4, ATM Protocol) of the Communication Processor Modudule.
- *
- * PARAMETERS: none
- *
- * RETURNS: void
- *
- ****************************************************************************/
-void atmCpmInit()
-{
-  unsigned immr = CONFIG_SYS_IMMR;
-
-  memset((char *)immr + 0x3F00, 0x00, 0xC0);
-
-  /*-----------------------------------------------------------------*/
-  /* RBDBASE - Receive buffer descriptors base address               */
-  /* The RBDs reside in cache safe external memory.                  */
-  /*-----------------------------------------------------------------*/
-  *RBDBASE(immr) = (uint32)g_atm.rbd_base_ptr;
-
-  /*-----------------------------------------------------------------*/
-  /* SRFCR - SAR receive function code                               */
-  /* 0-2 rsvd = 000                                                  */
-  /* 3-4 BO   = 11  Byte ordering (big endian).                      */
-  /* 5-7 FC   = 000 Value driven on the address type signals AT[1-3] */
-  /*                when the SDMA channel accesses memory.           */
-  /*-----------------------------------------------------------------*/
-  *SRFCR(immr) = 0x18;
-
-  /*-----------------------------------------------------------------*/
-  /* SRSTATE - SAR receive status                                    */
-  /* 0 EXT  = 0 Extended mode off.                                   */
-  /* 1 ACP  = 0 Valid only if EXT = 1.                               */
-  /* 2 EC   = 0 Standard 53-byte ATM cell.                           */
-  /* 3 SNC  = 0 In sync. Must be set to 0 during initialization.     */
-  /* 4 ESAR = 1 Enhanced SAR functionality enabled.                  */
-  /* 5 MCF  = 1 Management Cell Filter active.                       */
-  /* 6 SER  = 0 UTOPIA mode.                                         */
-  /* 7 MPY  = 1 Multiple PHY mode.                                   */
-  /*-----------------------------------------------------------------*/
-  *SRSTATE(immr) = 0x0D;
-
-  /*-----------------------------------------------------------------*/
-  /* MRBLR - Maximum receive buffer length register.                 */
-  /* Must be cleared for ATM operation (see also SMRBLR).            */
-  /*-----------------------------------------------------------------*/
-  *MRBLR(immr) = 0;
-
-  /*-----------------------------------------------------------------*/
-  /* RSTATE - SCC internal receive state parameters                  */
-  /* The first byte must be initialized with the value of SRFCR.     */
-  /*-----------------------------------------------------------------*/
-  *RSTATE(immr) = (uint32)(*SRFCR(immr)) << 24;
-
-  /*-----------------------------------------------------------------*/
-  /* STFCR - SAR transmit function code                              */
-  /* 0-2 rsvd = 000                                                  */
-  /* 3-4 BO   = 11  Byte ordering (big endian).                      */
-  /* 5-7 FC   = 000 Value driven on the address type signals AT[1-3] */
-  /*                when the SDMA channel accesses memory.           */
-  /*-----------------------------------------------------------------*/
-  *STFCR(immr) = 0x18;
-
-  /*-----------------------------------------------------------------*/
-  /* SRSTATE - SAR transmit status                                   */
-  /* 0 EXT  = 0 : Extended mode off                                  */
-  /* 1 rsvd = 0 :                                                    */
-  /* 2 EC   = 0 : Standard 53-byte ATM cell                          */
-  /* 3 rsvd = 0 :                                                    */
-  /* 4 ESAR = 1 : Enhanced SAR functionality enabled                 */
-  /* 5 rsvd = 0 :                                                    */
-  /* 6 SER  = 0 : UTOPIA mode                                        */
-  /* 7 MPY  = 1 : Multiple PHY mode                                  */
-  /*-----------------------------------------------------------------*/
-  *STSTATE(immr) = 0x09;
-
-  /*-----------------------------------------------------------------*/
-  /* TBDBASE - Transmit buffer descriptors base address              */
-  /* The TBDs reside in cache safe external memory.                  */
-  /*-----------------------------------------------------------------*/
-  *TBDBASE(immr) = (uint32)g_atm.tbd_base_ptr;
-
-  /*-----------------------------------------------------------------*/
-  /* TSTATE - SCC internal transmit state parameters                 */
-  /* The first byte must be initialized with the value of STFCR.     */
-  /*-----------------------------------------------------------------*/
-  *TSTATE(immr) = (uint32)(*STFCR(immr)) << 24;
-
-  /*-----------------------------------------------------------------*/
-  /* CTBASE - Connection table base address                          */
-  /* Offset from the beginning of DPRAM (64-byte aligned).           */
-  /*-----------------------------------------------------------------*/
-  *CTBASE(immr) = CT_BASE;
-
-  /*-----------------------------------------------------------------*/
-  /* INTBASE - Interrupt queue base pointer.                         */
-  /* The interrupt queue resides in cache safe external memory.      */
-  /*-----------------------------------------------------------------*/
-  *INTBASE(immr) = (uint32)g_atm.int_reload_ptr;
-
-  /*-----------------------------------------------------------------*/
-  /* INTPTR - Pointer into interrupt queue.                          */
-  /* Initialize to INTBASE.                                          */
-  /*-----------------------------------------------------------------*/
-  *INTPTR(immr) = *INTBASE(immr);
-
-  /*-----------------------------------------------------------------*/
-  /* C_MASK - Constant mask for CRC32                                */
-  /* Must be initialized to 0xDEBB20E3.                              */
-  /*-----------------------------------------------------------------*/
-  *C_MASK(immr) = 0xDEBB20E3;
-
-  /*-----------------------------------------------------------------*/
-  /* INT_ICNT - Interrupt threshold value                            */
-  /*-----------------------------------------------------------------*/
-  *INT_ICNT(immr) = 1;
-
-  /*-----------------------------------------------------------------*/
-  /* INT_CNT - Interrupt counter                                     */
-  /* Initalize to INT_ICNT. Decremented for each interrupt entry     */
-  /* reported in the interrupt queue. On zero an interrupt is        */
-  /* signaled to the host by setting the GINT bit in the event       */
-  /* register. The counter is reinitialized with INT_ICNT.           */
-  /*-----------------------------------------------------------------*/
-  *INT_CNT(immr) = *INT_ICNT(immr);
-
-  /*-----------------------------------------------------------------*/
-  /* SMRBLR - SAR maximum receive buffer length register.            */
-  /* Must be a multiple of 48 bytes. Common for all ATM connections. */
-  /*-----------------------------------------------------------------*/
-  *SMRBLR(immr) = SAR_RXB_SIZE;
-
-  /*-----------------------------------------------------------------*/
-  /* APCST - APC status register.                                    */
-  /* 0     rsvd 0                                                    */
-  /* 1-2   CSER 11  Initialize with the same value as NSER.          */
-  /* 3-4   NSER 11  Next serial or UTOPIA channel.                   */
-  /* 5-7   rsvd 000                                                  */
-  /* 8-10  rsvd 000                                                  */
-  /* 11    rsvd 0                                                    */
-  /* 12    ESAR 1   UTOPIA Level 2 MPHY enabled.                     */
-  /* 13    DIS  0   APC disable. Must be initiazed to 0.             */
-  /* 14    PL2  0   Not used.                                        */
-  /* 15    MPY  1   Multiple PHY mode on.                            */
-  /*-----------------------------------------------------------------*/
-  *APCST(immr) = 0x7809;
-
-  /*-----------------------------------------------------------------*/
-  /* APCPTR - Pointer to the APC parameter table                     */
-  /* In MPHY master mode this parameter points to the MPHY pointing  */
-  /* table. 2-byte aligned.                                          */
-  /*-----------------------------------------------------------------*/
-  *APCPTR(immr) = MPHYPT_BASE;
-
-  /*-----------------------------------------------------------------*/
-  /* HMASK - Header mask                                             */
-  /* Each incoming cell is masked with HMASK before being compared   */
-  /* to the entries in the address matching table.                   */
-  /*-----------------------------------------------------------------*/
-  *HMASK(immr) = AM_HMASK;
-
-  /*-----------------------------------------------------------------*/
-  /* AMBASE - Address matching table base address                    */
-  /*-----------------------------------------------------------------*/
-  *AMBASE(immr) = AM_BASE;
-
-  /*-----------------------------------------------------------------*/
-  /* AMEND - Address matching table end address                      */
-  /*-----------------------------------------------------------------*/
-  *AMEND(immr) = AM_BASE;
-
-  /*-----------------------------------------------------------------*/
-  /* APBASE - Address pointing table base address                    */
-  /*-----------------------------------------------------------------*/
-  *APBASE(immr) = AP_BASE;
-
-  /*-----------------------------------------------------------------*/
-  /* MPHYST - MPHY status register                                   */
-  /* 0-1   rsvd  00                                                  */
-  /* 2-6   NMPHY 00000 1 PHY                                         */
-  /* 7-9   rsvd  000                                                 */
-  /* 10-14 CMPHY 00000 Initialize with same value as NMPHY           */
-  /*-----------------------------------------------------------------*/
-  *MPHYST(immr) = 0x0000;
-
-  /*-----------------------------------------------------------------*/
-  /* TCTEBASE - Transmit connection table extension base address     */
-  /* Offset from the beginning of DPRAM (32-byte aligned).           */
-  /*-----------------------------------------------------------------*/
-  *TCTEBASE(immr) = TCTE_BASE;
-
-  /*-----------------------------------------------------------------*/
-  /* Clear not used registers.                                       */
-  /*-----------------------------------------------------------------*/
-}
-
-/*****************************************************************************
- *
- * FUNCTION NAME: atmUtpInit
- *
- * DESCRIPTION:
- *
- * This function initializes the ATM interface for
- *
- * - UTOPIA mode
- * - muxed bus
- * - master operation
- * - multi PHY (because of a bug in the MPC860P rev. E.0)
- * - internal clock = SYSCLK / 2
- *
- * EXTERNAL EFFECTS:
- *
- * After calling this function, the MPC860ESAR UTOPIA bus is
- * active and uses the following ports/pins:
- *
- * Port    Pin  Signal   Description
- * ------  ---  -------  -------------------------------------------
- * PB[15]  R17  TxClav   Transmit cell available input/output signal
- * PC[15]  D16  RxClav   Receive cell available input/output signal
- * PD[15]  U17  UTPB[0]  UTOPIA bus bit 0 input/output signal
- * PD[14]  V19  UTPB[1]  UTOPIA bus bit 1 input/output signal
- * PD[13]  V18  UTPB[2]  UTOPIA bus bit 2 input/output signal
- * PD[12]  R16  UTPB[3]  UTOPIA bus bit 3 input/output signal
- * PD[11]  T16  RXENB    Receive enable input/output signal
- * PD[10]  W18  TXENB    Transmit enable input/output signal
- * PD[9]   V17  UTPCLK   UTOPIA clock input/output signal
- * PD[7]   T15  UTPB[4]  UTOPIA bus bit 4 input/output signal
- * PD[6]   V16  UTPB[5]  UTOPIA bus bit 5 input/output signal
- * PD[5]   U15  UTPB[6]  UTOPIA bus bit 6 input/output signal
- * PD[4]   U16  UTPB[7]  UTOPIA bus bit 7 input/output signal
- * PD[3]   W16  SOC      Start of cell input/output signal
- *
- * PARAMETERS: none
- *
- * RETURNS: void
- *
- * REMARK:
- *
- * The ATM parameters and data structures must be configured before
- * initializing the UTOPIA port. The UTOPIA port activates immediately
- * upon initialization, and if its associated data structures are not
- * initialized, the CPM will lock up.
- *
- ****************************************************************************/
-void atmUtpInit()
-{
-  volatile immap_t       *immap  = (immap_t *)CONFIG_SYS_IMMR;
-  volatile iop8xx_t      *iop    = &immap->im_ioport;
-  volatile car8xx_t	 *car    = &immap->im_clkrst;
-  volatile cpm8xx_t	 *cpm    = &immap->im_cpm;
-  int flag;
-
-  flag = disable_interrupts();
-
-  /*-----------------------------------------------------------------*/
-  /* SCCR - System Clock Control Register                            */
-  /*                                                                 */
-  /* The UTOPIA clock can be selected to be internal clock or        */
-  /* external clock (selected by the UTOPIA mode register).          */
-  /* In case of internal clock, the UTOPIA clock is derived from     */
-  /* the system frequency divided by two dividers.                   */
-  /* Bits 27-31 of the SCCR register are defined to control the      */
-  /* UTOPIA clock.                                                   */
-  /*                                                                 */
-  /* SCCR[27:29] DFUTP  Division factor. Divide the system clock     */
-  /*                    by 2^DFUTP.                                  */
-  /* SCCR[30:31] DFAUTP Additional division factor. Divide the       */
-  /*                    system clock by the following value:         */
-  /*                    00 = divide by 1                             */
-  /*                    00 = divide by 3                             */
-  /*                    10 = divide by 5                             */
-  /*                    11 = divide by 7                             */
-  /*                                                                 */
-  /* Note that the UTOPIA clock must be programmed as to operate     */
-  /* within the range SYSCLK/10 .. 50MHz.                            */
-  /*-----------------------------------------------------------------*/
-  car->car_sccr &= 0xFFFFFFE0;
-  car->car_sccr |= 0x00000008; /* UTPCLK = SYSCLK / 4 */
-
-  /*-----------------------------------------------------------------*/
-  /* RCCR - RISC Controller Configuration Register                   */
-  /*                                                                 */
-  /* RCCR[8]     DR1M IDMA Request 0 Mode                            */
-  /*                  0 = edge sensitive                             */
-  /*                  1 = level sensitive                            */
-  /* RCCR[9]     DR0M IDMA Request 0 Mode                            */
-  /*                  0 = edge sensitive                             */
-  /*                  1 = level sensitive                            */
-  /* RCCR[10:11] DRQP IDMA Request Priority                          */
-  /*                  00 = IDMA req. have more prio. than SCCs       */
-  /*                  01 = IDMA req. have less prio. then SCCs       */
-  /*                  10 = IDMA requests have the lowest prio.       */
-  /*                  11 = reserved                                  */
-  /*                                                                 */
-  /* The RCCR[DR0M] and RCCR[DR1M] bits must be set to enable UTOPIA */
-  /* operation. Also, program RCCR[DPQP] to 01 to give SCC transfers */
-  /* higher priority.                                                */
-  /*-----------------------------------------------------------------*/
-  cpm->cp_rccr &= 0xFF0F;
-  cpm->cp_rccr |= 0x00D0;
-
-  /*-----------------------------------------------------------------*/
-  /* Port B - TxClav Signal                                          */
-  /*-----------------------------------------------------------------*/
-  cpm->cp_pbpar |= 0x00010000; /* PBPAR[15] = 1 */
-  cpm->cp_pbdir &= 0xFFFEFFFF; /* PBDIR[15] = 0 */
-
-  /*-----------------------------------------------------------------*/
-  /* UTOPIA Mode Register                                            */
-  /*                                                                 */
-  /* - muxed bus (master operation only)                             */
-  /* - multi PHY (because of a bug in the MPC860P rev.E.0)           */
-  /* - internal clock                                                */
-  /* - no loopback                                                   */
-  /* - do no activate statistical counters                           */
-  /*-----------------------------------------------------------------*/
-  iop->utmode = 0x00000004; SYNC;
-
-  /*-----------------------------------------------------------------*/
-  /* Port D - UTOPIA Data and Control Signals                        */
-  /*                                                                 */
-  /* 15-12 UTPB[0:3] UTOPIA bus bit 0 - 3 input/output signals       */
-  /* 11    RXENB     UTOPIA receive enable input/output signal       */
-  /* 10    TXENB     UTOPIA transmit enable input/output signal      */
-  /* 9     TUPCLK    UTOPIA clock input/output signal                */
-  /* 8     MII-MDC   Used by MII in simult. MII and UTOPIA operation */
-  /* 7-4   UTPB[4:7] UTOPIA bus bit 4 - 7 input/output signals       */
-  /* 3     SOC       UTOPIA Start of cell input/output signal        */
-  /* 2               Reserved                                        */
-  /* 1               Enable UTOPIA mode                              */
-  /* 0               Enable SAR                                      */
-  /*-----------------------------------------------------------------*/
-  iop->iop_pdpar |= 0xDF7F; SYNC;
-  iop->iop_pddir &= 0x2080; SYNC;
-
-  /*-----------------------------------------------------------------*/
-  /* Port C - RxClav Signal                                          */
-  /*-----------------------------------------------------------------*/
-  iop->iop_pcpar  |= 0x0001; /* PCPAR[15] = 1 */
-  iop->iop_pcdir  &= 0xFFFE; /* PCDIR[15] = 0 */
-  iop->iop_pcso   &= 0xFFFE; /* PCSO[15]  = 0 */
-
-  if (flag)
-    enable_interrupts();
-}
diff --git a/board/siemens/IAD210/atm.h b/board/siemens/IAD210/atm.h
deleted file mode 100644
index cd5b45e..0000000
--- a/board/siemens/IAD210/atm.h
+++ /dev/null
@@ -1,287 +0,0 @@ 
-typedef unsigned char uint8;
-typedef unsigned short uint16;
-typedef unsigned int uint32;
-typedef volatile unsigned char vuint8;
-typedef volatile unsigned short vuint16;
-typedef volatile unsigned int vuint32;
-
-
-#define DPRAM_ATM CONFIG_SYS_IMMR + 0x3000
-
-#define ATM_DPRAM_BEGIN  (DPRAM_ATM - CONFIG_SYS_IMMR - 0x2000)
-#define NUM_CONNECTIONS  1
-#define SAR_RXB_SIZE     1584
-#define AM_HMASK         0x0FFFFFF0
-
-#define NUM_CT_ENTRIES           (NUM_CONNECTIONS)
-#define NUM_TCTE_ENTRIES         (NUM_CONNECTIONS)
-#define NUM_AM_ENTRIES           (NUM_CONNECTIONS+1)
-#define NUM_AP_ENTRIES           (NUM_CONNECTIONS+1)
-#define NUM_MPHYPT_ENTRIES       1
-#define NUM_APCP_ENTRIES         1
-#define NUM_APCT_PRIO_1_ENTRIES  146	/* Determines minimum rate */
-#define NUM_TQ_ENTRIES           12
-
-#define SIZE_OF_CT_ENTRY         64
-#define SIZE_OF_TCTE_ENTRY       32
-#define SIZE_OF_AM_ENTRY         4
-#define SIZE_OF_AP_ENTRY         2
-#define SIZE_OF_MPHYPT_ENTRY     2
-#define SIZE_OF_APCP_ENTRY       32
-#define SIZE_OF_APCT_ENTRY       2
-#define SIZE_OF_TQ_ENTRY         2
-
-#define CT_BASE           ((ATM_DPRAM_BEGIN + 63) & 0xFFC0)	/*64 */
-#define TCTE_BASE         (CT_BASE + NUM_CT_ENTRIES * SIZE_OF_CT_ENTRY)	/*32 */
-#define APCP_BASE         (TCTE_BASE + NUM_TCTE_ENTRIES * SIZE_OF_TCTE_ENTRY)	/*32 */
-#define AM_BEGIN          (APCP_BASE + NUM_APCP_ENTRIES * SIZE_OF_APCP_ENTRY)	/*4 */
-#define AM_BASE           (AM_BEGIN + (NUM_AM_ENTRIES - 1) * SIZE_OF_AM_ENTRY)
-#define AP_BEGIN          (AM_BEGIN + NUM_AM_ENTRIES * SIZE_OF_AM_ENTRY)	/*2 */
-#define AP_BASE           (AP_BEGIN + (NUM_AP_ENTRIES - 1) * SIZE_OF_AP_ENTRY)
-#define MPHYPT_BASE       (AP_BEGIN + NUM_AP_ENTRIES * SIZE_OF_AP_ENTRY)	/*2 */
-#define APCT_PRIO_1_BASE  (MPHYPT_BASE + NUM_MPHYPT_ENTRIES * SIZE_OF_MPHYPT_ENTRY)	/*2 */
-#define TQ_BASE           (APCT_PRIO_1_BASE + NUM_APCT_PRIO_1_ENTRIES * SIZE_OF_APCT_ENTRY)	/*2 */
-#define ATM_DPRAM_SIZE    ((TQ_BASE + NUM_TQ_ENTRIES * SIZE_OF_TQ_ENTRY) - ATM_DPRAM_BEGIN)
-
-#define CT_PTR(base)      ((struct ct_entry_t *)((char *)(base) + 0x2000 + CT_BASE))
-#define TCTE_PTR(base)    ((struct tcte_entry_t *)((char *)(base) + 0x2000 + TCTE_BASE))
-#define AM_PTR(base)      ((uint32 *)((char *)(base) + 0x2000 + AM_BASE))
-#define AP_PTR(base)      ((uint16 *)((char *)(base) + 0x2000 + AP_BASE))
-#define MPHYPT_PTR(base)  ((uint16 *)((char *)(base) + 0x2000 + MPHYPT_BASE))
-#define APCP_PTR(base)    ((struct apc_params_t *)((char*)(base) + 0x2000 + APCP_BASE))
-#define APCT1_PTR(base)   ((uint16 *)((char *)(base) + 0x2000 + APCT_PRIO_1_BASE))
-#define APCT2_PTR(base)   ((uint16 *)((char *)(base) + 0x2000 + APCT_PRIO_2_BASE))
-#define APCT3_PTR(base)   ((uint16 *)((char *)(base) + 0x2000 + APCT_PRIO_3_BASE))
-#define TQ_PTR(base)      ((uint16 *)((char *)(base) + 0x2000 + TQ_BASE))
-
-/* SAR registers */
-#define RBDBASE(base)	  ((vuint32 *)(base + 0x3F00))	/* Base address of RxBD-List */
-#define SRFCR(base)	  ((vuint8 *)(base + 0x3F04))	/* DMA Receive function code */
-#define SRSTATE(base)	  ((vuint8 *)(base + 0x3F05))	/* DMA Receive status */
-#define MRBLR(base)	  ((vuint16 *)(base + 0x3F06))	/* Init to 0 for ATM */
-#define RSTATE(base)	  ((vuint32 *)(base + 0x3F08))	/* Do not write to */
-#define R_CNT(base)	  ((vuint16 *)(base + 0x3F10))	/* Do not write to */
-#define STFCR(base)	  ((vuint8 *)(base + 0x3F12))	/* DMA Transmit function code */
-#define STSTATE(base)	  ((vuint8 *)(base + 0x3F13))	/* DMA Transmit status */
-#define TBDBASE(base)	  ((vuint32 *)(base + 0x3F14))	/* Base address of TxBD-List */
-#define TSTATE(base)	  ((vuint32 *)(base + 0x3F18))	/* Do not write to */
-#define COMM_CH(base)	  ((vuint16 *)(base + 0x3F1C))	/* Command channel */
-#define STCHNUM(base)	  ((vuint16 *)(base + 0x3F1E))	/* Do not write to */
-#define T_CNT(base)	  ((vuint16 *)(base + 0x3F20))	/* Do not write to */
-#define CTBASE(base)	  ((vuint16 *)(base + 0x3F22))	/* Base address of Connection-table */
-#define ECTBASE(base)	  ((vuint32 *)(base + 0x3F24))	/* Valid only for external Conn.-table */
-#define INTBASE(base)	  ((vuint32 *)(base + 0x3F28))	/* Base address of Interrupt-table */
-#define INTPTR(base)	  ((vuint32 *)(base + 0x3F2C))	/* Pointer to Interrupt-queue */
-#define C_MASK(base)	  ((vuint32 *)(base + 0x3F30))	/* CRC-mask */
-#define SRCHNUM(base)	  ((vuint16 *)(base + 0x3F34))	/* Do not write to */
-#define INT_CNT(base)	  ((vuint16 *)(base + 0x3F36))	/* Interrupt-Counter */
-#define INT_ICNT(base)	  ((vuint16 *)(base + 0x3F38))	/* Interrupt threshold */
-#define TSTA(base)	  ((vuint16 *)(base + 0x3F3A))	/* Time-stamp-address */
-#define OLDLEN(base)	  ((vuint16 *)(base + 0x3F3C))	/* Do not write to */
-#define SMRBLR(base)	  ((vuint16 *)(base + 0x3F3E))	/* SAR max RXBuffer length */
-#define EHEAD(base)	  ((vuint32 *)(base + 0x3F40))	/* Valid for serial mode */
-#define EPAYLOAD(base)	  ((vuint32 *)(base + 0x3F44))	/* Valid for serial mode */
-#define TQBASE(base)	  ((vuint16 *)(base + 0x3F48))	/* Base address of Tx queue */
-#define TQEND(base)	  ((vuint16 *)(base + 0x3F4A))	/* End address of Tx queue */
-#define TQAPTR(base)	  ((vuint16 *)(base + 0x3F4C))	/* TQ APC pointer */
-#define TQTPTR(base)	  ((vuint16 *)(base + 0x3F4E))	/* TQ Tx pointer */
-#define APCST(base)	  ((vuint16 *)(base + 0x3F50))	/* APC status */
-#define APCPTR(base)	  ((vuint16 *)(base + 0x3F52))	/* APC parameter pointer */
-#define HMASK(base)	  ((vuint32 *)(base + 0x3F54))	/* Header mask */
-#define AMBASE(base)	  ((vuint16 *)(base + 0x3F58))	/* Address match table base */
-#define AMEND(base)	  ((vuint16 *)(base + 0x3F5A))	/* Address match table end */
-#define APBASE(base)	  ((vuint16 *)(base + 0x3F5C))	/* Address match parameter */
-#define FLBASE(base)	  ((vuint32 *)(base + 0x3F54))	/* First-level table base */
-#define SLBASE(base)	  ((vuint32 *)(base + 0x3F58))	/* Second-level table base */
-#define FLMASK(base)	  ((vuint16 *)(base + 0x3F5C))	/* First-level mask */
-#define ECSIZE(base)	  ((vuint16 *)(base + 0x3F5E))	/* Valid for extended mode */
-#define APCT_REAL(base)	  ((vuint32 *)(base + 0x3F60))	/* APC 32 bit counter */
-#define R_PTR(base)	  ((vuint32 *)(base + 0x3F64))	/* Do not write to */
-#define RTEMP(base)	  ((vuint32 *)(base + 0x3F68))	/* Do not write to */
-#define T_PTR(base)	  ((vuint32 *)(base + 0x3F6C))	/* Do not write to */
-#define TTEMP(base)	  ((vuint32 *)(base + 0x3F70))	/* Do not write to */
-
-/* ESAR registers */
-#define FMCTIMESTMP(base) ((vuint32 *)(base + 0x3F80))	/* Perf.Mon.Timestamp */
-#define FMCTEMPLATE(base) ((vuint32 *)(base + 0x3F84))	/* Perf.Mon.Template */
-#define PMPTR(base)       ((vuint16 *)(base + 0x3F88))	/* Perf.Mon.Table */
-#define PMCHANNEL(base)	  ((vuint16 *)(base + 0x3F8A))	/* Perf.Mon.Channel */
-#define MPHYST(base)	  ((vuint16 *)(base + 0x3F90))	/* Multi-PHY Status */
-#define TCTEBASE(base)	  ((vuint16 *)(base + 0x3F92))	/* Internal TCT Extension Base */
-#define ETCTEBASE(base)	  ((vuint32 *)(base + 0x3F94))	/* External TCT Extension Base */
-#define COMM_CH2(base)	  ((vuint32 *)(base + 0x3F98))	/* 2nd command channel word */
-#define STATBASE(base)	  ((vuint16 *)(base + 0x3F9C))	/* Statistics table pointer */
-
-/* UTOPIA Mode Register */
-#define UTMODE(base)      (CAST(vuint32 *)(base + 0x0978))
-
-/* SAR commands */
-#define TRANSMIT_CHANNEL_ACTIVATE_CMD   0x0FC1
-#define TRANSMIT_CHANNEL_DEACTIVATE_CMD 0x1FC1
-#define STOP_TRANSMIT_CMD               0x2FC1
-#define RESTART_TRANSMIT_CMD            0x3FC1
-#define STOP_RECEIVE_CMD                0x4FC1
-#define RESTART_RECEIVE_CMD             0x5FC1
-#define APC_BYPASS_CMD                  0x6FC1
-#define MEM_WRITE_CMD                   0x7FC1
-#define CPCR_FLG                        0x0001
-
-/* INT flags */
-#define INT_VALID	0x80000000
-#define INT_WRAP	0x40000000
-#define INT_APCO	0x00800000
-#define INT_TQF		0x00200000
-#define INT_RXF		0x00080000
-#define INT_BSY		0x00040000
-#define INT_TXB		0x00020000
-#define INT_RXB		0x00010000
-
-#define NUM_INT_ENTRIES   80
-#define SIZE_OF_INT_ENTRY 4
-
-struct apc_params_t {
-	vuint16 apct_base1;	/* APC Table - First Priority Base pointer */
-	vuint16 apct_end1;	/* First APC Table - Length */
-	vuint16 apct_ptr1;	/* First APC Table Pointer */
-	vuint16 apct_sptr1;	/* APC Table First Priority Service pointer */
-	vuint16 etqbase;	/* Enhanced Transmit Queue Base pointer */
-	vuint16 etqend;		/* Enhanced Transmit Queue End pointer */
-	vuint16 etqaptr;	/* Enhanced Transmit Queue APC pointer */
-	vuint16 etqtptr;	/* Enhanced Transmit Queue Transmitter pointer */
-	vuint16 apc_mi;		/* APC - Max Iteration */
-	vuint16 ncits;		/* Number of Cells In TimeSlot  */
-	vuint16 apcnt;		/* APC - N Timer */
-	vuint16 reserved1;	/* reserved */
-	vuint16 eapcst;		/* APC status */
-	vuint16 ptp_counter;	/* PTP queue length */
-	vuint16 ptp_txch;	/* PTP channel */
-	vuint16 reserved2;	/* reserved */
-};
-
-struct ct_entry_t {
-	/* RCT */
-	unsigned fhnt:1;
-	unsigned pm_rct:1;
-	unsigned reserved0:6;
-	unsigned hec:1;
-	unsigned clp:1;
-	unsigned cng_ncrc:1;
-	unsigned inf_rct:1;
-	unsigned cngi_ptp:1;
-	unsigned cdis_rct:1;
-	unsigned aal_rct:2;
-	uint16 rbalen;
-	uint32 rcrc;
-	uint32 rb_ptr;
-	uint16 rtmlen;
-	uint16 rbd_ptr;
-	uint16 rbase;
-	uint16 tstamp;
-	uint16 imask;
-	unsigned ft:2;
-	unsigned nim:1;
-	unsigned reserved1:2;
-	unsigned rpmt:6;
-	unsigned reserved2:5;
-	uint8 reserved3[8];
-	/* TCT */
-	unsigned reserved4:1;
-	unsigned pm_tct:1;
-	unsigned reserved5:6;
-	unsigned pc:1;
-	unsigned reserved6:2;
-	unsigned inf_tct:1;
-	unsigned cr10:1;
-	unsigned cdis_tct:1;
-	unsigned aal_tct:2;
-	uint16 tbalen;
-	uint32 tcrc;
-	uint32 tb_ptr;
-	uint16 ttmlen;
-	uint16 tbd_ptr;
-	uint16 tbase;
-	unsigned reserved7:5;
-	unsigned tpmt:6;
-	unsigned reserved8:3;
-	unsigned avcf:1;
-	unsigned act:1;
-	uint32 chead;
-	uint16 apcl;
-	uint16 apcpr;
-	unsigned out:1;
-	unsigned bnr:1;
-	unsigned tservice:2;
-	unsigned apcp:12;
-	uint16 apcpf;
-};
-
-struct tcte_entry_t {
-	unsigned res1:4;
-	unsigned scr:12;
-	uint16 scrf;
-	uint16 bt;
-	uint16 buptrh;
-	uint32 buptrl;
-	unsigned vbr2:1;
-	unsigned res2:15;
-	uint16 oobr;
-	uint16 res3[8];
-};
-
-#define SIZE_OF_RBD  12
-#define SIZE_OF_TBD  12
-
-struct atm_bd_t {
-	vuint16 flags;
-	vuint16 length;
-	unsigned char *buffer_ptr;
-	vuint16 cpcs_uu_cpi;
-	vuint16 reserved;
-};
-
-/* BD flags */
-#define EMPTY		0x8000
-#define READY		0x8000
-#define WRAP		0x2000
-#define INTERRUPT	0x1000
-#define LAST		0x0800
-#define FIRST		0x0400
-#define OAM             0x0400
-#define CONTINUOUS	0x0200
-#define HEC_ERROR	0x0080
-#define CELL_LOSS	0x0040
-#define CONGESTION	0x0020
-#define ABORT		0x0010
-#define LEN_ERROR	0x0002
-#define CRC_ERROR	0x0001
-
-struct atm_connection_t {
-	struct atm_bd_t *rbd_ptr;
-	int num_rbd;
-	struct atm_bd_t *tbd_ptr;
-	int num_tbd;
-	struct ct_entry_t *ct_ptr;
-	struct tcte_entry_t *tcte_ptr;
-	void *drv;
-	void (*notify) (void *drv, int event);
-};
-
-struct atm_driver_t {
-	int loaded;
-	int started;
-	char *csram;
-	int csram_size;
-	uint32 *am_top;
-	uint16 *ap_top;
-	uint32 *int_reload_ptr;
-	uint32 *int_serv_ptr;
-	struct atm_bd_t *rbd_base_ptr;
-	struct atm_bd_t *tbd_base_ptr;
-	unsigned linerate_in_bps;
-};
-
-extern struct atm_connection_t g_conn[NUM_CONNECTIONS];
-extern struct atm_driver_t g_atm;
-
-extern int atmLoad (void);
-extern void atmUnload (void);
diff --git a/board/siemens/IAD210/flash.c b/board/siemens/IAD210/flash.c
deleted file mode 100644
index c262e0f..0000000
--- a/board/siemens/IAD210/flash.c
+++ /dev/null
@@ -1,502 +0,0 @@ 
-/*
- * (C) Copyright 2000, 2001, 2002
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <mpc8xx.h>
-
-flash_info_t	flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
-
-/*-----------------------------------------------------------------------
- * Functions
- */
-static ulong flash_get_size (vu_long *addr, flash_info_t *info);
-static int write_word (flash_info_t *info, ulong dest, ulong data);
-static void flash_get_offsets (ulong base, flash_info_t *info);
-
-/*-----------------------------------------------------------------------
- */
-
-unsigned long flash_init (void)
-{
-  volatile immap_t     *immap  = (immap_t *)CONFIG_SYS_IMMR;
-  volatile memctl8xx_t *memctl = &immap->im_memctl;
-  unsigned long size;
-  int i;
-
-  /* Init: no FLASHes known */
-  for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
-    flash_info[i].flash_id = FLASH_UNKNOWN;
-  }
-
-  /* Static FLASH Bank configuration here - FIXME XXX */
-
-  size = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
-
-  if (flash_info[0].flash_id == FLASH_UNKNOWN) {
-    printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
-			size, size<<20);
-  }
-
-
-  /* Remap FLASH according to real size */
-  memctl->memc_or0 = CONFIG_SYS_OR_TIMING_FLASH | (-size & 0xFFFF8000);
-  memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_V;
-
-  /* Re-do sizing to get full correct info */
-  size = flash_get_size((vu_long *)CONFIG_SYS_FLASH_BASE, &flash_info[0]);
-
-  flash_get_offsets (CONFIG_SYS_FLASH_BASE, &flash_info[0]);
-
-  flash_info[0].size = size;
-
-  return (size);
-}
-
-/*-----------------------------------------------------------------------
- */
-static void flash_get_offsets (ulong base, flash_info_t *info)
-{
-  int i;
-
-  /* set up sector start address table */
-  if (info->flash_id & FLASH_BTYPE) {
-    /* set sector offsets for bottom boot block type	*/
-    info->start[0] = base + 0x00000000;
-    info->start[1] = base + 0x00008000;
-    info->start[2] = base + 0x0000C000;
-    info->start[3] = base + 0x00010000;
-    for (i = 4; i < info->sector_count; i++) {
-      info->start[i] = base + (i * 0x00020000) - 0x00060000;
-    }
-  } else {
-    /* set sector offsets for top boot block type		*/
-    i = info->sector_count - 1;
-    info->start[i--] = base + info->size - 0x00008000;
-    info->start[i--] = base + info->size - 0x0000C000;
-    info->start[i--] = base + info->size - 0x00010000;
-    for (; i >= 0; i--) {
-      info->start[i] = base + i * 0x00020000;
-    }
-  }
-
-}
-
-/*-----------------------------------------------------------------------
- */
-void flash_print_info  (flash_info_t *info)
-{
-  int i;
-
-  if (info->flash_id == FLASH_UNKNOWN) {
-    printf ("missing or unknown FLASH type\n");
-    return;
-  }
-
-  switch (info->flash_id & FLASH_VENDMASK) {
-  case FLASH_MAN_AMD:	printf ("AMD ");		break;
-  case FLASH_MAN_FUJ:	printf ("FUJITSU ");		break;
-  default:		printf ("Unknown Vendor ");	break;
-  }
-
-  switch (info->flash_id & FLASH_TYPEMASK) {
-  case FLASH_AM400B:	printf ("AM29LV400B (4 Mbit, bottom boot sect)\n");
-    break;
-  case FLASH_AM400T:	printf ("AM29LV400T (4 Mbit, top boot sector)\n");
-    break;
-  case FLASH_AM800B:	printf ("AM29LV800B (8 Mbit, bottom boot sect)\n");
-    break;
-  case FLASH_AM800T:	printf ("AM29LV800T (8 Mbit, top boot sector)\n");
-    break;
-  case FLASH_AM160B:	printf ("AM29LV160B (16 Mbit, bottom boot sect)\n");
-    break;
-  case FLASH_AM160T:	printf ("AM29LV160T (16 Mbit, top boot sector)\n");
-    break;
-  case FLASH_AM320B:	printf ("AM29LV320B (32 Mbit, bottom boot sect)\n");
-    break;
-  case FLASH_AM320T:	printf ("AM29LV320T (32 Mbit, top boot sector)\n");
-    break;
-  default:		printf ("Unknown Chip Type\n");
-    break;
-  }
-
-  printf ("  Size: %ld MB in %d Sectors\n",
-	  info->size >> 20, info->sector_count);
-
-  printf ("  Sector Start Addresses:");
-  for (i=0; i<info->sector_count; ++i) {
-    if ((i % 5) == 0)
-      printf ("\n   ");
-    printf (" %08lX%s",
-			info->start[i],
-			info->protect[i] ? " (RO)" : "     "
-	    );
-  }
-  printf ("\n");
-}
-
-/*-----------------------------------------------------------------------
- */
-
-
-/*-----------------------------------------------------------------------
- */
-
-/*
- * The following code cannot be run from FLASH!
- */
-
-static ulong flash_get_size (vu_long *addr, flash_info_t *info)
-{
-  short i;
-  ulong value;
-  ulong base = (ulong)addr;
-
-
-  /* Write auto select command: read Manufacturer ID */
-  addr[0x0555] = 0x00AA00AA;
-  addr[0x02AA] = 0x00550055;
-  addr[0x0555] = 0x00900090;
-
-  value = addr[0];
-
-  switch (value) {
-  case AMD_MANUFACT:
-    info->flash_id = FLASH_MAN_AMD;
-    break;
-  case FUJ_MANUFACT:
-    info->flash_id = FLASH_MAN_FUJ;
-    break;
-  default:
-    info->flash_id = FLASH_UNKNOWN;
-    info->sector_count = 0;
-    info->size = 0;
-    return (0);			/* no or unknown flash	*/
-  }
-
-  value = addr[1];			/* device ID		*/
-
-  switch (value) {
-  case AMD_ID_LV400T:
-    info->flash_id += FLASH_AM400T;
-    info->sector_count = 11;
-    info->size = 0x00100000;
-    break;				/* => 1 MB		*/
-
-  case AMD_ID_LV400B:
-    info->flash_id += FLASH_AM400B;
-    info->sector_count = 11;
-    info->size = 0x00100000;
-    break;				/* => 1 MB		*/
-
-  case AMD_ID_LV800T:
-    info->flash_id += FLASH_AM800T;
-    info->sector_count = 19;
-    info->size = 0x00200000;
-    break;				/* => 2 MB		*/
-
-  case AMD_ID_LV800B:
-    info->flash_id += FLASH_AM800B;
-    info->sector_count = 19;
-    info->size = 0x00200000;
-    break;				/* => 2 MB		*/
-
-  case AMD_ID_LV160T:
-    info->flash_id += FLASH_AM160T;
-    info->sector_count = 35;
-    info->size = 0x00400000;
-    break;				/* => 4 MB		*/
-
-  case AMD_ID_LV160B:
-    info->flash_id += FLASH_AM160B;
-    info->sector_count = 35;
-    info->size = 0x00400000;
-    break;				/* => 4 MB		*/
-#if 0	/* enable when device IDs are available */
-  case AMD_ID_LV320T:
-    info->flash_id += FLASH_AM320T;
-    info->sector_count = 67;
-    info->size = 0x00800000;
-    break;				/* => 8 MB		*/
-
-  case AMD_ID_LV320B:
-    info->flash_id += FLASH_AM320B;
-    info->sector_count = 67;
-    info->size = 0x00800000;
-    break;				/* => 8 MB		*/
-#endif
-  default:
-    info->flash_id = FLASH_UNKNOWN;
-    return (0);			/* => no or unknown flash */
-
-  }
-
-  /* set up sector start address table */
-  if (info->flash_id & FLASH_BTYPE) {
-    /* set sector offsets for bottom boot block type	*/
-    info->start[0] = base + 0x00000000;
-    info->start[1] = base + 0x00008000;
-    info->start[2] = base + 0x0000C000;
-    info->start[3] = base + 0x00010000;
-    for (i = 4; i < info->sector_count; i++) {
-      info->start[i] = base + (i * 0x00020000) - 0x00060000;
-    }
-  } else {
-    /* set sector offsets for top boot block type		*/
-    i = info->sector_count - 1;
-    info->start[i--] = base + info->size - 0x00008000;
-    info->start[i--] = base + info->size - 0x0000C000;
-    info->start[i--] = base + info->size - 0x00010000;
-    for (; i >= 0; i--) {
-      info->start[i] = base + i * 0x00020000;
-    }
-  }
-
-  /* check for protected sectors */
-  for (i = 0; i < info->sector_count; i++) {
-    /* read sector protection at sector address, (A7 .. A0) = 0x02 */
-    /* D0 = 1 if protected */
-    addr = (volatile unsigned long *)(info->start[i]);
-    info->protect[i] = addr[2] & 1;
-  }
-
-  /*
-   * Prevent writes to uninitialized FLASH.
-   */
-  if (info->flash_id != FLASH_UNKNOWN) {
-    addr = (volatile unsigned long *)info->start[0];
-
-    *addr = 0x00F000F0;	/* reset bank */
-  }
-
-  return (info->size);
-}
-
-
-/*-----------------------------------------------------------------------
- */
-
-int	flash_erase (flash_info_t *info, int s_first, int s_last)
-{
-  vu_long *addr = (vu_long*)(info->start[0]);
-  int flag, prot, sect, l_sect;
-  ulong start, now, last;
-
-  if ((s_first < 0) || (s_first > s_last)) {
-    if (info->flash_id == FLASH_UNKNOWN) {
-      printf ("- missing\n");
-    } else {
-      printf ("- no sectors to erase\n");
-    }
-    return 1;
-  }
-
-  if ((info->flash_id == FLASH_UNKNOWN) ||
-      (info->flash_id > FLASH_AMD_COMP)) {
-    printf ("Can't erase unknown flash type %08lx - aborted\n",
-			info->flash_id);
-    return 1;
-  }
-
-  prot = 0;
-  for (sect=s_first; sect<=s_last; ++sect) {
-    if (info->protect[sect]) {
-      prot++;
-    }
-  }
-
-  if (prot) {
-    printf ("- Warning: %d protected sectors will not be erased!\n",
-			prot);
-  } else {
-    printf ("\n");
-  }
-
-  l_sect = -1;
-
-  /* Disable interrupts which might cause a timeout here */
-  flag = disable_interrupts();
-
-  addr[0x0555] = 0x00AA00AA;
-  addr[0x02AA] = 0x00550055;
-  addr[0x0555] = 0x00800080;
-  addr[0x0555] = 0x00AA00AA;
-  addr[0x02AA] = 0x00550055;
-
-  /* Start erase on unprotected sectors */
-  for (sect = s_first; sect<=s_last; sect++) {
-    if (info->protect[sect] == 0) {	/* not protected */
-      addr = (vu_long*)(info->start[sect]);
-      addr[0] = 0x00300030;
-      l_sect = sect;
-    }
-  }
-
-  /* re-enable interrupts if necessary */
-  if (flag)
-    enable_interrupts();
-
-  /* wait at least 80us - let's wait 1 ms */
-  udelay (1000);
-
-  /*
-   * We wait for the last triggered sector
-   */
-  if (l_sect < 0)
-    goto DONE;
-
-  start = get_timer (0);
-  last  = start;
-  addr = (vu_long*)(info->start[l_sect]);
-  while ((addr[0] & 0x00800080) != 0x00800080) {
-    if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
-      printf ("Timeout\n");
-      return 1;
-    }
-    /* show that we're waiting */
-    if ((now - last) > 1000) {	/* every second */
-      putc ('.');
-      last = now;
-    }
-  }
-
- DONE:
-  /* reset to read mode */
-  addr = (volatile unsigned long *)info->start[0];
-  addr[0] = 0x00F000F0;	/* reset bank */
-
-  printf (" done\n");
-  return 0;
-}
-
-/*-----------------------------------------------------------------------
- * Copy memory to flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-
-int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
-{
-  ulong cp, wp, data;
-  int i, l, rc;
-
-  wp = (addr & ~3);	/* get lower word aligned address */
-
-  /*
-   * handle unaligned start bytes
-   */
-  if ((l = addr - wp) != 0) {
-    data = 0;
-    for (i=0, cp=wp; i<l; ++i, ++cp) {
-      data = (data << 8) | (*(uchar *)cp);
-    }
-    for (; i<4 && cnt>0; ++i) {
-      data = (data << 8) | *src++;
-      --cnt;
-      ++cp;
-    }
-    for (; cnt==0 && i<4; ++i, ++cp) {
-      data = (data << 8) | (*(uchar *)cp);
-    }
-
-    if ((rc = write_word(info, wp, data)) != 0) {
-      return (rc);
-    }
-    wp += 4;
-  }
-
-  /*
-   * handle word aligned part
-   */
-  while (cnt >= 4) {
-    data = 0;
-    for (i=0; i<4; ++i) {
-      data = (data << 8) | *src++;
-    }
-    if ((rc = write_word(info, wp, data)) != 0) {
-      return (rc);
-    }
-    wp  += 4;
-    cnt -= 4;
-  }
-
-  if (cnt == 0) {
-    return (0);
-  }
-
-  /*
-   * handle unaligned tail bytes
-   */
-  data = 0;
-  for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
-    data = (data << 8) | *src++;
-    --cnt;
-  }
-  for (; i<4; ++i, ++cp) {
-    data = (data << 8) | (*(uchar *)cp);
-  }
-
-  return (write_word(info, wp, data));
-}
-
-/*-----------------------------------------------------------------------
- * Write a word to Flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-static int write_word (flash_info_t *info, ulong dest, ulong data)
-{
-  vu_long *addr = (vu_long*)(info->start[0]);
-  ulong start;
-  int flag;
-
-  /* Check if Flash is (sufficiently) erased */
-  if ((*((vu_long *)dest) & data) != data) {
-    return (2);
-  }
-  /* Disable interrupts which might cause a timeout here */
-  flag = disable_interrupts();
-
-  addr[0x0555] = 0x00AA00AA;
-  addr[0x02AA] = 0x00550055;
-  addr[0x0555] = 0x00A000A0;
-
-  *((vu_long *)dest) = data;
-
-  /* re-enable interrupts if necessary */
-  if (flag)
-    enable_interrupts();
-
-  /* data polling for D7 */
-  start = get_timer (0);
-  while ((*((vu_long *)dest) & 0x00800080) != (data & 0x00800080)) {
-    if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
-      return (1);
-    }
-  }
-  return (0);
-}
-
-/*-----------------------------------------------------------------------
- */
diff --git a/board/siemens/IAD210/u-boot.lds b/board/siemens/IAD210/u-boot.lds
deleted file mode 100644
index c0f1073..0000000
--- a/board/siemens/IAD210/u-boot.lds
+++ /dev/null
@@ -1,107 +0,0 @@ 
-/*
- * (C) Copyright 2000-2010
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_ARCH(powerpc)
-
-SECTIONS
-{
-  /* Read-only sections, merged into text segment: */
-  . = + SIZEOF_HEADERS;
-  .text      :
-  {
-    /* WARNING - the following is hand-optimized to fit within	*/
-    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
-
-    arch/powerpc/cpu/mpc8xx/start.o	(.text*)
-    arch/powerpc/cpu/mpc8xx/traps.o	(.text*)
-    arch/powerpc/cpu/mpc8xx/libmpc8xx.o	(.text*)
-    net/libnet.o			(.text*)
-    drivers/rtc/librtc.o		(.text*)
-
-    . = env_offset;
-    common/env_embedded.o		(.text*)
-
-    *(.text*)
-  }
-  _etext = .;
-  PROVIDE (etext = .);
-  .rodata    :
-  {
-    *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
-  }
-
-  /* Read-write section, merged into data segment: */
-  . = (. + 0x00FF) & 0xFFFFFF00;
-  _erotext = .;
-  PROVIDE (erotext = .);
-  .reloc   :
-  {
-    _GOT2_TABLE_ = .;
-    KEEP(*(.got2))
-    KEEP(*(.got))
-    PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4);
-    _FIXUP_TABLE_ = .;
-    KEEP(*(.fixup))
-  }
-  __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1;
-  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
-  .data    :
-  {
-    *(.data*)
-    *(.sdata*)
-  }
-  _edata  =  .;
-  PROVIDE (edata = .);
-
-  . = .;
-
-  . = ALIGN(4);
-  .u_boot_list : {
-	#include <u-boot.lst>
-  }
-
-
-  . = .;
-  __start___ex_table = .;
-  __ex_table : { *(__ex_table) }
-  __stop___ex_table = .;
-
-  . = ALIGN(256);
-  __init_begin = .;
-  .text.init : { *(.text.init) }
-  .data.init : { *(.data.init) }
-  . = ALIGN(256);
-  __init_end = .;
-
-  __bss_start = .;
-  .bss (NOLOAD)       :
-  {
-   *(.bss*)
-   *(.sbss*)
-   *(COMMON)
-   . = ALIGN(4);
-  }
-  __bss_end__ = . ;
-  PROVIDE (end = .);
-}
diff --git a/board/siemens/SCM/Makefile b/board/siemens/SCM/Makefile
deleted file mode 100644
index 07db9d4..0000000
--- a/board/siemens/SCM/Makefile
+++ /dev/null
@@ -1,49 +0,0 @@ 
-#
-# (C) Copyright 2001-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-include $(TOPDIR)/config.mk
-
-ifneq ($(OBJTREE),$(SRCTREE))
-$(shell mkdir -p $(obj)../common $(obj)../../tqc/tqm8xx)
-endif
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	= scm.o flash.o fpga_scm.o ../common/fpga.o \
-	  ../../tqc/tqm8xx/load_sernum_ethaddr.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
diff --git a/board/siemens/SCM/flash.c b/board/siemens/SCM/flash.c
deleted file mode 100644
index 4a6d538..0000000
--- a/board/siemens/SCM/flash.c
+++ /dev/null
@@ -1,488 +0,0 @@ 
-/*
- * (C) Copyright 2001, 2002
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * Flash Routines for AMD devices on the TQM8260 board
- *
- *--------------------------------------------------------------------
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <mpc8xx.h>
-
-#define V_ULONG(a)	(*(volatile unsigned long *)( a ))
-#define V_BYTE(a)	(*(volatile unsigned char *)( a ))
-
-
-flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
-
-
-/*-----------------------------------------------------------------------
- */
-void flash_reset (void)
-{
-	if (flash_info[0].flash_id != FLASH_UNKNOWN) {
-		V_ULONG (flash_info[0].start[0]) = 0x00F000F0;
-		V_ULONG (flash_info[0].start[0] + 4) = 0x00F000F0;
-	}
-}
-
-/*-----------------------------------------------------------------------
- */
-ulong flash_get_size (ulong baseaddr, flash_info_t * info)
-{
-	short i;
-	unsigned long flashtest_h, flashtest_l;
-
-	/* Write auto select command sequence and test FLASH answer */
-	V_ULONG (baseaddr + ((ulong) 0x0555 << 3)) = 0x00AA00AA;
-	V_ULONG (baseaddr + ((ulong) 0x02AA << 3)) = 0x00550055;
-	V_ULONG (baseaddr + ((ulong) 0x0555 << 3)) = 0x00900090;
-	V_ULONG (baseaddr + 4 + ((ulong) 0x0555 << 3)) = 0x00AA00AA;
-	V_ULONG (baseaddr + 4 + ((ulong) 0x02AA << 3)) = 0x00550055;
-	V_ULONG (baseaddr + 4 + ((ulong) 0x0555 << 3)) = 0x00900090;
-
-	flashtest_h = V_ULONG (baseaddr);	/* manufacturer ID     */
-	flashtest_l = V_ULONG (baseaddr + 4);
-
-	switch ((int) flashtest_h) {
-	case AMD_MANUFACT:
-		info->flash_id = FLASH_MAN_AMD;
-		break;
-	case FUJ_MANUFACT:
-		info->flash_id = FLASH_MAN_FUJ;
-		break;
-	default:
-		info->flash_id = FLASH_UNKNOWN;
-		info->sector_count = 0;
-		info->size = 0;
-		return (0);			/* no or unknown flash     */
-	}
-
-	flashtest_h = V_ULONG (baseaddr + 8);	/* device ID           */
-	flashtest_l = V_ULONG (baseaddr + 12);
-	if (flashtest_h != flashtest_l) {
-		info->flash_id = FLASH_UNKNOWN;
-	} else {
-		switch (flashtest_h) {
-		case AMD_ID_LV800T:
-			info->flash_id += FLASH_AM800T;
-			info->sector_count = 19;
-			info->size = 0x00400000;
-			break;			/* 4 * 1 MB = 4 MB  */
-		case AMD_ID_LV800B:
-			info->flash_id += FLASH_AM800B;
-			info->sector_count = 19;
-			info->size = 0x00400000;
-			break;			/* 4 * 1 MB = 4 MB  */
-		case AMD_ID_LV160T:
-			info->flash_id += FLASH_AM160T;
-			info->sector_count = 35;
-			info->size = 0x00800000;
-			break;			/* 4 * 2 MB = 8 MB  */
-		case AMD_ID_LV160B:
-			info->flash_id += FLASH_AM160B;
-			info->sector_count = 35;
-			info->size = 0x00800000;
-			break;			/* 4 * 2 MB = 8 MB  */
-		case AMD_ID_DL322T:
-			info->flash_id += FLASH_AMDL322T;
-			info->sector_count = 71;
-			info->size = 0x01000000;
-			break;			/* 4 * 4 MB = 16 MB */
-		case AMD_ID_DL322B:
-			info->flash_id += FLASH_AMDL322B;
-			info->sector_count = 71;
-			info->size = 0x01000000;
-			break;			/* 4 * 4 MB = 16 MB */
-		case AMD_ID_DL323T:
-			info->flash_id += FLASH_AMDL323T;
-			info->sector_count = 71;
-			info->size = 0x01000000;
-			break;			/* 4 * 4 MB = 16 MB */
-		case AMD_ID_DL323B:
-			info->flash_id += FLASH_AMDL323B;
-			info->sector_count = 71;
-			info->size = 0x01000000;
-			break;			/* 4 * 4 MB = 16 MB */
-		case AMD_ID_LV640U:
-			info->flash_id += FLASH_AM640U;
-			info->sector_count = 128;
-			info->size = 0x02000000;
-			break;			/* 4 * 8 MB = 32 MB */
-		default:
-			info->flash_id = FLASH_UNKNOWN;
-			return (0);		/* no or unknown flash     */
-		}
-	}
-
-	if (flashtest_h == AMD_ID_LV640U) {
-
-		/* set up sector start adress table (uniform sector type) */
-		for (i = 0; i < info->sector_count; i++)
-			info->start[i] = baseaddr + (i * 0x00040000);
-
-	} else if (info->flash_id & FLASH_BTYPE) {
-
-		/* set up sector start adress table (bottom sector type) */
-		info->start[0] = baseaddr + 0x00000000;
-		info->start[1] = baseaddr + 0x00010000;
-		info->start[2] = baseaddr + 0x00018000;
-		info->start[3] = baseaddr + 0x00020000;
-		for (i = 4; i < info->sector_count; i++) {
-			info->start[i] = baseaddr + (i * 0x00040000) - 0x000C0000;
-		}
-
-	} else {
-
-		/* set up sector start adress table (top sector type) */
-		i = info->sector_count - 1;
-		info->start[i--] = baseaddr + info->size - 0x00010000;
-		info->start[i--] = baseaddr + info->size - 0x00018000;
-		info->start[i--] = baseaddr + info->size - 0x00020000;
-		for (; i >= 0; i--) {
-			info->start[i] = baseaddr + i * 0x00040000;
-		}
-	}
-
-	/* check for protected sectors */
-	for (i = 0; i < info->sector_count; i++) {
-		/* read sector protection at sector address, (A7 .. A0) = 0x02 */
-		if ((V_ULONG (info->start[i] + 16) & 0x00010001) ||
-			(V_ULONG (info->start[i] + 20) & 0x00010001)) {
-			info->protect[i] = 1;	/* D0 = 1 if protected */
-		} else {
-			info->protect[i] = 0;
-		}
-	}
-
-	flash_reset ();
-	return (info->size);
-}
-
-/*-----------------------------------------------------------------------
- */
-unsigned long flash_init (void)
-{
-	unsigned long size_b0 = 0;
-	int i;
-
-	/* Init: no FLASHes known */
-	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
-		flash_info[i].flash_id = FLASH_UNKNOWN;
-	}
-
-	/* Static FLASH Bank configuration here (only one bank) */
-
-	size_b0 = flash_get_size (CONFIG_SYS_FLASH0_BASE, &flash_info[0]);
-	if (flash_info[0].flash_id == FLASH_UNKNOWN || size_b0 == 0) {
-		printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
-				size_b0, size_b0 >> 20);
-	}
-
-	/*
-	 * protect monitor and environment sectors
-	 */
-
-#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH0_BASE
-	flash_protect (FLAG_PROTECT_SET,
-		       CONFIG_SYS_MONITOR_BASE,
-		       CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1, &flash_info[0]);
-#endif
-
-#if defined(CONFIG_ENV_IS_IN_FLASH) && defined(CONFIG_ENV_ADDR)
-# ifndef  CONFIG_ENV_SIZE
-#  define CONFIG_ENV_SIZE	CONFIG_ENV_SECT_SIZE
-# endif
-	flash_protect (FLAG_PROTECT_SET,
-		       CONFIG_ENV_ADDR,
-		       CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[0]);
-#endif
-
-	return (size_b0);
-}
-
-/*-----------------------------------------------------------------------
- */
-void flash_print_info (flash_info_t * info)
-{
-	int i;
-
-	if (info->flash_id == FLASH_UNKNOWN) {
-		printf ("missing or unknown FLASH type\n");
-		return;
-	}
-
-	switch (info->flash_id & FLASH_VENDMASK) {
-	case FLASH_MAN_AMD:
-		printf ("AMD ");
-		break;
-	case FLASH_MAN_FUJ:
-		printf ("FUJITSU ");
-		break;
-	default:
-		printf ("Unknown Vendor ");
-		break;
-	}
-
-	switch (info->flash_id & FLASH_TYPEMASK) {
-	case FLASH_AM800T:
-		printf ("29LV800T (8 M, top sector)\n");
-		break;
-	case FLASH_AM800B:
-		printf ("29LV800T (8 M, bottom sector)\n");
-		break;
-	case FLASH_AM160T:
-		printf ("29LV160T (16 M, top sector)\n");
-		break;
-	case FLASH_AM160B:
-		printf ("29LV160B (16 M, bottom sector)\n");
-		break;
-	case FLASH_AMDL322T:
-		printf ("29DL322T (32 M, top sector)\n");
-		break;
-	case FLASH_AMDL322B:
-		printf ("29DL322B (32 M, bottom sector)\n");
-		break;
-	case FLASH_AMDL323T:
-		printf ("29DL323T (32 M, top sector)\n");
-		break;
-	case FLASH_AMDL323B:
-		printf ("29DL323B (32 M, bottom sector)\n");
-		break;
-	case FLASH_AM640U:
-		printf ("29LV640D (64 M, uniform sector)\n");
-		break;
-	default:
-		printf ("Unknown Chip Type\n");
-		break;
-	}
-
-	printf ("  Size: %ld MB in %d Sectors\n",
-			info->size >> 20, info->sector_count);
-
-	printf ("  Sector Start Addresses:");
-	for (i = 0; i < info->sector_count; ++i) {
-		if ((i % 5) == 0)
-			printf ("\n   ");
-		printf (" %08lX%s",
-			info->start[i],
-			info->protect[i] ? " (RO)" : "     "
-		);
-	}
-	printf ("\n");
-	return;
-}
-
-/*-----------------------------------------------------------------------
- */
-int flash_erase (flash_info_t * info, int s_first, int s_last)
-{
-	int flag, prot, sect, l_sect;
-	ulong start, now, last;
-
-	if ((s_first < 0) || (s_first > s_last)) {
-		if (info->flash_id == FLASH_UNKNOWN) {
-			printf ("- missing\n");
-		} else {
-			printf ("- no sectors to erase\n");
-		}
-		return 1;
-	}
-
-	prot = 0;
-	for (sect = s_first; sect <= s_last; sect++) {
-		if (info->protect[sect])
-			prot++;
-	}
-
-	if (prot) {
-		printf ("- Warning: %d protected sectors will not be erased!\n",
-			prot);
-	} else {
-		printf ("\n");
-	}
-
-	l_sect = -1;
-
-	/* Disable interrupts which might cause a timeout here */
-	flag = disable_interrupts ();
-
-	V_ULONG (info->start[0] + (0x0555 << 3)) = 0x00AA00AA;
-	V_ULONG (info->start[0] + (0x02AA << 3)) = 0x00550055;
-	V_ULONG (info->start[0] + (0x0555 << 3)) = 0x00800080;
-	V_ULONG (info->start[0] + (0x0555 << 3)) = 0x00AA00AA;
-	V_ULONG (info->start[0] + (0x02AA << 3)) = 0x00550055;
-	V_ULONG (info->start[0] + 4 + (0x0555 << 3)) = 0x00AA00AA;
-	V_ULONG (info->start[0] + 4 + (0x02AA << 3)) = 0x00550055;
-	V_ULONG (info->start[0] + 4 + (0x0555 << 3)) = 0x00800080;
-	V_ULONG (info->start[0] + 4 + (0x0555 << 3)) = 0x00AA00AA;
-	V_ULONG (info->start[0] + 4 + (0x02AA << 3)) = 0x00550055;
-	udelay (1000);
-
-	/* Start erase on unprotected sectors */
-	for (sect = s_first; sect <= s_last; sect++) {
-		if (info->protect[sect] == 0) {	/* not protected */
-			V_ULONG (info->start[sect]) = 0x00300030;
-			V_ULONG (info->start[sect] + 4) = 0x00300030;
-			l_sect = sect;
-		}
-	}
-
-	/* re-enable interrupts if necessary */
-	if (flag)
-		enable_interrupts ();
-
-	/* wait at least 80us - let's wait 1 ms */
-	udelay (1000);
-
-	/*
-	 * We wait for the last triggered sector
-	 */
-	if (l_sect < 0)
-		goto DONE;
-
-	start = get_timer (0);
-	last = start;
-	while ((V_ULONG (info->start[l_sect]) & 0x00800080) != 0x00800080 ||
-	       (V_ULONG (info->start[l_sect] + 4) & 0x00800080) != 0x00800080)
-	{
-		if ((now = get_timer (start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
-			printf ("Timeout\n");
-			return 1;
-		}
-		/* show that we're waiting */
-		if ((now - last) > 1000) {	/* every second */
-			serial_putc ('.');
-			last = now;
-		}
-	}
-
-  DONE:
-	/* reset to read mode */
-	flash_reset ();
-
-	printf (" done\n");
-	return 0;
-}
-
-static int write_dword (flash_info_t *, ulong, unsigned char *);
-
-/*-----------------------------------------------------------------------
- * Copy memory to flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-
-int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
-{
-	ulong dp;
-	static unsigned char bb[8];
-	int i, l, rc, cc = cnt;
-
-	dp = (addr & ~7);		/* get lower dword aligned address */
-
-	/*
-	 * handle unaligned start bytes
-	 */
-	if ((l = addr - dp) != 0) {
-		for (i = 0; i < 8; i++)
-			bb[i] = (i < l || (i - l) >= cc) ? V_BYTE (dp + i) : *src++;
-		if ((rc = write_dword (info, dp, bb)) != 0) {
-			return (rc);
-		}
-		dp += 8;
-		cc -= 8 - l;
-	}
-
-	/*
-	 * handle word aligned part
-	 */
-	while (cc >= 8) {
-		if ((rc = write_dword (info, dp, src)) != 0) {
-			return (rc);
-		}
-		dp += 8;
-		src += 8;
-		cc -= 8;
-	}
-
-	if (cc <= 0) {
-		return (0);
-	}
-
-	/*
-	 * handle unaligned tail bytes
-	 */
-	for (i = 0; i < 8; i++) {
-		bb[i] = (i < cc) ? *src++ : V_BYTE (dp + i);
-	}
-	return (write_dword (info, dp, bb));
-}
-
-/*-----------------------------------------------------------------------
- * Write a dword to Flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-static int write_dword (flash_info_t * info, ulong dest, unsigned char *pdata)
-{
-	ulong start, cl, ch;
-	int flag, i;
-
-	for (ch = 0, i = 0; i < 4; i++)
-		ch = (ch << 8) + *pdata++;	/* high word    */
-	for (cl = 0, i = 0; i < 4; i++)
-		cl = (cl << 8) + *pdata++;	/* low word */
-
-	/* Check if Flash is (sufficiently) erased */
-	if ((*((vu_long *) dest) & ch) != ch
-		|| (*((vu_long *) (dest + 4)) & cl) != cl) {
-		return (2);
-	}
-
-	/* Disable interrupts which might cause a timeout here */
-	flag = disable_interrupts ();
-
-	V_ULONG (info->start[0] + (0x0555 << 3)) = 0x00AA00AA;
-	V_ULONG (info->start[0] + (0x02AA << 3)) = 0x00550055;
-	V_ULONG (info->start[0] + (0x0555 << 3)) = 0x00A000A0;
-	V_ULONG (dest) = ch;
-	V_ULONG (info->start[0] + 4 + (0x0555 << 3)) = 0x00AA00AA;
-	V_ULONG (info->start[0] + 4 + (0x02AA << 3)) = 0x00550055;
-	V_ULONG (info->start[0] + 4 + (0x0555 << 3)) = 0x00A000A0;
-	V_ULONG (dest + 4) = cl;
-
-	/* re-enable interrupts if necessary */
-	if (flag)
-		enable_interrupts ();
-
-	/* data polling for D7 */
-	start = get_timer (0);
-	while (((V_ULONG (dest) & 0x00800080) != (ch & 0x00800080)) ||
-		   ((V_ULONG (dest + 4) & 0x00800080) != (cl & 0x00800080))) {
-		if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
-			return (1);
-		}
-	}
-	return (0);
-}
diff --git a/board/siemens/SCM/fpga_scm.c b/board/siemens/SCM/fpga_scm.c
deleted file mode 100644
index acd9c15..0000000
--- a/board/siemens/SCM/fpga_scm.c
+++ /dev/null
@@ -1,104 +0,0 @@ 
-/*
- * (C) Copyright 2002
- * Wolfgang Grandegger, DENX Software Engineering, wg@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-
-#include <common.h>
-#include <mpc8260.h>
-#include <common.h>
-#include "../common/fpga.h"
-
-fpga_t fpga_list[] = {
-	{"FIOX", CONFIG_SYS_FIOX_BASE,
-	 CONFIG_SYS_PD_FIOX_INIT, CONFIG_SYS_PD_FIOX_PROG, CONFIG_SYS_PD_FIOX_DONE}
-	,
-	{"FDOHM", CONFIG_SYS_FDOHM_BASE,
-	 CONFIG_SYS_PD_FDOHM_INIT, CONFIG_SYS_PD_FDOHM_PROG, CONFIG_SYS_PD_FDOHM_DONE}
-};
-int fpga_count = sizeof (fpga_list) / sizeof (fpga_t);
-
-
-ulong fpga_control (fpga_t * fpga, int cmd)
-{
-	volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
-
-	switch (cmd) {
-	case FPGA_INIT_IS_HIGH:
-		immr->im_ioport.iop_pdird &= ~fpga->init_mask;	/* input */
-		return (immr->im_ioport.iop_pdatd & fpga->init_mask) ? 1 : 0;
-
-	case FPGA_INIT_SET_LOW:
-		immr->im_ioport.iop_pdird |= fpga->init_mask;	/* output */
-		immr->im_ioport.iop_pdatd &= ~fpga->init_mask;
-		break;
-
-	case FPGA_INIT_SET_HIGH:
-		immr->im_ioport.iop_pdird |= fpga->init_mask;	/* output */
-		immr->im_ioport.iop_pdatd |= fpga->init_mask;
-		break;
-
-	case FPGA_PROG_SET_LOW:
-		immr->im_ioport.iop_pdatd &= ~fpga->prog_mask;
-		break;
-
-	case FPGA_PROG_SET_HIGH:
-		immr->im_ioport.iop_pdatd |= fpga->prog_mask;
-		break;
-
-	case FPGA_DONE_IS_HIGH:
-		return (immr->im_ioport.iop_pdatd & fpga->done_mask) ? 1 : 0;
-
-	case FPGA_READ_MODE:
-		break;
-
-	case FPGA_LOAD_MODE:
-		break;
-
-	case FPGA_GET_ID:
-		if (fpga->conf_base == CONFIG_SYS_FIOX_BASE) {
-			ulong ver =
-				*(volatile ulong *) (fpga->conf_base + 0x10);
-			return ((ver >> 10) & 0xf) + ((ver >> 2) & 0xf0);
-		} else if (fpga->conf_base == CONFIG_SYS_FDOHM_BASE) {
-			return (*(volatile ushort *) fpga->conf_base) & 0xff;
-		} else {
-			return *(volatile ulong *) fpga->conf_base;
-		}
-
-	case FPGA_INIT_PORTS:
-		immr->im_ioport.iop_ppard &= ~fpga->init_mask;	/* INIT I/O */
-		immr->im_ioport.iop_psord &= ~fpga->init_mask;
-		immr->im_ioport.iop_pdird &= ~fpga->init_mask;
-
-		immr->im_ioport.iop_ppard &= ~fpga->prog_mask;	/* PROG Output */
-		immr->im_ioport.iop_psord &= ~fpga->prog_mask;
-		immr->im_ioport.iop_pdird |= fpga->prog_mask;
-
-		immr->im_ioport.iop_ppard &= ~fpga->done_mask;	/* DONE Input */
-		immr->im_ioport.iop_psord &= ~fpga->done_mask;
-		immr->im_ioport.iop_pdird &= ~fpga->done_mask;
-
-		break;
-
-	}
-	return 0;
-}
diff --git a/board/siemens/SCM/scm.c b/board/siemens/SCM/scm.c
deleted file mode 100644
index 461b56e..0000000
--- a/board/siemens/SCM/scm.c
+++ /dev/null
@@ -1,541 +0,0 @@ 
-/*
- * (C) Copyright 2001
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <ioports.h>
-#include <mpc8260.h>
-#include <linux/compiler.h>
-
-#include "scm.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-static void config_scoh_cs(void);
-extern int  fpga_init(void);
-
-#if 0
-#define DEBUGF(fmt,args...)   printf (fmt ,##args)
-#else
-#define DEBUGF(fmt,args...)
-#endif
-
-/*
- * I/O Port configuration table
- *
- * if conf is 1, then that port pin will be configured at boot time
- * according to the five values podr/pdir/ppar/psor/pdat for that entry
- */
-
-const iop_conf_t iop_conf_tab[4][32] = {
-
-    /* Port A configuration */
-    {	/*	      conf ppar psor pdir podr pdat */
-	/* PA31 */ {   1,   1,   1,   0,   0,   0   }, /* FCC1 MII COL */
-	/* PA30 */ {   1,   1,   1,   0,   0,   0   }, /* FCC1 MII CRS */
-	/* PA29 */ {   1,   1,   1,   1,   0,   0   }, /* FCC1 MII TX_ER */
-	/* PA28 */ {   1,   1,   1,   1,   0,   0   }, /* FCC1 MII TX_EN */
-	/* PA27 */ {   1,   1,   1,   0,   0,   0   }, /* FCC1 MII RX_DV */
-	/* PA26 */ {   1,   1,   1,   0,   0,   0   }, /* FCC1 MII RX_ER */
-	/* PA25 */ {   0,   0,   0,   1,   0,   0   },
-	/* PA24 */ {   0,   0,   0,   1,   0,   0   },
-	/* PA23 */ {   0,   0,   0,   1,   0,   0   },
-	/* PA22 */ {   0,   0,   0,   1,   0,   0   },
-	/* PA21 */ {   1,   1,   0,   1,   0,   0   }, /* FCC1 MII TxD[3] */
-	/* PA20 */ {   1,   1,   0,   1,   0,   0   }, /* FCC1 MII TxD[2] */
-	/* PA19 */ {   1,   1,   0,   1,   0,   0   }, /* FCC1 MII TxD[1] */
-	/* PA18 */ {   1,   1,   0,   1,   0,   0   }, /* FCC1 MII TxD[0] */
-	/* PA17 */ {   1,   1,   0,   0,   0,   0   }, /* FCC1 MII RxD[0] */
-	/* PA16 */ {   1,   1,   0,   0,   0,   0   }, /* FCC1 MII RxD[1]*/
-	/* PA15 */ {   1,   1,   0,   0,   0,   0   }, /* FCC1 MII RxD[2] */
-	/* PA14 */ {   1,   1,   0,   0,   0,   0   }, /* FCC1 MII RxD[3] */
-	/* PA13 */ {   0,   0,   0,   1,   0,   0   },
-	/* PA12 */ {   0,   0,   0,   1,   0,   0   },
-	/* PA11 */ {   0,   0,   0,   1,   0,   0   },
-	/* PA10 */ {   0,   0,   0,   1,   0,   0   },
-	/* PA9  */ {   1,   1,   1,   1,   0,   0   }, /* TDM_A1 L1TXD0 */
-	/* PA8  */ {   1,   1,   1,   0,   0,   0   }, /* TDM_A1 L1RXD0 */
-	/* PA7  */ {   1,   1,   1,   0,   0,   0   }, /* TDM_A1 L1TSYNC */
-	/* PA6  */ {   1,   1,   1,   0,   0,   0   }, /* TDM_A1 L1RSYNC */
-	/* PA5  */ {   1,   0,   0,   0,   0,   0   }, /* FIOX_FPGA_PR */
-	/* PA4  */ {   1,   0,   0,   0,   0,   0   }, /* DOHM_FPGA_PR */
-	/* PA3  */ {   1,   1,   0,   0,   0,   0   }, /* TDM RXCLK4 */
-	/* PA2  */ {   1,   1,   0,   0,   0,   0   }, /* TDM TXCLK4 */
-	/* PA1  */ {   0,   0,   0,   1,   0,   0   },
-	/* PA0  */ {   1,   0,   0,   0,   0,   0   }  /* BUSY */
-    },
-
-    /* Port B configuration */
-    {   /*	      conf ppar psor pdir podr pdat */
-	/* PB31 */ {   1,   0,   0,   1,   0,   0   }, /* EQ_ALARM_MIN */
-	/* PB30 */ {   1,   0,   0,   1,   0,   0   }, /* EQ_ALARM_MAJ */
-	/* PB29 */ {   1,   0,   0,   1,   0,   0   }, /* COM_ALARM_MIN */
-	/* PB28 */ {   1,   0,   0,   1,   0,   0   }, /* COM_ALARM_MAJ */
-	/* PB27 */ {   0,   1,   0,   0,   0,   0   },
-	/* PB26 */ {   0,   1,   0,   0,   0,   0   },
-	/* PB25 */ {   1,   0,   0,   1,   0,   0   }, /* LED_GREEN_L */
-	/* PB24 */ {   1,   0,   0,   1,   0,   0   }, /* LED_RED_L */
-	/* PB23 */ {   1,   1,   1,   0,   0,   0   }, /* TDM_D2 L1TXD */
-	/* PB22 */ {   1,   1,   1,   0,   0,   0   }, /* TDM_D2 L1RXD */
-	/* PB21 */ {   1,   1,   1,   0,   0,   0   }, /* TDM_D2 L1TSYNC */
-	/* PB20 */ {   1,   1,   1,   0,   0,   0   }, /* TDM_D2 L1RSYNC */
-	/* PB19 */ {   1,   0,   0,   0,   0,   0   }, /* UID */
-	/* PB18 */ {   0,   1,   0,   0,   0,   0   },
-	/* PB17 */ {   1,   1,   0,   0,   0,   0   }, /* FCC3 MII RX_DV */
-	/* PB16 */ {   1,   1,   0,   0,   0,   0   }, /* FCC3 MII RX_ER */
-	/* PB15 */ {   1,   1,   0,   1,   0,   0   }, /* FCC3 MII TX_ER */
-	/* PB14 */ {   1,   1,   0,   1,   0,   0   }, /* FCC3 MII TX_EN */
-	/* PB13 */ {   1,   1,   0,   0,   0,   0   }, /* FCC3 MII COL */
-	/* PB12 */ {   1,   1,   0,   0,   0,   0   }, /* FCC3 MII CRS */
-	/* PB11 */ {   1,   1,   0,   0,   0,   0   }, /* FCC3 MII RxD[3] */
-	/* PB10 */ {   1,   1,   0,   0,   0,   0   }, /* FCC3 MII RxD[2] */
-	/* PB9  */ {   1,   1,   0,   0,   0,   0   }, /* FCC3 MII RxD[1] */
-	/* PB8  */ {   1,   1,   0,   0,   0,   0   }, /* FCC3 MII RxD[0] */
-	/* PB7  */ {   1,   1,   0,   1,   0,   0   }, /* FCC3 MII TxD[3] */
-	/* PB6  */ {   1,   1,   0,   1,   0,   0   }, /* FCC3 MII TxD[2] */
-	/* PB5  */ {   1,   1,   0,   1,   0,   0   }, /* FCC3 MII TxD[1] */
-	/* PB4  */ {   1,   1,   0,   1,   0,   0   }, /* FCC3 MII TxD[0] */
-	/* PB3  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
-	/* PB2  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
-	/* PB1  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
-	/* PB0  */ {   0,   0,   0,   0,   0,   0   }  /* pin doesn't exist */
-    },
-
-    /* Port C configuration */
-    {   /*	      conf ppar psor pdir podr pdat */
-	/* PC31 */ {   1,   1,   0,   0,   0,   0   }, /* TDM RXCLK1 */
-	/* PC30 */ {   1,   1,   0,   0,   0,   0   }, /* TDM TXCLK1 */
-	/* PC29 */ {   1,   1,   0,   0,   0,   0   }, /* TDM RXCLK3 */
-	/* PC28 */ {   1,   1,   0,   0,   0,   0   }, /* TDM TXCLK3 */
-	/* PC27 */ {   1,   1,   0,   0,   0,   0   }, /* TDM RXCLK2 */
-	/* PC26 */ {   1,   1,   0,   0,   0,   0   }, /* TDM TXCLK2 */
-	/* PC25 */ {   0,   0,   0,   1,   0,   0   },
-	/* PC24 */ {   0,   0,   0,   1,   0,   0   },
-	/* PC23 */ {   0,   1,   0,   1,   0,   0   },
-	/* PC22 */ {   0,   1,   0,   0,   0,   0   },
-	/* PC21 */ {   1,   1,   0,   0,   0,   0   }, /* FCC1 MII TX_CLK */
-	/* PC20 */ {   1,   1,   0,   0,   0,   0   }, /* FCC1 MII RX_CLK */
-	/* PC19 */ {   0,   1,   0,   0,   0,   0   },
-	/* PC18 */ {   0,   1,   0,   0,   0,   0   },
-	/* PC17 */ {   1,   1,   0,   0,   0,   0   }, /* FCC3 MII RX_CLK */
-	/* PC16 */ {   1,   1,   0,   0,   0,   0   }, /* FCC3 MII TX_CLK */
-	/* PC15 */ {   0,   0,   0,   1,   0,   0   },
-	/* PC14 */ {   0,   1,   0,   0,   0,   0   },
-	/* PC13 */ {   0,   0,   0,   1,   0,   0   }, /* RES_PHY_L */
-	/* PC12 */ {   0,   0,   0,   1,   0,   0   },
-	/* PC11 */ {   0,   0,   0,   1,   0,   0   },
-	/* PC10 */ {   0,   0,   0,   1,   0,   0   },
-	/* PC9  */ {   0,   1,   1,   0,   0,   0   }, /* TDM_A2 L1TSYNC */
-	/* PC8  */ {   0,   0,   0,   0,   0,   0   }, /* FEP_RDY */
-	/* PC7  */ {   0,   0,   0,   0,   0,   0   },
-	/* PC6  */ {   0,   0,   0,   0,   0,   0   }, /* UC4_ALARM_L */
-	/* PC5  */ {   0,   0,   0,   0,   0,   0   }, /* UC3_ALARM_L */
-	/* PC4  */ {   0,   0,   0,   0,   0,   0   }, /* UC2_ALARM_L */
-	/* PC3  */ {   0,   0,   0,   1,   0,   0   }, /* RES_MISC_L */
-	/* PC2  */ {   0,   0,   0,   1,   0,   0   }, /* RES_OH_L */
-	/* PC1  */ {   0,   0,   0,   1,   0,   0   }, /* RES_DOHM_L */
-	/* PC0  */ {   0,   0,   0,   1,   0,   0   }, /* RES_FIOX_L */
-    },
-
-    /* Port D configuration */
-    {   /*	      conf ppar psor pdir podr pdat */
-	/* PD31 */ {   1,   1,   0,   0,   0,   0   }, /* SCC1 EN RxD */
-	/* PD30 */ {   1,   1,   1,   1,   0,   0   }, /* SCC1 EN TxD */
-	/* PD29 */ {   0,   0,   0,   0,   0,   0   }, /* INIT_F */
-	/* PD28 */ {   0,   0,   0,   1,   0,   0   }, /* DONE_F */
-	/* PD27 */ {   0,   0,   0,   0,   0,   0   }, /* INIT_D */
-	/* PD26 */ {   0,   0,   0,   1,   0,   0   }, /* DONE_D */
-	/* PD25 */ {   0,   0,   0,   1,   0,   0   },
-	/* PD24 */ {   0,   0,   0,   1,   0,   0   },
-	/* PD23 */ {   0,   0,   0,   1,   0,   0   },
-	/* PD22 */ {   1,   1,   1,   0,   0,   0   }, /* TDM_A2 L1TXD */
-	/* PD21 */ {   1,   1,   1,   0,   0,   0   }, /* TDM_A2 L1RXD */
-	/* PD20 */ {   1,   1,   1,   0,   0,   0   }, /* TDM_A2 L1RSYNC */
-	/* PD19 */ {   1,   1,   1,   0,   0,   0   }, /* SPI SPISEL */
-	/* PD18 */ {   1,   1,   1,   0,   0,   0   }, /* SPI SPICLK */
-	/* PD17 */ {   1,   1,   1,   0,   0,   0   }, /* SPI SPIMOSI */
-	/* PD16 */ {   1,   1,   1,   0,   0,   0   }, /* SPI SPIMOSO */
-#if defined(CONFIG_SOFT_I2C)
-	/* PD15 */ {   1,   0,   0,   1,   1,   1   }, /* I2C SDA */
-	/* PD14 */ {   1,   0,   0,   1,   1,   1   }, /* I2C SCL */
-#else
-#if defined(CONFIG_HARD_I2C)
-	/* PD15 */ {   1,   1,   1,   0,   1,   0   }, /* I2C SDA */
-	/* PD14 */ {   1,   1,   1,   0,   1,   0   }, /* I2C SCL */
-#else /* normal I/O port pins */
-	/* PD15 */ {   0,   1,   1,   0,   1,   0   }, /* I2C SDA */
-	/* PD14 */ {   0,   1,   1,   0,   1,   0   }, /* I2C SCL */
-#endif
-#endif
-	/* PD13 */ {   1,   1,   1,   0,   0,   0   }, /* TDM_B1 L1TXD */
-	/* PD12 */ {   1,   1,   1,   0,   0,   0   }, /* TDM_B1 L1RXD */
-	/* PD11 */ {   1,   1,   1,   0,   0,   0   }, /* TDM_B1 L1TSYNC */
-	/* PD10 */ {   1,   1,   1,   0,   0,   0   }, /* TDM_B1 L1RSYNC */
-	/* PD9  */ {   1,   1,   0,   1,   0,   0   }, /* SMC1 TXD */
-	/* PD8  */ {   1,   1,   0,   0,   0,   0   }, /* SMC1 RXD */
-	/* PD7  */ {   0,   0,   0,   1,   0,   1   },
-	/* PD6  */ {   0,   0,   0,   1,   0,   1   },
-	/* PD5  */ {   0,   0,   0,   1,   0,   0   }, /* PROG_F */
-	/* PD4  */ {   0,   0,   0,   1,   0,   0   }, /* PROG_D */
-	/* PD3  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
-	/* PD2  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
-	/* PD1  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
-	/* PD0  */ {   0,   0,   0,   0,   0,   0   }  /* pin doesn't exist */
-    }
-};
-
-/* ------------------------------------------------------------------------- */
-
-/* Check Board Identity:
- */
-int checkboard (void)
-{
-	char str[64];
-	int i = getenv_f("serial#", str, sizeof (str));
-
-	puts ("Board: ");
-
-	if (!i || strncmp (str, "TQM8260", 7)) {
-		puts ("### No HW ID - assuming TQM8260\n");
-		return (0);
-	}
-
-	puts (str);
-	putc ('\n');
-
-	return 0;
-}
-
-/* ------------------------------------------------------------------------- */
-
-/* Try SDRAM initialization with P/LSDMR=sdmr and ORx=orx
- *
- * This routine performs standard 8260 initialization sequence
- * and calculates the available memory size. It may be called
- * several times to try different SDRAM configurations on both
- * 60x and local buses.
- */
-static long int try_init (volatile memctl8260_t * memctl, ulong sdmr,
-						  ulong orx, volatile uchar * base)
-{
-	volatile uchar c = 0xff;
-	volatile uint *sdmr_ptr;
-	volatile uint *orx_ptr;
-	ulong maxsize, size;
-	int i;
-
-	/* We must be able to test a location outsize the maximum legal size
-	 * to find out THAT we are outside; but this address still has to be
-	 * mapped by the controller. That means, that the initial mapping has
-	 * to be (at least) twice as large as the maximum expected size.
-	 */
-	maxsize = (1 + (~orx | 0x7fff)) / 2;
-
-	/* Since CONFIG_SYS_SDRAM_BASE is always 0 (??), we assume that
-	 * we are configuring CS1 if base != 0
-	 */
-	sdmr_ptr = base ? &memctl->memc_lsdmr : &memctl->memc_psdmr;
-	orx_ptr = base ? &memctl->memc_or2 : &memctl->memc_or1;
-
-	*orx_ptr = orx;
-
-	/*
-	 * Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35):
-	 *
-	 * "At system reset, initialization software must set up the
-	 *  programmable parameters in the memory controller banks registers
-	 *  (ORx, BRx, P/LSDMR). After all memory parameters are configured,
-	 *  system software should execute the following initialization sequence
-	 *  for each SDRAM device.
-	 *
-	 *  1. Issue a PRECHARGE-ALL-BANKS command
-	 *  2. Issue eight CBR REFRESH commands
-	 *  3. Issue a MODE-SET command to initialize the mode register
-	 *
-	 *  The initial commands are executed by setting P/LSDMR[OP] and
-	 *  accessing the SDRAM with a single-byte transaction."
-	 *
-	 * The appropriate BRx/ORx registers have already been set when we
-	 * get here. The SDRAM can be accessed at the address CONFIG_SYS_SDRAM_BASE.
-	 */
-
-	*sdmr_ptr = sdmr | PSDMR_OP_PREA;
-	*base = c;
-
-	*sdmr_ptr = sdmr | PSDMR_OP_CBRR;
-	for (i = 0; i < 8; i++)
-		*base = c;
-
-	*sdmr_ptr = sdmr | PSDMR_OP_MRW;
-	*(base + CONFIG_SYS_MRS_OFFS) = c;	/* setting MR on address lines */
-
-	*sdmr_ptr = sdmr | PSDMR_OP_NORM | PSDMR_RFEN;
-	*base = c;
-
-	size = get_ram_size((long *)base, maxsize);
-
-	*orx_ptr = orx | ~(size - 1);
-
-	return (size);
-}
-
-/*
- * Test Power-On-Reset.
- */
-int power_on_reset (void)
-{
-	/* Test Reset Status Register */
-	return gd->reset_status & RSR_CSRS ? 0 : 1;
-}
-
-phys_size_t initdram (int board_type)
-{
-	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
-	volatile memctl8260_t *memctl = &immap->im_memctl;
-
-#ifndef CONFIG_SYS_RAMBOOT
-	long size8, size9;
-#endif
-	long psize, lsize;
-
-	psize = 16 * 1024 * 1024;
-	lsize = 0;
-
-	memctl->memc_psrt = CONFIG_SYS_PSRT;
-	memctl->memc_mptpr = CONFIG_SYS_MPTPR;
-
-#if 0							/* Just for debugging */
-#define	prt_br_or(brX,orX) do {				\
-    ulong start =  memctl->memc_ ## brX & 0xFFFF8000;	\
-    ulong sizem = ~memctl->memc_ ## orX | 0x00007FFF;	\
-    printf ("\n"					\
-	    #brX " 0x%08x  " #orX " 0x%08x "		\
-	    "==> 0x%08lx ... 0x%08lx = %ld MB\n",	\
-	memctl->memc_ ## brX, memctl->memc_ ## orX,	\
-	start, start+sizem, (sizem+1)>>20);		\
-    } while (0)
-	prt_br_or (br0, or0);
-	prt_br_or (br1, or1);
-	prt_br_or (br2, or2);
-	prt_br_or (br3, or3);
-#endif
-
-#ifndef CONFIG_SYS_RAMBOOT
-	/* 60x SDRAM setup:
-	 */
-	size8 = try_init (memctl, CONFIG_SYS_PSDMR_8COL, CONFIG_SYS_OR1_8COL,
-					  (uchar *) CONFIG_SYS_SDRAM_BASE);
-	size9 = try_init (memctl, CONFIG_SYS_PSDMR_9COL, CONFIG_SYS_OR1_9COL,
-					  (uchar *) CONFIG_SYS_SDRAM_BASE);
-
-	if (size8 < size9) {
-		psize = size9;
-		printf ("(60x:9COL - %ld MB, ", psize >> 20);
-	} else {
-		psize = try_init (memctl, CONFIG_SYS_PSDMR_8COL, CONFIG_SYS_OR1_8COL,
-						  (uchar *) CONFIG_SYS_SDRAM_BASE);
-		printf ("(60x:8COL - %ld MB, ", psize >> 20);
-	}
-
-	/* Local SDRAM setup:
-	 */
-#ifdef CONFIG_SYS_INIT_LOCAL_SDRAM
-	memctl->memc_lsrt = CONFIG_SYS_LSRT;
-	size8 = try_init (memctl, CONFIG_SYS_LSDMR_8COL, CONFIG_SYS_OR2_8COL,
-					  (uchar *) SDRAM_BASE2_PRELIM);
-	size9 = try_init (memctl, CONFIG_SYS_LSDMR_9COL, CONFIG_SYS_OR2_9COL,
-					  (uchar *) SDRAM_BASE2_PRELIM);
-
-	if (size8 < size9) {
-		lsize = size9;
-		printf ("Local:9COL - %ld MB) using ", lsize >> 20);
-	} else {
-		lsize = try_init (memctl, CONFIG_SYS_LSDMR_8COL, CONFIG_SYS_OR2_8COL,
-						  (uchar *) SDRAM_BASE2_PRELIM);
-		printf ("Local:8COL - %ld MB) using ", lsize >> 20);
-	}
-
-#if 0
-	/* Set up BR2 so that the local SDRAM goes
-	 * right after the 60x SDRAM
-	 */
-	memctl->memc_br2 = (CONFIG_SYS_BR2_PRELIM & ~BRx_BA_MSK) |
-			(CONFIG_SYS_SDRAM_BASE + psize);
-#endif
-#endif /* CONFIG_SYS_INIT_LOCAL_SDRAM */
-#endif /* CONFIG_SYS_RAMBOOT */
-
-	icache_enable ();
-
-	config_scoh_cs ();
-
-	return (psize);
-}
-
-/* ------------------------------------------------------------------------- */
-
-static void config_scoh_cs (void)
-{
-	volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
-	volatile memctl8260_t *memctl = &immr->im_memctl;
-	volatile can_reg_t *can = (volatile can_reg_t *) CONFIG_SYS_CAN0_BASE;
-	__maybe_unused volatile uint tmp, i;
-
-	/* Initialize OR3 / BR3 for CAN Bus Controller 0 */
-	memctl->memc_or3 = CONFIG_SYS_CAN0_OR3;
-	memctl->memc_br3 = CONFIG_SYS_CAN0_BR3;
-	/* Initialize OR4 / BR4 for CAN Bus Controller 1 */
-	memctl->memc_or4 = CONFIG_SYS_CAN1_OR4;
-	memctl->memc_br4 = CONFIG_SYS_CAN1_BR4;
-
-	/* Initialize MAMR to write in the array at address 0x0 */
-	memctl->memc_mamr = 0x00 | MxMR_OP_WARR | MxMR_GPL_x4DIS;
-
-	/* Initialize UPMA for CAN: single read */
-	memctl->memc_mdr = 0xcffeec00;
-	udelay (1);					/* Necessary to have the data correct in the UPM array!!!! */
-	/* The read on the CAN controller write the data of mdr in UPMA array. */
-	/* The index to the array will be incremented automatically
-	   through this read */
-	tmp = can->cpu_interface;
-
-	memctl->memc_mdr = 0x0ffcec00;
-	udelay (1);
-	tmp = can->cpu_interface;
-
-	memctl->memc_mdr = 0x0ffcec00;
-	udelay (1);
-	tmp = can->cpu_interface;
-
-	memctl->memc_mdr = 0x0ffcec00;
-	udelay (1);
-	tmp = can->cpu_interface;
-
-	memctl->memc_mdr = 0x0ffcec00;
-	udelay (1);
-	tmp = can->cpu_interface;
-
-	memctl->memc_mdr = 0x0ffcfc00;
-	udelay (1);
-	tmp = can->cpu_interface;
-
-	memctl->memc_mdr = 0x0ffcfc00;
-	udelay (1);
-	tmp = can->cpu_interface;
-
-	memctl->memc_mdr = 0xfffdec07;
-	udelay (1);
-	tmp = can->cpu_interface;
-
-
-	/* Initialize MAMR to write in the array at address 0x18 */
-	memctl->memc_mamr = 0x18 | MxMR_OP_WARR | MxMR_GPL_x4DIS;
-
-	/* Initialize UPMA for CAN: single write */
-	memctl->memc_mdr = 0xfcffec00;
-	udelay (1);
-	tmp = can->cpu_interface;
-
-	memctl->memc_mdr = 0x00ffec00;
-	udelay (1);
-	tmp = can->cpu_interface;
-
-	memctl->memc_mdr = 0x00ffec00;
-	udelay (1);
-	tmp = can->cpu_interface;
-
-	memctl->memc_mdr = 0x00ffec00;
-	udelay (1);
-	tmp = can->cpu_interface;
-
-	memctl->memc_mdr = 0x00ffec00;
-	udelay (1);
-	tmp = can->cpu_interface;
-
-	memctl->memc_mdr = 0x00fffc00;
-	udelay (1);
-	tmp = can->cpu_interface;
-
-	memctl->memc_mdr = 0x00fffc00;
-	udelay (1);
-	tmp = can->cpu_interface;
-
-	memctl->memc_mdr = 0x30ffec07;
-	udelay (1);
-	tmp = can->cpu_interface;
-
-	/* Initialize MAMR */
-	memctl->memc_mamr = MxMR_GPL_x4DIS;	/* GPL_B4 ouput line Disable */
-
-
-	/* Initialize OR5 / BR5 for the extended EEPROM Bank0 */
-	memctl->memc_or5 = CONFIG_SYS_EXTPROM_OR5;
-	memctl->memc_br5 = CONFIG_SYS_EXTPROM_BR5;
-	/* Initialize OR6 / BR6 for the extended EEPROM Bank1 */
-	memctl->memc_or6 = CONFIG_SYS_EXTPROM_OR6;
-	memctl->memc_br6 = CONFIG_SYS_EXTPROM_BR6;
-
-	/* Initialize OR7 / BR7 for the Glue Logic */
-	memctl->memc_or7 = CONFIG_SYS_FIOX_OR7;
-	memctl->memc_br7 = CONFIG_SYS_FIOX_BR7;
-
-	/* Initialize OR8 / BR8 for the DOH Logic */
-	memctl->memc_or8 = CONFIG_SYS_FDOHM_OR8;
-	memctl->memc_br8 = CONFIG_SYS_FDOHM_BR8;
-
-	DEBUGF ("OR0 %08x   BR0 %08x\n", memctl->memc_or0, memctl->memc_br0);
-	DEBUGF ("OR1 %08x   BR1 %08x\n", memctl->memc_or1, memctl->memc_br1);
-	DEBUGF ("OR2 %08x   BR2 %08x\n", memctl->memc_or2, memctl->memc_br2);
-	DEBUGF ("OR3 %08x   BR3 %08x\n", memctl->memc_or3, memctl->memc_br3);
-	DEBUGF ("OR4 %08x   BR4 %08x\n", memctl->memc_or4, memctl->memc_br4);
-	DEBUGF ("OR5 %08x   BR5 %08x\n", memctl->memc_or5, memctl->memc_br5);
-	DEBUGF ("OR6 %08x   BR6 %08x\n", memctl->memc_or6, memctl->memc_br6);
-	DEBUGF ("OR7 %08x   BR7 %08x\n", memctl->memc_or7, memctl->memc_br7);
-	DEBUGF ("OR8 %08x   BR8 %08x\n", memctl->memc_or8, memctl->memc_br8);
-
-	DEBUGF ("UPMA  addr 0x0\n");
-	memctl->memc_mamr = 0x00 | MxMR_OP_RARR | MxMR_GPL_x4DIS;
-	for (i = 0; i < 0x8; i++) {
-		tmp = can->cpu_interface;
-		udelay (1);
-		DEBUGF (" %08x ", memctl->memc_mdr);
-	}
-	DEBUGF ("\nUPMA  addr 0x18\n");
-	memctl->memc_mamr = 0x18 | MxMR_OP_RARR | MxMR_GPL_x4DIS;
-	for (i = 0; i < 0x8; i++) {
-		tmp = can->cpu_interface;
-		udelay (1);
-		DEBUGF (" %08x ", memctl->memc_mdr);
-	}
-	DEBUGF ("\n");
-	memctl->memc_mamr = MxMR_GPL_x4DIS;
-}
-
-/* ------------------------------------------------------------------------- */
-
-int misc_init_r (void)
-{
-	fpga_init ();
-	return (0);
-}
-
-/* ------------------------------------------------------------------------- */
diff --git a/board/siemens/SCM/scm.h b/board/siemens/SCM/scm.h
deleted file mode 100644
index cb5e03e..0000000
--- a/board/siemens/SCM/scm.h
+++ /dev/null
@@ -1,89 +0,0 @@ 
-/*
- * (C) Copyright 2001
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __SCM_H
-#define __SCM_H
-
-/*----------------*/
-/* CAN Structures */
-/*----------------*/
-
-/* Message */
-struct can_msg {
-    uchar	ctrl_0;
-    uchar	ctrl_1;
-    uchar	arbit_0;
-    uchar	arbit_1;
-    uchar	arbit_2;
-    uchar	arbit_3;
-    uchar	config;
-    uchar	data[8];
-} __attribute__ ((packed));
-
-typedef struct can_msg can_msg_t;
-
-/* CAN Register */
-typedef struct can_reg {
-    uchar	ctrl;
-    uchar	status;
-    uchar	cpu_interface;
-    uchar	resv0;
-    ushort	high_speed_rd;
-    ushort	gbl_mask_std;
-    uint	gbl_mask_extd;
-    uint	msg15_mask;
-    can_msg_t	msg1;
-    uchar	clkout;
-    can_msg_t	msg2;
-    uchar	bus_config;
-    can_msg_t	msg3;
-    uchar	bit_timing_0;
-    can_msg_t	msg4;
-    uchar	bit_timing_1;
-    can_msg_t	msg5;
-    uchar	interrupt;
-    can_msg_t	msg6;
-    uchar	resv1;
-    can_msg_t	msg7;
-    uchar	resv2;
-    can_msg_t	msg8;
-    uchar	resv3;
-    can_msg_t	msg9;
-    uchar	p1conf;
-    can_msg_t	msg10;
-    uchar	p2conf;
-    can_msg_t	msg11;
-    uchar	p1in;
-    can_msg_t	msg12;
-    uchar	p2in;
-    can_msg_t	msg13;
-    uchar	p1out;
-    can_msg_t	msg14;
-    uchar	p2out;
-    can_msg_t	msg15;
-    uchar	ser_res_addr;
-    uchar	resv_cs[0x8000-0x100];	/* 0x8000 is the min size for CS */
-} can_reg_t;
-
-
-#endif /* __SCM_H */
diff --git a/board/siemens/common/README b/board/siemens/common/README
deleted file mode 100644
index 7f1c8cd..0000000
--- a/board/siemens/common/README
+++ /dev/null
@@ -1,27 +0,0 @@ 
-CCM/SCM-Ergaenzungen fuer U-Boot und Linux:
--------------------------------------------
-
-Es gibt nun ein gemeinsames Kommando zum Laden der FPGAs:
-
-  => help fpga
-  fpga fpga status [name] - print FPGA status
-  fpga reset  [name] - reset FPGA
-  fpga load [name] addr - load FPGA configuration data
-
-Der Name kann beim CCM-Module auch weggelassen werden.
-Die Laengenangabe und damit "puma_len" ist nicht mehr
-noetig:
-
-  => fpga load puma 40600000
-  FPGA load PUMA: addr 40600000: (00000005)... done
-
-Die MTD-Partitionierung kann nun mittels "bootargs" ueber-
-geben werden:
-
-  => printenv addmtd
-  addmtd=setenv bootargs ${bootargs}
-    mtdparts=0:256k(U-Boot)ro,768k(Kernel),-(Rest)\;1:-(myJFFS2)
-
-Die Portierung auf SMC ist natuerlich noch nicht getestet.
-
-Wolfgang Grandegger (04.06.2002)
diff --git a/board/siemens/common/fpga.c b/board/siemens/common/fpga.c
deleted file mode 100644
index ef8bfde..0000000
--- a/board/siemens/common/fpga.c
+++ /dev/null
@@ -1,369 +0,0 @@ 
-/*
- * (C) Copyright 2002
- * Wolfgang Grandegger, DENX Software Engineering, wg@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-
-#include <common.h>
-#include <command.h>
-#include <linux/ctype.h>
-#include <common.h>
-
-#include "fpga.h"
-
-int  power_on_reset(void);
-
-/* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . */
-
-
-static int fpga_get_version(fpga_t* fpga, char* name)
-{
-    char vname[12];
-    /*
-     * Net-list string format:
-     *     "vvvvvvvvddddddddn...".
-     *     Version Date    Name
-     *     "0000000322042002PUMA" = PUMA version 3 from 22.04.2002.
-     */
-    if (strlen(name) < (16 + strlen(fpga->name)))
-	goto failure;
-    /* Check FPGA name */
-    if (strcmp(&name[16], fpga->name) != 0)
-	goto failure;
-    /* Get version number */
-    memcpy(vname, name, 8);
-    vname[8] = '\0';
-    return simple_strtoul(vname, NULL, 16);
-
- failure:
-    printf("Image name %s is invalid\n", name);
-    return -1;
-}
-
-/* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . */
-
-static fpga_t* fpga_get(char* fpga_name)
-{
-    char name[FPGA_NAME_LEN];
-    int i;
-
-    if (strlen(fpga_name) >= FPGA_NAME_LEN)
-	goto failure;
-    for (i = 0; i < strlen(fpga_name); i++)
-	name[i] = toupper(fpga_name[i]);
-    name[i] = '\0';
-    for (i = 0; i < fpga_count; i++) {
-	if (strcmp(name, fpga_list[i].name) == 0)
-	    return &fpga_list[i];
-    }
- failure:
-    printf("FPGA: name %s is invalid\n", fpga_name);
-    return NULL;
-}
-
-/* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . */
-
-static void fpga_status (fpga_t* fpga)
-{
-    /* Check state */
-    if (fpga_control(fpga, FPGA_DONE_IS_HIGH))
-	printf ("%s is loaded (%08lx)\n",
-		fpga->name, fpga_control(fpga, FPGA_GET_ID));
-    else
-	printf ("%s is NOT loaded\n", fpga->name);
-}
-
-/* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . */
-
-#define FPGA_RESET_TIMEOUT 100 /* = 10 ms */
-
-static int fpga_reset (fpga_t* fpga)
-{
-    int i;
-
-    /* Set PROG to low and wait til INIT goes low */
-    fpga_control(fpga, FPGA_PROG_SET_LOW);
-    for (i = 0; i < FPGA_RESET_TIMEOUT; i++) {
-	udelay (100);
-	if (!fpga_control(fpga, FPGA_INIT_IS_HIGH))
-	    break;
-    }
-    if (i == FPGA_RESET_TIMEOUT)
-	goto failure;
-
-    /* Set PROG to high and wait til INIT goes high */
-    fpga_control(fpga, FPGA_PROG_SET_HIGH);
-    for (i = 0; i < FPGA_RESET_TIMEOUT; i++) {
-	udelay (100);
-	if (fpga_control(fpga, FPGA_INIT_IS_HIGH))
-	    break;
-    }
-    if (i == FPGA_RESET_TIMEOUT)
-	goto failure;
-
-    return 0;
- failure:
-    return 1;
-}
-
-/* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . */
-
-#define FPGA_LOAD_TIMEOUT 100 /* = 10 ms */
-
-static int fpga_load (fpga_t* fpga, ulong addr, int checkall)
-{
-    volatile uchar *fpga_addr = (volatile uchar *)fpga->conf_base;
-    image_header_t *hdr = (image_header_t *)addr;
-    ulong len;
-    uchar *data;
-    char msg[32];
-    int verify, i;
-
-#if defined(CONFIG_FIT)
-    if (genimg_get_format ((void *)hdr) != IMAGE_FORMAT_LEGACY) {
-	puts ("Non legacy image format not supported\n");
-	return -1;
-    }
-#endif
-
-    /*
-     * Check the image header and data of the net-list
-     */
-    if (!image_check_magic (hdr)) {
-	strcpy (msg, "Bad Image Magic Number");
-	goto failure;
-    }
-
-    if (!image_check_hcrc (hdr)) {
-	strcpy (msg, "Bad Image Header CRC");
-	goto failure;
-    }
-
-    data = (uchar*)image_get_data (hdr);
-    len  = image_get_data_size (hdr);
-
-    verify = getenv_yesno ("verify");
-    if (verify) {
-	if (!image_check_dcrc (hdr)) {
-	    strcpy (msg, "Bad Image Data CRC");
-	    goto failure;
-	}
-    }
-
-    if (checkall && fpga_get_version(fpga, image_get_name (hdr)) < 0)
-	return 1;
-
-    /* align length */
-    if (len & 1)
-	++len;
-
-    /*
-     * Reset FPGA and wait for completion
-     */
-    if (fpga_reset(fpga)) {
-	strcpy (msg, "Reset Timeout");
-	goto failure;
-    }
-
-    printf ("(%s)... ", image_get_name (hdr));
-    /*
-     * Copy data to FPGA
-     */
-    fpga_control (fpga, FPGA_LOAD_MODE);
-    while (len--) {
-	*fpga_addr = *data++;
-    }
-    fpga_control (fpga, FPGA_READ_MODE);
-
-    /*
-     * Wait for completion and check error status if timeout
-     */
-    for (i = 0; i < FPGA_LOAD_TIMEOUT; i++) {
-	udelay (100);
-	if (fpga_control (fpga, FPGA_DONE_IS_HIGH))
-	    break;
-    }
-    if (i == FPGA_LOAD_TIMEOUT) {
-	if (fpga_control(fpga, FPGA_INIT_IS_HIGH))
-	    strcpy(msg, "Invalid Size");
-	else
-	    strcpy(msg, "CRC Error");
-	goto failure;
-    }
-
-    printf("done\n");
-    return 0;
-
- failure:
-
-    printf("ERROR: %s\n", msg);
-    return 1;
-}
-
-#if defined(CONFIG_CMD_BSP)
-
-/* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . */
-
-int do_fpga (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
-    ulong addr = 0;
-    int i;
-    fpga_t* fpga;
-
-    if (argc < 2)
-	goto failure;
-
-    if (strncmp(argv[1], "stat", 4) == 0) {		/* status */
-	if (argc == 2) {
-	    for (i = 0; i < fpga_count; i++) {
-		fpga_status (&fpga_list[i]);
-	    }
-	}
-	else if (argc == 3) {
-	    if ((fpga = fpga_get(argv[2])) == 0)
-		goto failure;
-	    fpga_status (fpga);
-	}
-	else
-	    goto failure;
-    }
-    else if (strcmp(argv[1],"load") == 0) {		/* load */
-	if (argc == 3 && fpga_count == 1) {
-	    fpga = &fpga_list[0];
-	}
-	else if (argc == 4) {
-	    if ((fpga = fpga_get(argv[2])) == 0)
-		goto failure;
-	}
-	else
-	    goto failure;
-
-	addr = simple_strtoul(argv[argc-1], NULL, 16);
-
-	printf ("FPGA load %s: addr %08lx: ",
-		fpga->name, addr);
-	fpga_load (fpga, addr, 1);
-
-    }
-    else if (strncmp(argv[1], "rese", 4) == 0) {	/* reset */
-	if (argc == 2 && fpga_count == 1) {
-	    fpga = &fpga_list[0];
-	}
-	else if (argc == 3) {
-	    if ((fpga = fpga_get(argv[2])) == 0)
-		goto failure;
-	}
-	else
-	    goto failure;
-
-	printf ("FPGA reset %s: ", fpga->name);
-	if (fpga_reset(fpga))
-	    printf ("ERROR: Timeout\n");
-	else
-	    printf ("done\n");
-    }
-    else
-	goto failure;
-
-    return 0;
-
- failure:
-    return cmd_usage(cmdtp);
-}
-
-U_BOOT_CMD(
-	fpga,	4,	1,	do_fpga,
-	"access FPGA(s)",
-	"fpga status [name] - print FPGA status\n"
-	"fpga reset  [name] - reset FPGA\n"
-	"fpga load [name] addr - load FPGA configuration data"
-);
-
-#endif
-
-/* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . */
-
-int fpga_init (void)
-{
-    ulong addr;
-    ulong new_id, old_id = 0;
-    image_header_t *hdr;
-    fpga_t* fpga;
-    int do_load, i, j;
-    char name[16], *s;
-
-    /*
-     *  Port setup for FPGA control
-     */
-    for (i = 0; i < fpga_count; i++) {
-	fpga_control(&fpga_list[i], FPGA_INIT_PORTS);
-    }
-
-    /*
-     * Load FPGA(s): a new net-list is loaded if the FPGA is
-     * empty, Power-on-Reset or the old one is not up-to-date
-     */
-    for (i = 0; i < fpga_count; i++) {
-	fpga = &fpga_list[i];
-	printf ("%s:  ", fpga->name);
-
-	for (j = 0; j < strlen(fpga->name); j++)
-	    name[j] = tolower(fpga->name[j]);
-	name[j] = '\0';
-	sprintf(name, "%s_addr", name);
-	addr = 0;
-	if ((s = getenv(name)) != NULL)
-	    addr = simple_strtoul(s, NULL, 16);
-
-	if (!addr) {
-	    printf ("env. variable %s undefined\n", name);
-	    return 1;
-	}
-
-	hdr = (image_header_t *)addr;
-#if defined(CONFIG_FIT)
-	if (genimg_get_format ((void *)hdr) != IMAGE_FORMAT_LEGACY) {
-	   puts ("Non legacy image format not supported\n");
-	   return -1;
-	}
-#endif
-
-	if ((new_id = fpga_get_version(fpga, image_get_name (hdr))) == -1)
-	    return 1;
-
-	do_load = 1;
-
-	if (!power_on_reset() && fpga_control(fpga, FPGA_DONE_IS_HIGH)) {
-	    old_id = fpga_control(fpga, FPGA_GET_ID);
-	    if (new_id == old_id)
-		do_load = 0;
-	}
-
-	if (do_load) {
-	    printf ("loading ");
-	    fpga_load (fpga, addr, 0);
-	} else {
-	    printf ("loaded (%08lx)\n", old_id);
-	}
-    }
-
-    return 0;
-}
diff --git a/board/siemens/common/fpga.h b/board/siemens/common/fpga.h
deleted file mode 100644
index 2de25b0..0000000
--- a/board/siemens/common/fpga.h
+++ /dev/null
@@ -1,53 +0,0 @@ 
-/*
- * (C) Copyright 2002
- * Wolfgang Grandegger, DENX Software Engineering, wg@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-
-#ifndef _FPGA_H_
-#define _FPGA_H_
-
-#define FPGA_INIT_IS_HIGH   0
-#define FPGA_INIT_SET_HIGH  1
-#define FPGA_INIT_SET_LOW   2
-#define FPGA_PROG_SET_HIGH  3
-#define FPGA_PROG_SET_LOW   4
-#define FPGA_DONE_IS_HIGH   5
-#define	FPGA_READ_MODE      6
-#define FPGA_LOAD_MODE      7
-#define FPGA_GET_ID         8
-#define FPGA_INIT_PORTS     9
-
-#define FPGA_NAME_LEN       8
-typedef struct {
-    char  name[FPGA_NAME_LEN];
-    ulong conf_base;
-    uint  init_mask;
-    uint  prog_mask;
-    uint  done_mask;
-} fpga_t;
-
-extern fpga_t fpga_list[];
-extern int    fpga_count;
-
-ulong fpga_control (fpga_t* fpga, int cmd);
-
-#endif /* _FPGA_H_ */
diff --git a/board/westel/amx860/Makefile b/board/westel/amx860/Makefile
deleted file mode 100644
index 12e4aa6..0000000
--- a/board/westel/amx860/Makefile
+++ /dev/null
@@ -1,44 +0,0 @@ 
-#
-# (C) Copyright 2001-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	= $(BOARD).o flash.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
diff --git a/board/westel/amx860/amx860.c b/board/westel/amx860/amx860.c
deleted file mode 100644
index 91dcc0d..0000000
--- a/board/westel/amx860/amx860.c
+++ /dev/null
@@ -1,93 +0,0 @@ 
-/*
- * (C) Copyright 2001
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <config.h>
-#include <mpc8xx.h>
-
-/* ------------------------------------------------------------------------- */
-
-#define	_NOT_USED_	0xFFFFFFFF
-
-const uint edo_60ns[] =
-{ 0x8ffbec24, 0x0ff3ec04, 0x0cf3ec04, 0x00f3ec04,
-  0x00f3ec00, 0x37f7ec47, _NOT_USED_, _NOT_USED_,
-  0x8fffec24, 0x0ffbec04, 0x08f3ec04, 0x07f3ec08,
-  0x08f3ec04, 0x07f3ec48, 0x08f3ec04, 0x07f3ec48,
-  0x08f3ec04, 0x07f3ec48, 0x1ff7ec47, _NOT_USED_,
-  _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
-  0x8fffcc24, 0x0fefcc04, 0x0cafcc00, 0x11bfcc47,
-  _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
-  0x8fffcc24, 0x0fefcc04, 0x0cafcc00, 0x03afcc4c,
-  0x0cafcc00, 0x03afcc4c, 0x0cafcc00, 0x03afcc4c,
-  0x0cafcc00, 0x33bfcc4f, _NOT_USED_, _NOT_USED_,
-  _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
-  0xc0ffcc84, 0x00ffcc04, 0x07ffcc04, 0x3fffcc06,
-  0xffffcc85, 0xffffcc05, _NOT_USED_, _NOT_USED_,
-  _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
-  0x33ffcc07, _NOT_USED_, _NOT_USED_, _NOT_USED_ };
-
-/* ------------------------------------------------------------------------- */
-
-/*
- * Check Board Identity:
- */
-
-int checkboard (void)
-{
-	puts ("Board: AMX860\n");
-	return 0;
-}
-
-/* ------------------------------------------------------------------------- */
-
-phys_size_t initdram (int board_type)
-{
-
-	volatile immap_t     *immap = (immap_t *)CONFIG_SYS_IMMR;
-	volatile memctl8xx_t *memctl = &immap->im_memctl;
-
-	/* AMX860: has 4 Mb of 60ns EDO DRAM, so start DRAM at 0 */
-
-	upmconfig(UPMA, (uint *) edo_60ns, sizeof(edo_60ns)/sizeof(uint));
-
-#ifndef CONFIG_AMX_RAM_EXT
-	memctl->memc_mptpr = 0x0400; /* divide by 16 */
-#else
-	memctl->memc_mptpr = 0x0200;
-#endif
-
-	memctl->memc_mamr = 0x30a21114;
-	memctl->memc_or2 = 0xffc00800;
-#ifndef CONFIG_AMX_RAM_EXT
-	memctl->memc_br2 = 0x81;
-
-	return (4 << 20);
-#else
-	memctl->memc_or1 = 0xff000800;
-	memctl->memc_br1 = 0x00000081;
-	memctl->memc_br2 = 0x01000081;
-
-	return (20 << 20);
-#endif
-}
diff --git a/board/westel/amx860/flash.c b/board/westel/amx860/flash.c
deleted file mode 100644
index fe8bce4..0000000
--- a/board/westel/amx860/flash.c
+++ /dev/null
@@ -1,637 +0,0 @@ 
-/*
- * (C) Copyright 2001
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <mpc8xx.h>
-
-flash_info_t	flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
-
-#if defined(CONFIG_ENV_IS_IN_FLASH)
-# ifndef  CONFIG_ENV_ADDR
-#  define CONFIG_ENV_ADDR	(CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
-# endif
-# ifndef  CONFIG_ENV_SIZE
-#  define CONFIG_ENV_SIZE	CONFIG_ENV_SECT_SIZE
-# endif
-# ifndef  CONFIG_ENV_SECT_SIZE
-#  define CONFIG_ENV_SECT_SIZE  CONFIG_ENV_SIZE
-# endif
-#endif
-
-/*---------------------------------------------------------------------*/
-#undef DEBUG_FLASH
-
-#ifdef DEBUG_FLASH
-#define DEBUGF(fmt,args...) printf(fmt ,##args)
-#else
-#define DEBUGF(fmt,args...)
-#endif
-/*---------------------------------------------------------------------*/
-
-/*-----------------------------------------------------------------------
- * Functions
- */
-static ulong flash_get_size (vu_long *addr, flash_info_t *info);
-static int write_word (flash_info_t *info, ulong dest, ulong data);
-static void flash_get_offsets (ulong base, flash_info_t *info);
-
-/*-----------------------------------------------------------------------
- */
-
-unsigned long flash_init (void)
-{
-	volatile immap_t     *immap  = (immap_t *)CONFIG_SYS_IMMR;
-	volatile memctl8xx_t *memctl = &immap->im_memctl;
-	unsigned long size_b0, size_b1;
-	int i;
-
-	/* Init: no FLASHes known */
-	for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
-		flash_info[i].flash_id = FLASH_UNKNOWN;
-	}
-
-	/* Static FLASH Bank configuration here - FIXME XXX */
-
-	DEBUGF("\n## Get flash bank 1 size @ 0x%08x\n",FLASH_BASE0_PRELIM);
-
-	size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
-
-	if (flash_info[0].flash_id == FLASH_UNKNOWN) {
-		printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
-			size_b0, size_b0<<20);
-	}
-
-#if defined(FLASH_BASE1_PRELIM) && (FLASH_BASE1_PRELIM != 0)
-	DEBUGF("## Get flash bank 2 size @ 0x%08x\n",FLASH_BASE1_PRELIM);
-
-	size_b1 = flash_get_size((vu_long *)FLASH_BASE1_PRELIM, &flash_info[1]);
-
-	if (size_b1 > size_b0) {
-		printf ("## ERROR: "
-			"Bank 1 (0x%08lx = %ld MB) > Bank 0 (0x%08lx = %ld MB)\n",
-			size_b1, size_b1<<20,
-			size_b0, size_b0<<20
-		);
-		flash_info[0].flash_id	= FLASH_UNKNOWN;
-		flash_info[1].flash_id	= FLASH_UNKNOWN;
-		flash_info[0].sector_count	= -1;
-		flash_info[1].sector_count	= -1;
-		flash_info[0].size		= 0;
-		flash_info[1].size		= 0;
-		return (0);
-	}
-#else
-	size_b1 = 0;
-#endif	/* FLASH_BASE1_PRELIM */
-
-	DEBUGF("## Prelim. Flash bank sizes: %08lx + 0x%08lx\n",size_b0,size_b1);
-
-	DEBUGF ("## Before remap: "
-		"BR0: 0x%08x    OR0: 0x%08x    "
-		"BR1: 0x%08x    OR1: 0x%08x\n",
-		memctl->memc_br0, memctl->memc_or0,
-		memctl->memc_br1, memctl->memc_or1);
-
-	/* Remap FLASH according to real size */
-	memctl->memc_or0 = CONFIG_SYS_OR_TIMING_FLASH | (-size_b0 & OR_AM_MSK);
-	memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_V;
-
-	DEBUGF("## BR0: 0x%08x    OR0: 0x%08x\n",
-		memctl->memc_br0, memctl->memc_or0);
-
-	/* Re-do sizing to get full correct info */
-	size_b0 = flash_get_size((vu_long *)CONFIG_SYS_FLASH_BASE, &flash_info[0]);
-
-	flash_get_offsets (CONFIG_SYS_FLASH_BASE, &flash_info[0]);
-
-	flash_info[0].size = size_b0;
-
-#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
-	/* monitor protection ON by default */
-	flash_protect(FLAG_PROTECT_SET,
-		      CONFIG_SYS_MONITOR_BASE,
-		      CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1,
-		      &flash_info[0]);
-#endif
-
-#ifdef	CONFIG_ENV_IS_IN_FLASH
-	/* ENV protection ON by default */
-	flash_protect(FLAG_PROTECT_SET,
-		      CONFIG_ENV_ADDR,
-		      CONFIG_ENV_ADDR+CONFIG_ENV_SECT_SIZE-1,
-		      &flash_info[0]);
-#endif
-
-	if (size_b1) {
-		memctl->memc_or1 = CONFIG_SYS_OR_TIMING_FLASH | (-size_b1 & OR_AM_MSK);
-		memctl->memc_br1 = ((CONFIG_SYS_FLASH_BASE + size_b0) & BR_BA_MSK) |
-				   BR_MS_GPCM | BR_V;
-
-		DEBUGF("## BR1: 0x%08x    OR1: 0x%08x\n",
-			memctl->memc_br1, memctl->memc_or1);
-
-		/* Re-do sizing to get full correct info */
-		size_b1 = flash_get_size((vu_long *)(CONFIG_SYS_FLASH_BASE + size_b0),
-					  &flash_info[1]);
-
-		flash_info[1].size = size_b1;
-
-		flash_get_offsets (CONFIG_SYS_FLASH_BASE + size_b0, &flash_info[1]);
-
-# if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
-		/* monitor protection ON by default */
-		flash_protect(FLAG_PROTECT_SET,
-			      CONFIG_SYS_MONITOR_BASE,
-			      CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1,
-			      &flash_info[1]);
-# endif
-
-# ifdef CONFIG_ENV_IS_IN_FLASH
-		/* ENV protection ON by default */
-		flash_protect(FLAG_PROTECT_SET,
-			      CONFIG_ENV_ADDR,
-			      CONFIG_ENV_ADDR+CONFIG_ENV_SECT_SIZE-1,
-			      &flash_info[1]);
-#endif
-	} else {
-#ifndef CONFIG_AMX_RAM_EXT
-		memctl->memc_br1 = 0;		/* invalidate bank */
-		memctl->memc_or1 = 0;		/* invalidate bank */
-#endif
-
-		DEBUGF("## DISABLE BR1: 0x%08x    OR1: 0x%08x\n",
-			memctl->memc_br1, memctl->memc_or1);
-
-		flash_info[1].flash_id = FLASH_UNKNOWN;
-		flash_info[1].sector_count = -1;
-		flash_info[1].size = 0;
-	}
-
-	DEBUGF("## Final Flash bank sizes: %08lx + 0x%08lx\n",size_b0,size_b1);
-
-	return (size_b0 + size_b1);
-}
-
-/*-----------------------------------------------------------------------
- */
-static void flash_get_offsets (ulong base, flash_info_t *info)
-{
-	int i;
-
-	/* set up sector start address table */
-	if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040) {
-		/* set sector offsets for uniform sector type	*/
-		for (i = 0; i < info->sector_count; i++) {
-			info->start[i] = base + (i * 0x00040000);
-		}
-	} else if (info->flash_id & FLASH_BTYPE) {
-		/* set sector offsets for bottom boot block type	*/
-		info->start[0] = base + 0x00000000;
-		info->start[1] = base + 0x00008000;
-		info->start[2] = base + 0x0000C000;
-		info->start[3] = base + 0x00010000;
-		for (i = 4; i < info->sector_count; i++) {
-			info->start[i] = base + (i * 0x00020000) - 0x00060000;
-		}
-	} else {
-		/* set sector offsets for top boot block type		*/
-		i = info->sector_count - 1;
-		info->start[i--] = base + info->size - 0x00008000;
-		info->start[i--] = base + info->size - 0x0000C000;
-		info->start[i--] = base + info->size - 0x00010000;
-		for (; i >= 0; i--) {
-			info->start[i] = base + i * 0x00020000;
-		}
-	}
-}
-
-/*-----------------------------------------------------------------------
- */
-void flash_print_info  (flash_info_t *info)
-{
-	int i;
-
-	if (info->flash_id == FLASH_UNKNOWN) {
-		printf ("missing or unknown FLASH type\n");
-		return;
-	}
-
-	switch (info->flash_id & FLASH_VENDMASK) {
-	case FLASH_MAN_AMD:	printf ("AMD ");		break;
-	case FLASH_MAN_FUJ:	printf ("FUJITSU ");		break;
-	case FLASH_MAN_BM:	printf ("BRIGHT MICRO ");	break;
-	default:		printf ("Unknown Vendor ");	break;
-	}
-
-	switch (info->flash_id & FLASH_TYPEMASK) {
-	case FLASH_AM040:	printf ("29F040 or 29LV040 (4 Mbit, uniform sectors)\n");
-				break;
-	case FLASH_AM400B:	printf ("AM29LV400B (4 Mbit, bottom boot sect)\n");
-				break;
-	case FLASH_AM400T:	printf ("AM29LV400T (4 Mbit, top boot sector)\n");
-				break;
-	case FLASH_AM800B:	printf ("AM29LV800B (8 Mbit, bottom boot sect)\n");
-				break;
-	case FLASH_AM800T:	printf ("AM29LV800T (8 Mbit, top boot sector)\n");
-				break;
-	case FLASH_AM160B:	printf ("AM29LV160B (16 Mbit, bottom boot sect)\n");
-				break;
-	case FLASH_AM160T:	printf ("AM29LV160T (16 Mbit, top boot sector)\n");
-				break;
-	case FLASH_AM320B:	printf ("AM29LV320B (32 Mbit, bottom boot sect)\n");
-				break;
-	case FLASH_AM320T:	printf ("AM29LV320T (32 Mbit, top boot sector)\n");
-				break;
-	default:		printf ("Unknown Chip Type\n");
-				break;
-	}
-
-	printf ("  Size: %ld MB in %d Sectors\n",
-		info->size >> 20, info->sector_count);
-
-	printf ("  Sector Start Addresses:");
-	for (i=0; i<info->sector_count; ++i) {
-		if ((i % 5) == 0)
-			printf ("\n   ");
-		printf (" %08lX%s",
-			info->start[i],
-			info->protect[i] ? " (RO)" : "     "
-		);
-	}
-	printf ("\n");
-}
-
-/*-----------------------------------------------------------------------
- */
-
-
-/*-----------------------------------------------------------------------
- */
-
-/*
- * The following code cannot be run from FLASH!
- */
-
-static ulong flash_get_size (vu_long *addr, flash_info_t *info)
-{
-	short i;
-	ulong value;
-	ulong base = (ulong)addr;
-
-	/* Write auto select command: read Manufacturer ID */
-	addr[0x0555] = 0x00AA00AA;
-	addr[0x02AA] = 0x00550055;
-	addr[0x0555] = 0x00900090;
-
-	value = addr[0];
-
-	DEBUGF("Manuf. ID @ 0x%08lx: 0x%08lx\n", (ulong)addr, value);
-
-	switch (value) {
-	case AMD_MANUFACT:
-		info->flash_id = FLASH_MAN_AMD;
-		break;
-	case FUJ_MANUFACT:
-		info->flash_id = FLASH_MAN_FUJ;
-		break;
-	default:
-		info->flash_id = FLASH_UNKNOWN;
-		info->sector_count = 0;
-		info->size = 0;
-		return (0);			/* no or unknown flash	*/
-	}
-
-	value = addr[1];			/* device ID		*/
-
-	DEBUGF("Device ID @ 0x%08lx: 0x%08lx\n", (ulong)(&addr[1]), value);
-
-	switch (value) {
-	case AMD_ID_F040B:
-		info->flash_id += FLASH_AM040;
-		info->sector_count = 8;
-		info->size = 0x00200000;
-		break;				/* => 2 MB		*/
-
-	case AMD_ID_LV400T:
-		info->flash_id += FLASH_AM400T;
-		info->sector_count = 11;
-		info->size = 0x00100000;
-		break;				/* => 1 MB		*/
-
-	case AMD_ID_LV400B:
-		info->flash_id += FLASH_AM400B;
-		info->sector_count = 11;
-		info->size = 0x00100000;
-		break;				/* => 1 MB		*/
-
-	case AMD_ID_LV800T:
-		info->flash_id += FLASH_AM800T;
-		info->sector_count = 19;
-		info->size = 0x00200000;
-		break;				/* => 2 MB		*/
-
-	case AMD_ID_LV800B:
-		info->flash_id += FLASH_AM800B;
-		info->sector_count = 19;
-		info->size = 0x00200000;
-		break;				/* => 2 MB		*/
-
-	case AMD_ID_LV160T:
-		info->flash_id += FLASH_AM160T;
-		info->sector_count = 35;
-		info->size = 0x00400000;
-		break;				/* => 4 MB		*/
-
-	case AMD_ID_LV160B:
-		info->flash_id += FLASH_AM160B;
-		info->sector_count = 35;
-		info->size = 0x00400000;
-		break;				/* => 4 MB		*/
-#if 0	/* enable when device IDs are available */
-	case AMD_ID_LV320T:
-		info->flash_id += FLASH_AM320T;
-		info->sector_count = 67;
-		info->size = 0x00800000;
-		break;				/* => 8 MB		*/
-
-	case AMD_ID_LV320B:
-		info->flash_id += FLASH_AM320B;
-		info->sector_count = 67;
-		info->size = 0x00800000;
-		break;				/* => 8 MB		*/
-#endif
-	default:
-		info->flash_id = FLASH_UNKNOWN;
-		return (0);			/* => no or unknown flash */
-	}
-
-	/* set up sector start address table */
-	if (info->flash_id & FLASH_BTYPE) {
-		/* set sector offsets for bottom boot block type	*/
-		info->start[0] = base + 0x00000000;
-		info->start[1] = base + 0x00008000;
-		info->start[2] = base + 0x0000C000;
-		info->start[3] = base + 0x00010000;
-		for (i = 4; i < info->sector_count; i++) {
-			info->start[i] = base + (i * 0x00020000) - 0x00060000;
-		}
-	} else {
-		/* set sector offsets for top boot block type		*/
-		i = info->sector_count - 1;
-		info->start[i--] = base + info->size - 0x00008000;
-		info->start[i--] = base + info->size - 0x0000C000;
-		info->start[i--] = base + info->size - 0x00010000;
-		for (; i >= 0; i--) {
-			info->start[i] = base + i * 0x00020000;
-		}
-	}
-
-	/* check for protected sectors */
-	for (i = 0; i < info->sector_count; i++) {
-		/* read sector protection at sector address, (A7 .. A0) = 0x02 */
-		/* D0 = 1 if protected */
-		addr = (volatile unsigned long *)(info->start[i]);
-		info->protect[i] = addr[2] & 1;
-	}
-
-	/*
-	 * Prevent writes to uninitialized FLASH.
-	 */
-	if (info->flash_id != FLASH_UNKNOWN) {
-		addr = (volatile unsigned long *)info->start[0];
-
-		*addr = 0x00F000F0;	/* reset bank */
-	}
-
-	return (info->size);
-}
-
-
-/*-----------------------------------------------------------------------
- */
-
-int	flash_erase (flash_info_t *info, int s_first, int s_last)
-{
-	vu_long *addr = (vu_long*)(info->start[0]);
-	int flag, prot, sect, l_sect;
-	ulong start, now, last;
-
-	if ((s_first < 0) || (s_first > s_last)) {
-		if (info->flash_id == FLASH_UNKNOWN) {
-			printf ("- missing\n");
-		} else {
-			printf ("- no sectors to erase\n");
-		}
-		return 1;
-	}
-
-	if ((info->flash_id == FLASH_UNKNOWN) ||
-	    (info->flash_id > FLASH_AMD_COMP)) {
-		printf ("Can't erase unknown flash type %08lx - aborted\n",
-			info->flash_id);
-		return 1;
-	}
-
-	prot = 0;
-	for (sect=s_first; sect<=s_last; ++sect) {
-		if (info->protect[sect]) {
-			prot++;
-		}
-	}
-
-	if (prot) {
-		printf ("- Warning: %d protected sectors will not be erased!\n",
-			prot);
-	} else {
-		printf ("\n");
-	}
-
-	l_sect = -1;
-
-	/* Disable interrupts which might cause a timeout here */
-	flag = disable_interrupts();
-
-	addr[0x0555] = 0x00AA00AA;
-	addr[0x02AA] = 0x00550055;
-	addr[0x0555] = 0x00800080;
-	addr[0x0555] = 0x00AA00AA;
-	addr[0x02AA] = 0x00550055;
-
-	/* Start erase on unprotected sectors */
-	for (sect = s_first; sect<=s_last; sect++) {
-		if (info->protect[sect] == 0) {	/* not protected */
-			addr = (vu_long*)(info->start[sect]);
-			addr[0] = 0x00300030;
-			l_sect = sect;
-		}
-	}
-
-	/* re-enable interrupts if necessary */
-	if (flag)
-		enable_interrupts();
-
-	/* wait at least 80us - let's wait 1 ms */
-	udelay (1000);
-
-	/*
-	 * We wait for the last triggered sector
-	 */
-	if (l_sect < 0)
-		goto DONE;
-
-	start = get_timer (0);
-	last  = start;
-	addr = (vu_long*)(info->start[l_sect]);
-	while ((addr[0] & 0x00800080) != 0x00800080) {
-		if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
-			printf ("Timeout\n");
-			return 1;
-		}
-		/* show that we're waiting */
-		if ((now - last) > 1000) {	/* every second */
-			putc ('.');
-			last = now;
-		}
-	}
-
-DONE:
-	/* reset to read mode */
-	addr = (volatile unsigned long *)info->start[0];
-	addr[0] = 0x00F000F0;	/* reset bank */
-
-	printf (" done\n");
-	return 0;
-}
-
-/*-----------------------------------------------------------------------
- * Copy memory to flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-
-int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
-{
-	ulong cp, wp, data;
-	int i, l, rc;
-
-	wp = (addr & ~3);	/* get lower word aligned address */
-
-	/*
-	 * handle unaligned start bytes
-	 */
-	if ((l = addr - wp) != 0) {
-		data = 0;
-		for (i=0, cp=wp; i<l; ++i, ++cp) {
-			data = (data << 8) | (*(uchar *)cp);
-		}
-		for (; i<4 && cnt>0; ++i) {
-			data = (data << 8) | *src++;
-			--cnt;
-			++cp;
-		}
-		for (; cnt==0 && i<4; ++i, ++cp) {
-			data = (data << 8) | (*(uchar *)cp);
-		}
-
-		if ((rc = write_word(info, wp, data)) != 0) {
-			return (rc);
-		}
-		wp += 4;
-	}
-
-	/*
-	 * handle word aligned part
-	 */
-	while (cnt >= 4) {
-		data = 0;
-		for (i=0; i<4; ++i) {
-			data = (data << 8) | *src++;
-		}
-		if ((rc = write_word(info, wp, data)) != 0) {
-			return (rc);
-		}
-		wp  += 4;
-		cnt -= 4;
-	}
-
-	if (cnt == 0) {
-		return (0);
-	}
-
-	/*
-	 * handle unaligned tail bytes
-	 */
-	data = 0;
-	for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
-		data = (data << 8) | *src++;
-		--cnt;
-	}
-	for (; i<4; ++i, ++cp) {
-		data = (data << 8) | (*(uchar *)cp);
-	}
-
-	return (write_word(info, wp, data));
-}
-
-/*-----------------------------------------------------------------------
- * Write a word to Flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-static int write_word (flash_info_t *info, ulong dest, ulong data)
-{
-	vu_long *addr = (vu_long*)(info->start[0]);
-	ulong start;
-	int flag;
-
-	/* Check if Flash is (sufficiently) erased */
-	if ((*((vu_long *)dest) & data) != data) {
-		return (2);
-	}
-	/* Disable interrupts which might cause a timeout here */
-	flag = disable_interrupts();
-
-	addr[0x0555] = 0x00AA00AA;
-	addr[0x02AA] = 0x00550055;
-	addr[0x0555] = 0x00A000A0;
-
-	*((vu_long *)dest) = data;
-
-	/* re-enable interrupts if necessary */
-	if (flag)
-		enable_interrupts();
-
-	/* data polling for D7 */
-	start = get_timer (0);
-	while ((*((vu_long *)dest) & 0x00800080) != (data & 0x00800080)) {
-		if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
-			return (1);
-		}
-	}
-	return (0);
-}
-
-/*-----------------------------------------------------------------------
- */
diff --git a/board/westel/amx860/u-boot.lds b/board/westel/amx860/u-boot.lds
deleted file mode 100644
index 9b69d3d..0000000
--- a/board/westel/amx860/u-boot.lds
+++ /dev/null
@@ -1,107 +0,0 @@ 
-/*
- * (C) Copyright 2001
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_ARCH(powerpc)
-
-SECTIONS
-{
-  /* Read-only sections, merged into text segment: */
-  . = + SIZEOF_HEADERS;
-  .text      :
-  {
-    /* WARNING - the following is hand-optimized to fit within	*/
-    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
-
-    arch/powerpc/cpu/mpc8xx/start.o	(.text*)
-    arch/powerpc/cpu/mpc8xx/traps.o	(.text*)
-    net/libnet.o			(.text*)
-    board/westel/amx860/libamx860.o	(.text*)
-    *(.text.*printf)
-
-    . = env_offset;
-    common/env_embedded.o		(.text*)
-
-    *(.text*)
-  }
-  _etext = .;
-  PROVIDE (etext = .);
-  .rodata    :
-  {
-    *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
-  }
-
-  /* Read-write section, merged into data segment: */
-  . = (. + 0x00FF) & 0xFFFFFF00;
-  _erotext = .;
-  PROVIDE (erotext = .);
-  .reloc   :
-  {
-    _GOT2_TABLE_ = .;
-    KEEP(*(.got2))
-    KEEP(*(.got))
-    PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4);
-    _FIXUP_TABLE_ = .;
-    KEEP(*(.fixup))
-  }
-  __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1;
-  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
-  .data    :
-  {
-    *(.data*)
-    *(.sdata*)
-  }
-  _edata  =  .;
-  PROVIDE (edata = .);
-
-  . = .;
-
-  . = ALIGN(4);
-  .u_boot_list : {
-	#include <u-boot.lst>
-  }
-
-
-  . = .;
-  __start___ex_table = .;
-  __ex_table : { *(__ex_table) }
-  __stop___ex_table = .;
-
-  . = ALIGN(256);
-  __init_begin = .;
-  .text.init : { *(.text.init) }
-  .data.init : { *(.data.init) }
-  . = ALIGN(256);
-  __init_end = .;
-
-  __bss_start = .;
-  .bss (NOLOAD)       :
-  {
-   *(.bss*)
-   *(.sbss*)
-   *(COMMON)
-   . = ALIGN(4);
-  }
-  __bss_end__ = . ;
-  PROVIDE (end = .);
-}
diff --git a/board/westel/amx860/u-boot.lds.debug b/board/westel/amx860/u-boot.lds.debug
deleted file mode 100644
index 3e075a8..0000000
--- a/board/westel/amx860/u-boot.lds.debug
+++ /dev/null
@@ -1,138 +0,0 @@ 
-/*
- * (C) Copyright 2001
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_ARCH(powerpc)
-/* Do we need any of these for elf?
-   __DYNAMIC = 0;    */
-SECTIONS
-{
-  /* Read-only sections, merged into text segment: */
-  . = + SIZEOF_HEADERS;
-  .interp : { *(.interp) }
-  .hash          : { *(.hash)		}
-  .dynsym        : { *(.dynsym)		}
-  .dynstr        : { *(.dynstr)		}
-  .rel.text      : { *(.rel.text)		}
-  .rela.text     : { *(.rela.text)	}
-  .rel.data      : { *(.rel.data)		}
-  .rela.data     : { *(.rela.data)	}
-  .rel.rodata    : { *(.rel.rodata)	}
-  .rela.rodata   : { *(.rela.rodata)	}
-  .rel.got       : { *(.rel.got)		}
-  .rela.got      : { *(.rela.got)		}
-  .rel.ctors     : { *(.rel.ctors)	}
-  .rela.ctors    : { *(.rela.ctors)	}
-  .rel.dtors     : { *(.rel.dtors)	}
-  .rela.dtors    : { *(.rela.dtors)	}
-  .rel.bss       : { *(.rel.bss)		}
-  .rela.bss      : { *(.rela.bss)		}
-  .rel.plt       : { *(.rel.plt)		}
-  .rela.plt      : { *(.rela.plt)		}
-  .init          : { *(.init)	}
-  .plt : { *(.plt) }
-  .text      :
-  {
-    /* WARNING - the following is hand-optimized to fit within	*/
-    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
-
-    arch/powerpc/cpu/mpc8xx/start.o	(.text)
-    common/dlmalloc.o	(.text)
-    lib/vsprintf.o	(.text)
-    lib/crc32.o		(.text)
-    arch/powerpc/lib/extable.o	(.text)
-
-    . = env_offset;
-    common/env_embedded.o(.text)
-
-    *(.text)
-    *(.got1)
-  }
-  _etext = .;
-  PROVIDE (etext = .);
-  .rodata    :
-  {
-    *(.rodata)
-    *(.rodata1)
-    *(.rodata.str1.4)
-    *(.eh_frame)
-  }
-  .fini      : { *(.fini)    } =0
-  .ctors     : { *(.ctors)   }
-  .dtors     : { *(.dtors)   }
-
-  /* Read-write section, merged into data segment: */
-  . = (. + 0x0FFF) & 0xFFFFF000;
-  _erotext = .;
-  PROVIDE (erotext = .);
-  .reloc   :
-  {
-    *(.got)
-    _GOT2_TABLE_ = .;
-    *(.got2)
-    _FIXUP_TABLE_ = .;
-    *(.fixup)
-  }
-  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
-  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
-  .data    :
-  {
-    *(.data)
-    *(.data1)
-    *(.sdata)
-    *(.sdata2)
-    *(.dynamic)
-    CONSTRUCTORS
-  }
-  _edata  =  .;
-  PROVIDE (edata = .);
-
-
-  . = ALIGN(4);
-  .u_boot_list : {
-	#include <u-boot.lst>
-  }
-
-
-  __start___ex_table = .;
-  __ex_table : { *(__ex_table) }
-  __stop___ex_table = .;
-
-  . = ALIGN(4096);
-  __init_begin = .;
-  .text.init : { *(.text.init) }
-  .data.init : { *(.data.init) }
-  . = ALIGN(4096);
-  __init_end = .;
-
-  __bss_start = .;
-  .bss       :
-  {
-   *(.sbss) *(.scommon)
-   *(.dynbss)
-   *(.bss)
-   *(COMMON)
-  }
-  __bss_end__ = . ;
-  PROVIDE (end = .);
-}
diff --git a/boards.cfg b/boards.cfg
index b14a08f..90cfb79 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -619,7 +619,6 @@  PQ2FADS-ZU_lowboot           powerpc     mpc8260     mpc8260ads          freesca
 VoVPN-GW_66MHz               powerpc     mpc8260     vovpn-gw            funkwerk       -           VoVPN-GW:CLKIN_66MHz
 mgcoge                       powerpc     mpc8260     km82xx              keymile        -           km82xx:MGCOGE
 mgcoge3ne                    powerpc     mpc8260     km82xx              keymile        -           km82xx:MGCOGE3NE
-SCM                          powerpc     mpc8260     -                   siemens
 TQM8255_AA                   powerpc     mpc8260     tqm8260             tqc            -           TQM8260:MPC8255,300MHz
 TQM8260_AA                   powerpc     mpc8260     tqm8260             tqc            -           TQM8260:MPC8260,200MHz
 TQM8260_AB                   powerpc     mpc8260     tqm8260             tqc            -           TQM8260:MPC8260,200MHz,L2_CACHE,BUSMODE_60x
@@ -855,11 +854,8 @@  Adder87x                     powerpc     mpc8xx      adder               -
 AdderII                      powerpc     mpc8xx      adder               -              -           Adder:MPC852T
 AdderUSB                     powerpc     mpc8xx      adder               -              -           Adder
 ADS860                       powerpc     mpc8xx      fads
-c2mon                        powerpc     mpc8xx
 cogent_mpc8xx                powerpc     mpc8xx      cogent
-EP88x                        powerpc     mpc8xx      ep88x
 ESTEEM192E                   powerpc     mpc8xx      esteem192e
-ETX094                       powerpc     mpc8xx      etx094
 FADS823                      powerpc     mpc8xx      fads
 FADS850SAR                   powerpc     mpc8xx      fads
 FADS860T                     powerpc     mpc8xx      fads
@@ -877,7 +873,6 @@  IVML24_256                   powerpc     mpc8xx      ivm                 -
 IVMS8                        powerpc     mpc8xx      ivm                 -              -           IVMS8:IVMS8_16M
 IVMS8_128                    powerpc     mpc8xx      ivm                 -              -           IVMS8:IVMS8_32M
 IVMS8_256                    powerpc     mpc8xx      ivm                 -              -           IVMS8:IVMS8_64M
-LANTEC                       powerpc     mpc8xx      lantec
 lwmon                        powerpc     mpc8xx
 MBX                          powerpc     mpc8xx      mbx8xx
 MBX860T                      powerpc     mpc8xx      mbx8xx
@@ -924,7 +919,6 @@  KUP4K                        powerpc     mpc8xx      kup4k               kup
 KUP4X                        powerpc     mpc8xx      kup4x               kup
 ELPT860                      powerpc     mpc8xx      elpt860             LEOX
 uc100                        powerpc     mpc8xx      -                   manroland
-IAD210                       powerpc     mpc8xx      -                   siemens
 QS823                        powerpc     mpc8xx      qs850               snmc
 QS850                        powerpc     mpc8xx      qs850               snmc
 QS860T                       powerpc     mpc8xx      qs860t              snmc
@@ -950,7 +944,6 @@  TQM885D                      powerpc     mpc8xx      tqm8xx              tqc
 TTTech                       powerpc     mpc8xx      tqm8xx              tqc            -           TQM823L:LCD,SHARP_LQ104V7DS01
 virtlab2                     powerpc     mpc8xx      tqm8xx              tqc
 wtk                          powerpc     mpc8xx      tqm8xx              tqc            -           TQM823L:LCD,SHARP_LQ065T9DR51U
-AMX860                       powerpc     mpc8xx      amx860              westel
 csb272                       powerpc     ppc4xx
 csb472                       powerpc     ppc4xx
 G2000                        powerpc     ppc4xx      g2000
diff --git a/doc/README.scrapyard b/doc/README.scrapyard
index d0f4716..44c428f 100644
--- a/doc/README.scrapyard
+++ b/doc/README.scrapyard
@@ -11,7 +11,13 @@  easily if here is something they might want to dig for...
 
 Board	Arch	CPU	removed	    Commit	last known maintainer/contact
 =============================================================================
-TQM85xx	powerpc	MPC85xx	-	  -		Stefan Roese <sr@denx.de>
+AMX860	powerpc	mpc860	-	  -		Wolfgang Denk <wd@denx.de>
+c2mon	powerpc	mpc855	-	  -		Wolfgang Denk <wd@denx.de>
+ETX094	powerpc	mpc850	-	  -		Wolfgang Denk <wd@denx.de>
+IAD210	powerpc	mpc860	-	  -		-
+LANTEC	powerpc	mpc850	-	  -		Wolfgang Denk <wd@denx.de>
+SCM	powerpc	mpc8260	-	  -		Wolfgang Grandegger <wg@denx.de>
+TQM85xx	powerpc	MPC85xx	d923a5d	  2012-10-03	Stefan Roese <sr@denx.de>
 apollon arm     omap24xx 535c74f  2012-09-18    Kyungmin Park <kyungmin.park@samsung.com>
 tb0229	mips	mips32	3f3110d	  2011-12-12
 rmu	powerpc	MPC850	fb82fd7   2011-12-07	Wolfgang Denk <wd@denx.de>
diff --git a/include/commproc.h b/include/commproc.h
index 8b8cc45..7ca28c8 100644
--- a/include/commproc.h
+++ b/include/commproc.h
@@ -466,39 +466,6 @@  typedef struct scc_enet {
 
 #endif	/* MPC860ADS */
 
-/***  AMX860  **********************************************/
-
-#if defined(CONFIG_AMX860)
-
-/* This ENET stuff is for the AMX860 with ethernet on SCC1.
- */
-
-#define PROFF_ENET	PROFF_SCC1
-#define CPM_CR_ENET	CPM_CR_CH_SCC1
-#define SCC_ENET	0
-
-#define PA_ENET_RXD	((ushort)0x0001)
-#define PA_ENET_TXD	((ushort)0x0002)
-#define PA_ENET_TCLK	((ushort)0x0400)
-#define PA_ENET_RCLK	((ushort)0x0800)
-
-#define PB_ENET_TENA	((uint)0x00001000)
-
-#define PC_ENET_CLSN	((ushort)0x0010)
-#define PC_ENET_RENA	((ushort)0x0020)
-
-#define SICR_ENET_MASK	((uint)0x000000ff)
-#define SICR_ENET_CLKRT	((uint)0x0000003e)
-
-/* 68160 PHY control */
-
-#define PB_ENET_ETHLOOP	((uint)0x00020000)
-#define PB_ENET_TPFLDL	((uint)0x00010000)
-#define PB_ENET_TPSQEL	((uint)0x00008000)
-#define PD_ENET_ETH_EN	((ushort)0x0004)
-
-#endif	/* CONFIG_AMX860 */
-
 /***  BSEIP  **********************************************************/
 
 #ifdef CONFIG_BSEIP
@@ -547,38 +514,6 @@  typedef struct scc_enet {
 #define SICR_ENET_CLKRT	((uint)0x00003400)
 #endif	/* CONFIG_FLAGADM */
 
-/***  C2MON  **********************************************************/
-
-#ifdef CONFIG_C2MON
-
-# ifndef CONFIG_FEC_ENET	/* use SCC for 10Mbps Ethernet	*/
-#  error "Ethernet on SCC not supported on C2MON Board!"
-# else				/* Use FEC for Fast Ethernet */
-
-#undef	SCC_ENET
-#define FEC_ENET
-
-#define PD_MII_TXD1	((ushort)0x1000)	/* PD  3 */
-#define PD_MII_TXD2	((ushort)0x0800)	/* PD  4 */
-#define PD_MII_TXD3	((ushort)0x0400)	/* PD  5 */
-#define PD_MII_RX_DV	((ushort)0x0200)	/* PD  6 */
-#define PD_MII_RX_ERR	((ushort)0x0100)	/* PD  7 */
-#define PD_MII_RX_CLK	((ushort)0x0080)	/* PD  8 */
-#define PD_MII_TXD0	((ushort)0x0040)	/* PD  9 */
-#define PD_MII_RXD0	((ushort)0x0020)	/* PD 10 */
-#define PD_MII_TX_ERR	((ushort)0x0010)	/* PD 11 */
-#define PD_MII_MDC	((ushort)0x0008)	/* PD 12 */
-#define PD_MII_RXD1	((ushort)0x0004)	/* PD 13 */
-#define PD_MII_RXD2	((ushort)0x0002)	/* PD 14 */
-#define PD_MII_RXD3	((ushort)0x0001)	/* PD 15 */
-
-#define PD_MII_MASK	((ushort)0x1FFF)	/* PD 3...15 */
-
-# endif	/* CONFIG_FEC_ENET */
-#endif	/* CONFIG_C2MON */
-
-/*********************************************************************/
-
 /***  ELPT860 *********************************************************/
 
 #ifdef CONFIG_ELPT860
@@ -828,33 +763,6 @@  typedef struct scc_enet {
 
 #endif	/* CONFIG_HERMES */
 
-/***  IAD210  **********************************************************/
-
-/* The IAD210 uses the FEC on a MPC860P for Ethernet */
-
-#if defined(CONFIG_IAD210)
-
-# define  FEC_ENET    /* use FEC for Ethernet */
-# undef   SCC_ENET
-
-# define PD_MII_TXD1    ((ushort) 0x1000 )	/* PD  3 */
-# define PD_MII_TXD2    ((ushort) 0x0800 )	/* PD  4 */
-# define PD_MII_TXD3    ((ushort) 0x0400 )	/* PD  5 */
-# define PD_MII_RX_DV   ((ushort) 0x0200 )	/* PD  6 */
-# define PD_MII_RX_ERR  ((ushort) 0x0100 )	/* PD  7 */
-# define PD_MII_RX_CLK  ((ushort) 0x0080 )	/* PD  8 */
-# define PD_MII_TXD0    ((ushort) 0x0040 )	/* PD  9 */
-# define PD_MII_RXD0    ((ushort) 0x0020 )	/* PD 10 */
-# define PD_MII_TX_ERR  ((ushort) 0x0010 )	/* PD 11 */
-# define PD_MII_MDC     ((ushort) 0x0008 )	/* PD 12 */
-# define PD_MII_RXD1    ((ushort) 0x0004 )	/* PD 13 */
-# define PD_MII_RXD2    ((ushort) 0x0002 )	/* PD 14 */
-# define PD_MII_RXD3    ((ushort) 0x0001 )	/* PD 15 */
-
-# define PD_MII_MASK    ((ushort) 0x1FFF )   /* PD 3...15 */
-
-#endif	/* CONFIG_IAD210 */
-
 /*** ICU862  **********************************************************/
 
 #if defined(CONFIG_ICU862)
@@ -954,34 +862,6 @@  typedef struct scc_enet {
 
 #endif	/* CONFIG_KUP4K */
 
-
-/***  LANTEC  *********************************************************/
-
-#if defined(CONFIG_LANTEC) && CONFIG_LANTEC >= 2
-/* Bits in parallel I/O port registers that have to be set/cleared
- * to configure the pins for SCC2 use.
- */
-#define	PROFF_ENET	PROFF_SCC2
-#define	CPM_CR_ENET	CPM_CR_CH_SCC2
-#define	SCC_ENET	1
-#define PA_ENET_RXD	((ushort)0x0004)	/* PA 13 */
-#define PA_ENET_TXD	((ushort)0x0008)	/* PA 12 */
-#define PA_ENET_RCLK	((ushort)0x0200)	/* PA  6 */
-#define PA_ENET_TCLK	((ushort)0x0400)	/* PA  5 */
-
-#define PB_ENET_TENA	((uint)0x00002000)	/* PB 18 */
-
-#define PC_ENET_LBK	((ushort)0x0010)	/* PC 11 */
-#define PC_ENET_CLSN	((ushort)0x0040)	/* PC  9 */
-#define PC_ENET_RENA	((ushort)0x0080)	/* PC  8 */
-
-/* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK2) to
- * SCC2.  Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero.
- */
-#define SICR_ENET_MASK	((uint)0x0000FF00)
-#define SICR_ENET_CLKRT	((uint)0x00002E00)
-#endif	/* CONFIG_LANTEC v2 */
-
 /***  LWMON  **********************************************************/
 
 #if defined(CONFIG_LWMON)
@@ -1373,15 +1253,14 @@  typedef struct scc_enet {
 
 #endif	/* CONFIG_SXNI855T */
 
-/***  MVS1, TQM823L/M, TQM850L/M, TQM885D, ETX094, R360MPI  **********/
+/***  MVS1, TQM823L/M, TQM850L/M, TQM885D, R360MPI  **********/
 
 #if (defined(CONFIG_MVS) && CONFIG_MVS < 2) || \
     defined(CONFIG_R360MPI) || defined(CONFIG_RBC823)  || \
-    defined(CONFIG_TQM823L) || defined(CONFIG_TQM823M) || \
-    defined(CONFIG_TQM850L) || defined(CONFIG_TQM850M) || \
-    defined(CONFIG_TQM885D) || defined(CONFIG_ETX094)  || \
-    defined(CONFIG_RRVISION)|| defined(CONFIG_VIRTLAB2)|| \
-   (defined(CONFIG_LANTEC) && CONFIG_LANTEC < 2)
+    defined(CONFIG_RRVISION)|| defined(CONFIG_TQM823L) || \
+    defined(CONFIG_TQM823M) || defined(CONFIG_TQM850L) || \
+    defined(CONFIG_TQM850M) || defined(CONFIG_TQM885D) || \
+    defined(CONFIG_RRVISION)|| defined(CONFIG_VIRTLAB2)
 
 /* Bits in parallel I/O port registers that have to be set/cleared
  * to configure the pins for SCC2 use.
diff --git a/include/configs/AMX860.h b/include/configs/AMX860.h
deleted file mode 100644
index e7a6c80..0000000
--- a/include/configs/AMX860.h
+++ /dev/null
@@ -1,299 +0,0 @@ 
-/*
- * (C) Copyright 2001-2005
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_MPC860		1
-#define CONFIG_AMX860		1
-
-#define	CONFIG_SYS_TEXT_BASE	0x40000000
-
-#undef	CONFIG_8xx_CONS_SMC1		/* Console is on SCC2		*/
-#undef	CONFIG_8xx_CONS_SMC2
-#define	CONFIG_8xx_CONS_SCC2	1
-#undef	CONFIG_8xx_CONS_NONE
-#define CONFIG_BAUDRATE		9600
-#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
-
-#define MPC8XX_FACT		10		/* Multiply by 10	*/
-#define MPC8XX_XIN		5000000			/* 5 MHz in	*/
-#define MPC8XX_HZ ((MPC8XX_XIN) * (MPC8XX_FACT))
-
-#if 0
-#define CONFIG_BOOTDELAY	-1	/* autoboot disabled		*/
-#else
-#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
-#endif
-
-#define CONFIG_BOOTCOMMAND							\
-	"bootp;"								\
-	"setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} "	\
-	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;"	\
-	"bootm"				/* autoboot command */
-
-#undef CONFIG_BOOTARGS
-
-#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
-
-#define	CONFIG_SCC1_ENET	1	/* use SCC1 ethernet */
-
-#define	CONFIG_RTC_MPC8xx		/* use internal RTC of MPC8xx	*/
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_DATE
-#define CONFIG_CMD_NFS
-#define CONFIG_CMD_SNTP
-
-
-#if defined(CONFIG_CMD_KGDB)
-#undef	CONFIG_KGDB_ON_SMC		/* define if kgdb on SMC */
-#define	CONFIG_KGDB_ON_SCC		/* define if kgdb on SCC */
-#undef	CONFIG_KGDB_NONE		/* define if kgdb on something else */
-#define CONFIG_KGDB_INDEX	1	/* which serial channel for kgdb */
-#define CONFIG_KGDB_BAUDRATE	9600	/* speed to run kgdb serial port at */
-#endif
-
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-#define CONFIG_BOOTP_SUBNETMASK
-
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
-#define	CONFIG_SYS_PROMPT		"=> "	/* Monitor Command Prompt	*/
-#if defined(CONFIG_CMD_KGDB)
-#define	CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
-#else
-#define	CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
-#endif
-#define	CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define	CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
-#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
-
-#define CONFIG_SYS_MEMTEST_START	0x0100000	/* memtest works on	*/
-#define CONFIG_SYS_MEMTEST_END		0x0200000	/* 1 ... 4 MB in DRAM	*/
-
-#define CONFIG_SYS_LOAD_ADDR		0x00100000
-
-#define	CONFIG_SYS_HZ		1000		/* decrementer freq: 1 ms ticks	*/
-
-/*
- * Low Level Configuration Settings
- * (address mappings, register initial values, etc.)
- * You should know what you are doing if you make changes here.
- */
-
-/*-----------------------------------------------------------------------
- * Internal Memory Mapped Register
- */
-#define CONFIG_SYS_IMMR			0xFF000000
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in DPRAM)
- */
-#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
-#define	CONFIG_SYS_INIT_RAM_SIZE	0x2F00	/* Size of used area in DPRAM	*/
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define	CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- */
-#define	CONFIG_SYS_SDRAM_BASE		0x00000000
-#define CONFIG_SYS_FLASH_BASE		0x40000000
-#if defined(DEBUG)
-#define	CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
-#else
-#define	CONFIG_SYS_MONITOR_LEN		(192 << 10)	/* Reserve 192 kB for Monitor	*/
-#endif
-#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
-#define	CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
-
-/*
- * U-Boot for AMX board supports two types of memory extension
- * modules: one that provides 4 MB flash memory, and another one with
- * 16 MB EDO DRAM.
- *
- * The flash module swaps the CS0 and CS1 signals: if the module is
- * installed, CS0 is connected to Flash on the module and CS1 is
- * connected to the on-board Flash. This means that you must intall
- * U-Boot when the Flash module is plugged in, if you plan to use
- * it.
- *
- * To enable support for the DRAM extension card, CONFIG_AMX_RAM_EXT
- * must be defined. The DRAM module uses CS1.
- *
- * Only one of these modules may be installed at a time. If U-Boot
- * is compiled with the CONFIG_AMX_RAM_EXT option set, it will not
- * work if the Flash extension module is installed instead of the
- * DRAM module.
- */
-#define CONFIG_AMX_RAM_EXT	/* 16Mb Ext. DRAM module support */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- *
- * Use 4 MB for without and 8 MB with 16 MB DRAM extension module
- * (CONFIG_AMX_RAM_EXT)
- */
-#ifdef CONFIG_AMX_RAM_EXT
-# define	CONFIG_SYS_BOOTMAPSZ	(8 << 20)	/* Initial Memory map for Linux	*/
-#else
-# define	CONFIG_SYS_BOOTMAPSZ	(4 << 20)	/* Initial Memory map for Linux	*/
-#endif
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max number of memory banks		*/
-#define CONFIG_SYS_MAX_FLASH_SECT	35	/* max number of sectors on one chip	*/
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
-
-#define	CONFIG_ENV_IS_IN_FLASH	1
-#define	CONFIG_ENV_OFFSET		0x8000	/*   Offset   of Environment Sector	*/
-#define	CONFIG_ENV_SIZE		0x4000	/* Total Size of Environment Sector	*/
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CONFIG_SYS_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
-#endif
-
-/*-----------------------------------------------------------------------
- * SYPCR - System Protection Control					11-9
- * SYPCR can only be written once after reset!
- *-----------------------------------------------------------------------
- * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
- */
-#if defined(CONFIG_WATCHDOG)
-#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
-			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
-#else
-#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
-#endif
-
-/*-----------------------------------------------------------------------
- * SIUMCR - SIU Module Configuration					11-6
- *-----------------------------------------------------------------------
- * PCMCIA config., multi-function pin tri-state
- */
-#define CONFIG_SYS_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
-
-/*-----------------------------------------------------------------------
- * TBSCR - Time Base Status and Control					11-26
- *-----------------------------------------------------------------------
- * Clear Reference Interrupt Status, Timebase freezing enabled
- */
-#define CONFIG_SYS_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBE)
-
-/*-----------------------------------------------------------------------
- * PISCR - Periodic Interrupt Status and Control		11-31
- *-----------------------------------------------------------------------
- * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
- */
-#define CONFIG_SYS_PISCR	(PISCR_PS | PISCR_PITF)
-
-/*-----------------------------------------------------------------------
- * PLPRCR - PLL, Low-Power, and Reset Control Register	15-30
- *-----------------------------------------------------------------------
- * set the PLL, the low-power modes and the reset control (15-29)
- */
-#define CONFIG_SYS_PLPRCR	(((MPC8XX_FACT-1) << PLPRCR_MF_SHIFT) |	\
-				PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
-
-/*-----------------------------------------------------------------------
- * SCCR - System Clock and reset Control Register		15-27
- *-----------------------------------------------------------------------
- * Set clock output, timebase and RTC source and divider,
- * power management and some other internal clocks
- */
-#define SCCR_MASK	SCCR_EBDF11
-#define CONFIG_SYS_SCCR	(SCCR_TBS|SCCR_COM00|SCCR_DFSYNC00|SCCR_DFBRG00|SCCR_DFNL000|SCCR_DFNH000|SCCR_DFLCD000|SCCR_DFALCD00)
-
-#define CONFIG_SYS_DER		0
-
-/*
- * Init Memory Controller:
- *
- * BR0/1 and OR0/1 (FLASH)
- */
-
-#define FLASH_BASE0_PRELIM	0x40000000	/* FLASH bank #0	*/
-#ifndef CONFIG_AMX_RAM_EXT
-#define FLASH_BASE1_PRELIM	0x60000000	/* FLASH bank #1	*/
-#endif
-
-#define CONFIG_SYS_REMAP_OR_AM		0x80000000	/* OR addr mask */
-#define CONFIG_SYS_PRELIM_OR_AM	0xFFC00000	/* OR addr mask */
-
-/* FLASH timing: ACS = 10, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 0	*/
-/*				 0x00000800	0x00000400 0x00000100 0x00000030     0x00000004 */
-#define CONFIG_SYS_OR_TIMING_FLASH	(OR_CSNT_SAM  | OR_ACS_DIV4 | OR_BI | OR_SCY_5_CLK | OR_TRLX)
-
-#define CONFIG_SYS_OR0_REMAP	(CONFIG_SYS_REMAP_OR_AM  | CONFIG_SYS_OR_TIMING_FLASH)
-
-#define CONFIG_SYS_OR0_PRELIM	0xFFC00954	/* Real values for the board */
-#define CONFIG_SYS_BR0_PRELIM	0x40000001	/* Real values for the board */
-
-#ifndef CONFIG_AMX_RAM_EXT
-#define CONFIG_SYS_OR1_REMAP	CONFIG_SYS_OR0_REMAP
-#define CONFIG_SYS_OR1_PRELIM	0xFFC00954	/* Real values for the board */
-#define CONFIG_SYS_BR1_PRELIM	0x60000001	/* Real values for the board */
-#endif
-
-/* DSP ("Glue") Xilinx */
-#define CONFIG_SYS_OR6_PRELIM	0xFFFF8000	/* 32kB, 15 waits, cs after addr, no bursts */
-#define CONFIG_SYS_BR6_PRELIM	0x60000401	/* use GPCM for CS generation, 8 bit port */
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/ETX094.h b/include/configs/ETX094.h
deleted file mode 100644
index 2703625..0000000
--- a/include/configs/ETX094.h
+++ /dev/null
@@ -1,357 +0,0 @@ 
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_MPC850		1	/* This is a MPC850 CPU		*/
-#define CONFIG_ETX094		1	/* ...on a ETX_094 board	*/
-
-#define	CONFIG_SYS_TEXT_BASE	0x40000000
-
-#define	CONFIG_8xx_CONS_SMC1    1       /* Console is on SMC1           */
-#undef	CONFIG_8xx_CONS_SMC2
-#undef	CONFIG_8xx_CONS_NONE
-#define CONFIG_BAUDRATE		57600
-#if 0
-#define CONFIG_BOOTDELAY	-1	/* autoboot disabled		*/
-#else
-#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
-#endif
-
-#define	CONFIG_CLOCKS_IN_MHZ	1	/* clocks passsed to Linux in MHz */
-
-#define CONFIG_BOARD_TYPES	1	/* support board types		*/
-
-#define	CONFIG_FLASH_16BIT		/* for board with 16bit wide flash	*/
-#undef	SB_ETX094			/* only for SB-Board with 16MB SDRAM	*/
-#define	CONFIG_BOOTP_RANDOM_DELAY	/* graceful BOOTP recovery mode		*/
-
-#define CONFIG_ETHADDR 08:00:06:00:00:00
-
-#ifdef	CONFIG_ETHADDR
-#define CONFIG_OVERWRITE_ETHADDR_ONCE 1	/* default MAC can be overwritten once	*/
-#endif
-
-#undef	CONFIG_BOOTARGS
-#define CONFIG_RAMBOOTCOMMAND							\
-	"bootp; "								\
-	"setenv bootargs root=/dev/ram rw ramdisk_size=4690 "			\
-	"U-Boot_version=U-Boot-1.0.x-Date "					\
-	"panic=1 "								\
-	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; "	\
-	"bootm"
-#define CONFIG_NFSBOOTCOMMAND							\
-	"bootp; "								\
-	"setenv bootargs root=/dev/nfs rw nfsroot=${nfsip}:${rootpath} "	\
-	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; "	\
-	"bootm"
-#define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND
-
-#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
-#undef	CONFIG_SYS_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
-
-#define	CONFIG_WATCHDOG		1	/* watchdog enabled		*/
-
-#define	CONFIG_STATUS_LED	1	/* Status LED enabled		*/
-
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_SUBNETMASK
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_BOOTFILESIZE
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-
-/*
- * Miscellaneous configurable options
- */
-#define	CONFIG_SYS_LONGHELP			/* undef to save memory		*/
-#define	CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt	*/
-#if defined(CONFIG_CMD_KGDB)
-#define	CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
-#else
-#define	CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
-#endif
-#define	CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define	CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
-#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
-
-#define CONFIG_SYS_MEMTEST_START	0x0300000	/* memtest works on	*/
-#define CONFIG_SYS_MEMTEST_END		0x0700000	/* 3 ... 7 MB in DRAM	*/
-
-#define	CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address	*/
-
-#define	CONFIG_SYS_HZ		1000		/* decrementer freq: 1 ms ticks	*/
-
-/*
- * Low Level Configuration Settings
- * (address mappings, register initial values, etc.)
- * You should know what you are doing if you make changes here.
- */
-/*-----------------------------------------------------------------------
- * Internal Memory Mapped Register
- */
-#define CONFIG_SYS_IMMR		0xFFF00000
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in DPRAM)
- */
-#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
-#define	CONFIG_SYS_INIT_RAM_SIZE	0x2F00	/* Size of used area in DPRAM	*/
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define	CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- */
-#define	CONFIG_SYS_SDRAM_BASE		0x00000000
-#define CONFIG_SYS_FLASH_BASE		0x40000000
-#ifdef	DEBUG
-#define	CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
-#else
-#define	CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
-#endif
-#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
-#define	CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define	CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
-#define CONFIG_SYS_MAX_FLASH_SECT	35	/* max number of sectors on one chip	*/
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CONFIG_SYS_FLASH_WRITE_TOUT	1000	/* Timeout for Flash Write (in ms)	*/
-
-#define	CONFIG_ENV_IS_IN_FLASH	1
-#ifdef CONFIG_FLASH_16BIT
-#define CONFIG_ENV_OFFSET		0x8000	/* Offset   of Environment Sector	*/
-#define	CONFIG_ENV_SIZE		0x8000	/* Total Size of Environment Sector	*/
-#else
-#define CONFIG_ENV_OFFSET		0x8000	/* Offset   of Environment Sector	*/
-#define	CONFIG_ENV_SIZE		0x4000	/* Total Size of Environment Sector	*/
-#endif
-
-/*-----------------------------------------------------------------------
- * Hardware Information Block
- */
-#define CONFIG_SYS_HWINFO_OFFSET	0x0003FFC0	/* offset of HW Info block */
-#define CONFIG_SYS_HWINFO_SIZE		0x00000040	/* size   of HW Info block */
-#define CONFIG_SYS_HWINFO_MAGIC	0x54514D38	/* 'TQM8' */
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CONFIG_SYS_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
-#endif
-
-/*-----------------------------------------------------------------------
- * SYPCR - System Protection Control				11-9
- * SYPCR can only be written once after reset!
- *-----------------------------------------------------------------------
- * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
- */
-#if defined(CONFIG_WATCHDOG)
-#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
-			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
-#else
-#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
-#endif	/* CONFIG_WATCHDOG */
-
-/*-----------------------------------------------------------------------
- * SIUMCR - SIU Module Configuration				11-6
- *-----------------------------------------------------------------------
- * PCMCIA config., multi-function pin tri-state
- */
-#define CONFIG_SYS_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
-
-/*-----------------------------------------------------------------------
- * TBSCR - Time Base Status and Control				11-26
- *-----------------------------------------------------------------------
- * Clear Reference Interrupt Status, Timebase freezing enabled
- */
-#define CONFIG_SYS_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
-
-/*-----------------------------------------------------------------------
- * RTCSC - Real-Time Clock Status and Control Register		11-27
- *-----------------------------------------------------------------------
- */
-#define CONFIG_SYS_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
-
-/*-----------------------------------------------------------------------
- * PISCR - Periodic Interrupt Status and Control		11-31
- *-----------------------------------------------------------------------
- * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
- */
-#define CONFIG_SYS_PISCR	(PISCR_PS | PISCR_PITF)
-
-/*-----------------------------------------------------------------------
- * PLPRCR - PLL, Low-Power, and Reset Control Register		15-30
- *-----------------------------------------------------------------------
- * Reset PLL lock status sticky bit, timer expired status bit and timer
- * interrupt status bit - leave PLL multiplication factor unchanged !
- */
-#define CONFIG_SYS_PLPRCR	(PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
-
-/*-----------------------------------------------------------------------
- * SCCR - System Clock and reset Control Register		15-27
- *-----------------------------------------------------------------------
- * Set clock output, timebase and RTC source and divider,
- * power management and some other internal clocks
- */
-#define SCCR_MASK	SCCR_EBDF11
-#define CONFIG_SYS_SCCR	(SCCR_TBS     | \
-			 SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
-			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
-			 SCCR_DFALCD00)
-
-/*-----------------------------------------------------------------------
- * PCMCIA stuff
- *-----------------------------------------------------------------------
- *
- */
-#define CONFIG_SYS_PCMCIA_MEM_ADDR	(0xE0000000)
-#define CONFIG_SYS_PCMCIA_MEM_SIZE	( 64 << 20 )
-#define CONFIG_SYS_PCMCIA_DMA_ADDR	(0xE4000000)
-#define CONFIG_SYS_PCMCIA_DMA_SIZE	( 64 << 20 )
-#define CONFIG_SYS_PCMCIA_ATTRB_ADDR	(0xE8000000)
-#define CONFIG_SYS_PCMCIA_ATTRB_SIZE	( 64 << 20 )
-#define CONFIG_SYS_PCMCIA_IO_ADDR	(0xEC000000)
-#define CONFIG_SYS_PCMCIA_IO_SIZE	( 64 << 20 )
-
-/*-----------------------------------------------------------------------
- *
- *-----------------------------------------------------------------------
- *
- */
-#define CONFIG_SYS_DER	0
-
-/*
- * Init Memory Controller:
- *
- * BR0/1 and OR0/1 (FLASH)
- */
-
-#define FLASH_BASE0_PRELIM	0x40000000	/* FLASH bank #0	*/
-#define FLASH_BASE1_PRELIM	0x60000000	/* FLASH bank #0	*/
-
-/* used to re-map FLASH both when starting from SRAM or FLASH:
- * restrict access enough to keep SRAM working (if any)
- * but not too much to meddle with FLASH accesses
- */
-#define CONFIG_SYS_REMAP_OR_AM		0x80000000	/* OR addr mask */
-#define CONFIG_SYS_PRELIM_OR_AM	0xE0000000	/* OR addr mask */
-
-/* FLASH timing: ACS = 11, TRLX = 1, CSNT = 0, SCY = 2, EHTR = 0	*/
-#define CONFIG_SYS_OR_TIMING_FLASH    (OR_ACS_DIV2 | OR_BI | \
-			       OR_SCY_2_CLK | OR_TRLX )
-
-#define CONFIG_SYS_OR0_REMAP	(CONFIG_SYS_REMAP_OR_AM  | CONFIG_SYS_OR_TIMING_FLASH)
-#define CONFIG_SYS_OR0_PRELIM	(CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
-
-#ifdef CONFIG_FLASH_16BIT	/* 16 bit data port */
-#define CONFIG_SYS_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V | BR_PS_16)
-#define CONFIG_SYS_BR1_PRELIM	((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V | BR_PS_16)
-#else				/* 32 bit data port */
-#define CONFIG_SYS_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V | BR_PS_32)
-#define CONFIG_SYS_BR1_PRELIM	((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V | BR_PS_32)
-#endif	/* CONFIG_FLASH_16BIT */
-
-#define CONFIG_SYS_OR1_REMAP	CONFIG_SYS_OR0_REMAP
-#define CONFIG_SYS_OR1_PRELIM	CONFIG_SYS_OR0_PRELIM
-
-/*
- * BR2/3 and OR2/3 (SDRAM)
- *
- */
-#define SDRAM_BASE2_PRELIM	0x00000000	/* SDRAM bank #0	*/
-#define SDRAM_BASE3_PRELIM	0x20000000	/* SDRAM bank #1	*/
-#define	SDRAM_MAX_SIZE		0x04000000	/* max 64 MB per bank	*/
-
-/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)	*/
-#define CONFIG_SYS_OR_TIMING_SDRAM	0x00000A00
-
-#define CONFIG_SYS_OR2_PRELIM	(CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM )
-#define CONFIG_SYS_BR2_PRELIM	((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
-
-#define	CONFIG_SYS_OR3_PRELIM	CONFIG_SYS_OR2_PRELIM
-#define CONFIG_SYS_BR3_PRELIM	((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
-
-/*
- * Memory Periodic Timer Prescaler
- */
-
-/* periodic timer for refresh */
-#define CONFIG_SYS_MAMR_PTA	23		/* start with divider for 100 MHz	*/
-
-/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit	*/
-#define CONFIG_SYS_MPTPR_2BK_4K	MPTPR_PTP_DIV16		/* setting for 2 banks	*/
-#define CONFIG_SYS_MPTPR_1BK_4K	MPTPR_PTP_DIV32		/* setting for 1 bank	*/
-
-/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit		*/
-#define CONFIG_SYS_MPTPR_2BK_8K	MPTPR_PTP_DIV8		/* setting for 2 banks	*/
-#define CONFIG_SYS_MPTPR_1BK_8K	MPTPR_PTP_DIV16		/* setting for 1 bank	*/
-
-/*
- * MAMR settings for SDRAM
- */
-
-/* 8 column SDRAM */
-#define CONFIG_SYS_MAMR_8COL	((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
-			 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 |	\
-			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_1X)
-/* 9 column SDRAM */
-#define CONFIG_SYS_MAMR_9COL	((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
-			 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |	\
-			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_1X)
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/IAD210.h b/include/configs/IAD210.h
deleted file mode 100644
index 94b05dc..0000000
--- a/include/configs/IAD210.h
+++ /dev/null
@@ -1,381 +0,0 @@ 
-/*
- * (C) Copyright 2001, 2002
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#include <mpc8xx_irq.h>
-
-
-# ifdef DEBUG
-#  warning DEBUG Defined
-# endif /* DEBUG */
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-#define CONFIG_MPC860		1
-#define CONFIG_IAD210		1	/* ...on a IAD210  module	*/
-#define CONFIG_MPC860T		1
-#define CONFIG_MPC862		1
-
-#define	CONFIG_SYS_TEXT_BASE	0x08000000
-
-#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
-
-#undef  CONFIG_8xx_CONS_SMC1
-#undef  CONFIG_8xx_CONS_SMC2
-#define CONFIG_8xx_CONS_SCC2   /* V24 on SCC2 */
-#undef  CONFIG_8xx_CONS_NONE
-#define CONFIG_BAUDRATE		9600
-
-
-# define MPC8XX_FACT            16
-# define CONFIG_8xx_GCLK_FREQ   (64000000L)  /* define if can't use get_gclk_freq */
-# define CONFIG_CLOCKS_IN_MHZ	1            /* clocks passsed to Linux in MHz */
-
-#if 0
-# define CONFIG_BOOTDELAY	-1	/* autoboot disabled		*/
-#else
-# define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
-#endif
-
-#define CONFIG_PREBOOT	"echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo"
-
-/* using this define saves us updating another source file */
-#define CONFIG_BOARD_EARLY_INIT_F 1
-#define CONFIG_MISC_INIT_R
-
-#undef	CONFIG_BOOTARGS
-/* #define CONFIG_BOOTCOMMAND							\
-	"bootp;"								\
-	"setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} "	\
-	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;"	\
-	"bootm"
-*/
-
-#define CONFIG_BOOTCOMMAND	\
-	"setenv bootargs root=/dev/nfs"	\
-	"ip=192.168.28.129:139.10.137.138:192.168.28.1:255.255.255.0:iadlinux002::off; "	\
-
-#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
-
-/* #define	CONFIG_STATUS_LED	1*/	/* Status LED enabled		*/
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_SUBNETMASK
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_BOOTFILESIZE
-
-
-# undef  CONFIG_SCC1_ENET		/* disable SCC1 ethernet */
-# define CONFIG_FEC_ENET    1	/* use FEC ethernet  */
-# define CONFIG_MII         1
-# define CONFIG_SYS_DISCOVER_PHY   1
-# define CONFIG_FEC_UTOPIA  1
-# define CONFIG_ETHADDR     08:00:06:26:A2:6D
-# define CONFIG_IPADDR      192.168.28.128
-# define CONFIG_SERVERIP    139.10.137.138
-# define CONFIG_SYS_DISCOVER_PHY   1
-
-#define CONFIG_MAC_PARTITION
-#define CONFIG_DOS_PARTITION
-
-/* enable I2C and select the hardware/software driver */
-#undef  CONFIG_HARD_I2C			/* I2C with hardware support    */
-#define CONFIG_SOFT_I2C		1	/* I2C bit-banged               */
-# define CONFIG_SYS_I2C_SPEED		50000
-# define CONFIG_SYS_I2C_SLAVE		0xDD
-# define CONFIG_SYS_I2C_EEPROM_ADDR	0x50
-/*
- * Software (bit-bang) I2C driver configuration
- */
-#define PB_SCL		0x00000020	/* PB 26 */
-#define PB_SDA		0x00000010	/* PB 27 */
-
-#define I2C_INIT	(immr->im_cpm.cp_pbdir |=  PB_SCL)
-#define I2C_ACTIVE	(immr->im_cpm.cp_pbdir |=  PB_SDA)
-#define I2C_TRISTATE	(immr->im_cpm.cp_pbdir &= ~PB_SDA)
-#define I2C_READ	((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
-#define I2C_SDA(bit)	if(bit) immr->im_cpm.cp_pbdat |=  PB_SDA; \
-			else    immr->im_cpm.cp_pbdat &= ~PB_SDA
-#define I2C_SCL(bit)	if(bit) immr->im_cpm.cp_pbdat |=  PB_SCL; \
-			else    immr->im_cpm.cp_pbdat &= ~PB_SCL
-#define I2C_DELAY	udelay(5)	/* 1/4 I2C clock duration */
-
-#define	CONFIG_RTC_MPC8xx		/* use internal RTC of MPC8xx	*/
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_DATE
-
-
-/*
- * Miscellaneous configurable options
- */
-#define	CONFIG_SYS_LONGHELP			/* undef to save memory		*/
-#define	CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt	*/
-#if defined(CONFIG_CMD_KGDB)
-#define	CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
-#else
-#define	CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
-#endif
-#define	CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define	CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
-#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
-
-#define CONFIG_SYS_MEMTEST_START	0x0100000	/* memtest works on	*/
-#define CONFIG_SYS_MEMTEST_END		0x0400000	/* 1 ... 4 MB in DRAM	*/
-
-#define CONFIG_SYS_LOAD_ADDR		0x00100000
-
-#define	CONFIG_SYS_HZ		1000		/* decrementer freq: 1 ms ticks	*/
-
-/*
- * Low Level Configuration Settings
- * (address mappings, register initial values, etc.)
- * You should know what you are doing if you make changes here.
- */
-/*-----------------------------------------------------------------------
- * Internal Memory Mapped Register
- */
-#define CONFIG_SYS_IMMR		0xFFF00000
-#define CONFIG_SYS_IMMR_SIZE		((uint)(64 * 1024))
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in DPRAM)
- */
-#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
-#define	CONFIG_SYS_INIT_RAM_SIZE	0x2F00	/* Size of used area in DPRAM	*/
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define	CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- */
-#define	CONFIG_SYS_SDRAM_BASE		0x00000000
-#define CONFIG_SYS_FLASH_BASE		0x08000000
-#define CONFIG_SYS_FLASH_SIZE		((uint)(4 * 1024 * 1024))	/* max 16Mbyte */
-
-#define CONFIG_SYS_RESET_ADDRESS	0xFFF00100
-
-#if defined(DEBUG)
-# define	CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
-#else
-# define	CONFIG_SYS_MONITOR_LEN		(192 << 10)	/* Reserve 192 kB for Monitor	*/
-#endif
-
-# define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
-# define CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define	CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
-#define CONFIG_SYS_MAX_FLASH_SECT	67	/* max number of sectors on one chip	*/
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CONFIG_SYS_FLASH_WRITE_TOUT	500		/* Timeout for Flash Write (in ms)	*/
-
-#define	CONFIG_ENV_IS_IN_FLASH	1
-#define CONFIG_ENV_OFFSET		0x8000
-#define	CONFIG_ENV_SIZE		0x4000	/* Total Size of Environment Sector	*/
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CONFIG_SYS_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
-#endif
-
-/*-----------------------------------------------------------------------
- * SYPCR - System Protection Control					11-9
- * SYPCR can only be written once after reset!
- *-----------------------------------------------------------------------
- * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
- */
-#if defined(CONFIG_WATCHDOG)
-#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
-			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
-#else
-#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
-#endif
-
-/*-----------------------------------------------------------------------
- * SIUMCR - SIU Module Configuration					11-6
- *-----------------------------------------------------------------------
- * PCMCIA config., multi-function pin tri-state
- */
-#define CONFIG_SYS_SIUMCR	(SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
-
-/*-----------------------------------------------------------------------
- * TBSCR - Time Base Status and Control					11-26
- *-----------------------------------------------------------------------
- * Clear Reference Interrupt Status, Timebase freezing enabled
- */
-#define CONFIG_SYS_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
-
-/*-----------------------------------------------------------------------
- * PISCR - Periodic Interrupt Status and Control		11-31
- *-----------------------------------------------------------------------
- * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
- */
-#define CONFIG_SYS_PISCR	(PISCR_PS | PISCR_PITF)
-
-/*-----------------------------------------------------------------------
- * PLPRCR - PLL, Low-Power, and Reset Control Register	15-30
- *-----------------------------------------------------------------------
- * set the PLL, the low-power modes and the reset control (15-29)
- */
-#define CONFIG_SYS_PLPRCR	(((MPC8XX_FACT-1) << PLPRCR_MF_SHIFT) |	\
-				PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
-
-/*-----------------------------------------------------------------------
- * SCCR - System Clock and reset Control Register		15-27
- *-----------------------------------------------------------------------
- * Set clock output, timebase and RTC source and divider,
- * power management and some other internal clocks
- */
-#define SCCR_MASK	SCCR_EBDF11
-
-#define CONFIG_SYS_SCCR	(SCCR_TBS	| SCCR_COM00	| SCCR_DFSYNC00	| \
-			 SCCR_DFBRG00	| SCCR_DFNL000	| SCCR_DFNH000	| \
-			 SCCR_DFLCD000	|SCCR_DFALCD00	)
-
-/*-----------------------------------------------------------------------
- * RCCR - RISC Controller Configuration Register		19-4
- *-----------------------------------------------------------------------
- */
-/* +0x09C4 => DRQP = 10 (IDMA requests have lowest priority) */
-#define CONFIG_SYS_RCCR 0x0020
-
-/*-----------------------------------------------------------------------
- * PCMCIA stuff
- *-----------------------------------------------------------------------
- */
-#define PCMCIA_MEM_ADDR		((uint)0xff020000)
-#define PCMCIA_MEM_SIZE		((uint)(64 * 1024))
-
-/*-----------------------------------------------------------------------
- *
- *-----------------------------------------------------------------------
- *
- */
-#define CONFIG_SYS_DER		0
-
-/* Because of the way the 860 starts up and assigns CS0 the
-* entire address space, we have to set the memory controller
-* differently.  Normally, you write the option register
-* first, and then enable the chip select by writing the
-* base register.  For CS0, you must write the base register
-* first, followed by the option register.
-*/
-
-/*
- * Init Memory Controller:
- *
- * BR0 and OR0 (FLASH)
- */
-
-#define FLASH_BASE0_PRELIM	CONFIG_SYS_FLASH_BASE	/* FLASH bank #0	*/
-
-/* used to re-map FLASH both when starting from SRAM or FLASH:
- * restrict access enough to keep SRAM working (if any)
- * but not too much to meddle with FLASH accesses
- */
-#define CONFIG_SYS_REMAP_OR_AM		0xF8000000	/* OR addr mask */
-#define CONFIG_SYS_PRELIM_OR_AM	0xF8000000	/* OR addr mask */
-
-/* FLASH timing:
- TRLX = 0, CSNT = 1, SCY = 3, EHTR = 1	*/
-#define CONFIG_SYS_OR_TIMING_FLASH	(OR_CSNT_SAM  | OR_BI | \
-				 OR_SCY_3_CLK | OR_EHTR)
-
-#define CONFIG_SYS_OR0_PRELIM	(CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
-#define CONFIG_SYS_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
-
-/*
- * BR2/3 and OR2/3 (SDRAM)
- *
- */
-#define SDRAM_BASE_PRELIM	0x00000000	/* SDRAM bank #0	*/
-#define	SDRAM_MAX_SIZE		0x04000000	/* max 64 MB per bank	*/
-
-/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)	*/
-
-#define CONFIG_SYS_OR2_PRELIM	(CONFIG_SYS_PRELIM_OR_AM | OR_CSNT_SAM  | OR_BI | OR_ACS_DIV4)
-#define CONFIG_SYS_BR2_PRELIM	((SDRAM_BASE_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
-#define CONFIG_SYS_BR1_PRELIM	((SDRAM_BASE1_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V)
-
-/*
- * Memory Periodic Timer Prescaler
- */
-
-/* periodic timer for refresh */
-#define CONFIG_SYS_MAMR_PTA	124		/* start with divider for 64 MHz	*/
-
-/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit	*/
-#define CONFIG_SYS_MPTPR	        MPTPR_PTP_DIV32		/* setting for 1 bank	*/
-
-/*
- * MAMR settings for SDRAM
- */
-
-#define CONFIG_SYS_MAMR	((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
-			 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 |	\
-			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_8X)
-
-#ifdef CONFIG_MPC860T
-
-/* Interrupt level assignments.
-*/
-#define FEC_INTERRUPT	SIU_LEVEL1	/* FEC interrupt */
-
-#endif /* CONFIG_MPC860T */
-
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/LANTEC.h b/include/configs/LANTEC.h
deleted file mode 100644
index c3855c3..0000000
--- a/include/configs/LANTEC.h
+++ /dev/null
@@ -1,358 +0,0 @@ 
-/*
- * (C) Copyright 2000, 2001
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- * (C) Copyright 2001
- * Torsten Stevens, FHG IMS, stevens@ims.fhg.de
- * Bruno Achauer, Exet AG, bruno@exet-ag.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * board/config.h - configuration options, board specific
- * [derived from config_TQM850L.h]
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_MPC850		1	/* This is a MPC850 CPU		*/
-#define CONFIG_LANTEC		2	/* ...on a Lantec rev.2 board	*/
-
-#define	CONFIG_SYS_TEXT_BASE	0x40000000
-
-/*
- *  Port assignments (CONFIG_LANTEC == 1):
- *  - SMC1: J11 (MDB) ?
- *  - SMC2: J6  (Feature connector)
- *  - SCC2: J9  (RJ45)
- *  - SCC3: J8  (Sub-D9)
- *
- *  Port assignments (CONFIG_LANTEC == 2): TBD
- */
-
-
-#undef CONFIG_8xx_CONS_SMC2           /* Console is on SMC2           */
-#define	CONFIG_8xx_CONS_SCC3
-#undef  CONFIG_8xx_CONS_NONE
-#define CONFIG_BAUDRATE         38400   /* console baudrate = 38.4kbps  */
-#if 0
-#define CONFIG_BOOTDELAY	-1	/* autoboot disabled		*/
-#else
-#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
-#endif
-
-#define	CONFIG_CLOCKS_IN_MHZ	1	/* clocks passsed to Linux in MHz */
-
-#undef	CONFIG_BOOTARGS
-#define CONFIG_BOOTCOMMAND							\
-	"setenv bootargs root=/dev/ram panic=5;bootm 40040000 400A0000"
-
-#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
-#undef	CONFIG_SYS_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
-
-#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
-
-#define	CONFIG_STATUS_LED	1	/* Status LED enabled		*/
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_SUBNETMASK
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_BOOTFILESIZE
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_CACHE
-#define CONFIG_CMD_CDP
-#define CONFIG_CMD_DATE
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_DIAG
-#define CONFIG_CMD_FAT
-#define CONFIG_CMD_IMMAP
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_PORTIO
-#define CONFIG_CMD_REGINFO
-#define CONFIG_CMD_SAVES
-#define CONFIG_CMD_SDRAM
-#define CONFIG_CMD_SNTP
-
-#undef CONFIG_CMD_XIMG
-
-#if !(CONFIG_LANTEC >= 2)
-    #undef CONFIG_CMD_DATE
-    #undef CONFIG_CMD_NET
-#endif
-
-
-#if CONFIG_LANTEC >= 2
-#define	CONFIG_RTC_MPC8xx		/* use internal RTC of MPC8xx	*/
-#endif
-
-/*
- * Miscellaneous configurable options
- */
-#define	CONFIG_SYS_LONGHELP			/* undef to save memory		*/
-#define	CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt	*/
-#if defined(CONFIG_CMD_KGDB)
-#define	CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
-#else
-#define	CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
-#endif
-#define	CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define	CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
-#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
-
-#define CONFIG_SYS_MEMTEST_START	0x0400000	/* memtest works on	*/
-#define CONFIG_SYS_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
-
-#define	CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address	*/
-
-#define	CONFIG_SYS_HZ		1000		/* decrementer freq: 1 ms ticks	*/
-
-/*
- * Low Level Configuration Settings
- * (address mappings, register initial values, etc.)
- * You should know what you are doing if you make changes here.
- */
-/*-----------------------------------------------------------------------
- * Internal Memory Mapped Register
- */
-#define CONFIG_SYS_IMMR		0xFFF00000
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in DPRAM)
- */
-#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
-#define	CONFIG_SYS_INIT_RAM_SIZE	0x2F00	/* Size of used area in DPRAM	*/
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define	CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- */
-#define	CONFIG_SYS_SDRAM_BASE		0x00000000
-#define CONFIG_SYS_FLASH_BASE		0x40000000
-#define	CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
-#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
-#define	CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define	CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
-
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max number of memory banks		*/
-#define CONFIG_SYS_MAX_FLASH_SECT	67	/* max number of sectors on one chip	*/
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
-
-#define	CONFIG_ENV_IS_IN_FLASH	1
-#define	CONFIG_ENV_OFFSET		0x8000	/*   Offset   of Environment Sector	*/
-#define	CONFIG_ENV_SIZE		0x4000	/* Total Size of Environment Sector	*/
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CONFIG_SYS_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
-#endif
-
-/*-----------------------------------------------------------------------
- * SYPCR - System Protection Control				11-9
- * SYPCR can only be written once after reset!
- *-----------------------------------------------------------------------
- * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
- */
-#if defined(CONFIG_WATCHDOG)
-#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
-			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
-#else
-#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
-#endif
-
-/*-----------------------------------------------------------------------
- * SIUMCR - SIU Module Configuration				11-6
- *-----------------------------------------------------------------------
- * PCMCIA config., multi-function pin tri-state
- */
-#define CONFIG_SYS_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01 | SIUMCR_DLK)
-
-/*-----------------------------------------------------------------------
- * Clock Setting - Has the Lantec board a 32kHz clock ??? [XXX]
- *-----------------------------------------------------------------------
- */
-#define	CONFIG_8xx_GCLK_FREQ	33000000
-
-/*-----------------------------------------------------------------------
- * TBSCR - Time Base Status and Control				11-26
- *-----------------------------------------------------------------------
- * Clear Reference Interrupt Status, Timebase freezing enabled
- */
-#define CONFIG_SYS_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
-
-/*-----------------------------------------------------------------------
- * RTCSC - Real-Time Clock Status and Control Register		11-27
- *-----------------------------------------------------------------------
- */
-#define CONFIG_SYS_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
-
-/*-----------------------------------------------------------------------
- * PISCR - Periodic Interrupt Status and Control		11-31
- *-----------------------------------------------------------------------
- * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
- */
-#define CONFIG_SYS_PISCR	(PISCR_PS | PISCR_PITF)
-
-/*-----------------------------------------------------------------------
- * PLPRCR - PLL, Low-Power, and Reset Control Register		15-30
- *-----------------------------------------------------------------------
- * Reset PLL lock status sticky bit, timer expired status bit and timer
- * interrupt status bit
- *
- * If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)!
- */
-			/* up to 50 MHz we use a 1:1 clock */
-#define CONFIG_SYS_PLPRCR	(PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
-
-/*-----------------------------------------------------------------------
- * SCCR - System Clock and reset Control Register		15-27
- *-----------------------------------------------------------------------
- * Set clock output, timebase and RTC source and divider,
- * power management and some other internal clocks
- */
-#define SCCR_MASK	SCCR_EBDF11
-			/* up to 50 MHz we use a 1:1 clock */
-#define CONFIG_SYS_SCCR	(SCCR_TBS     | \
-			 SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
-			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
-			 SCCR_DFALCD00)
-
-/*-----------------------------------------------------------------------
- *
- *-----------------------------------------------------------------------
- *
- */
-#define CONFIG_SYS_DER	0
-
-/*
- * Init Memory Controller:
- *
- * BR0/5 and OR0/5 (FLASH)
- */
-
-#define FLASH_BASE0_PRELIM	0x40000000	/* FLASH bank #0	*/
-#define FLASH_BASE5_PRELIM	0x60000000	/* FLASH bank #1	*/
-
-/* used to re-map FLASH both when starting from SRAM or FLASH:
- * restrict access enough to keep SRAM working (if any)
- * but not too much to meddle with FLASH accesses
- */
-#define CONFIG_SYS_REMAP_OR_AM		0x80000000	/* OR addr mask */
-#define CONFIG_SYS_PRELIM_OR_AM	0xE0000000	/* OR addr mask */
-
-/* FLASH timing */
-#define CONFIG_SYS_OR_TIMING_FLASH     (OR_CSNT_SAM  | OR_BI | \
-				 OR_SCY_5_CLK | OR_TRLX)
-
-#define CONFIG_SYS_OR0_REMAP	(CONFIG_SYS_REMAP_OR_AM  | CONFIG_SYS_OR_TIMING_FLASH)
-#define CONFIG_SYS_OR0_PRELIM	(CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
-#define CONFIG_SYS_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
-
-#define CONFIG_SYS_OR5_REMAP   CONFIG_SYS_OR0_REMAP
-#define CONFIG_SYS_OR5_PRELIM  CONFIG_SYS_OR0_PRELIM
-#define CONFIG_SYS_BR5_PRELIM  ((FLASH_BASE5_PRELIM & BR_BA_MSK) | BR_V )
-
-/*
- * BR2/3 and OR2/3 (SDRAM)
- *
- */
-#define SDRAM_BASE3_PRELIM      0x00000000      /* SDRAM bank #0        */
-#define SDRAM_MAX_SIZE          0x04000000      /* max 64 MB per bank   */
-
-/* SDRAM timing: Multiplexed addresses					*/
-#define CONFIG_SYS_OR_TIMING_SDRAM     (OR_CSNT_SAM)
-
-#define CONFIG_SYS_OR3_PRELIM  (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM )
-#define CONFIG_SYS_BR3_PRELIM  ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
-
-/*
- * Memory Periodic Timer Prescaler
- */
-
-/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit	*/
-#define CONFIG_SYS_MPTPR_2BK_4K	MPTPR_PTP_DIV16		/* setting for 2 banks	*/
-#define CONFIG_SYS_MPTPR_1BK_4K	MPTPR_PTP_DIV32		/* setting for 1 bank	*/
-
-/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit		*/
-#define CONFIG_SYS_MPTPR_2BK_8K	MPTPR_PTP_DIV8		/* setting for 2 banks	*/
-#define CONFIG_SYS_MPTPR_1BK_8K	MPTPR_PTP_DIV16		/* setting for 1 bank	*/
-
-/*
- * MAMR settings for SDRAM
- */
-/* periodic timer for refresh */
-#define CONFIG_SYS_MAMR_PTA	97		/* start with divider for 100 MHz	*/
-
-/* 8 column SDRAM */
-#define CONFIG_SYS_MAMR_8COL \
-			((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE      |	\
-			 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 |	\
-			 MAMR_RLFA_1X    | MAMR_WLFA_1X    | MAMR_TLFA_4X)
-
-/*
- * JFFS2 partitions
- *
- */
-/* No command line, one static partition, whole device */
-#undef CONFIG_CMD_MTDPARTS
-#define CONFIG_JFFS2_DEV		"nor0"
-#define CONFIG_JFFS2_PART_SIZE		0xFFFFFFFF
-#define CONFIG_JFFS2_PART_OFFSET	0x00000000
-
-/* mtdparts command line support */
-/*
-#define CONFIG_CMD_MTDPARTS
-#define MTDIDS_DEFAULT		""
-#define MTDPARTS_DEFAULT	""
-*/
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/SCM.h b/include/configs/SCM.h
deleted file mode 100644
index 87d52ba..0000000
--- a/include/configs/SCM.h
+++ /dev/null
@@ -1,710 +0,0 @@ 
-/*
- * (C) Copyright 2001
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_MPC8260		1	/* This is a MPC8260 CPU		*/
-#define CONFIG_TQM8260		200	/* ...on a TQM8260 module Rev.200	*/
-#define CONFIG_SCM              1	/* ...on a System Controller Module	*/
-#define CONFIG_CPM2		1	/* Has a CPM2 */
-
-#define	CONFIG_SYS_TEXT_BASE	0x40000000
-
-#if (CONFIG_TQM8260 <= 100)
-#  error "TQM8260 module revison not supported"
-#endif
-
-/* We use a TQM8260 module with a 300MHz CPU */
-#define CONFIG_300MHz
-
-/* Define 60x busmode only if your TQM8260 has L2 cache! */
-#ifdef CONFIG_L2_CACHE
-#  define CONFIG_BUSMODE_60x	1	/* bus mode: 60x			*/
-#else
-#  undef  CONFIG_BUSMODE_60x		/* bus mode: 8260			*/
-#endif
-
-/* The board with 300MHz CPU doesn't have L2 cache, but works in 60x bus mode */
-#ifdef CONFIG_300MHz
-#  define CONFIG_BUSMODE_60x
-#endif
-
-#define CONFIG_82xx_CONS_SMC1	1	/* console on SMC1			*/
-
-#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
-
-#define	CONFIG_CLOCKS_IN_MHZ	1	/* clocks passsed to Linux in MHz */
-
-#define CONFIG_PREBOOT	"echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo"
-
-#undef	CONFIG_BOOTARGS
-#define CONFIG_BOOTCOMMAND							\
-	"bootp; "								\
-	"setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} "	\
-	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; "	\
-	"bootm"
-
-/* enable I2C and select the hardware/software driver */
-#undef  CONFIG_HARD_I2C			/* I2C with hardware support	*/
-#define CONFIG_SOFT_I2C		1	/* I2C bit-banged		*/
-#define CONFIG_SYS_I2C_SPEED		400000	/* I2C speed and slave address	*/
-#define CONFIG_SYS_I2C_SLAVE		0x7F
-
-/*
- * Software (bit-bang) I2C driver configuration
- */
-
-#define I2C_PORT	3		/* Port A=0, B=1, C=2, D=3 */
-#define I2C_ACTIVE	(iop->pdir |=  0x00010000)
-#define I2C_TRISTATE	(iop->pdir &= ~0x00010000)
-#define I2C_READ	((iop->pdat & 0x00010000) != 0)
-#define I2C_SDA(bit)	if(bit) iop->pdat |=  0x00010000; \
-			else    iop->pdat &= ~0x00010000
-#define I2C_SCL(bit)	if(bit) iop->pdat |=  0x00020000; \
-			else    iop->pdat &= ~0x00020000
-#define I2C_DELAY	udelay(5)	/* 1/4 I2C clock duration */
-
-#define CONFIG_SYS_I2C_EEPROM_ADDR	0x50
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	4
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10	/* and takes up to 10 msec */
-
-#define CONFIG_I2C_X
-
-/*
- * select serial console configuration
- *
- * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
- * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
- * for SCC).
- *
- * if CONFIG_CONS_NONE is defined, then the serial console routines must
- * defined elsewhere (for example, on the cogent platform, there are serial
- * ports on the motherboard which are used for the serial console - see
- * cogent/cma101/serial.[ch]).
- */
-#define CONFIG_CONS_ON_SMC		/* define if console on SMC */
-#undef  CONFIG_CONS_ON_SCC		/* define if console on SCC */
-#undef  CONFIG_CONS_NONE		/* define if console on something else*/
-#ifdef CONFIG_82xx_CONS_SMC1
-#define CONFIG_CONS_INDEX	1	/* which serial channel for console */
-#endif
-#ifdef CONFIG_82xx_CONS_SMC2
-#define CONFIG_CONS_INDEX	2	/* which serial channel for console */
-#endif
-
-#undef  CONFIG_CONS_USE_EXTC		/* SMC/SCC use ext clock not brg_clk */
-#define CONFIG_CONS_EXTC_RATE	3686400	/* SMC/SCC ext clk rate in Hz */
-#define CONFIG_CONS_EXTC_PINSEL	0	/* pin select 0=CLK3/CLK9 */
-
-/*
- * select ethernet configuration
- *
- * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
- * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
- * for FCC)
- *
- * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
- * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
- *
- * (On TQM8260 either SCC1 or FCC2 may be chosen: SCC1 is hardwired to the
- * X.29 connector, and FCC2 is hardwired to the X.1 connector)
- */
-#undef	CONFIG_ETHER_ON_SCC		/* define if ether on SCC       */
-#define	CONFIG_ETHER_ON_FCC		/* define if ether on FCC       */
-#undef	CONFIG_ETHER_NONE		/* define if ether on something else */
-#define	CONFIG_ETHER_INDEX    1		/* which SCC/FCC channel for ethernet */
-
-#if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 1)
-
-/*
- * - Rx-CLK is CLK12
- * - Tx-CLK is CLK11
- * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
- * - Enable Full Duplex in FSMR
- */
-# define CONFIG_SYS_CMXFCR_MASK1	(CMXFCR_FC1|CMXFCR_RF1CS_MSK|CMXFCR_TF1CS_MSK)
-# define CONFIG_SYS_CMXFCR_VALUE1	(CMXFCR_RF1CS_CLK12|CMXFCR_TF1CS_CLK11)
-# define CONFIG_SYS_CPMFCR_RAMTYPE	0
-# define CONFIG_SYS_FCC_PSMR		(FCC_PSMR_FDE|FCC_PSMR_LPB)
-
-#elif defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 3)
-
-/*
- * - Rx-CLK is CLK15
- * - Tx-CLK is CLK16
- * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
- * - Enable Full Duplex in FSMR
- */
-# define CONFIG_SYS_CMXFCR_MASK3	(CMXFCR_FC3|CMXFCR_RF3CS_MSK|CMXFCR_TF3CS_MSK)
-# define CONFIG_SYS_CMXFCR_VALUE3	(CMXFCR_RF3CS_CLK15|CMXFCR_TF3CS_CLK16)
-# define CONFIG_SYS_CPMFCR_RAMTYPE	0
-# define CONFIG_SYS_FCC_PSMR		(FCC_PSMR_FDE|FCC_PSMR_LPB)
-
-#endif /* CONFIG_ETHER_ON_FCC, CONFIG_ETHER_INDEX */
-
-
-/* system clock rate (CLKIN) - equal to the 60x and local bus speed */
-#ifndef CONFIG_300MHz
-#define CONFIG_8260_CLKIN	66666666	/* in Hz */
-#else
-#define CONFIG_8260_CLKIN	83333000	/* in Hz */
-#endif
-
-#if defined(CONFIG_CONS_NONE) || defined(CONFIG_CONS_USE_EXTC)
-#define CONFIG_BAUDRATE		230400
-#else
-#define CONFIG_BAUDRATE		115200
-#endif
-
-#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
-#undef	CONFIG_SYS_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
-
-#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_SUBNETMASK
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_BOOTFILESIZE
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_BSP
-
-
-/*
- * Miscellaneous configurable options
- */
-#define	CONFIG_SYS_LONGHELP			/* undef to save memory		*/
-#define	CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt	*/
-#if defined(CONFIG_CMD_KGDB)
-#define	CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
-#else
-#define	CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
-#endif
-#define	CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define	CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
-#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
-
-#define CONFIG_SYS_MEMTEST_START 0x0400000	/* memtest works on		*/
-#define CONFIG_SYS_MEMTEST_END	0x0C00000	/* 4 ... 12 MB in DRAM		*/
-
-#define	CONFIG_SYS_LOAD_ADDR	0x100000	/* default load address		*/
-
-#define	CONFIG_SYS_HZ		1000		/* decrementer freq: 1 ms ticks	*/
-
-#define	CONFIG_SYS_RESET_ADDRESS 0xFFFFFFFC	/* "bad" address		*/
-
-#define CONFIG_MISC_INIT_R		/* have misc_init_r() function	*/
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ        (8 << 20)       /* Initial Memory map for Linux */
-
-
-/* What should the base address of the main FLASH be and how big is
- * it (in MBytes)? This must contain CONFIG_SYS_TEXT_BASE from board/tqm8260/config.mk
- * The main FLASH is whichever is connected to *CS0.
- */
-#define CONFIG_SYS_FLASH0_BASE 0x40000000
-#define CONFIG_SYS_FLASH1_BASE 0x60000000
-#define CONFIG_SYS_FLASH0_SIZE 32
-#define CONFIG_SYS_FLASH1_SIZE 32
-
-/* Flash bank size (for preliminary settings)
- */
-#define CONFIG_SYS_FLASH_SIZE CONFIG_SYS_FLASH0_SIZE
-
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max num of memory banks      */
-#define CONFIG_SYS_MAX_FLASH_SECT	128	/* max num of sects on one chip */
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT	240000	/* Flash Erase Timeout (in ms)  */
-#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (in ms)  */
-
-#if 0
-/* Start port with environment in flash; switch to EEPROM later */
-#define CONFIG_ENV_IS_IN_FLASH	1
-#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE+0x40000)
-#define CONFIG_ENV_SIZE		0x40000
-#define CONFIG_ENV_SECT_SIZE	0x40000
-#else
-/* Final version: environment in EEPROM */
-#define CONFIG_ENV_IS_IN_EEPROM	1
-#define CONFIG_ENV_OFFSET		0
-#define CONFIG_ENV_SIZE		2048
-#endif
-
-/*-----------------------------------------------------------------------
- * Hardware Information Block
- */
-#define CONFIG_SYS_HWINFO_OFFSET	0x0003FFC0	/* offset of HW Info block */
-#define CONFIG_SYS_HWINFO_SIZE		0x00000040	/* size   of HW Info block */
-#define CONFIG_SYS_HWINFO_MAGIC	0x54514D38	/* 'TQM8' */
-
-/*-----------------------------------------------------------------------
- * Hard Reset Configuration Words
- *
- * if you change bits in the HRCW, you must also change the CONFIG_SYS_*
- * defines for the various registers affected by the HRCW e.g. changing
- * HRCW_DPPCxx requires you to also change CONFIG_SYS_SIUMCR.
- */
-#if defined(CONFIG_266MHz)
-#define CONFIG_SYS_HRCW_MASTER		(HRCW_CIP | HRCW_ISB111 | HRCW_BMS | \
-							      HRCW_MODCK_H0111)
-#elif defined(CONFIG_300MHz)
-#define CONFIG_SYS_HRCW_MASTER		(HRCW_CIP | HRCW_ISB111 | HRCW_BMS | \
-							      HRCW_MODCK_H0110)
-#else
-#define CONFIG_SYS_HRCW_MASTER		(HRCW_CIP | HRCW_ISB111 | HRCW_BMS)
-#endif
-
-/* no slaves so just fill with zeros */
-#define CONFIG_SYS_HRCW_SLAVE1		0
-#define CONFIG_SYS_HRCW_SLAVE2		0
-#define CONFIG_SYS_HRCW_SLAVE3		0
-#define CONFIG_SYS_HRCW_SLAVE4		0
-#define CONFIG_SYS_HRCW_SLAVE5		0
-#define CONFIG_SYS_HRCW_SLAVE6		0
-#define CONFIG_SYS_HRCW_SLAVE7		0
-
-/*-----------------------------------------------------------------------
- * Internal Memory Mapped Register
- */
-#define CONFIG_SYS_IMMR		0xFFF00000
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in DPRAM)
- */
-#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_SIZE	0x4000  /* Size of used area in DPRAM    */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- *
- * 60x SDRAM is mapped at CONFIG_SYS_SDRAM_BASE, local SDRAM
- * is mapped at SDRAM_BASE2_PRELIM.
- */
-#define CONFIG_SYS_SDRAM_BASE		0x00000000
-#define CONFIG_SYS_FLASH_BASE		CONFIG_SYS_FLASH0_BASE
-#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor */
-#define CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()*/
-
-/*-----------------------------------------------------------------------
- * Hardware Information Block
- */
-#define CONFIG_SYS_HWINFO_OFFSET	0x0003FFC0	/* offset of HW Info block */
-#define CONFIG_SYS_HWINFO_SIZE		0x00000040	/* size   of HW Info block */
-#define CONFIG_SYS_HWINFO_MAGIC	0x54514D38	/* 'TQM8' */
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CONFIG_SYS_CACHELINE_SIZE      32      /* For MPC8260 CPU              */
-#if defined(CONFIG_CMD_KGDB)
-# define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value */
-#endif
-
-/*-----------------------------------------------------------------------
- * HIDx - Hardware Implementation-dependent Registers                    2-11
- *-----------------------------------------------------------------------
- * HID0 also contains cache control - initially enable both caches and
- * invalidate contents, then the final state leaves only the instruction
- * cache enabled. Note that Power-On and Hard reset invalidate the caches,
- * but Soft reset does not.
- *
- * HID1 has only read-only information - nothing to set.
- */
-#define CONFIG_SYS_HID0_INIT   (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|\
-				HID0_IFEM|HID0_ABE)
-#define CONFIG_SYS_HID0_FINAL  (HID0_IFEM|HID0_ABE)
-#define CONFIG_SYS_HID2        0
-
-/*-----------------------------------------------------------------------
- * RMR - Reset Mode Register                                     5-5
- *-----------------------------------------------------------------------
- * turn on Checkstop Reset Enable
- */
-#define CONFIG_SYS_RMR         RMR_CSRE
-
-/*-----------------------------------------------------------------------
- * BCR - Bus Configuration                                       4-25
- *-----------------------------------------------------------------------
- */
-#ifdef	CONFIG_BUSMODE_60x
-#define CONFIG_SYS_BCR         (BCR_EBM|BCR_L2C|BCR_LETM|\
-			 BCR_NPQM0|BCR_NPQM1|BCR_NPQM2)	/* 60x mode  */
-#else
-#define BCR_APD01	0x10000000
-#define CONFIG_SYS_BCR		(BCR_APD01|BCR_ETM|BCR_LETM)	/* 8260 mode */
-#endif
-
-/*-----------------------------------------------------------------------
- * SIUMCR - SIU Module Configuration                             4-31
- *-----------------------------------------------------------------------
- */
-#if 0
-#define CONFIG_SYS_SIUMCR      (SIUMCR_DPPC10|SIUMCR_APPC10)
-#else
-#define CONFIG_SYS_SIUMCR      (SIUMCR_DPPC00|SIUMCR_APPC10)
-#endif
-
-
-/*-----------------------------------------------------------------------
- * SYPCR - System Protection Control                             4-35
- * SYPCR can only be written once after reset!
- *-----------------------------------------------------------------------
- * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
- */
-#if defined(CONFIG_WATCHDOG)
-#define CONFIG_SYS_SYPCR       (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
-			 SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
-#else
-#define CONFIG_SYS_SYPCR       (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
-			 SYPCR_SWRI|SYPCR_SWP)
-#endif /* CONFIG_WATCHDOG */
-
-/*-----------------------------------------------------------------------
- * TMCNTSC - Time Counter Status and Control                     4-40
- *-----------------------------------------------------------------------
- * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
- * and enable Time Counter
- */
-#define CONFIG_SYS_TMCNTSC     (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
-
-/*-----------------------------------------------------------------------
- * PISCR - Periodic Interrupt Status and Control                 4-42
- *-----------------------------------------------------------------------
- * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
- * Periodic timer
- */
-#define CONFIG_SYS_PISCR       (PISCR_PS|PISCR_PTF|PISCR_PTE)
-
-/*-----------------------------------------------------------------------
- * SCCR - System Clock Control                                   9-8
- *-----------------------------------------------------------------------
- * Ensure DFBRG is Divide by 16
- */
-#define CONFIG_SYS_SCCR        0
-
-/*-----------------------------------------------------------------------
- * RCCR - RISC Controller Configuration                         13-7
- *-----------------------------------------------------------------------
- */
-#define CONFIG_SYS_RCCR        0
-
-/*
- * Init Memory Controller:
- *
- * Bank Bus     Machine PortSz  Device
- * ---- ---     ------- ------  ------
- *  0   60x     GPCM    64 bit  FLASH
- *  1   60x     SDRAM   64 bit  SDRAM
- *  2   Local   SDRAM   32 bit  SDRAM
- *
- */
-
-	/* Initialize SDRAM on local bus
-	 */
-#define CONFIG_SYS_INIT_LOCAL_SDRAM
-
-#define SDRAM_MAX_SIZE	0x08000000	/* max. 128 MB		*/
-
-/* Minimum mask to separate preliminary
- * address ranges for CS[0:2]
- */
-#define CONFIG_SYS_GLOBAL_SDRAM_LIMIT	(512<<20)	/* less than 512 MB */
-#define CONFIG_SYS_LOCAL_SDRAM_LIMIT	(128<<20)	/* less than 128 MB */
-
-#define CONFIG_SYS_MPTPR       0x4000
-
-/*-----------------------------------------------------------------------------
- * Address for Mode Register Set (MRS) command
- *-----------------------------------------------------------------------------
- * In fact, the address is rather configuration data presented to the SDRAM on
- * its address lines. Because the address lines may be mux'ed externally either
- * for 8 column or 9 column devices, some bits appear twice in the 8260's
- * address:
- *
- * |   (RFU)   |   (RFU)   | WBL |    TM    |     CL    |  BT | Burst Length |
- * | BA1   BA0 | A12 : A10 |  A9 |  A8   A7 |  A6 : A4  |  A3 |   A2 :  A0   |
- *  8 columns mux'ing:     |  A9 | A10  A21 | A22 : A24 | A25 |  A26 : A28   |
- *  9 columns mux'ing:     |  A8 | A20  A21 | A22 : A24 | A25 |  A26 : A28   |
- *  Settings:              |  0  |  0    0  |  0  1  0  |  0  |   0  1  0    |
- *-----------------------------------------------------------------------------
- */
-#define CONFIG_SYS_MRS_OFFS	0x00000110
-
-
-/* Bank 0 - FLASH
- */
-#define CONFIG_SYS_BR0_PRELIM  ((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK)  |\
-			 BRx_PS_64                      |\
-			 BRx_MS_GPCM_P                  |\
-			 BRx_V)
-
-#define CONFIG_SYS_OR0_PRELIM  (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE)      |\
-			 ORxG_CSNT                      |\
-			 ORxG_ACS_DIV1                  |\
-			 ORxG_SCY_3_CLK                 |\
-			 ORxG_EHTR                      |\
-			 ORxG_TRLX)
-
-	/* SDRAM on TQM8260 can have either 8 or 9 columns.
-	 * The number affects configuration values.
-	 */
-
-/* Bank 1 - 60x bus SDRAM
- */
-#define CONFIG_SYS_PSRT        0x20
-#define CONFIG_SYS_LSRT        0x20
-#ifndef CONFIG_SYS_RAMBOOT
-#define CONFIG_SYS_BR1_PRELIM  ((CONFIG_SYS_SDRAM_BASE & BRx_BA_MSK)  |\
-			 BRx_PS_64                      |\
-			 BRx_MS_SDRAM_P                 |\
-			 BRx_V)
-
-#define CONFIG_SYS_OR1_PRELIM	CONFIG_SYS_OR1_8COL
-
-
-	/* SDRAM initialization values for 8-column chips
-	 */
-#define CONFIG_SYS_OR1_8COL    ((~(CONFIG_SYS_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
-			 ORxS_BPD_4                     |\
-			 ORxS_ROWST_PBI1_A7             |\
-			 ORxS_NUMR_12)
-
-#define CONFIG_SYS_PSDMR_8COL  (PSDMR_PBI                      |\
-			 PSDMR_SDAM_A15_IS_A5           |\
-			 PSDMR_BSMA_A12_A14             |\
-			 PSDMR_SDA10_PBI1_A8            |\
-			 PSDMR_RFRC_7_CLK               |\
-			 PSDMR_PRETOACT_2W              |\
-			 PSDMR_ACTTORW_2W               |\
-			 PSDMR_LDOTOPRE_1C              |\
-			 PSDMR_WRC_2C                   |\
-			 PSDMR_EAMUX                    |\
-			 PSDMR_CL_2)
-
-	/* SDRAM initialization values for 9-column chips
-	 */
-#define CONFIG_SYS_OR1_9COL    ((~(CONFIG_SYS_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
-			 ORxS_BPD_4                     |\
-			 ORxS_ROWST_PBI1_A5             |\
-			 ORxS_NUMR_13)
-
-#define CONFIG_SYS_PSDMR_9COL  (PSDMR_PBI                      |\
-			 PSDMR_SDAM_A16_IS_A5           |\
-			 PSDMR_BSMA_A12_A14             |\
-			 PSDMR_SDA10_PBI1_A7            |\
-			 PSDMR_RFRC_7_CLK               |\
-			 PSDMR_PRETOACT_2W              |\
-			 PSDMR_ACTTORW_2W               |\
-			 PSDMR_LDOTOPRE_1C              |\
-			 PSDMR_WRC_2C                   |\
-			 PSDMR_EAMUX                    |\
-			 PSDMR_CL_2)
-
-/* Bank 2 - Local bus SDRAM
- */
-#ifdef CONFIG_SYS_INIT_LOCAL_SDRAM
-#define CONFIG_SYS_BR2_PRELIM  ((SDRAM_BASE2_PRELIM & BRx_BA_MSK) |\
-			 BRx_PS_32                      |\
-			 BRx_MS_SDRAM_L                 |\
-			 BRx_V)
-
-#define CONFIG_SYS_OR2_PRELIM	CONFIG_SYS_OR2_8COL
-
-#define SDRAM_BASE2_PRELIM	0x80000000
-
-	/* SDRAM initialization values for 8-column chips
-	 */
-#define CONFIG_SYS_OR2_8COL    ((~(CONFIG_SYS_LOCAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
-			 ORxS_BPD_4                     |\
-			 ORxS_ROWST_PBI1_A8             |\
-			 ORxS_NUMR_12)
-
-#define CONFIG_SYS_LSDMR_8COL  (PSDMR_PBI                      |\
-			 PSDMR_SDAM_A15_IS_A5           |\
-			 PSDMR_BSMA_A13_A15             |\
-			 PSDMR_SDA10_PBI1_A9            |\
-			 PSDMR_RFRC_7_CLK               |\
-			 PSDMR_PRETOACT_2W              |\
-			 PSDMR_ACTTORW_2W               |\
-			 PSDMR_BL                       |\
-			 PSDMR_LDOTOPRE_1C              |\
-			 PSDMR_WRC_2C                   |\
-			 PSDMR_CL_2)
-
-	/* SDRAM initialization values for 9-column chips
-	 */
-#define CONFIG_SYS_OR2_9COL    ((~(CONFIG_SYS_LOCAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
-			 ORxS_BPD_4                     |\
-			 ORxS_ROWST_PBI1_A6             |\
-			 ORxS_NUMR_13)
-
-#define CONFIG_SYS_LSDMR_9COL  (PSDMR_PBI                      |\
-			 PSDMR_SDAM_A16_IS_A5           |\
-			 PSDMR_BSMA_A13_A15             |\
-			 PSDMR_SDA10_PBI1_A8            |\
-			 PSDMR_RFRC_7_CLK               |\
-			 PSDMR_PRETOACT_2W              |\
-			 PSDMR_ACTTORW_2W               |\
-			 PSDMR_BL                       |\
-			 PSDMR_LDOTOPRE_1C              |\
-			 PSDMR_WRC_2C                   |\
-			 PSDMR_CL_2)
-
-#endif /* CONFIG_SYS_INIT_LOCAL_SDRAM */
-
-#endif /* CONFIG_SYS_RAMBOOT */
-
-#define CONFIG_SYS_CAN0_BASE		0xc0000000
-#define CONFIG_SYS_CAN1_BASE		0xc0008000
-#define CONFIG_SYS_FIOX_BASE		0xc0010000
-#define CONFIG_SYS_FDOHM_BASE		0xc0018000
-#define CONFIG_SYS_EXTPROM_BASE	0xc2000000
-
-#define CONFIG_SYS_CAN_SIZE		0x00000100
-#define CONFIG_SYS_FIOX_SIZE		0x00000020
-#define CONFIG_SYS_FDOHM_SIZE		0x00002000
-#define CONFIG_SYS_EXTPROM_BANK_SIZE	0x01000000
-
-#define EXT_EEPROM_MAX_FLASH_BANKS	0x02
-
-/* CS3 - CAN 0
- */
-#define CONFIG_SYS_CAN0_BR3   ((CONFIG_SYS_CAN0_BASE & BRx_BA_MSK)	|\
-			BRx_PS_8			|\
-			BRx_MS_UPMA			|\
-			BRx_V)
-
-#define CONFIG_SYS_CAN0_OR3   (P2SZ_TO_AM(CONFIG_SYS_CAN_SIZE)	|\
-			ORxU_BI				|\
-			ORxU_EHTR_4IDLE)
-
-/* CS4 - CAN 1
- */
-#define CONFIG_SYS_CAN1_BR4   ((CONFIG_SYS_CAN1_BASE & BRx_BA_MSK)	|\
-			BRx_PS_8			|\
-			BRx_MS_UPMA			|\
-			BRx_V)
-
-#define CONFIG_SYS_CAN1_OR4   (P2SZ_TO_AM(CONFIG_SYS_CAN_SIZE)	|\
-			ORxU_BI				|\
-			ORxU_EHTR_4IDLE)
-
-/* CS5 - Extended PROM (16MB optional)
- */
-#define CONFIG_SYS_EXTPROM_BR5 ((CONFIG_SYS_EXTPROM_BASE & BRx_BA_MSK)|\
-			BRx_PS_32			|\
-			BRx_MS_GPCM_P			|\
-			BRx_V)
-
-#define CONFIG_SYS_EXTPROM_OR5 (P2SZ_TO_AM(CONFIG_SYS_EXTPROM_BANK_SIZE)|\
-			ORxG_CSNT			|\
-			ORxG_ACS_DIV4			|\
-			ORxG_SCY_5_CLK			|\
-			ORxG_TRLX)
-
-/* CS6 - Extended PROM (16MB optional)
- */
-#define CONFIG_SYS_EXTPROM_BR6 (((CONFIG_SYS_EXTPROM_BASE + \
-			CONFIG_SYS_EXTPROM_BANK_SIZE) & BRx_BA_MSK)|\
-			BRx_PS_32			|\
-			BRx_MS_GPCM_P			|\
-			BRx_V)
-
-#define CONFIG_SYS_EXTPROM_OR6 (P2SZ_TO_AM(CONFIG_SYS_EXTPROM_BANK_SIZE)|\
-			ORxG_CSNT			|\
-			ORxG_ACS_DIV4			|\
-			ORxG_SCY_5_CLK			|\
-			ORxG_TRLX)
-
-/* CS7 - FPGA FIOX: Glue Logic
- */
-#define CONFIG_SYS_FIOX_BR7   ((CONFIG_SYS_FIOX_BASE & BRx_BA_MSK)	|\
-			BRx_PS_32			|\
-			BRx_MS_GPCM_P			|\
-			BRx_V)
-
-#define CONFIG_SYS_FIOX_OR7   (P2SZ_TO_AM(CONFIG_SYS_FIOX_SIZE)	|\
-			ORxG_ACS_DIV4			|\
-			ORxG_SCY_5_CLK			|\
-			ORxG_TRLX)
-
-/* CS8 - FPGA DOH Master
- */
-#define CONFIG_SYS_FDOHM_BR8  ((CONFIG_SYS_FDOHM_BASE & BRx_BA_MSK)	|\
-			BRx_PS_16			|\
-			BRx_MS_GPCM_P			|\
-			BRx_V)
-
-#define CONFIG_SYS_FDOHM_OR8  (P2SZ_TO_AM(CONFIG_SYS_FDOHM_SIZE)	|\
-			ORxG_ACS_DIV4			|\
-			ORxG_SCY_5_CLK			|\
-			ORxG_TRLX)
-
-
-/* FPGA configuration */
-#define CONFIG_SYS_PD_FIOX_PROG	(1 << (31- 5))	/* PD  5 */
-#define CONFIG_SYS_PD_FIOX_DONE	(1 << (31-28))	/* PD 28 */
-#define CONFIG_SYS_PD_FIOX_INIT	(1 << (31-29))	/* PD 29 */
-
-#define CONFIG_SYS_PD_FDOHM_PROG	(1 << (31- 4))	/* PD  4 */
-#define CONFIG_SYS_PD_FDOHM_DONE	(1 << (31-26))	/* PD 26 */
-#define CONFIG_SYS_PD_FDOHM_INIT	(1 << (31-27))	/* PD 27 */
-
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/c2mon.h b/include/configs/c2mon.h
deleted file mode 100644
index 41ff008..0000000
--- a/include/configs/c2mon.h
+++ /dev/null
@@ -1,417 +0,0 @@ 
-/*
- * (C) Copyright 2001-2005
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_MPC855		1	/* This is a MPC855 CPU		*/
-#define CONFIG_C2MON		1	/* ...on a C2MON module		*/
-
-#define	CONFIG_SYS_TEXT_BASE	0x40000000
-
-#define CONFIG_80MHz		1	/* Running at 5 * 16 = 80 MHz	*/
-
-#define	CONFIG_8xx_CONS_SMC1	1	/* Console is on SMC1		*/
-#undef	CONFIG_8xx_CONS_SMC2
-#undef	CONFIG_8xx_CONS_NONE
-#define CONFIG_BAUDRATE		115200	/* console baudrate = 115kbps	*/
-#if 0
-#define CONFIG_BOOTDELAY	-1	/* autoboot disabled		*/
-#else
-#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
-#endif
-
-#define	CONFIG_CLOCKS_IN_MHZ	1	/* clocks passsed to Linux in MHz */
-
-#define CONFIG_PREBOOT	"echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo"
-
-#undef	CONFIG_BOOTARGS
-#define CONFIG_BOOTCOMMAND							\
-	"bootp; "								\
-	"setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} "	\
-	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; "	\
-	"bootm"
-
-#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
-#undef	CONFIG_SYS_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
-
-#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
-
-#undef	CONFIG_STATUS_LED		/* Status LED disabled		*/
-
-#undef	CONFIG_CAN_DRIVER		/* CAN Driver support disabled	*/
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_SUBNETMASK
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_BOOTFILESIZE
-
-
-#define CONFIG_MAC_PARTITION
-#define CONFIG_DOS_PARTITION
-
-#define CONFIG_FEC_ENET		1	/* Use Fast Ethernet Controller	*/
-
-#define	CONFIG_RTC_MPC8xx		/* use internal RTC of MPC8xx	*/
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_DATE
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_IDE
-#define CONFIG_CMD_NFS
-#define CONFIG_CMD_SNTP
-
-
-/*
- * Miscellaneous configurable options
- */
-#define	CONFIG_SYS_LONGHELP			/* undef to save memory		*/
-#define	CONFIG_SYS_PROMPT		"=> "	/* Monitor Command Prompt	*/
-
-#undef	CONFIG_SYS_HUSH_PARSER			/* use "hush" command parser	*/
-
-#if defined(CONFIG_CMD_KGDB)
-#define	CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size	*/
-#else
-#define	CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size	*/
-#endif
-#define	CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define	CONFIG_SYS_MAXARGS		16	/* max number of command args	*/
-#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
-
-#define CONFIG_SYS_MEMTEST_START	0x0400000	/* memtest works on	*/
-#define CONFIG_SYS_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
-
-#define	CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address	*/
-
-#define	CONFIG_SYS_HZ			1000	/* decrementer freq: 1 ms ticks	*/
-
-/*
- * Low Level Configuration Settings
- * (address mappings, register initial values, etc.)
- * You should know what you are doing if you make changes here.
- */
-/*-----------------------------------------------------------------------
- * Internal Memory Mapped Register
- */
-#define CONFIG_SYS_IMMR		0xFFF00000
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in DPRAM)
- */
-#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
-#define	CONFIG_SYS_INIT_RAM_SIZE	0x2F00	/* Size of used area in DPRAM	*/
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define	CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- */
-#define	CONFIG_SYS_SDRAM_BASE		0x00000000
-#define CONFIG_SYS_FLASH_BASE		0x40000000
-#if defined(DEBUG)
-#define	CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
-#else
-#define	CONFIG_SYS_MONITOR_LEN		(192 << 10)	/* Reserve 192 kB for Monitor	*/
-#endif
-#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
-#define	CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define	CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
-
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max number of memory banks		*/
-#define CONFIG_SYS_MAX_FLASH_SECT	67	/* max number of sectors on one chip	*/
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
-
-#define	CONFIG_ENV_IS_IN_FLASH	1
-#define	CONFIG_ENV_OFFSET		0x8000	/*   Offset   of Environment Sector	*/
-#define	CONFIG_ENV_SIZE		0x4000	/* Total Size of Environment Sector	*/
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CONFIG_SYS_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
-#endif
-
-/*-----------------------------------------------------------------------
- * SYPCR - System Protection Control				11-9
- * SYPCR can only be written once after reset!
- *-----------------------------------------------------------------------
- * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
- */
-#if defined(CONFIG_WATCHDOG)
-#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
-			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
-#else
-#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
-#endif
-
-/*-----------------------------------------------------------------------
- * SIUMCR - SIU Module Configuration				11-6
- *-----------------------------------------------------------------------
- * PCMCIA config., multi-function pin tri-state
- */
-#ifndef	CONFIG_CAN_DRIVER
-#define CONFIG_SYS_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
-#else	/* we must activate GPL5 in the SIUMCR for CAN */
-#define CONFIG_SYS_SIUMCR	(SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
-#endif	/* CONFIG_CAN_DRIVER */
-
-/*-----------------------------------------------------------------------
- * TBSCR - Time Base Status and Control				11-26
- *-----------------------------------------------------------------------
- * Clear Reference Interrupt Status, Timebase freezing enabled
- */
-#define CONFIG_SYS_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
-
-/*-----------------------------------------------------------------------
- * RTCSC - Real-Time Clock Status and Control Register		11-27
- *-----------------------------------------------------------------------
- */
-#define CONFIG_SYS_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
-
-/*-----------------------------------------------------------------------
- * PISCR - Periodic Interrupt Status and Control		11-31
- *-----------------------------------------------------------------------
- * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
- */
-#define CONFIG_SYS_PISCR	(PISCR_PS | PISCR_PITF)
-
-/*-----------------------------------------------------------------------
- * PLPRCR - PLL, Low-Power, and Reset Control Register		15-30
- *-----------------------------------------------------------------------
- * Reset PLL lock status sticky bit, timer expired status bit and timer
- * interrupt status bit
- *
- * If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)!
- */
-#ifdef	CONFIG_80MHz	/* for 80 MHz, we use a 16 MHz clock * 5 */
-#define CONFIG_SYS_PLPRCR							\
-		( (5-1)<<PLPRCR_MF_SHIFT | PLPRCR_TEXPS | PLPRCR_TMIST )
-#else			/* up to 50 MHz we use a 1:1 clock */
-#define CONFIG_SYS_PLPRCR	(PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
-#endif	/* CONFIG_80MHz */
-
-/*-----------------------------------------------------------------------
- * SCCR - System Clock and reset Control Register		15-27
- *-----------------------------------------------------------------------
- * Set clock output, timebase and RTC source and divider,
- * power management and some other internal clocks
- */
-#define SCCR_MASK	SCCR_EBDF11
-#ifdef	CONFIG_80MHz	/* for 80 MHz, we use a 16 MHz clock * 5 */
-#define CONFIG_SYS_SCCR	(/* SCCR_TBS  | */ \
-			 SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
-			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
-			 SCCR_DFALCD00)
-#else			/* up to 50 MHz we use a 1:1 clock */
-#define CONFIG_SYS_SCCR	(SCCR_TBS     | \
-			 SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
-			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
-			 SCCR_DFALCD00)
-#endif	/* CONFIG_80MHz */
-
-/*-----------------------------------------------------------------------
- * PCMCIA stuff
- *-----------------------------------------------------------------------
- *
- */
-#define CONFIG_SYS_PCMCIA_MEM_ADDR	(0xE0000000)
-#define CONFIG_SYS_PCMCIA_MEM_SIZE	( 64 << 20 )
-#define CONFIG_SYS_PCMCIA_DMA_ADDR	(0xE4000000)
-#define CONFIG_SYS_PCMCIA_DMA_SIZE	( 64 << 20 )
-#define CONFIG_SYS_PCMCIA_ATTRB_ADDR	(0xE8000000)
-#define CONFIG_SYS_PCMCIA_ATTRB_SIZE	( 64 << 20 )
-#define CONFIG_SYS_PCMCIA_IO_ADDR	(0xEC000000)
-#define CONFIG_SYS_PCMCIA_IO_SIZE	( 64 << 20 )
-
-/*-----------------------------------------------------------------------
- * PCMCIA Power Switch
- *
- * The C2MON uses a TPS2211A PC-Card Power-Interface Switch to
- * control the voltages on the PCMCIA slot which is connected
- * to Port C (all outputs) and Port B (Over-Current Input)
- *-----------------------------------------------------------------------
- */
-			/* Output pins */
-#define TPS2211_VCCD0	0x0002		/* PC.14 */
-#define TPS2211_VCCD1	0x0004		/* PC.13 */
-#define TPS2211_VPPD0	0x0008		/* PC.12 */
-#define TPS2211_VPPD1	0x0010		/* PC.11 */
-#define TPS2211_OUTPUTS ( TPS2211_VCCD0 | TPS2211_VCCD1 | \
-			  TPS2211_VPPD0 | TPS2211_VPPD1 )
-
-			/* Input pins */
-#define TPS2211_OC	0x00000200	/* PB.22: Over-Current		*/
-#define TPS2211_INPUTS	( TPS2211_OC )
-
-/*-----------------------------------------------------------------------
- * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
- *-----------------------------------------------------------------------
- */
-
-#define CONFIG_IDE_PREINIT	1	/* Use preinit IDE hook */
-#define	CONFIG_IDE_8xx_PCCARD	1	/* Use IDE with PC Card	Adapter	*/
-
-#undef	CONFIG_IDE_8xx_DIRECT		/* Direct IDE    not supported	*/
-#undef	CONFIG_IDE_LED			/* LED   for ide not supported	*/
-#undef	CONFIG_IDE_RESET		/* reset for ide not supported	*/
-
-#define CONFIG_SYS_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
-#define CONFIG_SYS_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus	*/
-
-#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000
-
-#define CONFIG_SYS_ATA_BASE_ADDR	CONFIG_SYS_PCMCIA_MEM_ADDR
-
-/* Offset for data I/O			*/
-#define CONFIG_SYS_ATA_DATA_OFFSET	(CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
-
-/* Offset for normal register accesses	*/
-#define CONFIG_SYS_ATA_REG_OFFSET	(2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
-
-/* Offset for alternate registers	*/
-#define CONFIG_SYS_ATA_ALT_OFFSET	0x0100
-
-
-/*-----------------------------------------------------------------------
- *
- *-----------------------------------------------------------------------
- *
- */
-#define CONFIG_SYS_DER	0
-
-/*
- * Init Memory Controller:
- *
- * BR0/1 and OR0/1 (FLASH)
- */
-
-#define FLASH_BASE0_PRELIM	0x40000000	/* FLASH bank #0	*/
-#define FLASH_BASE1_PRELIM	0x60000000	/* FLASH bank #0	*/
-
-/* used to re-map FLASH both when starting from SRAM or FLASH:
- * restrict access enough to keep SRAM working (if any)
- * but not too much to meddle with FLASH accesses
- */
-#define CONFIG_SYS_REMAP_OR_AM		0x80000000	/* OR addr mask */
-#define CONFIG_SYS_PRELIM_OR_AM	0xE0000000	/* OR addr mask */
-
-/* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1	*/
-#define CONFIG_SYS_OR_TIMING_FLASH	(OR_CSNT_SAM  | OR_ACS_DIV2 | OR_BI | \
-				 OR_SCY_5_CLK | OR_EHTR)
-
-#define CONFIG_SYS_OR0_REMAP	(CONFIG_SYS_REMAP_OR_AM  | CONFIG_SYS_OR_TIMING_FLASH)
-#define CONFIG_SYS_OR0_PRELIM	(CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
-#define CONFIG_SYS_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
-
-#define CONFIG_SYS_OR1_REMAP	CONFIG_SYS_OR0_REMAP
-#define CONFIG_SYS_OR1_PRELIM	CONFIG_SYS_OR0_PRELIM
-#define CONFIG_SYS_BR1_PRELIM	((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )
-
-/*
- * BR2/3 and OR2/3 (SDRAM)
- *
- */
-#define SDRAM_BASE2_PRELIM	0x00000000	/* SDRAM bank #0	*/
-#define SDRAM_BASE3_PRELIM	0x20000000	/* SDRAM bank #1	*/
-#define	SDRAM_MAX_SIZE		0x04000000	/* max 64 MB per bank	*/
-
-/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)	*/
-#define CONFIG_SYS_OR_TIMING_SDRAM	0x00000A00
-
-#define CONFIG_SYS_OR2_PRELIM	(CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM )
-#define CONFIG_SYS_BR2_PRELIM	((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
-
-#ifndef	CONFIG_CAN_DRIVER
-#define	CONFIG_SYS_OR3_PRELIM	CONFIG_SYS_OR2_PRELIM
-#define CONFIG_SYS_BR3_PRELIM	((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
-#else	/* CAN uses CS3#, so we can have only one SDRAM bank anyway */
-#define	CONFIG_SYS_CAN_BASE		0xC0000000	/* CAN mapped at 0xC0000000	*/
-#define CONFIG_SYS_CAN_OR_AM		0xFFFF8000	/* 32 kB address mask		*/
-#define CONFIG_SYS_OR3_CAN		(CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI)
-#define CONFIG_SYS_BR3_CAN		((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \
-					BR_PS_8 | BR_MS_UPMB | BR_V )
-#endif	/* CONFIG_CAN_DRIVER */
-
-/*
- * Memory Periodic Timer Prescaler
- */
-
-/* periodic timer for refresh */
-#define CONFIG_SYS_MAMR_PTA	97		/* start with divider for 100 MHz	*/
-
-/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit	*/
-#define CONFIG_SYS_MPTPR_2BK_4K	MPTPR_PTP_DIV16		/* setting for 2 banks	*/
-#define CONFIG_SYS_MPTPR_1BK_4K	MPTPR_PTP_DIV32		/* setting for 1 bank	*/
-
-/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit		*/
-#define CONFIG_SYS_MPTPR_2BK_8K	MPTPR_PTP_DIV8		/* setting for 2 banks	*/
-#define CONFIG_SYS_MPTPR_1BK_8K	MPTPR_PTP_DIV16		/* setting for 1 bank	*/
-
-/*
- * MAMR settings for SDRAM
- */
-
-/* 8 column SDRAM */
-#define CONFIG_SYS_MAMR_8COL	((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
-			 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 |	\
-			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
-/* 9 column SDRAM */
-#define CONFIG_SYS_MAMR_9COL	((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
-			 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |	\
-			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
-
-#endif	/* __CONFIG_H */
diff --git a/include/pcmcia.h b/include/pcmcia.h
index ca0bf22..0cc7f3b 100644
--- a/include/pcmcia.h
+++ b/include/pcmcia.h
@@ -58,8 +58,6 @@ 
 # define CONFIG_PCMCIA_SLOT_B
 #elif defined(CONFIG_ICU862)		/* The ICU862 use SLOT_B	*/
 # define CONFIG_PCMCIA_SLOT_B
-#elif defined(CONFIG_C2MON)		/* The C2MON  use SLOT_B	*/
-# define CONFIG_PCMCIA_SLOT_B
 #elif defined(CONFIG_R360MPI)		/* The R360MPI use SLOT_B	*/
 # define CONFIG_PCMCIA_SLOT_B
 #elif defined(CONFIG_ATC)		/* The ATC use SLOT_A	*/
diff --git a/include/status_led.h b/include/status_led.h
index c85c206..da9fae9 100644
--- a/include/status_led.h
+++ b/include/status_led.h
@@ -72,22 +72,6 @@  void status_led_set  (int led, int state);
 
 # define STATUS_LED_BOOT	0		/* LED 0 used for boot status */
 
-/*****  ETX_094  ********************************************************/
-#elif defined(CONFIG_ETX094)
-
-# define STATUS_LED_PAR		im_ioport.iop_pdpar
-# define STATUS_LED_DIR		im_ioport.iop_pddir
-# undef  STATUS_LED_ODR
-# define STATUS_LED_DAT		im_ioport.iop_pddat
-
-# define STATUS_LED_BIT		0x00000001
-# define STATUS_LED_PERIOD	(CONFIG_SYS_HZ / 2)
-# define STATUS_LED_STATE	STATUS_LED_BLINKING
-
-# define STATUS_LED_ACTIVE	0		/* LED on for bit == 0	*/
-
-# define STATUS_LED_BOOT	0		/* LED 0 used for boot status */
-
 /*****  GEN860T  *********************************************************/
 #elif defined(CONFIG_GEN860T)
 
@@ -170,26 +154,6 @@  void status_led_set  (int led, int state);
 # define STATUS_LED_GREEN	1
 # define STATUS_LED_BOOT	2		/* IDE LED used for boot status */
 
-/*****  LANTEC  *********************************************************/
-#elif defined(CONFIG_LANTEC)
-
-# define STATUS_LED_PAR		im_ioport.iop_pdpar
-# define STATUS_LED_DIR		im_ioport.iop_pddir
-# undef  STATUS_LED_ODR
-# define STATUS_LED_DAT		im_ioport.iop_pddat
-
-# if CONFIG_LATEC < 2
-#  define STATUS_LED_BIT	0x1000
-# else
-#  define STATUS_LED_BIT	0x0800
-# endif
-# define STATUS_LED_PERIOD	(CONFIG_SYS_HZ / 2)
-# define STATUS_LED_STATE	STATUS_LED_BLINKING
-
-# define STATUS_LED_ACTIVE	0		/* LED on for bit == 0 */
-
-# define STATUS_LED_BOOT	0		/* LED 0 used for boot status */
-
 /*****  ICU862   ********************************************************/
 #elif defined(CONFIG_ICU862)
 
diff --git a/post/cpu/mpc8xx/ether.c b/post/cpu/mpc8xx/ether.c
index fcbb300..728f7e0 100644
--- a/post/cpu/mpc8xx/ether.c
+++ b/post/cpu/mpc8xx/ether.c
@@ -381,49 +381,6 @@  static void scc_init (int scc_index)
 	immr->im_cpm.cp_scc[scc_index].scc_psmr = SCC_PSMR_ENCRC |
 			SCC_PSMR_NIB22 | SCC_PSMR_LPB;
 
-#if 0
-	/*
-	 * Configure Ethernet TENA Signal
-	 */
-
-#if (defined(PC_ENET_TENA) && !defined(PB_ENET_TENA))
-	immr->im_ioport.iop_pcpar |= PC_ENET_TENA;
-	immr->im_ioport.iop_pcdir &= ~PC_ENET_TENA;
-#elif (defined(PB_ENET_TENA) && !defined(PC_ENET_TENA))
-	immr->im_cpm.cp_pbpar |= PB_ENET_TENA;
-	immr->im_cpm.cp_pbdir |= PB_ENET_TENA;
-#else
-#error Configuration Error: exactly ONE of PB_ENET_TENA, PC_ENET_TENA must be defined
-#endif
-
-#if defined(CONFIG_ADS) && defined(CONFIG_MPC860)
-	/*
-	 * Port C is used to control the PHY,MC68160.
-	 */
-	immr->im_ioport.iop_pcdir |=
-			(PC_ENET_ETHLOOP | PC_ENET_TPFLDL | PC_ENET_TPSQEL);
-
-	immr->im_ioport.iop_pcdat |= PC_ENET_TPFLDL;
-	immr->im_ioport.iop_pcdat &= ~(PC_ENET_ETHLOOP | PC_ENET_TPSQEL);
-	*((uint *) BCSR1) &= ~BCSR1_ETHEN;
-#endif /* MPC860ADS */
-
-#if defined(CONFIG_AMX860)
-	/*
-	 * Port B is used to control the PHY,MC68160.
-	 */
-	immr->im_cpm.cp_pbdir |=
-			(PB_ENET_ETHLOOP | PB_ENET_TPFLDL | PB_ENET_TPSQEL);
-
-	immr->im_cpm.cp_pbdat |= PB_ENET_TPFLDL;
-	immr->im_cpm.cp_pbdat &= ~(PB_ENET_ETHLOOP | PB_ENET_TPSQEL);
-
-	immr->im_ioport.iop_pddir |= PD_ENET_ETH_EN;
-	immr->im_ioport.iop_pddat &= ~PD_ENET_ETH_EN;
-#endif /* AMX860 */
-
-#endif /* 0 */
-
 #ifdef CONFIG_RPXCLASSIC
 	*((uchar *) BCSR0) &= ~BCSR0_ETHLPBK;
 	*((uchar *) BCSR0) |= (BCSR0_ETHEN | BCSR0_COLTEST | BCSR0_FULLDPLX);
@@ -449,7 +406,7 @@  static void scc_init (int scc_index)
 	 */
 #if defined (CONFIG_FADS)
 	udelay (10000);				/* wait 10 ms */
-#elif defined (CONFIG_AMX860) || defined(CONFIG_RPXCLASSIC)
+#elif defined(CONFIG_RPXCLASSIC)
 	udelay (100000);			/* wait 100 ms */
 #endif
 }