Patchwork Rename target_phys_addr_t to hwaddr

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Submitter Avi Kivity
Date Oct. 23, 2012, 10:30 a.m.
Message ID <1350988210-1318-1-git-send-email-avi@redhat.com>
Download mbox | patch
Permalink /patch/193455/
State New
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Comments

Avi Kivity - Oct. 23, 2012, 10:30 a.m.
target_phys_addr_t is unwieldly, violates the C standard (_t suffixes are
reserved) and its purpose doesn't match the name (most target_phys_addr_t
addresses are not target specific).  Replace it with a finger-friendly,
standards conformant hwaddr.

Outstanding patchsets can be fixed up with the command

  git rebase -i --exec 'find -name "*.[ch]"
                        | xargs s/target_phys_addr_t/hwaddr/g' origin

Signed-off-by: Avi Kivity <avi@redhat.com>
---
 HACKING                           |   2 +-
 cpu-all.h                         |   2 +-
 cpu-common.h                      |  68 ++++++++--------
 cpu-defs.h                        |   4 +-
 cputlb.c                          |   4 +-
 cputlb.h                          |   6 +-
 disas.h                           |   2 +-
 dma-helpers.c                     |   8 +-
 dma.h                             |   8 +-
 dump.c                            |  18 ++---
 exec-all.h                        |  10 +--
 exec.c                            | 162 +++++++++++++++++++-------------------
 hw/a9mpcore.c                     |   4 +-
 hw/alpha_pci.c                    |  12 +--
 hw/alpha_typhoon.c                |  12 +--
 hw/an5206.c                       |   2 +-
 hw/apb_pci.c                      |  24 +++---
 hw/apb_pci.h                      |   4 +-
 hw/apic.c                         |  14 ++--
 hw/apic_common.c                  |   2 +-
 hw/apic_internal.h                |   4 +-
 hw/arm-misc.h                     |  12 +--
 hw/arm11mpcore.c                  |   8 +-
 hw/arm_boot.c                     |  14 ++--
 hw/arm_gic.c                      |  20 ++---
 hw/arm_l2x0.c                     |   4 +-
 hw/arm_mptimer.c                  |  12 +--
 hw/arm_sysctl.c                   |   4 +-
 hw/arm_timer.c                    |  12 +--
 hw/armv7m.c                       |  12 +--
 hw/armv7m_nvic.c                  |   4 +-
 hw/axis_dev88.c                   |   8 +-
 hw/bonito.c                       |  38 ++++-----
 hw/cadence_gem.c                  |   8 +-
 hw/cadence_ttc.c                  |   8 +-
 hw/cadence_uart.c                 |   4 +-
 hw/cirrus_vga.c                   |  16 ++--
 hw/cris-boot.h                    |   2 +-
 hw/cs4231.c                       |   4 +-
 hw/cs4231a.c                      |   4 +-
 hw/cuda.c                         |  12 +--
 hw/dma.c                          |   4 +-
 hw/dp8393x.c                      |  18 ++---
 hw/ds1225y.c                      |   4 +-
 hw/dummy_m68k.c                   |   2 +-
 hw/e1000.c                        |   8 +-
 hw/eccmemctl.c                    |   8 +-
 hw/eepro100.c                     |   4 +-
 hw/elf_ops.h                      |   4 +-
 hw/empty_slot.c                   |   6 +-
 hw/empty_slot.h                   |   2 +-
 hw/escc.c                         |   8 +-
 hw/escc.h                         |   4 +-
 hw/esp-pci.c                      |   4 +-
 hw/esp.c                          |   8 +-
 hw/esp.h                          |   2 +-
 hw/etraxfs.h                      |   2 +-
 hw/etraxfs_dma.c                  |  22 +++---
 hw/etraxfs_dma.h                  |   2 +-
 hw/etraxfs_eth.c                  |   4 +-
 hw/etraxfs_pic.c                  |   4 +-
 hw/etraxfs_ser.c                  |   4 +-
 hw/etraxfs_timer.c                |   4 +-
 hw/exynos4210.h                   |   2 +-
 hw/exynos4210_combiner.c          |   4 +-
 hw/exynos4210_fimd.c              |  10 +--
 hw/exynos4210_i2c.c               |   4 +-
 hw/exynos4210_mct.c               |   4 +-
 hw/exynos4210_pmu.c               |   4 +-
 hw/exynos4210_pwm.c               |   4 +-
 hw/exynos4210_rtc.c               |   4 +-
 hw/exynos4210_uart.c              |  12 +--
 hw/fdc.c                          |   8 +-
 hw/fdc.h                          |   4 +-
 hw/flash.h                        |   8 +-
 hw/framebuffer.c                  |   4 +-
 hw/framebuffer.h                  |   2 +-
 hw/fw_cfg.c                       |  16 ++--
 hw/fw_cfg.h                       |   2 +-
 hw/g364fb.c                       |   4 +-
 hw/grlib.h                        |   6 +-
 hw/grlib_apbuart.c                |   4 +-
 hw/grlib_gptimer.c                |   8 +-
 hw/grlib_irqmp.c                  |   4 +-
 hw/gt64xxx.c                      |  20 ++---
 hw/heathrow_pic.c                 |   4 +-
 hw/highbank.c                     |   4 +-
 hw/hpet.c                         |   8 +-
 hw/i82378.c                       |   8 +-
 hw/i8259.c                        |   8 +-
 hw/ide.h                          |   2 +-
 hw/ide/ahci.c                     |  10 +--
 hw/ide/cmd646.c                   |  12 +--
 hw/ide/macio.c                    |  12 +--
 hw/ide/mmio.c                     |  10 +--
 hw/ide/pci.c                      |   4 +-
 hw/ide/piix.c                     |   4 +-
 hw/ide/via.c                      |   4 +-
 hw/imx.h                          |   6 +-
 hw/imx_avic.c                     |   4 +-
 hw/imx_ccm.c                      |   4 +-
 hw/imx_serial.c                   |   8 +-
 hw/imx_timer.c                    |  12 +--
 hw/integratorcp.c                 |  14 ++--
 hw/intel-hda.c                    |  26 +++---
 hw/ioapic.c                       |   4 +-
 hw/isa-bus.c                      |   2 +-
 hw/isa.h                          |   6 +-
 hw/isa_mmio.c                     |  16 ++--
 hw/ivshmem.c                      |   4 +-
 hw/jazz_led.c                     |   4 +-
 hw/kvm/apic.c                     |   4 +-
 hw/kvm/pci-assign.c               |  24 +++---
 hw/kvmvapic.c                     |  18 ++---
 hw/lan9118.c                      |  12 +--
 hw/lance.c                        |   4 +-
 hw/lm32_boards.c                  |  38 ++++-----
 hw/lm32_hwsetup.h                 |   2 +-
 hw/lm32_sys.c                     |   4 +-
 hw/lm32_timer.c                   |   4 +-
 hw/lm32_uart.c                    |   4 +-
 hw/lm4549.c                       |   4 +-
 hw/lm4549.h                       |   4 +-
 hw/loader.c                       |  30 +++----
 hw/loader.h                       |  22 +++---
 hw/lsi53c895a.c                   |  12 +--
 hw/m48t59.c                       |  14 ++--
 hw/mac_dbdma.c                    |   4 +-
 hw/mac_dbdma.h                    |   2 +-
 hw/mac_nvram.c                    |   8 +-
 hw/mainstone.c                    |   2 +-
 hw/marvell_88w8618_audio.c        |   4 +-
 hw/mcf.h                          |  10 +--
 hw/mcf5206.c                      |  20 ++---
 hw/mcf5208.c                      |  10 +--
 hw/mcf_fec.c                      |   6 +-
 hw/mcf_intc.c                     |   6 +-
 hw/mcf_uart.c                     |   6 +-
 hw/megasas.c                      |  28 +++----
 hw/microblaze_boot.c              |   6 +-
 hw/microblaze_boot.h              |   2 +-
 hw/milkymist-ac97.c               |   4 +-
 hw/milkymist-hpdmc.c              |   4 +-
 hw/milkymist-hw.h                 |  24 +++---
 hw/milkymist-memcard.c            |   4 +-
 hw/milkymist-minimac2.c           |   6 +-
 hw/milkymist-pfpu.c               |   8 +-
 hw/milkymist-softusb.c            |   4 +-
 hw/milkymist-sysctl.c             |   4 +-
 hw/milkymist-tmu2.c               |   8 +-
 hw/milkymist-uart.c               |   4 +-
 hw/milkymist-vgafb.c              |   4 +-
 hw/milkymist.c                    |  16 ++--
 hw/mips.h                         |   6 +-
 hw/mips_jazz.c                    |   8 +-
 hw/mips_malta.c                   |   6 +-
 hw/mips_r4k.c                     |   4 +-
 hw/mipsnet.c                      |   4 +-
 hw/mpc8544_guts.c                 |   4 +-
 hw/msix.c                         |   6 +-
 hw/mst_fpga.c                     |   4 +-
 hw/multiboot.c                    |  16 ++--
 hw/musicpal.c                     |  32 ++++----
 hw/ne2000.c                       |   4 +-
 hw/nvram.h                        |   2 +-
 hw/omap.h                         |  58 +++++++-------
 hw/omap1.c                        | 148 +++++++++++++++++-----------------
 hw/omap2.c                        |  28 +++----
 hw/omap_dma.c                     |  24 +++---
 hw/omap_dss.c                     |  36 ++++-----
 hw/omap_gpio.c                    |  16 ++--
 hw/omap_gpmc.c                    |  16 ++--
 hw/omap_gptimer.c                 |   8 +-
 hw/omap_i2c.c                     |   6 +-
 hw/omap_intc.c                    |   8 +-
 hw/omap_l4.c                      |  16 ++--
 hw/omap_lcdc.c                    |   8 +-
 hw/omap_mmc.c                     |   6 +-
 hw/omap_sdrc.c                    |   6 +-
 hw/omap_spi.c                     |   4 +-
 hw/omap_sx1.c                     |   4 +-
 hw/omap_synctimer.c               |   6 +-
 hw/omap_tap.c                     |   4 +-
 hw/omap_uart.c                    |  10 +--
 hw/onenand.c                      |   8 +-
 hw/opencores_eth.c                |   8 +-
 hw/openpic.c                      |  52 ++++++------
 hw/openpic.h                      |   2 +-
 hw/openrisc_sim.c                 |   6 +-
 hw/palm.c                         |   8 +-
 hw/parallel.c                     |  14 ++--
 hw/pc.c                           |   4 +-
 hw/pc.h                           |  16 ++--
 hw/pc_piix.c                      |   2 +-
 hw/pc_sysfw.c                     |   2 +-
 hw/pci.c                          |   2 +-
 hw/pci_host.c                     |   8 +-
 hw/pcie_host.c                    |  10 +--
 hw/pcie_host.h                    |   8 +-
 hw/pckbd.c                        |   8 +-
 hw/pcnet-pci.c                    |  20 ++---
 hw/pcnet.c                        |  34 ++++----
 hw/pcnet.h                        |   4 +-
 hw/pcspk.c                        |   4 +-
 hw/petalogix_ml605_mmu.c          |   2 +-
 hw/petalogix_s3adsp1800_mmu.c     |   2 +-
 hw/pflash_cfi01.c                 |  48 +++++------
 hw/pflash_cfi02.c                 |  40 +++++-----
 hw/piix_pci.c                     |  16 ++--
 hw/pl011.c                        |   4 +-
 hw/pl022.c                        |   4 +-
 hw/pl031.c                        |   4 +-
 hw/pl041.c                        |   6 +-
 hw/pl050.c                        |   4 +-
 hw/pl061.c                        |   4 +-
 hw/pl080.c                        |   4 +-
 hw/pl110.c                        |   4 +-
 hw/pl181.c                        |   4 +-
 hw/pl190.c                        |   4 +-
 hw/ppc/e500.c                     |  14 ++--
 hw/ppc405.h                       |  12 +--
 hw/ppc405_boards.c                |  28 +++----
 hw/ppc405_uc.c                    |  64 +++++++--------
 hw/ppc440_bamboo.c                |  16 ++--
 hw/ppc4xx.h                       |  16 ++--
 hw/ppc4xx_devs.c                  |  28 +++----
 hw/ppc4xx_pci.c                   |   8 +-
 hw/ppc_mac.h                      |   4 +-
 hw/ppc_newworld.c                 |   8 +-
 hw/ppc_oldworld.c                 |   2 +-
 hw/ppc_prep.c                     |  30 +++----
 hw/ppce500_pci.c                  |   4 +-
 hw/ppce500_spin.c                 |  16 ++--
 hw/prep_pci.c                     |   8 +-
 hw/puv3_dma.c                     |   4 +-
 hw/puv3_gpio.c                    |   4 +-
 hw/puv3_intc.c                    |   4 +-
 hw/puv3_ost.c                     |   4 +-
 hw/puv3_pm.c                      |   4 +-
 hw/pxa.h                          |  24 +++---
 hw/pxa2xx.c                       |  42 +++++-----
 hw/pxa2xx_dma.c                   |  10 +--
 hw/pxa2xx_gpio.c                  |   6 +-
 hw/pxa2xx_keypad.c                |   6 +-
 hw/pxa2xx_lcd.c                   |  20 ++---
 hw/pxa2xx_mmci.c                  |  18 ++---
 hw/pxa2xx_pcmcia.c                |  14 ++--
 hw/pxa2xx_pic.c                   |   6 +-
 hw/pxa2xx_timer.c                 |   4 +-
 hw/qdev-addr.c                    |  16 ++--
 hw/qdev-addr.h                    |   4 +-
 hw/qxl.c                          |   4 +-
 hw/r2d.c                          |   6 +-
 hw/rc4030.c                       |  34 ++++----
 hw/realview.c                     |   2 +-
 hw/rtl8139.c                      |  14 ++--
 hw/s390-virtio-bus.c              |   4 +-
 hw/s390-virtio.c                  |   4 +-
 hw/sbi.c                          |   4 +-
 hw/serial.c                       |   6 +-
 hw/serial.h                       |   2 +-
 hw/sh.h                           |   4 +-
 hw/sh7750.c                       |  24 +++---
 hw/sh_intc.c                      |   4 +-
 hw/sh_pci.c                       |   4 +-
 hw/sh_serial.c                    |  10 +--
 hw/sh_timer.c                     |  10 +--
 hw/sharpsl.h                      |   2 +-
 hw/shpc.c                         |   4 +-
 hw/slavio_intctl.c                |   8 +-
 hw/slavio_misc.c                  |  32 ++++----
 hw/slavio_timer.c                 |   4 +-
 hw/sm501.c                        |  18 ++---
 hw/smc91c111.c                    |  12 +--
 hw/soc_dma.c                      |   8 +-
 hw/soc_dma.h                      |  10 +--
 hw/spapr.c                        |  16 ++--
 hw/spapr.h                        |  10 +--
 hw/spapr_iommu.c                  |   6 +-
 hw/spapr_pci.c                    |   8 +-
 hw/spapr_pci.h                    |   4 +-
 hw/spapr_rtas.c                   |   4 +-
 hw/sparc32_dma.c                  |   8 +-
 hw/sparc32_dma.h                  |   4 +-
 hw/spitz.c                        |   4 +-
 hw/stellaris.c                    |  16 ++--
 hw/stellaris_enet.c               |   4 +-
 hw/strongarm.c                    |  28 +++----
 hw/sun4c_intctl.c                 |   4 +-
 hw/sun4m.c                        |  84 ++++++++++----------
 hw/sun4m.h                        |   6 +-
 hw/sun4m_iommu.c                  |  26 +++---
 hw/sun4u.c                        |   6 +-
 hw/sysbus.c                       |  20 ++---
 hw/sysbus.h                       |  18 ++---
 hw/tc6393xb.c                     |  16 ++--
 hw/tcx.c                          |  10 +--
 hw/tusb6010.c                     |  12 +--
 hw/unin_pci.c                     |   4 +-
 hw/usb/hcd-ehci.c                 |  20 ++---
 hw/usb/hcd-musb.c                 |  12 +--
 hw/usb/hcd-ohci.c                 |   4 +-
 hw/usb/hcd-xhci.c                 |  18 ++---
 hw/versatile_i2c.c                |   4 +-
 hw/versatile_pci.c                |   6 +-
 hw/versatilepb.c                  |   4 +-
 hw/vexpress.c                     |  12 +--
 hw/vfio_pci.c                     |  36 ++++-----
 hw/vga-isa-mm.c                   |  20 ++---
 hw/vga-pci.c                      |   8 +-
 hw/vga.c                          |  10 +--
 hw/vga_int.h                      |   4 +-
 hw/vhost.c                        |  16 ++--
 hw/virtex_ml507.c                 |  12 +--
 hw/virtio-pci.c                   |   4 +-
 hw/virtio-scsi.c                  |   2 +-
 hw/virtio.c                       |  76 +++++++++---------
 hw/virtio.h                       |  28 +++----
 hw/vmware_vga.c                   |   4 +-
 hw/wdt_i6300esb.c                 |  12 +--
 hw/xen_apic.c                     |   4 +-
 hw/xen_platform.c                 |   4 +-
 hw/xen_pt.c                       |   4 +-
 hw/xen_pt_msi.c                   |   4 +-
 hw/xgmac.c                        |   4 +-
 hw/xilinx.h                       |  10 +--
 hw/xilinx_axidma.c                |  10 +--
 hw/xilinx_axienet.c               |   4 +-
 hw/xilinx_ethlite.c               |   4 +-
 hw/xilinx_intc.c                  |   4 +-
 hw/xilinx_spi.c                   |   4 +-
 hw/xilinx_spips.c                 |   4 +-
 hw/xilinx_timer.c                 |   6 +-
 hw/xilinx_uartlite.c              |   4 +-
 hw/xtensa_lx60.c                  |  12 +--
 hw/zaurus.c                       |   6 +-
 hw/zynq_slcr.c                    |   6 +-
 hwaddr.h                          |  24 ++++++
 kvm-all.c                         |  28 +++----
 kvm.h                             |   2 +-
 memory-internal.h                 |   4 +-
 memory.c                          |  68 ++++++++--------
 memory.h                          |  70 ++++++++--------
 memory_mapping.c                  |  20 ++---
 memory_mapping.h                  |   6 +-
 monitor.c                         |  38 ++++-----
 softmmu_template.h                |  12 +--
 target-alpha/cpu.h                |   2 +-
 target-alpha/helper.c             |   2 +-
 target-alpha/mem_helper.c         |   2 +-
 target-arm/helper.c               |  28 +++----
 target-cris/helper.c              |   2 +-
 target-i386/arch_memory_mapping.c |  34 ++++----
 target-i386/helper.c              |   6 +-
 target-i386/kvm.c                 |   6 +-
 target-i386/svm_helper.c          |   6 +-
 target-lm32/helper.c              |   2 +-
 target-m68k/helper.c              |   2 +-
 target-microblaze/cpu.h           |   2 +-
 target-microblaze/helper.c        |   2 +-
 target-microblaze/op_helper.c     |   2 +-
 target-mips/cpu.h                 |  12 +--
 target-mips/helper.c              |  18 ++---
 target-mips/op_helper.c           |   6 +-
 target-openrisc/cpu.h             |  10 +--
 target-openrisc/mmu.c             |  14 ++--
 target-ppc/cpu.h                  |  24 +++---
 target-ppc/mmu_helper.c           |  52 ++++++------
 target-s390x/cpu.h                |   2 +-
 target-s390x/helper.c             |   8 +-
 target-s390x/mem_helper.c         |  10 +--
 target-sh4/cpu.h                  |  16 ++--
 target-sh4/helper.c               |  18 ++---
 target-sparc/cpu.h                |   4 +-
 target-sparc/ldst_helper.c        |  36 ++++-----
 target-sparc/mmu_helper.c         |  38 ++++-----
 target-unicore32/softmmu.c        |   2 +-
 target-xtensa/helper.c            |   2 +-
 target-xtensa/xtensa-semi.c       |   6 +-
 targphys.h                        |  24 ------
 xen-all.c                         |  36 ++++-----
 xen-mapcache.c                    |  32 ++++----
 xen-mapcache.h                    |   8 +-
 383 files changed, 2240 insertions(+), 2240 deletions(-)
 create mode 100644 hwaddr.h
 delete mode 100644 targphys.h
Anthony Liguori - Oct. 23, 2012, 12:55 p.m.
Avi Kivity <avi@redhat.com> writes:

> target_phys_addr_t is unwieldly, violates the C standard (_t suffixes are
> reserved) and its purpose doesn't match the name (most target_phys_addr_t
> addresses are not target specific).  Replace it with a finger-friendly,
> standards conformant hwaddr.
>
> Outstanding patchsets can be fixed up with the command
>
>   git rebase -i --exec 'find -name "*.[ch]"
>                         | xargs s/target_phys_addr_t/hwaddr/g' origin

We're getting pretty close to soft freeze so perhaps it's time to make a
couple big changes.

Paolo, are you ready to do the file rename changes?  I'd like to
coordinate this change with that one and do it all at the same time.

Regards,

Anthony Liguori

>
> Signed-off-by: Avi Kivity <avi@redhat.com>
> ---
>  HACKING                           |   2 +-
>  cpu-all.h                         |   2 +-
>  cpu-common.h                      |  68 ++++++++--------
>  cpu-defs.h                        |   4 +-
>  cputlb.c                          |   4 +-
>  cputlb.h                          |   6 +-
>  disas.h                           |   2 +-
>  dma-helpers.c                     |   8 +-
>  dma.h                             |   8 +-
>  dump.c                            |  18 ++---
>  exec-all.h                        |  10 +--
>  exec.c                            | 162 +++++++++++++++++++-------------------
>  hw/a9mpcore.c                     |   4 +-
>  hw/alpha_pci.c                    |  12 +--
>  hw/alpha_typhoon.c                |  12 +--
>  hw/an5206.c                       |   2 +-
>  hw/apb_pci.c                      |  24 +++---
>  hw/apb_pci.h                      |   4 +-
>  hw/apic.c                         |  14 ++--
>  hw/apic_common.c                  |   2 +-
>  hw/apic_internal.h                |   4 +-
>  hw/arm-misc.h                     |  12 +--
>  hw/arm11mpcore.c                  |   8 +-
>  hw/arm_boot.c                     |  14 ++--
>  hw/arm_gic.c                      |  20 ++---
>  hw/arm_l2x0.c                     |   4 +-
>  hw/arm_mptimer.c                  |  12 +--
>  hw/arm_sysctl.c                   |   4 +-
>  hw/arm_timer.c                    |  12 +--
>  hw/armv7m.c                       |  12 +--
>  hw/armv7m_nvic.c                  |   4 +-
>  hw/axis_dev88.c                   |   8 +-
>  hw/bonito.c                       |  38 ++++-----
>  hw/cadence_gem.c                  |   8 +-
>  hw/cadence_ttc.c                  |   8 +-
>  hw/cadence_uart.c                 |   4 +-
>  hw/cirrus_vga.c                   |  16 ++--
>  hw/cris-boot.h                    |   2 +-
>  hw/cs4231.c                       |   4 +-
>  hw/cs4231a.c                      |   4 +-
>  hw/cuda.c                         |  12 +--
>  hw/dma.c                          |   4 +-
>  hw/dp8393x.c                      |  18 ++---
>  hw/ds1225y.c                      |   4 +-
>  hw/dummy_m68k.c                   |   2 +-
>  hw/e1000.c                        |   8 +-
>  hw/eccmemctl.c                    |   8 +-
>  hw/eepro100.c                     |   4 +-
>  hw/elf_ops.h                      |   4 +-
>  hw/empty_slot.c                   |   6 +-
>  hw/empty_slot.h                   |   2 +-
>  hw/escc.c                         |   8 +-
>  hw/escc.h                         |   4 +-
>  hw/esp-pci.c                      |   4 +-
>  hw/esp.c                          |   8 +-
>  hw/esp.h                          |   2 +-
>  hw/etraxfs.h                      |   2 +-
>  hw/etraxfs_dma.c                  |  22 +++---
>  hw/etraxfs_dma.h                  |   2 +-
>  hw/etraxfs_eth.c                  |   4 +-
>  hw/etraxfs_pic.c                  |   4 +-
>  hw/etraxfs_ser.c                  |   4 +-
>  hw/etraxfs_timer.c                |   4 +-
>  hw/exynos4210.h                   |   2 +-
>  hw/exynos4210_combiner.c          |   4 +-
>  hw/exynos4210_fimd.c              |  10 +--
>  hw/exynos4210_i2c.c               |   4 +-
>  hw/exynos4210_mct.c               |   4 +-
>  hw/exynos4210_pmu.c               |   4 +-
>  hw/exynos4210_pwm.c               |   4 +-
>  hw/exynos4210_rtc.c               |   4 +-
>  hw/exynos4210_uart.c              |  12 +--
>  hw/fdc.c                          |   8 +-
>  hw/fdc.h                          |   4 +-
>  hw/flash.h                        |   8 +-
>  hw/framebuffer.c                  |   4 +-
>  hw/framebuffer.h                  |   2 +-
>  hw/fw_cfg.c                       |  16 ++--
>  hw/fw_cfg.h                       |   2 +-
>  hw/g364fb.c                       |   4 +-
>  hw/grlib.h                        |   6 +-
>  hw/grlib_apbuart.c                |   4 +-
>  hw/grlib_gptimer.c                |   8 +-
>  hw/grlib_irqmp.c                  |   4 +-
>  hw/gt64xxx.c                      |  20 ++---
>  hw/heathrow_pic.c                 |   4 +-
>  hw/highbank.c                     |   4 +-
>  hw/hpet.c                         |   8 +-
>  hw/i82378.c                       |   8 +-
>  hw/i8259.c                        |   8 +-
>  hw/ide.h                          |   2 +-
>  hw/ide/ahci.c                     |  10 +--
>  hw/ide/cmd646.c                   |  12 +--
>  hw/ide/macio.c                    |  12 +--
>  hw/ide/mmio.c                     |  10 +--
>  hw/ide/pci.c                      |   4 +-
>  hw/ide/piix.c                     |   4 +-
>  hw/ide/via.c                      |   4 +-
>  hw/imx.h                          |   6 +-
>  hw/imx_avic.c                     |   4 +-
>  hw/imx_ccm.c                      |   4 +-
>  hw/imx_serial.c                   |   8 +-
>  hw/imx_timer.c                    |  12 +--
>  hw/integratorcp.c                 |  14 ++--
>  hw/intel-hda.c                    |  26 +++---
>  hw/ioapic.c                       |   4 +-
>  hw/isa-bus.c                      |   2 +-
>  hw/isa.h                          |   6 +-
>  hw/isa_mmio.c                     |  16 ++--
>  hw/ivshmem.c                      |   4 +-
>  hw/jazz_led.c                     |   4 +-
>  hw/kvm/apic.c                     |   4 +-
>  hw/kvm/pci-assign.c               |  24 +++---
>  hw/kvmvapic.c                     |  18 ++---
>  hw/lan9118.c                      |  12 +--
>  hw/lance.c                        |   4 +-
>  hw/lm32_boards.c                  |  38 ++++-----
>  hw/lm32_hwsetup.h                 |   2 +-
>  hw/lm32_sys.c                     |   4 +-
>  hw/lm32_timer.c                   |   4 +-
>  hw/lm32_uart.c                    |   4 +-
>  hw/lm4549.c                       |   4 +-
>  hw/lm4549.h                       |   4 +-
>  hw/loader.c                       |  30 +++----
>  hw/loader.h                       |  22 +++---
>  hw/lsi53c895a.c                   |  12 +--
>  hw/m48t59.c                       |  14 ++--
>  hw/mac_dbdma.c                    |   4 +-
>  hw/mac_dbdma.h                    |   2 +-
>  hw/mac_nvram.c                    |   8 +-
>  hw/mainstone.c                    |   2 +-
>  hw/marvell_88w8618_audio.c        |   4 +-
>  hw/mcf.h                          |  10 +--
>  hw/mcf5206.c                      |  20 ++---
>  hw/mcf5208.c                      |  10 +--
>  hw/mcf_fec.c                      |   6 +-
>  hw/mcf_intc.c                     |   6 +-
>  hw/mcf_uart.c                     |   6 +-
>  hw/megasas.c                      |  28 +++----
>  hw/microblaze_boot.c              |   6 +-
>  hw/microblaze_boot.h              |   2 +-
>  hw/milkymist-ac97.c               |   4 +-
>  hw/milkymist-hpdmc.c              |   4 +-
>  hw/milkymist-hw.h                 |  24 +++---
>  hw/milkymist-memcard.c            |   4 +-
>  hw/milkymist-minimac2.c           |   6 +-
>  hw/milkymist-pfpu.c               |   8 +-
>  hw/milkymist-softusb.c            |   4 +-
>  hw/milkymist-sysctl.c             |   4 +-
>  hw/milkymist-tmu2.c               |   8 +-
>  hw/milkymist-uart.c               |   4 +-
>  hw/milkymist-vgafb.c              |   4 +-
>  hw/milkymist.c                    |  16 ++--
>  hw/mips.h                         |   6 +-
>  hw/mips_jazz.c                    |   8 +-
>  hw/mips_malta.c                   |   6 +-
>  hw/mips_r4k.c                     |   4 +-
>  hw/mipsnet.c                      |   4 +-
>  hw/mpc8544_guts.c                 |   4 +-
>  hw/msix.c                         |   6 +-
>  hw/mst_fpga.c                     |   4 +-
>  hw/multiboot.c                    |  16 ++--
>  hw/musicpal.c                     |  32 ++++----
>  hw/ne2000.c                       |   4 +-
>  hw/nvram.h                        |   2 +-
>  hw/omap.h                         |  58 +++++++-------
>  hw/omap1.c                        | 148 +++++++++++++++++-----------------
>  hw/omap2.c                        |  28 +++----
>  hw/omap_dma.c                     |  24 +++---
>  hw/omap_dss.c                     |  36 ++++-----
>  hw/omap_gpio.c                    |  16 ++--
>  hw/omap_gpmc.c                    |  16 ++--
>  hw/omap_gptimer.c                 |   8 +-
>  hw/omap_i2c.c                     |   6 +-
>  hw/omap_intc.c                    |   8 +-
>  hw/omap_l4.c                      |  16 ++--
>  hw/omap_lcdc.c                    |   8 +-
>  hw/omap_mmc.c                     |   6 +-
>  hw/omap_sdrc.c                    |   6 +-
>  hw/omap_spi.c                     |   4 +-
>  hw/omap_sx1.c                     |   4 +-
>  hw/omap_synctimer.c               |   6 +-
>  hw/omap_tap.c                     |   4 +-
>  hw/omap_uart.c                    |  10 +--
>  hw/onenand.c                      |   8 +-
>  hw/opencores_eth.c                |   8 +-
>  hw/openpic.c                      |  52 ++++++------
>  hw/openpic.h                      |   2 +-
>  hw/openrisc_sim.c                 |   6 +-
>  hw/palm.c                         |   8 +-
>  hw/parallel.c                     |  14 ++--
>  hw/pc.c                           |   4 +-
>  hw/pc.h                           |  16 ++--
>  hw/pc_piix.c                      |   2 +-
>  hw/pc_sysfw.c                     |   2 +-
>  hw/pci.c                          |   2 +-
>  hw/pci_host.c                     |   8 +-
>  hw/pcie_host.c                    |  10 +--
>  hw/pcie_host.h                    |   8 +-
>  hw/pckbd.c                        |   8 +-
>  hw/pcnet-pci.c                    |  20 ++---
>  hw/pcnet.c                        |  34 ++++----
>  hw/pcnet.h                        |   4 +-
>  hw/pcspk.c                        |   4 +-
>  hw/petalogix_ml605_mmu.c          |   2 +-
>  hw/petalogix_s3adsp1800_mmu.c     |   2 +-
>  hw/pflash_cfi01.c                 |  48 +++++------
>  hw/pflash_cfi02.c                 |  40 +++++-----
>  hw/piix_pci.c                     |  16 ++--
>  hw/pl011.c                        |   4 +-
>  hw/pl022.c                        |   4 +-
>  hw/pl031.c                        |   4 +-
>  hw/pl041.c                        |   6 +-
>  hw/pl050.c                        |   4 +-
>  hw/pl061.c                        |   4 +-
>  hw/pl080.c                        |   4 +-
>  hw/pl110.c                        |   4 +-
>  hw/pl181.c                        |   4 +-
>  hw/pl190.c                        |   4 +-
>  hw/ppc/e500.c                     |  14 ++--
>  hw/ppc405.h                       |  12 +--
>  hw/ppc405_boards.c                |  28 +++----
>  hw/ppc405_uc.c                    |  64 +++++++--------
>  hw/ppc440_bamboo.c                |  16 ++--
>  hw/ppc4xx.h                       |  16 ++--
>  hw/ppc4xx_devs.c                  |  28 +++----
>  hw/ppc4xx_pci.c                   |   8 +-
>  hw/ppc_mac.h                      |   4 +-
>  hw/ppc_newworld.c                 |   8 +-
>  hw/ppc_oldworld.c                 |   2 +-
>  hw/ppc_prep.c                     |  30 +++----
>  hw/ppce500_pci.c                  |   4 +-
>  hw/ppce500_spin.c                 |  16 ++--
>  hw/prep_pci.c                     |   8 +-
>  hw/puv3_dma.c                     |   4 +-
>  hw/puv3_gpio.c                    |   4 +-
>  hw/puv3_intc.c                    |   4 +-
>  hw/puv3_ost.c                     |   4 +-
>  hw/puv3_pm.c                      |   4 +-
>  hw/pxa.h                          |  24 +++---
>  hw/pxa2xx.c                       |  42 +++++-----
>  hw/pxa2xx_dma.c                   |  10 +--
>  hw/pxa2xx_gpio.c                  |   6 +-
>  hw/pxa2xx_keypad.c                |   6 +-
>  hw/pxa2xx_lcd.c                   |  20 ++---
>  hw/pxa2xx_mmci.c                  |  18 ++---
>  hw/pxa2xx_pcmcia.c                |  14 ++--
>  hw/pxa2xx_pic.c                   |   6 +-
>  hw/pxa2xx_timer.c                 |   4 +-
>  hw/qdev-addr.c                    |  16 ++--
>  hw/qdev-addr.h                    |   4 +-
>  hw/qxl.c                          |   4 +-
>  hw/r2d.c                          |   6 +-
>  hw/rc4030.c                       |  34 ++++----
>  hw/realview.c                     |   2 +-
>  hw/rtl8139.c                      |  14 ++--
>  hw/s390-virtio-bus.c              |   4 +-
>  hw/s390-virtio.c                  |   4 +-
>  hw/sbi.c                          |   4 +-
>  hw/serial.c                       |   6 +-
>  hw/serial.h                       |   2 +-
>  hw/sh.h                           |   4 +-
>  hw/sh7750.c                       |  24 +++---
>  hw/sh_intc.c                      |   4 +-
>  hw/sh_pci.c                       |   4 +-
>  hw/sh_serial.c                    |  10 +--
>  hw/sh_timer.c                     |  10 +--
>  hw/sharpsl.h                      |   2 +-
>  hw/shpc.c                         |   4 +-
>  hw/slavio_intctl.c                |   8 +-
>  hw/slavio_misc.c                  |  32 ++++----
>  hw/slavio_timer.c                 |   4 +-
>  hw/sm501.c                        |  18 ++---
>  hw/smc91c111.c                    |  12 +--
>  hw/soc_dma.c                      |   8 +-
>  hw/soc_dma.h                      |  10 +--
>  hw/spapr.c                        |  16 ++--
>  hw/spapr.h                        |  10 +--
>  hw/spapr_iommu.c                  |   6 +-
>  hw/spapr_pci.c                    |   8 +-
>  hw/spapr_pci.h                    |   4 +-
>  hw/spapr_rtas.c                   |   4 +-
>  hw/sparc32_dma.c                  |   8 +-
>  hw/sparc32_dma.h                  |   4 +-
>  hw/spitz.c                        |   4 +-
>  hw/stellaris.c                    |  16 ++--
>  hw/stellaris_enet.c               |   4 +-
>  hw/strongarm.c                    |  28 +++----
>  hw/sun4c_intctl.c                 |   4 +-
>  hw/sun4m.c                        |  84 ++++++++++----------
>  hw/sun4m.h                        |   6 +-
>  hw/sun4m_iommu.c                  |  26 +++---
>  hw/sun4u.c                        |   6 +-
>  hw/sysbus.c                       |  20 ++---
>  hw/sysbus.h                       |  18 ++---
>  hw/tc6393xb.c                     |  16 ++--
>  hw/tcx.c                          |  10 +--
>  hw/tusb6010.c                     |  12 +--
>  hw/unin_pci.c                     |   4 +-
>  hw/usb/hcd-ehci.c                 |  20 ++---
>  hw/usb/hcd-musb.c                 |  12 +--
>  hw/usb/hcd-ohci.c                 |   4 +-
>  hw/usb/hcd-xhci.c                 |  18 ++---
>  hw/versatile_i2c.c                |   4 +-
>  hw/versatile_pci.c                |   6 +-
>  hw/versatilepb.c                  |   4 +-
>  hw/vexpress.c                     |  12 +--
>  hw/vfio_pci.c                     |  36 ++++-----
>  hw/vga-isa-mm.c                   |  20 ++---
>  hw/vga-pci.c                      |   8 +-
>  hw/vga.c                          |  10 +--
>  hw/vga_int.h                      |   4 +-
>  hw/vhost.c                        |  16 ++--
>  hw/virtex_ml507.c                 |  12 +--
>  hw/virtio-pci.c                   |   4 +-
>  hw/virtio-scsi.c                  |   2 +-
>  hw/virtio.c                       |  76 +++++++++---------
>  hw/virtio.h                       |  28 +++----
>  hw/vmware_vga.c                   |   4 +-
>  hw/wdt_i6300esb.c                 |  12 +--
>  hw/xen_apic.c                     |   4 +-
>  hw/xen_platform.c                 |   4 +-
>  hw/xen_pt.c                       |   4 +-
>  hw/xen_pt_msi.c                   |   4 +-
>  hw/xgmac.c                        |   4 +-
>  hw/xilinx.h                       |  10 +--
>  hw/xilinx_axidma.c                |  10 +--
>  hw/xilinx_axienet.c               |   4 +-
>  hw/xilinx_ethlite.c               |   4 +-
>  hw/xilinx_intc.c                  |   4 +-
>  hw/xilinx_spi.c                   |   4 +-
>  hw/xilinx_spips.c                 |   4 +-
>  hw/xilinx_timer.c                 |   6 +-
>  hw/xilinx_uartlite.c              |   4 +-
>  hw/xtensa_lx60.c                  |  12 +--
>  hw/zaurus.c                       |   6 +-
>  hw/zynq_slcr.c                    |   6 +-
>  hwaddr.h                          |  24 ++++++
>  kvm-all.c                         |  28 +++----
>  kvm.h                             |   2 +-
>  memory-internal.h                 |   4 +-
>  memory.c                          |  68 ++++++++--------
>  memory.h                          |  70 ++++++++--------
>  memory_mapping.c                  |  20 ++---
>  memory_mapping.h                  |   6 +-
>  monitor.c                         |  38 ++++-----
>  softmmu_template.h                |  12 +--
>  target-alpha/cpu.h                |   2 +-
>  target-alpha/helper.c             |   2 +-
>  target-alpha/mem_helper.c         |   2 +-
>  target-arm/helper.c               |  28 +++----
>  target-cris/helper.c              |   2 +-
>  target-i386/arch_memory_mapping.c |  34 ++++----
>  target-i386/helper.c              |   6 +-
>  target-i386/kvm.c                 |   6 +-
>  target-i386/svm_helper.c          |   6 +-
>  target-lm32/helper.c              |   2 +-
>  target-m68k/helper.c              |   2 +-
>  target-microblaze/cpu.h           |   2 +-
>  target-microblaze/helper.c        |   2 +-
>  target-microblaze/op_helper.c     |   2 +-
>  target-mips/cpu.h                 |  12 +--
>  target-mips/helper.c              |  18 ++---
>  target-mips/op_helper.c           |   6 +-
>  target-openrisc/cpu.h             |  10 +--
>  target-openrisc/mmu.c             |  14 ++--
>  target-ppc/cpu.h                  |  24 +++---
>  target-ppc/mmu_helper.c           |  52 ++++++------
>  target-s390x/cpu.h                |   2 +-
>  target-s390x/helper.c             |   8 +-
>  target-s390x/mem_helper.c         |  10 +--
>  target-sh4/cpu.h                  |  16 ++--
>  target-sh4/helper.c               |  18 ++---
>  target-sparc/cpu.h                |   4 +-
>  target-sparc/ldst_helper.c        |  36 ++++-----
>  target-sparc/mmu_helper.c         |  38 ++++-----
>  target-unicore32/softmmu.c        |   2 +-
>  target-xtensa/helper.c            |   2 +-
>  target-xtensa/xtensa-semi.c       |   6 +-
>  targphys.h                        |  24 ------
>  xen-all.c                         |  36 ++++-----
>  xen-mapcache.c                    |  32 ++++----
>  xen-mapcache.h                    |   8 +-
>  383 files changed, 2240 insertions(+), 2240 deletions(-)
>  create mode 100644 hwaddr.h
>  delete mode 100644 targphys.h
>
> diff --git a/HACKING b/HACKING
> index dddd617..89a6b3a 100644
> --- a/HACKING
> +++ b/HACKING
> @@ -32,7 +32,7 @@ mandatory for VMState fields.
>  
>  Don't use Linux kernel internal types like u32, __u32 or __le32.
>  
> -Use target_phys_addr_t for guest physical addresses except pcibus_t
> +Use hwaddr for guest physical addresses except pcibus_t
>  for PCI addresses.  In addition, ram_addr_t is a QEMU internal address
>  space that maps guest RAM physical addresses into an intermediate
>  address space that can map to host virtual address spaces.  Generally
> diff --git a/cpu-all.h b/cpu-all.h
> index 6aa7e58..6606432 100644
> --- a/cpu-all.h
> +++ b/cpu-all.h
> @@ -474,7 +474,7 @@ void run_on_cpu(CPUArchState *env, void (*func)(void *data), void *data);
>  /* Return the physical page corresponding to a virtual one. Use it
>     only for debugging because no protection checks are done. Return -1
>     if no page found. */
> -target_phys_addr_t cpu_get_phys_page_debug(CPUArchState *env, target_ulong addr);
> +hwaddr cpu_get_phys_page_debug(CPUArchState *env, target_ulong addr);
>  
>  /* memory API */
>  
> diff --git a/cpu-common.h b/cpu-common.h
> index c0d27af..5f93089 100644
> --- a/cpu-common.h
> +++ b/cpu-common.h
> @@ -3,7 +3,7 @@
>  
>  /* CPU interfaces that are target independent.  */
>  
> -#include "targphys.h"
> +#include "hwaddr.h"
>  
>  #ifndef NEED_CPU_H
>  #include "poison.h"
> @@ -33,8 +33,8 @@ typedef uintptr_t ram_addr_t;
>  
>  /* memory API */
>  
> -typedef void CPUWriteMemoryFunc(void *opaque, target_phys_addr_t addr, uint32_t value);
> -typedef uint32_t CPUReadMemoryFunc(void *opaque, target_phys_addr_t addr);
> +typedef void CPUWriteMemoryFunc(void *opaque, hwaddr addr, uint32_t value);
> +typedef uint32_t CPUReadMemoryFunc(void *opaque, hwaddr addr);
>  
>  void qemu_ram_remap(ram_addr_t addr, ram_addr_t length);
>  /* This should only be used for ram local to a device.  */
> @@ -49,27 +49,27 @@ int qemu_ram_addr_from_host(void *ptr, ram_addr_t *ram_addr);
>  ram_addr_t qemu_ram_addr_from_host_nofail(void *ptr);
>  void qemu_ram_set_idstr(ram_addr_t addr, const char *name, DeviceState *dev);
>  
> -void cpu_physical_memory_rw(target_phys_addr_t addr, uint8_t *buf,
> +void cpu_physical_memory_rw(hwaddr addr, uint8_t *buf,
>                              int len, int is_write);
> -static inline void cpu_physical_memory_read(target_phys_addr_t addr,
> +static inline void cpu_physical_memory_read(hwaddr addr,
>                                              void *buf, int len)
>  {
>      cpu_physical_memory_rw(addr, buf, len, 0);
>  }
> -static inline void cpu_physical_memory_write(target_phys_addr_t addr,
> +static inline void cpu_physical_memory_write(hwaddr addr,
>                                               const void *buf, int len)
>  {
>      cpu_physical_memory_rw(addr, (void *)buf, len, 1);
>  }
> -void *cpu_physical_memory_map(target_phys_addr_t addr,
> -                              target_phys_addr_t *plen,
> +void *cpu_physical_memory_map(hwaddr addr,
> +                              hwaddr *plen,
>                                int is_write);
> -void cpu_physical_memory_unmap(void *buffer, target_phys_addr_t len,
> -                               int is_write, target_phys_addr_t access_len);
> +void cpu_physical_memory_unmap(void *buffer, hwaddr len,
> +                               int is_write, hwaddr access_len);
>  void *cpu_register_map_client(void *opaque, void (*callback)(void *opaque));
>  void cpu_unregister_map_client(void *cookie);
>  
> -bool cpu_physical_memory_is_io(target_phys_addr_t phys_addr);
> +bool cpu_physical_memory_is_io(hwaddr phys_addr);
>  
>  /* Coalesced MMIO regions are areas where write operations can be reordered.
>   * This usually implies that write operations are side-effect free.  This allows
> @@ -78,33 +78,33 @@ bool cpu_physical_memory_is_io(target_phys_addr_t phys_addr);
>   */
>  void qemu_flush_coalesced_mmio_buffer(void);
>  
> -uint32_t ldub_phys(target_phys_addr_t addr);
> -uint32_t lduw_le_phys(target_phys_addr_t addr);
> -uint32_t lduw_be_phys(target_phys_addr_t addr);
> -uint32_t ldl_le_phys(target_phys_addr_t addr);
> -uint32_t ldl_be_phys(target_phys_addr_t addr);
> -uint64_t ldq_le_phys(target_phys_addr_t addr);
> -uint64_t ldq_be_phys(target_phys_addr_t addr);
> -void stb_phys(target_phys_addr_t addr, uint32_t val);
> -void stw_le_phys(target_phys_addr_t addr, uint32_t val);
> -void stw_be_phys(target_phys_addr_t addr, uint32_t val);
> -void stl_le_phys(target_phys_addr_t addr, uint32_t val);
> -void stl_be_phys(target_phys_addr_t addr, uint32_t val);
> -void stq_le_phys(target_phys_addr_t addr, uint64_t val);
> -void stq_be_phys(target_phys_addr_t addr, uint64_t val);
> +uint32_t ldub_phys(hwaddr addr);
> +uint32_t lduw_le_phys(hwaddr addr);
> +uint32_t lduw_be_phys(hwaddr addr);
> +uint32_t ldl_le_phys(hwaddr addr);
> +uint32_t ldl_be_phys(hwaddr addr);
> +uint64_t ldq_le_phys(hwaddr addr);
> +uint64_t ldq_be_phys(hwaddr addr);
> +void stb_phys(hwaddr addr, uint32_t val);
> +void stw_le_phys(hwaddr addr, uint32_t val);
> +void stw_be_phys(hwaddr addr, uint32_t val);
> +void stl_le_phys(hwaddr addr, uint32_t val);
> +void stl_be_phys(hwaddr addr, uint32_t val);
> +void stq_le_phys(hwaddr addr, uint64_t val);
> +void stq_be_phys(hwaddr addr, uint64_t val);
>  
>  #ifdef NEED_CPU_H
> -uint32_t lduw_phys(target_phys_addr_t addr);
> -uint32_t ldl_phys(target_phys_addr_t addr);
> -uint64_t ldq_phys(target_phys_addr_t addr);
> -void stl_phys_notdirty(target_phys_addr_t addr, uint32_t val);
> -void stq_phys_notdirty(target_phys_addr_t addr, uint64_t val);
> -void stw_phys(target_phys_addr_t addr, uint32_t val);
> -void stl_phys(target_phys_addr_t addr, uint32_t val);
> -void stq_phys(target_phys_addr_t addr, uint64_t val);
> +uint32_t lduw_phys(hwaddr addr);
> +uint32_t ldl_phys(hwaddr addr);
> +uint64_t ldq_phys(hwaddr addr);
> +void stl_phys_notdirty(hwaddr addr, uint32_t val);
> +void stq_phys_notdirty(hwaddr addr, uint64_t val);
> +void stw_phys(hwaddr addr, uint32_t val);
> +void stl_phys(hwaddr addr, uint32_t val);
> +void stq_phys(hwaddr addr, uint64_t val);
>  #endif
>  
> -void cpu_physical_memory_write_rom(target_phys_addr_t addr,
> +void cpu_physical_memory_write_rom(hwaddr addr,
>                                     const uint8_t *buf, int len);
>  
>  extern struct MemoryRegion io_mem_ram;
> diff --git a/cpu-defs.h b/cpu-defs.h
> index 4018b88..a796577 100644
> --- a/cpu-defs.h
> +++ b/cpu-defs.h
> @@ -29,7 +29,7 @@
>  #include <signal.h>
>  #include "osdep.h"
>  #include "qemu-queue.h"
> -#include "targphys.h"
> +#include "hwaddr.h"
>  
>  #ifndef TARGET_LONG_BITS
>  #error TARGET_LONG_BITS must be defined before including this header
> @@ -111,7 +111,7 @@ extern int CPUTLBEntry_wrong_size[sizeof(CPUTLBEntry) == (1 << CPU_TLB_ENTRY_BIT
>  #define CPU_COMMON_TLB \
>      /* The meaning of the MMU modes is defined in the target code. */   \
>      CPUTLBEntry tlb_table[NB_MMU_MODES][CPU_TLB_SIZE];                  \
> -    target_phys_addr_t iotlb[NB_MMU_MODES][CPU_TLB_SIZE];               \
> +    hwaddr iotlb[NB_MMU_MODES][CPU_TLB_SIZE];               \
>      target_ulong tlb_flush_addr;                                        \
>      target_ulong tlb_flush_mask;
>  
> diff --git a/cputlb.c b/cputlb.c
> index 9027557..d6d0372 100644
> --- a/cputlb.c
> +++ b/cputlb.c
> @@ -237,7 +237,7 @@ static void tlb_add_large_page(CPUArchState *env, target_ulong vaddr,
>     is permitted. Only a single TARGET_PAGE_SIZE region is mapped, the
>     supplied size is only used by tlb_flush_page.  */
>  void tlb_set_page(CPUArchState *env, target_ulong vaddr,
> -                  target_phys_addr_t paddr, int prot,
> +                  hwaddr paddr, int prot,
>                    int mmu_idx, target_ulong size)
>  {
>      MemoryRegionSection *section;
> @@ -246,7 +246,7 @@ void tlb_set_page(CPUArchState *env, target_ulong vaddr,
>      target_ulong code_address;
>      uintptr_t addend;
>      CPUTLBEntry *te;
> -    target_phys_addr_t iotlb;
> +    hwaddr iotlb;
>  
>      assert(size >= TARGET_PAGE_SIZE);
>      if (size != TARGET_PAGE_SIZE) {
> diff --git a/cputlb.h b/cputlb.h
> index d537b77..733c885 100644
> --- a/cputlb.h
> +++ b/cputlb.h
> @@ -27,17 +27,17 @@ void tlb_unprotect_code_phys(CPUArchState *env, ram_addr_t ram_addr,
>  void tlb_reset_dirty_range(CPUTLBEntry *tlb_entry, uintptr_t start,
>                             uintptr_t length);
>  MemoryRegionSection *phys_page_find(struct AddressSpaceDispatch *d,
> -                                    target_phys_addr_t index);
> +                                    hwaddr index);
>  void cpu_tlb_reset_dirty_all(ram_addr_t start1, ram_addr_t length);
>  void tlb_set_dirty(CPUArchState *env, target_ulong vaddr);
>  extern int tlb_flush_count;
>  
>  /* exec.c */
>  void tb_flush_jmp_cache(CPUArchState *env, target_ulong addr);
> -target_phys_addr_t memory_region_section_get_iotlb(CPUArchState *env,
> +hwaddr memory_region_section_get_iotlb(CPUArchState *env,
>                                                     MemoryRegionSection *section,
>                                                     target_ulong vaddr,
> -                                                   target_phys_addr_t paddr,
> +                                                   hwaddr paddr,
>                                                     int prot,
>                                                     target_ulong *address);
>  bool memory_region_is_unassigned(MemoryRegion *mr);
> diff --git a/disas.h b/disas.h
> index 3ab42af..a8a0974 100644
> --- a/disas.h
> +++ b/disas.h
> @@ -22,7 +22,7 @@ struct elf64_sym;
>  #if defined(CONFIG_USER_ONLY)
>  typedef const char *(*lookup_symbol_t)(struct syminfo *s, target_ulong orig_addr);
>  #else
> -typedef const char *(*lookup_symbol_t)(struct syminfo *s, target_phys_addr_t orig_addr);
> +typedef const char *(*lookup_symbol_t)(struct syminfo *s, hwaddr orig_addr);
>  #endif
>  
>  struct syminfo {
> diff --git a/dma-helpers.c b/dma-helpers.c
> index 3f09dcb..0c18e9e 100644
> --- a/dma-helpers.c
> +++ b/dma-helpers.c
> @@ -281,7 +281,7 @@ void dma_acct_start(BlockDriverState *bs, BlockAcctCookie *cookie,
>  bool iommu_dma_memory_valid(DMAContext *dma, dma_addr_t addr, dma_addr_t len,
>                              DMADirection dir)
>  {
> -    target_phys_addr_t paddr, plen;
> +    hwaddr paddr, plen;
>  
>  #ifdef DEBUG_IOMMU
>      fprintf(stderr, "dma_memory_check context=%p addr=0x" DMA_ADDR_FMT
> @@ -308,7 +308,7 @@ bool iommu_dma_memory_valid(DMAContext *dma, dma_addr_t addr, dma_addr_t len,
>  int iommu_dma_memory_rw(DMAContext *dma, dma_addr_t addr,
>                          void *buf, dma_addr_t len, DMADirection dir)
>  {
> -    target_phys_addr_t paddr, plen;
> +    hwaddr paddr, plen;
>      int err;
>  
>  #ifdef DEBUG_IOMMU
> @@ -346,7 +346,7 @@ int iommu_dma_memory_rw(DMAContext *dma, dma_addr_t addr,
>  int iommu_dma_memory_set(DMAContext *dma, dma_addr_t addr, uint8_t c,
>                           dma_addr_t len)
>  {
> -    target_phys_addr_t paddr, plen;
> +    hwaddr paddr, plen;
>      int err;
>  
>  #ifdef DEBUG_IOMMU
> @@ -392,7 +392,7 @@ void *iommu_dma_memory_map(DMAContext *dma, dma_addr_t addr, dma_addr_t *len,
>                             DMADirection dir)
>  {
>      int err;
> -    target_phys_addr_t paddr, plen;
> +    hwaddr paddr, plen;
>      void *buf;
>  
>      if (dma->map) {
> diff --git a/dma.h b/dma.h
> index 1bd6f4a..91ccdb5 100644
> --- a/dma.h
> +++ b/dma.h
> @@ -48,8 +48,8 @@ typedef uint64_t dma_addr_t;
>  
>  typedef int DMATranslateFunc(DMAContext *dma,
>                               dma_addr_t addr,
> -                             target_phys_addr_t *paddr,
> -                             target_phys_addr_t *len,
> +                             hwaddr *paddr,
> +                             hwaddr *len,
>                               DMADirection dir);
>  typedef void* DMAMapFunc(DMAContext *dma,
>                           dma_addr_t addr,
> @@ -177,7 +177,7 @@ static inline void *dma_memory_map(DMAContext *dma,
>                                     DMADirection dir)
>  {
>      if (!dma_has_iommu(dma)) {
> -        target_phys_addr_t xlen = *len;
> +        hwaddr xlen = *len;
>          void *p;
>  
>          p = address_space_map(dma->as, addr, &xlen, dir == DMA_DIRECTION_FROM_DEVICE);
> @@ -196,7 +196,7 @@ static inline void dma_memory_unmap(DMAContext *dma,
>                                      DMADirection dir, dma_addr_t access_len)
>  {
>      if (!dma_has_iommu(dma)) {
> -        address_space_unmap(dma->as, buffer, (target_phys_addr_t)len,
> +        address_space_unmap(dma->as, buffer, (hwaddr)len,
>                              dir == DMA_DIRECTION_FROM_DEVICE, access_len);
>      } else {
>          iommu_dma_memory_unmap(dma, buffer, len, dir, access_len);
> diff --git a/dump.c b/dump.c
> index 6b7c127..5640c2c 100644
> --- a/dump.c
> +++ b/dump.c
> @@ -15,7 +15,7 @@
>  #include "elf.h"
>  #include "cpu.h"
>  #include "cpu-all.h"
> -#include "targphys.h"
> +#include "hwaddr.h"
>  #include "monitor.h"
>  #include "kvm.h"
>  #include "dump.h"
> @@ -66,7 +66,7 @@ static uint64_t cpu_convert_to_target64(uint64_t val, int endian)
>      bool have_section;
>      bool resume;
>      size_t note_size;
> -    target_phys_addr_t memory_offset;
> +    hwaddr memory_offset;
>      int fd;
>  
>      RAMBlock *block;
> @@ -187,7 +187,7 @@ static int write_elf32_header(DumpState *s)
>  }
>  
>  static int write_elf64_load(DumpState *s, MemoryMapping *memory_mapping,
> -                            int phdr_index, target_phys_addr_t offset)
> +                            int phdr_index, hwaddr offset)
>  {
>      Elf64_Phdr phdr;
>      int ret;
> @@ -216,7 +216,7 @@ static int write_elf64_load(DumpState *s, MemoryMapping *memory_mapping,
>  }
>  
>  static int write_elf32_load(DumpState *s, MemoryMapping *memory_mapping,
> -                            int phdr_index, target_phys_addr_t offset)
> +                            int phdr_index, hwaddr offset)
>  {
>      Elf32_Phdr phdr;
>      int ret;
> @@ -248,7 +248,7 @@ static int write_elf64_note(DumpState *s)
>  {
>      Elf64_Phdr phdr;
>      int endian = s->dump_info.d_endian;
> -    target_phys_addr_t begin = s->memory_offset - s->note_size;
> +    hwaddr begin = s->memory_offset - s->note_size;
>      int ret;
>  
>      memset(&phdr, 0, sizeof(Elf64_Phdr));
> @@ -296,7 +296,7 @@ static int write_elf64_notes(DumpState *s)
>  
>  static int write_elf32_note(DumpState *s)
>  {
> -    target_phys_addr_t begin = s->memory_offset - s->note_size;
> +    hwaddr begin = s->memory_offset - s->note_size;
>      Elf32_Phdr phdr;
>      int endian = s->dump_info.d_endian;
>      int ret;
> @@ -414,11 +414,11 @@ static int write_memory(DumpState *s, RAMBlock *block, ram_addr_t start,
>  }
>  
>  /* get the memory's offset in the vmcore */
> -static target_phys_addr_t get_offset(target_phys_addr_t phys_addr,
> +static hwaddr get_offset(hwaddr phys_addr,
>                                       DumpState *s)
>  {
>      RAMBlock *block;
> -    target_phys_addr_t offset = s->memory_offset;
> +    hwaddr offset = s->memory_offset;
>      int64_t size_in_block, start;
>  
>      if (s->has_filter) {
> @@ -463,7 +463,7 @@ static target_phys_addr_t get_offset(target_phys_addr_t phys_addr,
>  
>  static int write_elf_loads(DumpState *s)
>  {
> -    target_phys_addr_t offset;
> +    hwaddr offset;
>      MemoryMapping *memory_mapping;
>      uint32_t phdr_index = 1;
>      int ret;
> diff --git a/exec-all.h b/exec-all.h
> index 16caf49..2ea0e4f 100644
> --- a/exec-all.h
> +++ b/exec-all.h
> @@ -103,9 +103,9 @@ void tb_invalidate_phys_range(tb_page_addr_t start, tb_page_addr_t end,
>  void tlb_flush_page(CPUArchState *env, target_ulong addr);
>  void tlb_flush(CPUArchState *env, int flush_global);
>  void tlb_set_page(CPUArchState *env, target_ulong vaddr,
> -                  target_phys_addr_t paddr, int prot,
> +                  hwaddr paddr, int prot,
>                    int mmu_idx, target_ulong size);
> -void tb_invalidate_phys_addr(target_phys_addr_t addr);
> +void tb_invalidate_phys_addr(hwaddr addr);
>  #else
>  static inline void tlb_flush_page(CPUArchState *env, target_ulong addr)
>  {
> @@ -312,10 +312,10 @@ extern uintptr_t tci_tb_ptr;
>  
>  #if !defined(CONFIG_USER_ONLY)
>  
> -struct MemoryRegion *iotlb_to_region(target_phys_addr_t index);
> -uint64_t io_mem_read(struct MemoryRegion *mr, target_phys_addr_t addr,
> +struct MemoryRegion *iotlb_to_region(hwaddr index);
> +uint64_t io_mem_read(struct MemoryRegion *mr, hwaddr addr,
>                       unsigned size);
> -void io_mem_write(struct MemoryRegion *mr, target_phys_addr_t addr,
> +void io_mem_write(struct MemoryRegion *mr, hwaddr addr,
>                    uint64_t value, unsigned size);
>  
>  void tlb_fill(CPUArchState *env1, target_ulong addr, int is_write, int mmu_idx,
> diff --git a/exec.c b/exec.c
> index 750008c..b0ed593 100644
> --- a/exec.c
> +++ b/exec.c
> @@ -398,13 +398,13 @@ static void phys_map_nodes_reset(void)
>  }
>  
>  
> -static void phys_page_set_level(PhysPageEntry *lp, target_phys_addr_t *index,
> -                                target_phys_addr_t *nb, uint16_t leaf,
> +static void phys_page_set_level(PhysPageEntry *lp, hwaddr *index,
> +                                hwaddr *nb, uint16_t leaf,
>                                  int level)
>  {
>      PhysPageEntry *p;
>      int i;
> -    target_phys_addr_t step = (target_phys_addr_t)1 << (level * L2_BITS);
> +    hwaddr step = (hwaddr)1 << (level * L2_BITS);
>  
>      if (!lp->is_leaf && lp->ptr == PHYS_MAP_NODE_NIL) {
>          lp->ptr = phys_map_node_alloc();
> @@ -434,7 +434,7 @@ static void phys_page_set_level(PhysPageEntry *lp, target_phys_addr_t *index,
>  }
>  
>  static void phys_page_set(AddressSpaceDispatch *d,
> -                          target_phys_addr_t index, target_phys_addr_t nb,
> +                          hwaddr index, hwaddr nb,
>                            uint16_t leaf)
>  {
>      /* Wildly overreserve - it doesn't matter much. */
> @@ -443,7 +443,7 @@ static void phys_page_set(AddressSpaceDispatch *d,
>      phys_page_set_level(&d->phys_map, &index, &nb, leaf, P_L2_LEVELS - 1);
>  }
>  
> -MemoryRegionSection *phys_page_find(AddressSpaceDispatch *d, target_phys_addr_t index)
> +MemoryRegionSection *phys_page_find(AddressSpaceDispatch *d, hwaddr index)
>  {
>      PhysPageEntry lp = d->phys_map;
>      PhysPageEntry *p;
> @@ -1473,7 +1473,7 @@ static void breakpoint_invalidate(CPUArchState *env, target_ulong pc)
>      tb_invalidate_phys_page_range(pc, pc + 1, 0);
>  }
>  #else
> -void tb_invalidate_phys_addr(target_phys_addr_t addr)
> +void tb_invalidate_phys_addr(hwaddr addr)
>  {
>      ram_addr_t ram_addr;
>      MemoryRegionSection *section;
> @@ -1866,14 +1866,14 @@ int cpu_physical_memory_set_dirty_tracking(int enable)
>      return ret;
>  }
>  
> -target_phys_addr_t memory_region_section_get_iotlb(CPUArchState *env,
> +hwaddr memory_region_section_get_iotlb(CPUArchState *env,
>                                                     MemoryRegionSection *section,
>                                                     target_ulong vaddr,
> -                                                   target_phys_addr_t paddr,
> +                                                   hwaddr paddr,
>                                                     int prot,
>                                                     target_ulong *address)
>  {
> -    target_phys_addr_t iotlb;
> +    hwaddr iotlb;
>      CPUWatchpoint *wp;
>  
>      if (memory_region_is_ram(section->mr)) {
> @@ -2176,13 +2176,13 @@ int page_unprotect(target_ulong address, uintptr_t pc, void *puc)
>  #define SUBPAGE_IDX(addr) ((addr) & ~TARGET_PAGE_MASK)
>  typedef struct subpage_t {
>      MemoryRegion iomem;
> -    target_phys_addr_t base;
> +    hwaddr base;
>      uint16_t sub_section[TARGET_PAGE_SIZE];
>  } subpage_t;
>  
>  static int subpage_register (subpage_t *mmio, uint32_t start, uint32_t end,
>                               uint16_t section);
> -static subpage_t *subpage_init(target_phys_addr_t base);
> +static subpage_t *subpage_init(hwaddr base);
>  static void destroy_page_desc(uint16_t section_index)
>  {
>      MemoryRegionSection *section = &phys_sections[section_index];
> @@ -2241,14 +2241,14 @@ static void phys_sections_clear(void)
>  static void register_subpage(AddressSpaceDispatch *d, MemoryRegionSection *section)
>  {
>      subpage_t *subpage;
> -    target_phys_addr_t base = section->offset_within_address_space
> +    hwaddr base = section->offset_within_address_space
>          & TARGET_PAGE_MASK;
>      MemoryRegionSection *existing = phys_page_find(d, base >> TARGET_PAGE_BITS);
>      MemoryRegionSection subsection = {
>          .offset_within_address_space = base,
>          .size = TARGET_PAGE_SIZE,
>      };
> -    target_phys_addr_t start, end;
> +    hwaddr start, end;
>  
>      assert(existing->mr->subpage || existing->mr == &io_mem_unassigned);
>  
> @@ -2268,9 +2268,9 @@ static void register_subpage(AddressSpaceDispatch *d, MemoryRegionSection *secti
>  
>  static void register_multipage(AddressSpaceDispatch *d, MemoryRegionSection *section)
>  {
> -    target_phys_addr_t start_addr = section->offset_within_address_space;
> +    hwaddr start_addr = section->offset_within_address_space;
>      ram_addr_t size = section->size;
> -    target_phys_addr_t addr;
> +    hwaddr addr;
>      uint16_t section_index = phys_section_add(section);
>  
>      assert(size);
> @@ -2836,7 +2836,7 @@ ram_addr_t qemu_ram_addr_from_host_nofail(void *ptr)
>      return ram_addr;
>  }
>  
> -static uint64_t unassigned_mem_read(void *opaque, target_phys_addr_t addr,
> +static uint64_t unassigned_mem_read(void *opaque, hwaddr addr,
>                                      unsigned size)
>  {
>  #ifdef DEBUG_UNASSIGNED
> @@ -2848,7 +2848,7 @@ static uint64_t unassigned_mem_read(void *opaque, target_phys_addr_t addr,
>      return 0;
>  }
>  
> -static void unassigned_mem_write(void *opaque, target_phys_addr_t addr,
> +static void unassigned_mem_write(void *opaque, hwaddr addr,
>                                   uint64_t val, unsigned size)
>  {
>  #ifdef DEBUG_UNASSIGNED
> @@ -2865,13 +2865,13 @@ static void unassigned_mem_write(void *opaque, target_phys_addr_t addr,
>      .endianness = DEVICE_NATIVE_ENDIAN,
>  };
>  
> -static uint64_t error_mem_read(void *opaque, target_phys_addr_t addr,
> +static uint64_t error_mem_read(void *opaque, hwaddr addr,
>                                 unsigned size)
>  {
>      abort();
>  }
>  
> -static void error_mem_write(void *opaque, target_phys_addr_t addr,
> +static void error_mem_write(void *opaque, hwaddr addr,
>                              uint64_t value, unsigned size)
>  {
>      abort();
> @@ -2889,7 +2889,7 @@ static void error_mem_write(void *opaque, target_phys_addr_t addr,
>      .endianness = DEVICE_NATIVE_ENDIAN,
>  };
>  
> -static void notdirty_mem_write(void *opaque, target_phys_addr_t ram_addr,
> +static void notdirty_mem_write(void *opaque, hwaddr ram_addr,
>                                 uint64_t val, unsigned size)
>  {
>      int dirty_flags;
> @@ -2976,7 +2976,7 @@ static void check_watchpoint(int offset, int len_mask, int flags)
>  /* Watchpoint access routines.  Watchpoints are inserted using TLB tricks,
>     so these check for a hit then pass through to the normal out-of-line
>     phys routines.  */
> -static uint64_t watch_mem_read(void *opaque, target_phys_addr_t addr,
> +static uint64_t watch_mem_read(void *opaque, hwaddr addr,
>                                 unsigned size)
>  {
>      check_watchpoint(addr & ~TARGET_PAGE_MASK, ~(size - 1), BP_MEM_READ);
> @@ -2988,7 +2988,7 @@ static uint64_t watch_mem_read(void *opaque, target_phys_addr_t addr,
>      }
>  }
>  
> -static void watch_mem_write(void *opaque, target_phys_addr_t addr,
> +static void watch_mem_write(void *opaque, hwaddr addr,
>                              uint64_t val, unsigned size)
>  {
>      check_watchpoint(addr & ~TARGET_PAGE_MASK, ~(size - 1), BP_MEM_WRITE);
> @@ -3012,7 +3012,7 @@ static void watch_mem_write(void *opaque, target_phys_addr_t addr,
>      .endianness = DEVICE_NATIVE_ENDIAN,
>  };
>  
> -static uint64_t subpage_read(void *opaque, target_phys_addr_t addr,
> +static uint64_t subpage_read(void *opaque, hwaddr addr,
>                               unsigned len)
>  {
>      subpage_t *mmio = opaque;
> @@ -3030,7 +3030,7 @@ static uint64_t subpage_read(void *opaque, target_phys_addr_t addr,
>      return io_mem_read(section->mr, addr, len);
>  }
>  
> -static void subpage_write(void *opaque, target_phys_addr_t addr,
> +static void subpage_write(void *opaque, hwaddr addr,
>                            uint64_t value, unsigned len)
>  {
>      subpage_t *mmio = opaque;
> @@ -3055,7 +3055,7 @@ static void subpage_write(void *opaque, target_phys_addr_t addr,
>      .endianness = DEVICE_NATIVE_ENDIAN,
>  };
>  
> -static uint64_t subpage_ram_read(void *opaque, target_phys_addr_t addr,
> +static uint64_t subpage_ram_read(void *opaque, hwaddr addr,
>                                   unsigned size)
>  {
>      ram_addr_t raddr = addr;
> @@ -3068,7 +3068,7 @@ static uint64_t subpage_ram_read(void *opaque, target_phys_addr_t addr,
>      }
>  }
>  
> -static void subpage_ram_write(void *opaque, target_phys_addr_t addr,
> +static void subpage_ram_write(void *opaque, hwaddr addr,
>                                uint64_t value, unsigned size)
>  {
>      ram_addr_t raddr = addr;
> @@ -3112,7 +3112,7 @@ static int subpage_register (subpage_t *mmio, uint32_t start, uint32_t end,
>      return 0;
>  }
>  
> -static subpage_t *subpage_init(target_phys_addr_t base)
> +static subpage_t *subpage_init(hwaddr base)
>  {
>      subpage_t *mmio;
>  
> @@ -3143,7 +3143,7 @@ static uint16_t dummy_section(MemoryRegion *mr)
>      return phys_section_add(&section);
>  }
>  
> -MemoryRegion *iotlb_to_region(target_phys_addr_t index)
> +MemoryRegion *iotlb_to_region(hwaddr index)
>  {
>      return phys_sections[index & ~TARGET_PAGE_MASK].mr;
>  }
> @@ -3333,8 +3333,8 @@ int cpu_memory_rw_debug(CPUArchState *env, target_ulong addr,
>  
>  #else
>  
> -static void invalidate_and_set_dirty(target_phys_addr_t addr,
> -                                     target_phys_addr_t length)
> +static void invalidate_and_set_dirty(hwaddr addr,
> +                                     hwaddr length)
>  {
>      if (!cpu_physical_memory_is_dirty(addr)) {
>          /* invalidate code */
> @@ -3345,14 +3345,14 @@ static void invalidate_and_set_dirty(target_phys_addr_t addr,
>      xen_modified_memory(addr, length);
>  }
>  
> -void address_space_rw(AddressSpace *as, target_phys_addr_t addr, uint8_t *buf,
> +void address_space_rw(AddressSpace *as, hwaddr addr, uint8_t *buf,
>                        int len, bool is_write)
>  {
>      AddressSpaceDispatch *d = as->dispatch;
>      int l;
>      uint8_t *ptr;
>      uint32_t val;
> -    target_phys_addr_t page;
> +    hwaddr page;
>      MemoryRegionSection *section;
>  
>      while (len > 0) {
> @@ -3364,7 +3364,7 @@ void address_space_rw(AddressSpace *as, target_phys_addr_t addr, uint8_t *buf,
>  
>          if (is_write) {
>              if (!memory_region_is_ram(section->mr)) {
> -                target_phys_addr_t addr1;
> +                hwaddr addr1;
>                  addr1 = memory_region_section_addr(section, addr);
>                  /* XXX: could force cpu_single_env to NULL to avoid
>                     potential bugs */
> @@ -3397,7 +3397,7 @@ void address_space_rw(AddressSpace *as, target_phys_addr_t addr, uint8_t *buf,
>          } else {
>              if (!(memory_region_is_ram(section->mr) ||
>                    memory_region_is_romd(section->mr))) {
> -                target_phys_addr_t addr1;
> +                hwaddr addr1;
>                  /* I/O case */
>                  addr1 = memory_region_section_addr(section, addr);
>                  if (l >= 4 && ((addr1 & 3) == 0)) {
> @@ -3431,7 +3431,7 @@ void address_space_rw(AddressSpace *as, target_phys_addr_t addr, uint8_t *buf,
>      }
>  }
>  
> -void address_space_write(AddressSpace *as, target_phys_addr_t addr,
> +void address_space_write(AddressSpace *as, hwaddr addr,
>                           const uint8_t *buf, int len)
>  {
>      address_space_rw(as, addr, (uint8_t *)buf, len, true);
> @@ -3444,26 +3444,26 @@ void address_space_write(AddressSpace *as, target_phys_addr_t addr,
>   * @addr: address within that address space
>   * @buf: buffer with the data transferred
>   */
> -void address_space_read(AddressSpace *as, target_phys_addr_t addr, uint8_t *buf, int len)
> +void address_space_read(AddressSpace *as, hwaddr addr, uint8_t *buf, int len)
>  {
>      address_space_rw(as, addr, buf, len, false);
>  }
>  
>  
> -void cpu_physical_memory_rw(target_phys_addr_t addr, uint8_t *buf,
> +void cpu_physical_memory_rw(hwaddr addr, uint8_t *buf,
>                              int len, int is_write)
>  {
>      return address_space_rw(&address_space_memory, addr, buf, len, is_write);
>  }
>  
>  /* used for ROM loading : can write in RAM and ROM */
> -void cpu_physical_memory_write_rom(target_phys_addr_t addr,
> +void cpu_physical_memory_write_rom(hwaddr addr,
>                                     const uint8_t *buf, int len)
>  {
>      AddressSpaceDispatch *d = address_space_memory.dispatch;
>      int l;
>      uint8_t *ptr;
> -    target_phys_addr_t page;
> +    hwaddr page;
>      MemoryRegionSection *section;
>  
>      while (len > 0) {
> @@ -3494,8 +3494,8 @@ void cpu_physical_memory_write_rom(target_phys_addr_t addr,
>  
>  typedef struct {
>      void *buffer;
> -    target_phys_addr_t addr;
> -    target_phys_addr_t len;
> +    hwaddr addr;
> +    hwaddr len;
>  } BounceBuffer;
>  
>  static BounceBuffer bounce;
> @@ -3546,15 +3546,15 @@ static void cpu_notify_map_clients(void)
>   * likely to succeed.
>   */
>  void *address_space_map(AddressSpace *as,
> -                        target_phys_addr_t addr,
> -                        target_phys_addr_t *plen,
> +                        hwaddr addr,
> +                        hwaddr *plen,
>                          bool is_write)
>  {
>      AddressSpaceDispatch *d = as->dispatch;
> -    target_phys_addr_t len = *plen;
> -    target_phys_addr_t todo = 0;
> +    hwaddr len = *plen;
> +    hwaddr todo = 0;
>      int l;
> -    target_phys_addr_t page;
> +    hwaddr page;
>      MemoryRegionSection *section;
>      ram_addr_t raddr = RAM_ADDR_MAX;
>      ram_addr_t rlen;
> @@ -3600,8 +3600,8 @@ void *address_space_map(AddressSpace *as,
>   * Will also mark the memory as dirty if is_write == 1.  access_len gives
>   * the amount of memory that was actually read or written by the caller.
>   */
> -void address_space_unmap(AddressSpace *as, void *buffer, target_phys_addr_t len,
> -                         int is_write, target_phys_addr_t access_len)
> +void address_space_unmap(AddressSpace *as, void *buffer, hwaddr len,
> +                         int is_write, hwaddr access_len)
>  {
>      if (buffer != bounce.buffer) {
>          if (is_write) {
> @@ -3629,21 +3629,21 @@ void address_space_unmap(AddressSpace *as, void *buffer, target_phys_addr_t len,
>      cpu_notify_map_clients();
>  }
>  
> -void *cpu_physical_memory_map(target_phys_addr_t addr,
> -                              target_phys_addr_t *plen,
> +void *cpu_physical_memory_map(hwaddr addr,
> +                              hwaddr *plen,
>                                int is_write)
>  {
>      return address_space_map(&address_space_memory, addr, plen, is_write);
>  }
>  
> -void cpu_physical_memory_unmap(void *buffer, target_phys_addr_t len,
> -                               int is_write, target_phys_addr_t access_len)
> +void cpu_physical_memory_unmap(void *buffer, hwaddr len,
> +                               int is_write, hwaddr access_len)
>  {
>      return address_space_unmap(&address_space_memory, buffer, len, is_write, access_len);
>  }
>  
>  /* warning: addr must be aligned */
> -static inline uint32_t ldl_phys_internal(target_phys_addr_t addr,
> +static inline uint32_t ldl_phys_internal(hwaddr addr,
>                                           enum device_endian endian)
>  {
>      uint8_t *ptr;
> @@ -3686,23 +3686,23 @@ static inline uint32_t ldl_phys_internal(target_phys_addr_t addr,
>      return val;
>  }
>  
> -uint32_t ldl_phys(target_phys_addr_t addr)
> +uint32_t ldl_phys(hwaddr addr)
>  {
>      return ldl_phys_internal(addr, DEVICE_NATIVE_ENDIAN);
>  }
>  
> -uint32_t ldl_le_phys(target_phys_addr_t addr)
> +uint32_t ldl_le_phys(hwaddr addr)
>  {
>      return ldl_phys_internal(addr, DEVICE_LITTLE_ENDIAN);
>  }
>  
> -uint32_t ldl_be_phys(target_phys_addr_t addr)
> +uint32_t ldl_be_phys(hwaddr addr)
>  {
>      return ldl_phys_internal(addr, DEVICE_BIG_ENDIAN);
>  }
>  
>  /* warning: addr must be aligned */
> -static inline uint64_t ldq_phys_internal(target_phys_addr_t addr,
> +static inline uint64_t ldq_phys_internal(hwaddr addr,
>                                           enum device_endian endian)
>  {
>      uint8_t *ptr;
> @@ -3745,23 +3745,23 @@ static inline uint64_t ldq_phys_internal(target_phys_addr_t addr,
>      return val;
>  }
>  
> -uint64_t ldq_phys(target_phys_addr_t addr)
> +uint64_t ldq_phys(hwaddr addr)
>  {
>      return ldq_phys_internal(addr, DEVICE_NATIVE_ENDIAN);
>  }
>  
> -uint64_t ldq_le_phys(target_phys_addr_t addr)
> +uint64_t ldq_le_phys(hwaddr addr)
>  {
>      return ldq_phys_internal(addr, DEVICE_LITTLE_ENDIAN);
>  }
>  
> -uint64_t ldq_be_phys(target_phys_addr_t addr)
> +uint64_t ldq_be_phys(hwaddr addr)
>  {
>      return ldq_phys_internal(addr, DEVICE_BIG_ENDIAN);
>  }
>  
>  /* XXX: optimize */
> -uint32_t ldub_phys(target_phys_addr_t addr)
> +uint32_t ldub_phys(hwaddr addr)
>  {
>      uint8_t val;
>      cpu_physical_memory_read(addr, &val, 1);
> @@ -3769,7 +3769,7 @@ uint32_t ldub_phys(target_phys_addr_t addr)
>  }
>  
>  /* warning: addr must be aligned */
> -static inline uint32_t lduw_phys_internal(target_phys_addr_t addr,
> +static inline uint32_t lduw_phys_internal(hwaddr addr,
>                                            enum device_endian endian)
>  {
>      uint8_t *ptr;
> @@ -3812,17 +3812,17 @@ static inline uint32_t lduw_phys_internal(target_phys_addr_t addr,
>      return val;
>  }
>  
> -uint32_t lduw_phys(target_phys_addr_t addr)
> +uint32_t lduw_phys(hwaddr addr)
>  {
>      return lduw_phys_internal(addr, DEVICE_NATIVE_ENDIAN);
>  }
>  
> -uint32_t lduw_le_phys(target_phys_addr_t addr)
> +uint32_t lduw_le_phys(hwaddr addr)
>  {
>      return lduw_phys_internal(addr, DEVICE_LITTLE_ENDIAN);
>  }
>  
> -uint32_t lduw_be_phys(target_phys_addr_t addr)
> +uint32_t lduw_be_phys(hwaddr addr)
>  {
>      return lduw_phys_internal(addr, DEVICE_BIG_ENDIAN);
>  }
> @@ -3830,7 +3830,7 @@ uint32_t lduw_be_phys(target_phys_addr_t addr)
>  /* warning: addr must be aligned. The ram page is not masked as dirty
>     and the code inside is not invalidated. It is useful if the dirty
>     bits are used to track modified PTEs */
> -void stl_phys_notdirty(target_phys_addr_t addr, uint32_t val)
> +void stl_phys_notdirty(hwaddr addr, uint32_t val)
>  {
>      uint8_t *ptr;
>      MemoryRegionSection *section;
> @@ -3862,7 +3862,7 @@ void stl_phys_notdirty(target_phys_addr_t addr, uint32_t val)
>      }
>  }
>  
> -void stq_phys_notdirty(target_phys_addr_t addr, uint64_t val)
> +void stq_phys_notdirty(hwaddr addr, uint64_t val)
>  {
>      uint8_t *ptr;
>      MemoryRegionSection *section;
> @@ -3890,7 +3890,7 @@ void stq_phys_notdirty(target_phys_addr_t addr, uint64_t val)
>  }
>  
>  /* warning: addr must be aligned */
> -static inline void stl_phys_internal(target_phys_addr_t addr, uint32_t val,
> +static inline void stl_phys_internal(hwaddr addr, uint32_t val,
>                                       enum device_endian endian)
>  {
>      uint8_t *ptr;
> @@ -3934,30 +3934,30 @@ static inline void stl_phys_internal(target_phys_addr_t addr, uint32_t val,
>      }
>  }
>  
> -void stl_phys(target_phys_addr_t addr, uint32_t val)
> +void stl_phys(hwaddr addr, uint32_t val)
>  {
>      stl_phys_internal(addr, val, DEVICE_NATIVE_ENDIAN);
>  }
>  
> -void stl_le_phys(target_phys_addr_t addr, uint32_t val)
> +void stl_le_phys(hwaddr addr, uint32_t val)
>  {
>      stl_phys_internal(addr, val, DEVICE_LITTLE_ENDIAN);
>  }
>  
> -void stl_be_phys(target_phys_addr_t addr, uint32_t val)
> +void stl_be_phys(hwaddr addr, uint32_t val)
>  {
>      stl_phys_internal(addr, val, DEVICE_BIG_ENDIAN);
>  }
>  
>  /* XXX: optimize */
> -void stb_phys(target_phys_addr_t addr, uint32_t val)
> +void stb_phys(hwaddr addr, uint32_t val)
>  {
>      uint8_t v = val;
>      cpu_physical_memory_write(addr, &v, 1);
>  }
>  
>  /* warning: addr must be aligned */
> -static inline void stw_phys_internal(target_phys_addr_t addr, uint32_t val,
> +static inline void stw_phys_internal(hwaddr addr, uint32_t val,
>                                       enum device_endian endian)
>  {
>      uint8_t *ptr;
> @@ -4001,35 +4001,35 @@ static inline void stw_phys_internal(target_phys_addr_t addr, uint32_t val,
>      }
>  }
>  
> -void stw_phys(target_phys_addr_t addr, uint32_t val)
> +void stw_phys(hwaddr addr, uint32_t val)
>  {
>      stw_phys_internal(addr, val, DEVICE_NATIVE_ENDIAN);
>  }
>  
> -void stw_le_phys(target_phys_addr_t addr, uint32_t val)
> +void stw_le_phys(hwaddr addr, uint32_t val)
>  {
>      stw_phys_internal(addr, val, DEVICE_LITTLE_ENDIAN);
>  }
>  
> -void stw_be_phys(target_phys_addr_t addr, uint32_t val)
> +void stw_be_phys(hwaddr addr, uint32_t val)
>  {
>      stw_phys_internal(addr, val, DEVICE_BIG_ENDIAN);
>  }
>  
>  /* XXX: optimize */
> -void stq_phys(target_phys_addr_t addr, uint64_t val)
> +void stq_phys(hwaddr addr, uint64_t val)
>  {
>      val = tswap64(val);
>      cpu_physical_memory_write(addr, &val, 8);
>  }
>  
> -void stq_le_phys(target_phys_addr_t addr, uint64_t val)
> +void stq_le_phys(hwaddr addr, uint64_t val)
>  {
>      val = cpu_to_le64(val);
>      cpu_physical_memory_write(addr, &val, 8);
>  }
>  
> -void stq_be_phys(target_phys_addr_t addr, uint64_t val)
> +void stq_be_phys(hwaddr addr, uint64_t val)
>  {
>      val = cpu_to_be64(val);
>      cpu_physical_memory_write(addr, &val, 8);
> @@ -4040,7 +4040,7 @@ int cpu_memory_rw_debug(CPUArchState *env, target_ulong addr,
>                          uint8_t *buf, int len, int is_write)
>  {
>      int l;
> -    target_phys_addr_t phys_addr;
> +    hwaddr phys_addr;
>      target_ulong page;
>  
>      while (len > 0) {
> @@ -4195,7 +4195,7 @@ bool virtio_is_big_endian(void)
>  #endif
>  
>  #ifndef CONFIG_USER_ONLY
> -bool cpu_physical_memory_is_io(target_phys_addr_t phys_addr)
> +bool cpu_physical_memory_is_io(hwaddr phys_addr)
>  {
>      MemoryRegionSection *section;
>  
> diff --git a/hw/a9mpcore.c b/hw/a9mpcore.c
> index ebd5b29..824ff0a 100644
> --- a/hw/a9mpcore.c
> +++ b/hw/a9mpcore.c
> @@ -26,7 +26,7 @@
>      uint32_t num_irq;
>  } a9mp_priv_state;
>  
> -static uint64_t a9_scu_read(void *opaque, target_phys_addr_t offset,
> +static uint64_t a9_scu_read(void *opaque, hwaddr offset,
>                              unsigned size)
>  {
>      a9mp_priv_state *s = (a9mp_priv_state *)opaque;
> @@ -57,7 +57,7 @@ static uint64_t a9_scu_read(void *opaque, target_phys_addr_t offset,
>      }
>  }
>  
> -static void a9_scu_write(void *opaque, target_phys_addr_t offset,
> +static void a9_scu_write(void *opaque, hwaddr offset,
>                           uint64_t value, unsigned size)
>  {
>      a9mp_priv_state *s = (a9mp_priv_state *)opaque;
> diff --git a/hw/alpha_pci.c b/hw/alpha_pci.c
> index 8079a46..7e7b1d2 100644
> --- a/hw/alpha_pci.c
> +++ b/hw/alpha_pci.c
> @@ -15,7 +15,7 @@
>  /* PCI IO reads/writes, to byte-word addressable memory.  */
>  /* ??? Doesn't handle multiple PCI busses.  */
>  
> -static uint64_t bw_io_read(void *opaque, target_phys_addr_t addr, unsigned size)
> +static uint64_t bw_io_read(void *opaque, hwaddr addr, unsigned size)
>  {
>      switch (size) {
>      case 1:
> @@ -28,7 +28,7 @@ static uint64_t bw_io_read(void *opaque, target_phys_addr_t addr, unsigned size)
>      abort();
>  }
>  
> -static void bw_io_write(void *opaque, target_phys_addr_t addr,
> +static void bw_io_write(void *opaque, hwaddr addr,
>                          uint64_t val, unsigned size)
>  {
>      switch (size) {
> @@ -57,14 +57,14 @@ static void bw_io_write(void *opaque, target_phys_addr_t addr,
>  };
>  
>  /* PCI config space reads/writes, to byte-word addressable memory.  */
> -static uint64_t bw_conf1_read(void *opaque, target_phys_addr_t addr,
> +static uint64_t bw_conf1_read(void *opaque, hwaddr addr,
>                                unsigned size)
>  {
>      PCIBus *b = opaque;
>      return pci_data_read(b, addr, size);
>  }
>  
> -static void bw_conf1_write(void *opaque, target_phys_addr_t addr,
> +static void bw_conf1_write(void *opaque, hwaddr addr,
>                             uint64_t val, unsigned size)
>  {
>      PCIBus *b = opaque;
> @@ -83,12 +83,12 @@ static void bw_conf1_write(void *opaque, target_phys_addr_t addr,
>  
>  /* PCI/EISA Interrupt Acknowledge Cycle.  */
>  
> -static uint64_t iack_read(void *opaque, target_phys_addr_t addr, unsigned size)
> +static uint64_t iack_read(void *opaque, hwaddr addr, unsigned size)
>  {
>      return pic_read_irq(isa_pic);
>  }
>  
> -static void special_write(void *opaque, target_phys_addr_t addr,
> +static void special_write(void *opaque, hwaddr addr,
>                            uint64_t val, unsigned size)
>  {
>      qemu_log("pci: special write cycle");
> diff --git a/hw/alpha_typhoon.c b/hw/alpha_typhoon.c
> index b7cf4e2..9b16d96 100644
> --- a/hw/alpha_typhoon.c
> +++ b/hw/alpha_typhoon.c
> @@ -70,7 +70,7 @@ static void cpu_irq_change(CPUAlphaState *env, uint64_t req)
>      }
>  }
>  
> -static uint64_t cchip_read(void *opaque, target_phys_addr_t addr, unsigned size)
> +static uint64_t cchip_read(void *opaque, hwaddr addr, unsigned size)
>  {
>      CPUAlphaState *env = cpu_single_env;
>      TyphoonState *s = opaque;
> @@ -203,13 +203,13 @@ static uint64_t cchip_read(void *opaque, target_phys_addr_t addr, unsigned size)
>      return ret;
>  }
>  
> -static uint64_t dchip_read(void *opaque, target_phys_addr_t addr, unsigned size)
> +static uint64_t dchip_read(void *opaque, hwaddr addr, unsigned size)
>  {
>      /* Skip this.  It's all related to DRAM timing and setup.  */
>      return 0;
>  }
>  
> -static uint64_t pchip_read(void *opaque, target_phys_addr_t addr, unsigned size)
> +static uint64_t pchip_read(void *opaque, hwaddr addr, unsigned size)
>  {
>      TyphoonState *s = opaque;
>      uint64_t ret = 0;
> @@ -306,7 +306,7 @@ static uint64_t pchip_read(void *opaque, target_phys_addr_t addr, unsigned size)
>      return ret;
>  }
>  
> -static void cchip_write(void *opaque, target_phys_addr_t addr,
> +static void cchip_write(void *opaque, hwaddr addr,
>                          uint64_t v32, unsigned size)
>  {
>      TyphoonState *s = opaque;
> @@ -463,13 +463,13 @@ static void cchip_write(void *opaque, target_phys_addr_t addr,
>      }
>  }
>  
> -static void dchip_write(void *opaque, target_phys_addr_t addr,
> +static void dchip_write(void *opaque, hwaddr addr,
>                          uint64_t val, unsigned size)
>  {
>      /* Skip this.  It's all related to DRAM timing and setup.  */
>  }
>  
> -static void pchip_write(void *opaque, target_phys_addr_t addr,
> +static void pchip_write(void *opaque, hwaddr addr,
>                          uint64_t v32, unsigned size)
>  {
>      TyphoonState *s = opaque;
> diff --git a/hw/an5206.c b/hw/an5206.c
> index 042c5fc..d887c0e 100644
> --- a/hw/an5206.c
> +++ b/hw/an5206.c
> @@ -27,7 +27,7 @@ static void an5206_init(QEMUMachineInitArgs *args)
>      CPUM68KState *env;
>      int kernel_size;
>      uint64_t elf_entry;
> -    target_phys_addr_t entry;
> +    hwaddr entry;
>      MemoryRegion *address_space_mem = get_system_memory();
>      MemoryRegion *ram = g_new(MemoryRegion, 1);
>      MemoryRegion *sram = g_new(MemoryRegion, 1);
> diff --git a/hw/apb_pci.c b/hw/apb_pci.c
> index c28411a..054814f 100644
> --- a/hw/apb_pci.c
> +++ b/hw/apb_pci.c
> @@ -87,7 +87,7 @@
>  
>  static void pci_apb_set_irq(void *opaque, int irq_num, int level);
>  
> -static void apb_config_writel (void *opaque, target_phys_addr_t addr,
> +static void apb_config_writel (void *opaque, hwaddr addr,
>                                 uint64_t val, unsigned size)
>  {
>      APBState *s = opaque;
> @@ -152,7 +152,7 @@ static void apb_config_writel (void *opaque, target_phys_addr_t addr,
>  }
>  
>  static uint64_t apb_config_readl (void *opaque,
> -                                  target_phys_addr_t addr, unsigned size)
> +                                  hwaddr addr, unsigned size)
>  {
>      APBState *s = opaque;
>      uint32_t val;
> @@ -212,7 +212,7 @@ static uint64_t apb_config_readl (void *opaque,
>      .endianness = DEVICE_NATIVE_ENDIAN,
>  };
>  
> -static void apb_pci_config_write(void *opaque, target_phys_addr_t addr,
> +static void apb_pci_config_write(void *opaque, hwaddr addr,
>                                   uint64_t val, unsigned size)
>  {
>      APBState *s = opaque;
> @@ -222,7 +222,7 @@ static void apb_pci_config_write(void *opaque, target_phys_addr_t addr,
>      pci_data_write(s->bus, addr, val, size);
>  }
>  
> -static uint64_t apb_pci_config_read(void *opaque, target_phys_addr_t addr,
> +static uint64_t apb_pci_config_read(void *opaque, hwaddr addr,
>                                      unsigned size)
>  {
>      uint32_t ret;
> @@ -234,25 +234,25 @@ static uint64_t apb_pci_config_read(void *opaque, target_phys_addr_t addr,
>      return ret;
>  }
>  
> -static void pci_apb_iowriteb (void *opaque, target_phys_addr_t addr,
> +static void pci_apb_iowriteb (void *opaque, hwaddr addr,
>                                    uint32_t val)
>  {
>      cpu_outb(addr & IOPORTS_MASK, val);
>  }
>  
> -static void pci_apb_iowritew (void *opaque, target_phys_addr_t addr,
> +static void pci_apb_iowritew (void *opaque, hwaddr addr,
>                                    uint32_t val)
>  {
>      cpu_outw(addr & IOPORTS_MASK, bswap16(val));
>  }
>  
> -static void pci_apb_iowritel (void *opaque, target_phys_addr_t addr,
> +static void pci_apb_iowritel (void *opaque, hwaddr addr,
>                                  uint32_t val)
>  {
>      cpu_outl(addr & IOPORTS_MASK, bswap32(val));
>  }
>  
> -static uint32_t pci_apb_ioreadb (void *opaque, target_phys_addr_t addr)
> +static uint32_t pci_apb_ioreadb (void *opaque, hwaddr addr)
>  {
>      uint32_t val;
>  
> @@ -260,7 +260,7 @@ static uint32_t pci_apb_ioreadb (void *opaque, target_phys_addr_t addr)
>      return val;
>  }
>  
> -static uint32_t pci_apb_ioreadw (void *opaque, target_phys_addr_t addr)
> +static uint32_t pci_apb_ioreadw (void *opaque, hwaddr addr)
>  {
>      uint32_t val;
>  
> @@ -268,7 +268,7 @@ static uint32_t pci_apb_ioreadw (void *opaque, target_phys_addr_t addr)
>      return val;
>  }
>  
> -static uint32_t pci_apb_ioreadl (void *opaque, target_phys_addr_t addr)
> +static uint32_t pci_apb_ioreadl (void *opaque, hwaddr addr)
>  {
>      uint32_t val;
>  
> @@ -351,8 +351,8 @@ static int apb_pci_bridge_initfn(PCIDevice *dev)
>      return 0;
>  }
>  
> -PCIBus *pci_apb_init(target_phys_addr_t special_base,
> -                     target_phys_addr_t mem_base,
> +PCIBus *pci_apb_init(hwaddr special_base,
> +                     hwaddr mem_base,
>                       qemu_irq *ivec_irqs, PCIBus **bus2, PCIBus **bus3,
>                       qemu_irq **pbm_irqs)
>  {
> diff --git a/hw/apb_pci.h b/hw/apb_pci.h
> index 55f7c4c..736db61 100644
> --- a/hw/apb_pci.h
> +++ b/hw/apb_pci.h
> @@ -3,8 +3,8 @@
>  
>  #include "qemu-common.h"
>  
> -PCIBus *pci_apb_init(target_phys_addr_t special_base,
> -                     target_phys_addr_t mem_base,
> +PCIBus *pci_apb_init(hwaddr special_base,
> +                     hwaddr mem_base,
>                       qemu_irq *ivec_irqs, PCIBus **bus2, PCIBus **bus3,
>                       qemu_irq **pbm_irqs);
>  #endif
> diff --git a/hw/apic.c b/hw/apic.c
> index 385555e..49f0015 100644
> --- a/hw/apic.c
> +++ b/hw/apic.c
> @@ -630,25 +630,25 @@ static void apic_timer(void *opaque)
>      apic_timer_update(s, s->next_time);
>  }
>  
> -static uint32_t apic_mem_readb(void *opaque, target_phys_addr_t addr)
> +static uint32_t apic_mem_readb(void *opaque, hwaddr addr)
>  {
>      return 0;
>  }
>  
> -static uint32_t apic_mem_readw(void *opaque, target_phys_addr_t addr)
> +static uint32_t apic_mem_readw(void *opaque, hwaddr addr)
>  {
>      return 0;
>  }
>  
> -static void apic_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
> +static void apic_mem_writeb(void *opaque, hwaddr addr, uint32_t val)
>  {
>  }
>  
> -static void apic_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
> +static void apic_mem_writew(void *opaque, hwaddr addr, uint32_t val)
>  {
>  }
>  
> -static uint32_t apic_mem_readl(void *opaque, target_phys_addr_t addr)
> +static uint32_t apic_mem_readl(void *opaque, hwaddr addr)
>  {
>      DeviceState *d;
>      APICCommonState *s;
> @@ -732,7 +732,7 @@ static uint32_t apic_mem_readl(void *opaque, target_phys_addr_t addr)
>      return val;
>  }
>  
> -static void apic_send_msi(target_phys_addr_t addr, uint32_t data)
> +static void apic_send_msi(hwaddr addr, uint32_t data)
>  {
>      uint8_t dest = (addr & MSI_ADDR_DEST_ID_MASK) >> MSI_ADDR_DEST_ID_SHIFT;
>      uint8_t vector = (data & MSI_DATA_VECTOR_MASK) >> MSI_DATA_VECTOR_SHIFT;
> @@ -743,7 +743,7 @@ static void apic_send_msi(target_phys_addr_t addr, uint32_t data)
>      apic_deliver_irq(dest, dest_mode, delivery, vector, trigger_mode);
>  }
>  
> -static void apic_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
> +static void apic_mem_writel(void *opaque, hwaddr addr, uint32_t val)
>  {
>      DeviceState *d;
>      APICCommonState *s;
> diff --git a/hw/apic_common.c b/hw/apic_common.c
> index 371f95d..d68116d 100644
> --- a/hw/apic_common.c
> +++ b/hw/apic_common.c
> @@ -89,7 +89,7 @@ void apic_enable_tpr_access_reporting(DeviceState *d, bool enable)
>      }
>  }
>  
> -void apic_enable_vapic(DeviceState *d, target_phys_addr_t paddr)
> +void apic_enable_vapic(DeviceState *d, hwaddr paddr)
>  {
>      APICCommonState *s = DO_UPCAST(APICCommonState, busdev.qdev, d);
>      APICCommonClass *info = APIC_COMMON_GET_CLASS(s);
> diff --git a/hw/apic_internal.h b/hw/apic_internal.h
> index 4d8ff49..30932a3 100644
> --- a/hw/apic_internal.h
> +++ b/hw/apic_internal.h
> @@ -124,7 +124,7 @@ struct APICCommonState {
>  
>      uint32_t vapic_control;
>      DeviceState *vapic;
> -    target_phys_addr_t vapic_paddr; /* note: persistence via kvmvapic */
> +    hwaddr vapic_paddr; /* note: persistence via kvmvapic */
>  };
>  
>  typedef struct VAPICState {
> @@ -140,7 +140,7 @@ extern bool apic_report_tpr_access;
>  void apic_report_irq_delivered(int delivered);
>  bool apic_next_timer(APICCommonState *s, int64_t current_time);
>  void apic_enable_tpr_access_reporting(DeviceState *d, bool enable);
> -void apic_enable_vapic(DeviceState *d, target_phys_addr_t paddr);
> +void apic_enable_vapic(DeviceState *d, hwaddr paddr);
>  
>  void vapic_report_tpr_access(DeviceState *dev, void *cpu, target_ulong ip,
>                               TPRAccess access);
> diff --git a/hw/arm-misc.h b/hw/arm-misc.h
> index bdd8fec..d02f7f0 100644
> --- a/hw/arm-misc.h
> +++ b/hw/arm-misc.h
> @@ -30,15 +30,15 @@ struct arm_boot_info {
>      const char *kernel_cmdline;
>      const char *initrd_filename;
>      const char *dtb_filename;
> -    target_phys_addr_t loader_start;
> +    hwaddr loader_start;
>      /* multicore boards that use the default secondary core boot functions
>       * need to put the address of the secondary boot code, the boot reg,
>       * and the GIC address in the next 3 values, respectively. boards that
>       * have their own boot functions can use these values as they want.
>       */
> -    target_phys_addr_t smp_loader_start;
> -    target_phys_addr_t smp_bootreg_addr;
> -    target_phys_addr_t gic_cpu_if_addr;
> +    hwaddr smp_loader_start;
> +    hwaddr smp_bootreg_addr;
> +    hwaddr gic_cpu_if_addr;
>      int nb_cpus;
>      int board_id;
>      int (*atag_board)(const struct arm_boot_info *info, void *p);
> @@ -56,8 +56,8 @@ struct arm_boot_info {
>                                       const struct arm_boot_info *info);
>      /* Used internally by arm_boot.c */
>      int is_linux;
> -    target_phys_addr_t initrd_size;
> -    target_phys_addr_t entry;
> +    hwaddr initrd_size;
> +    hwaddr entry;
>  };
>  void arm_load_kernel(ARMCPU *cpu, struct arm_boot_info *info);
>  
> diff --git a/hw/arm11mpcore.c b/hw/arm11mpcore.c
> index 1bff3d3..105f158 100644
> --- a/hw/arm11mpcore.c
> +++ b/hw/arm11mpcore.c
> @@ -27,7 +27,7 @@
>  
>  /* Per-CPU private memory mapped IO.  */
>  
> -static uint64_t mpcore_scu_read(void *opaque, target_phys_addr_t offset,
> +static uint64_t mpcore_scu_read(void *opaque, hwaddr offset,
>                                  unsigned size)
>  {
>      mpcore_priv_state *s = (mpcore_priv_state *)opaque;
> @@ -48,7 +48,7 @@ static uint64_t mpcore_scu_read(void *opaque, target_phys_addr_t offset,
>      }
>  }
>  
> -static void mpcore_scu_write(void *opaque, target_phys_addr_t offset,
> +static void mpcore_scu_write(void *opaque, hwaddr offset,
>                               uint64_t value, unsigned size)
>  {
>      mpcore_priv_state *s = (mpcore_priv_state *)opaque;
> @@ -89,7 +89,7 @@ static void mpcore_priv_map_setup(mpcore_priv_state *s)
>       * at 0x200, 0x300...
>       */
>      for (i = 0; i < (s->num_cpu + 1); i++) {
> -        target_phys_addr_t offset = 0x100 + (i * 0x100);
> +        hwaddr offset = 0x100 + (i * 0x100);
>          memory_region_add_subregion(&s->container, offset,
>                                      sysbus_mmio_get_region(gicbusdev, i + 1));
>      }
> @@ -98,7 +98,7 @@ static void mpcore_priv_map_setup(mpcore_priv_state *s)
>       */
>      for (i = 0; i < (s->num_cpu + 1) * 2; i++) {
>          /* Timers at 0x600, 0x700, ...; watchdogs at 0x620, 0x720, ... */
> -        target_phys_addr_t offset = 0x600 + (i >> 1) * 0x100 + (i & 1) * 0x20;
> +        hwaddr offset = 0x600 + (i >> 1) * 0x100 + (i & 1) * 0x20;
>          memory_region_add_subregion(&s->container, offset,
>                                      sysbus_mmio_get_region(busdev, i));
>      }
> diff --git a/hw/arm_boot.c b/hw/arm_boot.c
> index a6e9143..09bf6c5 100644
> --- a/hw/arm_boot.c
> +++ b/hw/arm_boot.c
> @@ -89,8 +89,8 @@ static void default_reset_secondary(ARMCPU *cpu,
>  static void set_kernel_args(const struct arm_boot_info *info)
>  {
>      int initrd_size = info->initrd_size;
> -    target_phys_addr_t base = info->loader_start;
> -    target_phys_addr_t p;
> +    hwaddr base = info->loader_start;
> +    hwaddr p;
>  
>      p = base + KERNEL_ARGS_ADDR;
>      /* ATAG_CORE */
> @@ -142,10 +142,10 @@ static void set_kernel_args(const struct arm_boot_info *info)
>  
>  static void set_kernel_args_old(const struct arm_boot_info *info)
>  {
> -    target_phys_addr_t p;
> +    hwaddr p;
>      const char *s;
>      int initrd_size = info->initrd_size;
> -    target_phys_addr_t base = info->loader_start;
> +    hwaddr base = info->loader_start;
>  
>      /* see linux/include/asm-arm/setup.h */
>      p = base + KERNEL_ARGS_ADDR;
> @@ -213,7 +213,7 @@ static void set_kernel_args_old(const struct arm_boot_info *info)
>      }
>  }
>  
> -static int load_dtb(target_phys_addr_t addr, const struct arm_boot_info *binfo)
> +static int load_dtb(hwaddr addr, const struct arm_boot_info *binfo)
>  {
>  #ifdef CONFIG_FDT
>      uint32_t *mem_reg_property;
> @@ -342,7 +342,7 @@ void arm_load_kernel(ARMCPU *cpu, struct arm_boot_info *info)
>      int n;
>      int is_linux = 0;
>      uint64_t elf_entry;
> -    target_phys_addr_t entry;
> +    hwaddr entry;
>      int big_endian;
>      QemuOpts *machine_opts;
>  
> @@ -419,7 +419,7 @@ void arm_load_kernel(ARMCPU *cpu, struct arm_boot_info *info)
>           */
>          if (info->dtb_filename) {
>              /* Place the DTB after the initrd in memory */
> -            target_phys_addr_t dtb_start = TARGET_PAGE_ALIGN(info->loader_start
> +            hwaddr dtb_start = TARGET_PAGE_ALIGN(info->loader_start
>                                                               + INITRD_LOAD_ADDR
>                                                               + initrd_size);
>              if (load_dtb(dtb_start, info)) {
> diff --git a/hw/arm_gic.c b/hw/arm_gic.c
> index 56376c0..ce16e83 100644
> --- a/hw/arm_gic.c
> +++ b/hw/arm_gic.c
> @@ -212,7 +212,7 @@ void gic_complete_irq(GICState *s, int cpu, int irq)
>      }
>  }
>  
> -static uint32_t gic_dist_readb(void *opaque, target_phys_addr_t offset)
> +static uint32_t gic_dist_readb(void *opaque, hwaddr offset)
>  {
>      GICState *s = (GICState *)opaque;
>      uint32_t res;
> @@ -328,7 +328,7 @@ static uint32_t gic_dist_readb(void *opaque, target_phys_addr_t offset)
>      return 0;
>  }
>  
> -static uint32_t gic_dist_readw(void *opaque, target_phys_addr_t offset)
> +static uint32_t gic_dist_readw(void *opaque, hwaddr offset)
>  {
>      uint32_t val;
>      val = gic_dist_readb(opaque, offset);
> @@ -336,7 +336,7 @@ static uint32_t gic_dist_readw(void *opaque, target_phys_addr_t offset)
>      return val;
>  }
>  
> -static uint32_t gic_dist_readl(void *opaque, target_phys_addr_t offset)
> +static uint32_t gic_dist_readl(void *opaque, hwaddr offset)
>  {
>      uint32_t val;
>      val = gic_dist_readw(opaque, offset);
> @@ -344,7 +344,7 @@ static uint32_t gic_dist_readl(void *opaque, target_phys_addr_t offset)
>      return val;
>  }
>  
> -static void gic_dist_writeb(void *opaque, target_phys_addr_t offset,
> +static void gic_dist_writeb(void *opaque, hwaddr offset,
>                              uint32_t value)
>  {
>      GICState *s = (GICState *)opaque;
> @@ -490,14 +490,14 @@ static void gic_dist_writeb(void *opaque, target_phys_addr_t offset,
>      hw_error("gic_dist_writeb: Bad offset %x\n", (int)offset);
>  }
>  
> -static void gic_dist_writew(void *opaque, target_phys_addr_t offset,
> +static void gic_dist_writew(void *opaque, hwaddr offset,
>                              uint32_t value)
>  {
>      gic_dist_writeb(opaque, offset, value & 0xff);
>      gic_dist_writeb(opaque, offset + 1, value >> 8);
>  }
>  
> -static void gic_dist_writel(void *opaque, target_phys_addr_t offset,
> +static void gic_dist_writel(void *opaque, hwaddr offset,
>                              uint32_t value)
>  {
>      GICState *s = (GICState *)opaque;
> @@ -584,14 +584,14 @@ static void gic_cpu_write(GICState *s, int cpu, int offset, uint32_t value)
>  }
>  
>  /* Wrappers to read/write the GIC CPU interface for the current CPU */
> -static uint64_t gic_thiscpu_read(void *opaque, target_phys_addr_t addr,
> +static uint64_t gic_thiscpu_read(void *opaque, hwaddr addr,
>                                   unsigned size)
>  {
>      GICState *s = (GICState *)opaque;
>      return gic_cpu_read(s, gic_get_current_cpu(s), addr);
>  }
>  
> -static void gic_thiscpu_write(void *opaque, target_phys_addr_t addr,
> +static void gic_thiscpu_write(void *opaque, hwaddr addr,
>                                uint64_t value, unsigned size)
>  {
>      GICState *s = (GICState *)opaque;
> @@ -601,7 +601,7 @@ static void gic_thiscpu_write(void *opaque, target_phys_addr_t addr,
>  /* Wrappers to read/write the GIC CPU interface for a specific CPU.
>   * These just decode the opaque pointer into GICState* + cpu id.
>   */
> -static uint64_t gic_do_cpu_read(void *opaque, target_phys_addr_t addr,
> +static uint64_t gic_do_cpu_read(void *opaque, hwaddr addr,
>                                  unsigned size)
>  {
>      GICState **backref = (GICState **)opaque;
> @@ -610,7 +610,7 @@ static uint64_t gic_do_cpu_read(void *opaque, target_phys_addr_t addr,
>      return gic_cpu_read(s, id, addr);
>  }
>  
> -static void gic_do_cpu_write(void *opaque, target_phys_addr_t addr,
> +static void gic_do_cpu_write(void *opaque, hwaddr addr,
>                               uint64_t value, unsigned size)
>  {
>      GICState **backref = (GICState **)opaque;
> diff --git a/hw/arm_l2x0.c b/hw/arm_l2x0.c
> index de6a086..8f5921c 100644
> --- a/hw/arm_l2x0.c
> +++ b/hw/arm_l2x0.c
> @@ -51,7 +51,7 @@
>  };
>  
>  
> -static uint64_t l2x0_priv_read(void *opaque, target_phys_addr_t offset,
> +static uint64_t l2x0_priv_read(void *opaque, hwaddr offset,
>                                 unsigned size)
>  {
>      uint32_t cache_data;
> @@ -93,7 +93,7 @@ static uint64_t l2x0_priv_read(void *opaque, target_phys_addr_t offset,
>      return 0;
>  }
>  
> -static void l2x0_priv_write(void *opaque, target_phys_addr_t offset,
> +static void l2x0_priv_write(void *opaque, hwaddr offset,
>                              uint64_t value, unsigned size)
>  {
>      l2x0_state *s = (l2x0_state *)opaque;
> diff --git a/hw/arm_mptimer.c b/hw/arm_mptimer.c
> index fe43cbb..6790832 100644
> --- a/hw/arm_mptimer.c
> +++ b/hw/arm_mptimer.c
> @@ -92,7 +92,7 @@ static void timerblock_tick(void *opaque)
>      timerblock_update_irq(tb);
>  }
>  
> -static uint64_t timerblock_read(void *opaque, target_phys_addr_t addr,
> +static uint64_t timerblock_read(void *opaque, hwaddr addr,
>                                  unsigned size)
>  {
>      timerblock *tb = (timerblock *)opaque;
> @@ -120,7 +120,7 @@ static uint64_t timerblock_read(void *opaque, target_phys_addr_t addr,
>      }
>  }
>  
> -static void timerblock_write(void *opaque, target_phys_addr_t addr,
> +static void timerblock_write(void *opaque, hwaddr addr,
>                               uint64_t value, unsigned size)
>  {
>      timerblock *tb = (timerblock *)opaque;
> @@ -159,7 +159,7 @@ static void timerblock_write(void *opaque, target_phys_addr_t addr,
>  /* Wrapper functions to implement the "read timer/watchdog for
>   * the current CPU" memory regions.
>   */
> -static uint64_t arm_thistimer_read(void *opaque, target_phys_addr_t addr,
> +static uint64_t arm_thistimer_read(void *opaque, hwaddr addr,
>                                     unsigned size)
>  {
>      arm_mptimer_state *s = (arm_mptimer_state *)opaque;
> @@ -167,7 +167,7 @@ static uint64_t arm_thistimer_read(void *opaque, target_phys_addr_t addr,
>      return timerblock_read(&s->timerblock[id * 2], addr, size);
>  }
>  
> -static void arm_thistimer_write(void *opaque, target_phys_addr_t addr,
> +static void arm_thistimer_write(void *opaque, hwaddr addr,
>                                  uint64_t value, unsigned size)
>  {
>      arm_mptimer_state *s = (arm_mptimer_state *)opaque;
> @@ -175,7 +175,7 @@ static void arm_thistimer_write(void *opaque, target_phys_addr_t addr,
>      timerblock_write(&s->timerblock[id * 2], addr, value, size);
>  }
>  
> -static uint64_t arm_thiswdog_read(void *opaque, target_phys_addr_t addr,
> +static uint64_t arm_thiswdog_read(void *opaque, hwaddr addr,
>                                    unsigned size)
>  {
>      arm_mptimer_state *s = (arm_mptimer_state *)opaque;
> @@ -183,7 +183,7 @@ static uint64_t arm_thiswdog_read(void *opaque, target_phys_addr_t addr,
>      return timerblock_read(&s->timerblock[id * 2 + 1], addr, size);
>  }
>  
> -static void arm_thiswdog_write(void *opaque, target_phys_addr_t addr,
> +static void arm_thiswdog_write(void *opaque, hwaddr addr,
>                                 uint64_t value, unsigned size)
>  {
>      arm_mptimer_state *s = (arm_mptimer_state *)opaque;
> diff --git a/hw/arm_sysctl.c b/hw/arm_sysctl.c
> index 5f1237b..26318e1 100644
> --- a/hw/arm_sysctl.c
> +++ b/hw/arm_sysctl.c
> @@ -92,7 +92,7 @@ static void arm_sysctl_reset(DeviceState *d)
>      }
>  }
>  
> -static uint64_t arm_sysctl_read(void *opaque, target_phys_addr_t offset,
> +static uint64_t arm_sysctl_read(void *opaque, hwaddr offset,
>                                  unsigned size)
>  {
>      arm_sysctl_state *s = (arm_sysctl_state *)opaque;
> @@ -189,7 +189,7 @@ static uint64_t arm_sysctl_read(void *opaque, target_phys_addr_t offset,
>      }
>  }
>  
> -static void arm_sysctl_write(void *opaque, target_phys_addr_t offset,
> +static void arm_sysctl_write(void *opaque, hwaddr offset,
>                               uint64_t val, unsigned size)
>  {
>      arm_sysctl_state *s = (arm_sysctl_state *)opaque;
> diff --git a/hw/arm_timer.c b/hw/arm_timer.c
> index e3ecce2..2e13621 100644
> --- a/hw/arm_timer.c
> +++ b/hw/arm_timer.c
> @@ -45,7 +45,7 @@ static void arm_timer_update(arm_timer_state *s)
>      }
>  }
>  
> -static uint32_t arm_timer_read(void *opaque, target_phys_addr_t offset)
> +static uint32_t arm_timer_read(void *opaque, hwaddr offset)
>  {
>      arm_timer_state *s = (arm_timer_state *)opaque;
>  
> @@ -87,7 +87,7 @@ static void arm_timer_recalibrate(arm_timer_state *s, int reload)
>      ptimer_set_limit(s->timer, limit, reload);
>  }
>  
> -static void arm_timer_write(void *opaque, target_phys_addr_t offset,
> +static void arm_timer_write(void *opaque, hwaddr offset,
>                              uint32_t value)
>  {
>      arm_timer_state *s = (arm_timer_state *)opaque;
> @@ -202,7 +202,7 @@ static void sp804_set_irq(void *opaque, int irq, int level)
>      qemu_set_irq(s->irq, s->level[0] || s->level[1]);
>  }
>  
> -static uint64_t sp804_read(void *opaque, target_phys_addr_t offset,
> +static uint64_t sp804_read(void *opaque, hwaddr offset,
>                             unsigned size)
>  {
>      sp804_state *s = (sp804_state *)opaque;
> @@ -230,7 +230,7 @@ static uint64_t sp804_read(void *opaque, target_phys_addr_t offset,
>      return 0;
>  }
>  
> -static void sp804_write(void *opaque, target_phys_addr_t offset,
> +static void sp804_write(void *opaque, hwaddr offset,
>                          uint64_t value, unsigned size)
>  {
>      sp804_state *s = (sp804_state *)opaque;
> @@ -291,7 +291,7 @@ static int sp804_init(SysBusDevice *dev)
>      arm_timer_state *timer[3];
>  } icp_pit_state;
>  
> -static uint64_t icp_pit_read(void *opaque, target_phys_addr_t offset,
> +static uint64_t icp_pit_read(void *opaque, hwaddr offset,
>                               unsigned size)
>  {
>      icp_pit_state *s = (icp_pit_state *)opaque;
> @@ -306,7 +306,7 @@ static uint64_t icp_pit_read(void *opaque, target_phys_addr_t offset,
>      return arm_timer_read(s->timer[n], offset & 0xff);
>  }
>  
> -static void icp_pit_write(void *opaque, target_phys_addr_t offset,
> +static void icp_pit_write(void *opaque, hwaddr offset,
>                            uint64_t value, unsigned size)
>  {
>      icp_pit_state *s = (icp_pit_state *)opaque;
> diff --git a/hw/armv7m.c b/hw/armv7m.c
> index 9f66667..ce2ec9b 100644
> --- a/hw/armv7m.c
> +++ b/hw/armv7m.c
> @@ -25,14 +25,14 @@ static inline uint32_t bitband_addr(void * opaque, uint32_t addr)
>  
>  }
>  
> -static uint32_t bitband_readb(void *opaque, target_phys_addr_t offset)
> +static uint32_t bitband_readb(void *opaque, hwaddr offset)
>  {
>      uint8_t v;
>      cpu_physical_memory_read(bitband_addr(opaque, offset), &v, 1);
>      return (v & (1 << ((offset >> 2) & 7))) != 0;
>  }
>  
> -static void bitband_writeb(void *opaque, target_phys_addr_t offset,
> +static void bitband_writeb(void *opaque, hwaddr offset,
>                             uint32_t value)
>  {
>      uint32_t addr;
> @@ -48,7 +48,7 @@ static void bitband_writeb(void *opaque, target_phys_addr_t offset,
>      cpu_physical_memory_write(addr, &v, 1);
>  }
>  
> -static uint32_t bitband_readw(void *opaque, target_phys_addr_t offset)
> +static uint32_t bitband_readw(void *opaque, hwaddr offset)
>  {
>      uint32_t addr;
>      uint16_t mask;
> @@ -60,7 +60,7 @@ static uint32_t bitband_readw(void *opaque, target_phys_addr_t offset)
>      return (v & mask) != 0;
>  }
>  
> -static void bitband_writew(void *opaque, target_phys_addr_t offset,
> +static void bitband_writew(void *opaque, hwaddr offset,
>                             uint32_t value)
>  {
>      uint32_t addr;
> @@ -77,7 +77,7 @@ static void bitband_writew(void *opaque, target_phys_addr_t offset,
>      cpu_physical_memory_write(addr, (uint8_t *)&v, 2);
>  }
>  
> -static uint32_t bitband_readl(void *opaque, target_phys_addr_t offset)
> +static uint32_t bitband_readl(void *opaque, hwaddr offset)
>  {
>      uint32_t addr;
>      uint32_t mask;
> @@ -89,7 +89,7 @@ static uint32_t bitband_readl(void *opaque, target_phys_addr_t offset)
>      return (v & mask) != 0;
>  }
>  
> -static void bitband_writel(void *opaque, target_phys_addr_t offset,
> +static void bitband_writel(void *opaque, hwaddr offset,
>                             uint32_t value)
>  {
>      uint32_t addr;
> diff --git a/hw/armv7m_nvic.c b/hw/armv7m_nvic.c
> index c449e08..35c1aa6 100644
> --- a/hw/armv7m_nvic.c
> +++ b/hw/armv7m_nvic.c
> @@ -392,7 +392,7 @@ static void nvic_writel(void *opaque, uint32_t offset, uint32_t value)
>      }
>  }
>  
> -static uint64_t nvic_sysreg_read(void *opaque, target_phys_addr_t addr,
> +static uint64_t nvic_sysreg_read(void *opaque, hwaddr addr,
>                                   unsigned size)
>  {
>      /* At the moment we only support the ID registers for byte/word access.
> @@ -412,7 +412,7 @@ static uint64_t nvic_sysreg_read(void *opaque, target_phys_addr_t addr,
>      hw_error("NVIC: Bad read of size %d at offset 0x%x\n", size, offset);
>  }
>  
> -static void nvic_sysreg_write(void *opaque, target_phys_addr_t addr,
> +static void nvic_sysreg_write(void *opaque, hwaddr addr,
>                                uint64_t value, unsigned size)
>  {
>      uint32_t offset = addr;
> diff --git a/hw/axis_dev88.c b/hw/axis_dev88.c
> index 2fd7356..aa1ac9e 100644
> --- a/hw/axis_dev88.c
> +++ b/hw/axis_dev88.c
> @@ -47,7 +47,7 @@ struct nand_state_t
>  };
>  
>  static struct nand_state_t nand_state;
> -static uint64_t nand_read(void *opaque, target_phys_addr_t addr, unsigned size)
> +static uint64_t nand_read(void *opaque, hwaddr addr, unsigned size)
>  {
>      struct nand_state_t *s = opaque;
>      uint32_t r;
> @@ -62,7 +62,7 @@ static uint64_t nand_read(void *opaque, target_phys_addr_t addr, unsigned size)
>  }
>  
>  static void
> -nand_write(void *opaque, target_phys_addr_t addr, uint64_t value,
> +nand_write(void *opaque, hwaddr addr, uint64_t value,
>             unsigned size)
>  {
>      struct nand_state_t *s = opaque;
> @@ -166,7 +166,7 @@ static void tempsensor_clkedge(struct tempsensor_t *s,
>      uint32_t regs[0x5c / 4];
>  } gpio_state;
>  
> -static uint64_t gpio_read(void *opaque, target_phys_addr_t addr, unsigned size)
> +static uint64_t gpio_read(void *opaque, hwaddr addr, unsigned size)
>  {
>      struct gpio_state_t *s = opaque;
>      uint32_t r = 0;
> @@ -195,7 +195,7 @@ static uint64_t gpio_read(void *opaque, target_phys_addr_t addr, unsigned size)
>      D(printf("%s %x=%x\n", __func__, addr, r));
>  }
>  
> -static void gpio_write(void *opaque, target_phys_addr_t addr, uint64_t value,
> +static void gpio_write(void *opaque, hwaddr addr, uint64_t value,
>                         unsigned size)
>  {
>      struct gpio_state_t *s = opaque;
> diff --git a/hw/bonito.c b/hw/bonito.c
> index 6084ac4..0bf6d4a 100644
> --- a/hw/bonito.c
> +++ b/hw/bonito.c
> @@ -211,12 +211,12 @@
>      MemoryRegion iomem_ldma;
>      MemoryRegion iomem_cop;
>  
> -    target_phys_addr_t bonito_pciio_start;
> -    target_phys_addr_t bonito_pciio_length;
> +    hwaddr bonito_pciio_start;
> +    hwaddr bonito_pciio_length;
>      int bonito_pciio_handle;
>  
> -    target_phys_addr_t bonito_localio_start;
> -    target_phys_addr_t bonito_localio_length;
> +    hwaddr bonito_localio_start;
> +    hwaddr bonito_localio_length;
>      int bonito_localio_handle;
>  
>  } PCIBonitoState;
> @@ -232,7 +232,7 @@ struct BonitoState {
>      PCIBonitoState *pci_dev;
>  };
>  
> -static void bonito_writel(void *opaque, target_phys_addr_t addr,
> +static void bonito_writel(void *opaque, hwaddr addr,
>                            uint64_t val, unsigned size)
>  {
>      PCIBonitoState *s = opaque;
> @@ -295,7 +295,7 @@ static void bonito_writel(void *opaque, target_phys_addr_t addr,
>      }
>  }
>  
> -static uint64_t bonito_readl(void *opaque, target_phys_addr_t addr,
> +static uint64_t bonito_readl(void *opaque, hwaddr addr,
>                               unsigned size)
>  {
>      PCIBonitoState *s = opaque;
> @@ -322,7 +322,7 @@ static uint64_t bonito_readl(void *opaque, target_phys_addr_t addr,
>      },
>  };
>  
> -static void bonito_pciconf_writel(void *opaque, target_phys_addr_t addr,
> +static void bonito_pciconf_writel(void *opaque, hwaddr addr,
>                                    uint64_t val, unsigned size)
>  {
>      PCIBonitoState *s = opaque;
> @@ -332,7 +332,7 @@ static void bonito_pciconf_writel(void *opaque, target_phys_addr_t addr,
>      d->config_write(d, addr, val, 4);
>  }
>  
> -static uint64_t bonito_pciconf_readl(void *opaque, target_phys_addr_t addr,
> +static uint64_t bonito_pciconf_readl(void *opaque, hwaddr addr,
>                                       unsigned size)
>  {
>  
> @@ -355,7 +355,7 @@ static uint64_t bonito_pciconf_readl(void *opaque, target_phys_addr_t addr,
>      },
>  };
>  
> -static uint64_t bonito_ldma_readl(void *opaque, target_phys_addr_t addr,
> +static uint64_t bonito_ldma_readl(void *opaque, hwaddr addr,
>                                    unsigned size)
>  {
>      uint32_t val;
> @@ -366,7 +366,7 @@ static uint64_t bonito_ldma_readl(void *opaque, target_phys_addr_t addr,
>      return val;
>  }
>  
> -static void bonito_ldma_writel(void *opaque, target_phys_addr_t addr,
> +static void bonito_ldma_writel(void *opaque, hwaddr addr,
>                                 uint64_t val, unsigned size)
>  {
>      PCIBonitoState *s = opaque;
> @@ -384,7 +384,7 @@ static void bonito_ldma_writel(void *opaque, target_phys_addr_t addr,
>      },
>  };
>  
> -static uint64_t bonito_cop_readl(void *opaque, target_phys_addr_t addr,
> +static uint64_t bonito_cop_readl(void *opaque, hwaddr addr,
>                                   unsigned size)
>  {
>      uint32_t val;
> @@ -395,7 +395,7 @@ static uint64_t bonito_cop_readl(void *opaque, target_phys_addr_t addr,
>      return val;
>  }
>  
> -static void bonito_cop_writel(void *opaque, target_phys_addr_t addr,
> +static void bonito_cop_writel(void *opaque, hwaddr addr,
>                                uint64_t val, unsigned size)
>  {
>      PCIBonitoState *s = opaque;
> @@ -413,7 +413,7 @@ static void bonito_cop_writel(void *opaque, target_phys_addr_t addr,
>      },
>  };
>  
> -static uint32_t bonito_sbridge_pciaddr(void *opaque, target_phys_addr_t addr)
> +static uint32_t bonito_sbridge_pciaddr(void *opaque, hwaddr addr)
>  {
>      PCIBonitoState *s = opaque;
>      PCIHostState *phb = PCI_HOST_BRIDGE(s->pcihost);
> @@ -449,7 +449,7 @@ static uint32_t bonito_sbridge_pciaddr(void *opaque, target_phys_addr_t addr)
>      return pciaddr;
>  }
>  
> -static void bonito_spciconf_writeb(void *opaque, target_phys_addr_t addr,
> +static void bonito_spciconf_writeb(void *opaque, hwaddr addr,
>                                     uint32_t val)
>  {
>      PCIBonitoState *s = opaque;
> @@ -475,7 +475,7 @@ static void bonito_spciconf_writeb(void *opaque, target_phys_addr_t addr,
>      pci_set_word(d->config + PCI_STATUS, status);
>  }
>  
> -static void bonito_spciconf_writew(void *opaque, target_phys_addr_t addr,
> +static void bonito_spciconf_writew(void *opaque, hwaddr addr,
>                                     uint32_t val)
>  {
>      PCIBonitoState *s = opaque;
> @@ -503,7 +503,7 @@ static void bonito_spciconf_writew(void *opaque, target_phys_addr_t addr,
>      pci_set_word(d->config + PCI_STATUS, status);
>  }
>  
> -static void bonito_spciconf_writel(void *opaque, target_phys_addr_t addr,
> +static void bonito_spciconf_writel(void *opaque, hwaddr addr,
>                                     uint32_t val)
>  {
>      PCIBonitoState *s = opaque;
> @@ -531,7 +531,7 @@ static void bonito_spciconf_writel(void *opaque, target_phys_addr_t addr,
>      pci_set_word(d->config + PCI_STATUS, status);
>  }
>  
> -static uint32_t bonito_spciconf_readb(void *opaque, target_phys_addr_t addr)
> +static uint32_t bonito_spciconf_readb(void *opaque, hwaddr addr)
>  {
>      PCIBonitoState *s = opaque;
>      PCIDevice *d = PCI_DEVICE(s);
> @@ -557,7 +557,7 @@ static uint32_t bonito_spciconf_readb(void *opaque, target_phys_addr_t addr)
>      return pci_data_read(phb->bus, phb->config_reg, 1);
>  }
>  
> -static uint32_t bonito_spciconf_readw(void *opaque, target_phys_addr_t addr)
> +static uint32_t bonito_spciconf_readw(void *opaque, hwaddr addr)
>  {
>      PCIBonitoState *s = opaque;
>      PCIDevice *d = PCI_DEVICE(s);
> @@ -585,7 +585,7 @@ static uint32_t bonito_spciconf_readw(void *opaque, target_phys_addr_t addr)
>      return pci_data_read(phb->bus, phb->config_reg, 2);
>  }
>  
> -static uint32_t bonito_spciconf_readl(void *opaque, target_phys_addr_t addr)
> +static uint32_t bonito_spciconf_readl(void *opaque, hwaddr addr)
>  {
>      PCIBonitoState *s = opaque;
>      PCIDevice *d = PCI_DEVICE(s);
> diff --git a/hw/cadence_gem.c b/hw/cadence_gem.c
> index 967f625..0c037a2 100644
> --- a/hw/cadence_gem.c
> +++ b/hw/cadence_gem.c
> @@ -605,7 +605,7 @@ static int gem_mac_address_filter(GemState *s, const uint8_t *packet)
>  static ssize_t gem_receive(NetClientState *nc, const uint8_t *buf, size_t size)
>  {
>      unsigned    desc[2];
> -    target_phys_addr_t packet_desc_addr, last_desc_addr;
> +    hwaddr packet_desc_addr, last_desc_addr;
>      GemState *s;
>      unsigned   rxbufsize, bytes_to_copy;
>      unsigned   rxbuf_offset;
> @@ -824,7 +824,7 @@ static void gem_transmit_updatestats(GemState *s, const uint8_t *packet,
>  static void gem_transmit(GemState *s)
>  {
>      unsigned    desc[2];
> -    target_phys_addr_t packet_desc_addr;
> +    hwaddr packet_desc_addr;
>      uint8_t     tx_packet[2048];
>      uint8_t     *p;
>      unsigned    total_bytes;
> @@ -1021,7 +1021,7 @@ static void gem_phy_write(GemState *s, unsigned reg_num, uint16_t val)
>   * gem_read32:
>   * Read a GEM register.
>   */
> -static uint64_t gem_read(void *opaque, target_phys_addr_t offset, unsigned size)
> +static uint64_t gem_read(void *opaque, hwaddr offset, unsigned size)
>  {
>      GemState *s;
>      uint32_t retval;
> @@ -1067,7 +1067,7 @@ static uint64_t gem_read(void *opaque, target_phys_addr_t offset, unsigned size)
>   * gem_write32:
>   * Write a GEM register.
>   */
> -static void gem_write(void *opaque, target_phys_addr_t offset, uint64_t val,
> +static void gem_write(void *opaque, hwaddr offset, uint64_t val,
>          unsigned size)
>  {
>      GemState *s = (GemState *)opaque;
> diff --git a/hw/cadence_ttc.c b/hw/cadence_ttc.c
> index 77b6976..ec78a52 100644
> --- a/hw/cadence_ttc.c
> +++ b/hw/cadence_ttc.c
> @@ -76,7 +76,7 @@ static void cadence_timer_update(CadenceTimerState *s)
>  }
>  
>  static CadenceTimerState *cadence_timer_from_addr(void *opaque,
> -                                        target_phys_addr_t offset)
> +                                        hwaddr offset)
>  {
>      unsigned int index;
>      CadenceTTCState *s = (CadenceTTCState *)opaque;
> @@ -224,7 +224,7 @@ static void cadence_timer_tick(void *opaque)
>      cadence_timer_run(s);
>  }
>  
> -static uint32_t cadence_ttc_read_imp(void *opaque, target_phys_addr_t offset)
> +static uint32_t cadence_ttc_read_imp(void *opaque, hwaddr offset)
>  {
>      CadenceTimerState *s = cadence_timer_from_addr(opaque, offset);
>      uint32_t value;
> @@ -297,7 +297,7 @@ static uint32_t cadence_ttc_read_imp(void *opaque, target_phys_addr_t offset)
>      }
>  }
>  
> -static uint64_t cadence_ttc_read(void *opaque, target_phys_addr_t offset,
> +static uint64_t cadence_ttc_read(void *opaque, hwaddr offset,
>      unsigned size)
>  {
>      uint32_t ret = cadence_ttc_read_imp(opaque, offset);
> @@ -306,7 +306,7 @@ static uint64_t cadence_ttc_read(void *opaque, target_phys_addr_t offset,
>      return ret;
>  }
>  
> -static void cadence_ttc_write(void *opaque, target_phys_addr_t offset,
> +static void cadence_ttc_write(void *opaque, hwaddr offset,
>          uint64_t value, unsigned size)
>  {
>      CadenceTimerState *s = cadence_timer_from_addr(opaque, offset);
> diff --git a/hw/cadence_uart.c b/hw/cadence_uart.c
> index f8afc4e..a7d0504 100644
> --- a/hw/cadence_uart.c
> +++ b/hw/cadence_uart.c
> @@ -354,7 +354,7 @@ static void uart_read_rx_fifo(UartState *s, uint32_t *c)
>      uart_update_status(s);
>  }
>  
> -static void uart_write(void *opaque, target_phys_addr_t offset,
> +static void uart_write(void *opaque, hwaddr offset,
>                            uint64_t value, unsigned size)
>  {
>      UartState *s = (UartState *)opaque;
> @@ -397,7 +397,7 @@ static void uart_write(void *opaque, target_phys_addr_t offset,
>      }
>  }
>  
> -static uint64_t uart_read(void *opaque, target_phys_addr_t offset,
> +static uint64_t uart_read(void *opaque, hwaddr offset,
>          unsigned size)
>  {
>      UartState *s = (UartState *)opaque;
> diff --git a/hw/cirrus_vga.c b/hw/cirrus_vga.c
> index a101329..e4af2e9 100644
> --- a/hw/cirrus_vga.c
> +++ b/hw/cirrus_vga.c
> @@ -1952,7 +1952,7 @@ static void cirrus_mem_writeb_mode4and5_16bpp(CirrusVGAState * s,
>   ***************************************/
>  
>  static uint64_t cirrus_vga_mem_read(void *opaque,
> -                                    target_phys_addr_t addr,
> +                                    hwaddr addr,
>                                      uint32_t size)
>  {
>      CirrusVGAState *s = opaque;
> @@ -1996,7 +1996,7 @@ static uint64_t cirrus_vga_mem_read(void *opaque,
>  }
>  
>  static void cirrus_vga_mem_write(void *opaque,
> -                                 target_phys_addr_t addr,
> +                                 hwaddr addr,
>                                   uint64_t mem_value,
>                                   uint32_t size)
>  {
> @@ -2255,7 +2255,7 @@ static void cirrus_cursor_draw_line(VGACommonState *s1, uint8_t *d1, int scr_y)
>   *
>   ***************************************/
>  
> -static uint64_t cirrus_linear_read(void *opaque, target_phys_addr_t addr,
> +static uint64_t cirrus_linear_read(void *opaque, hwaddr addr,
>                                     unsigned size)
>  {
>      CirrusVGAState *s = opaque;
> @@ -2284,7 +2284,7 @@ static uint64_t cirrus_linear_read(void *opaque, target_phys_addr_t addr,
>      return ret;
>  }
>  
> -static void cirrus_linear_write(void *opaque, target_phys_addr_t addr,
> +static void cirrus_linear_write(void *opaque, hwaddr addr,
>                                  uint64_t val, unsigned size)
>  {
>      CirrusVGAState *s = opaque;
> @@ -2333,7 +2333,7 @@ static void cirrus_linear_write(void *opaque, target_phys_addr_t addr,
>  
>  
>  static uint64_t cirrus_linear_bitblt_read(void *opaque,
> -                                          target_phys_addr_t addr,
> +                                          hwaddr addr,
>                                            unsigned size)
>  {
>      CirrusVGAState *s = opaque;
> @@ -2346,7 +2346,7 @@ static uint64_t cirrus_linear_bitblt_read(void *opaque,
>  }
>  
>  static void cirrus_linear_bitblt_write(void *opaque,
> -                                       target_phys_addr_t addr,
> +                                       hwaddr addr,
>                                         uint64_t val,
>                                         unsigned size)
>  {
> @@ -2640,7 +2640,7 @@ static void cirrus_vga_ioport_write(void *opaque, uint32_t addr, uint32_t val)
>   *
>   ***************************************/
>  
> -static uint64_t cirrus_mmio_read(void *opaque, target_phys_addr_t addr,
> +static uint64_t cirrus_mmio_read(void *opaque, hwaddr addr,
>                                   unsigned size)
>  {
>      CirrusVGAState *s = opaque;
> @@ -2652,7 +2652,7 @@ static uint64_t cirrus_mmio_read(void *opaque, target_phys_addr_t addr,
>      }
>  }
>  
> -static void cirrus_mmio_write(void *opaque, target_phys_addr_t addr,
> +static void cirrus_mmio_write(void *opaque, hwaddr addr,
>                                uint64_t val, unsigned size)
>  {
>      CirrusVGAState *s = opaque;
> diff --git a/hw/cris-boot.h b/hw/cris-boot.h
> index 0a2c242..5b17d83 100644
> --- a/hw/cris-boot.h
> +++ b/hw/cris-boot.h
> @@ -5,7 +5,7 @@ struct cris_load_info
>      const char *cmdline;
>      int image_size;
>  
> -    target_phys_addr_t entry;
> +    hwaddr entry;
>  };
>  
>  void cris_load_image(CRISCPU *cpu, struct cris_load_info *li);
> diff --git a/hw/cs4231.c b/hw/cs4231.c
> index cfec1d9..23570d5 100644
> --- a/hw/cs4231.c
> +++ b/hw/cs4231.c
> @@ -55,7 +55,7 @@ static void cs_reset(DeviceState *d)
>      s->dregs[25] = CS_VER;
>  }
>  
> -static uint64_t cs_mem_read(void *opaque, target_phys_addr_t addr,
> +static uint64_t cs_mem_read(void *opaque, hwaddr addr,
>                              unsigned size)
>  {
>      CSState *s = opaque;
> @@ -82,7 +82,7 @@ static uint64_t cs_mem_read(void *opaque, target_phys_addr_t addr,
>      return ret;
>  }
>  
> -static void cs_mem_write(void *opaque, target_phys_addr_t addr,
> +static void cs_mem_write(void *opaque, hwaddr addr,
>                           uint64_t val, unsigned size)
>  {
>      CSState *s = opaque;
> diff --git a/hw/cs4231a.c b/hw/cs4231a.c
> index e07b9d6..0257fd8 100644
> --- a/hw/cs4231a.c
> +++ b/hw/cs4231a.c
> @@ -346,7 +346,7 @@ static void cs_reset_voices (CSState *s, uint32_t val)
>      }
>  }
>  
> -static uint64_t cs_read (void *opaque, target_phys_addr_t addr, unsigned size)
> +static uint64_t cs_read (void *opaque, hwaddr addr, unsigned size)
>  {
>      CSState *s = opaque;
>      uint32_t saddr, iaddr, ret;
> @@ -383,7 +383,7 @@ static uint64_t cs_read (void *opaque, target_phys_addr_t addr, unsigned size)
>      return ret;
>  }
>  
> -static void cs_write (void *opaque, target_phys_addr_t addr,
> +static void cs_write (void *opaque, hwaddr addr,
>                        uint64_t val64, unsigned size)
>  {
>      CSState *s = opaque;
> diff --git a/hw/cuda.c b/hw/cuda.c
> index 233ab66..f1f408b 100644
> --- a/hw/cuda.c
> +++ b/hw/cuda.c
> @@ -252,7 +252,7 @@ static void cuda_timer1(void *opaque)
>      cuda_update_irq(s);
>  }
>  
> -static uint32_t cuda_readb(void *opaque, target_phys_addr_t addr)
> +static uint32_t cuda_readb(void *opaque, hwaddr addr)
>  {
>      CUDAState *s = opaque;
>      uint32_t val;
> @@ -325,7 +325,7 @@ static uint32_t cuda_readb(void *opaque, target_phys_addr_t addr)
>      return val;
>  }
>  
> -static void cuda_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
> +static void cuda_writeb(void *opaque, hwaddr addr, uint32_t val)
>  {
>      CUDAState *s = opaque;
>  
> @@ -616,20 +616,20 @@ static void cuda_receive_packet_from_host(CUDAState *s,
>      }
>  }
>  
> -static void cuda_writew (void *opaque, target_phys_addr_t addr, uint32_t value)
> +static void cuda_writew (void *opaque, hwaddr addr, uint32_t value)
>  {
>  }
>  
> -static void cuda_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
> +static void cuda_writel (void *opaque, hwaddr addr, uint32_t value)
>  {
>  }
>  
> -static uint32_t cuda_readw (void *opaque, target_phys_addr_t addr)
> +static uint32_t cuda_readw (void *opaque, hwaddr addr)
>  {
>      return 0;
>  }
>  
> -static uint32_t cuda_readl (void *opaque, target_phys_addr_t addr)
> +static uint32_t cuda_readl (void *opaque, hwaddr addr)
>  {
>      return 0;
>  }
> diff --git a/hw/dma.c b/hw/dma.c
> index 0a9322d..d6aeac2 100644
> --- a/hw/dma.c
> +++ b/hw/dma.c
> @@ -411,7 +411,7 @@ void DMA_register_channel (int nchan,
>  int DMA_read_memory (int nchan, void *buf, int pos, int len)
>  {
>      struct dma_regs *r = &dma_controllers[nchan > 3].regs[nchan & 3];
> -    target_phys_addr_t addr = ((r->pageh & 0x7f) << 24) | (r->page << 16) | r->now[ADDR];
> +    hwaddr addr = ((r->pageh & 0x7f) << 24) | (r->page << 16) | r->now[ADDR];
>  
>      if (r->mode & 0x20) {
>          int i;
> @@ -433,7 +433,7 @@ int DMA_read_memory (int nchan, void *buf, int pos, int len)
>  int DMA_write_memory (int nchan, void *buf, int pos, int len)
>  {
>      struct dma_regs *r = &dma_controllers[nchan > 3].regs[nchan & 3];
> -    target_phys_addr_t addr = ((r->pageh & 0x7f) << 24) | (r->page << 16) | r->now[ADDR];
> +    hwaddr addr = ((r->pageh & 0x7f) << 24) | (r->page << 16) | r->now[ADDR];
>  
>      if (r->mode & 0x20) {
>          int i;
> diff --git a/hw/dp8393x.c b/hw/dp8393x.c
> index 4fa6ecc..3f6386e 100644
> --- a/hw/dp8393x.c
> +++ b/hw/dp8393x.c
> @@ -168,7 +168,7 @@
>      int loopback_packet;
>  
>      /* Memory access */
> -    void (*memory_rw)(void *opaque, target_phys_addr_t addr, uint8_t *buf, int len, int is_write);
> +    void (*memory_rw)(void *opaque, hwaddr addr, uint8_t *buf, int len, int is_write);
>      void* mem_opaque;
>  } dp8393xState;
>  
> @@ -603,7 +603,7 @@ static void dp8393x_watchdog(void *opaque)
>      dp8393x_update_irq(s);
>  }
>  
> -static uint32_t dp8393x_readw(void *opaque, target_phys_addr_t addr)
> +static uint32_t dp8393x_readw(void *opaque, hwaddr addr)
>  {
>      dp8393xState *s = opaque;
>      int reg;
> @@ -616,13 +616,13 @@ static uint32_t dp8393x_readw(void *opaque, target_phys_addr_t addr)
>      return read_register(s, reg);
>  }
>  
> -static uint32_t dp8393x_readb(void *opaque, target_phys_addr_t addr)
> +static uint32_t dp8393x_readb(void *opaque, hwaddr addr)
>  {
>      uint16_t v = dp8393x_readw(opaque, addr & ~0x1);
>      return (v >> (8 * (addr & 0x1))) & 0xff;
>  }
>  
> -static uint32_t dp8393x_readl(void *opaque, target_phys_addr_t addr)
> +static uint32_t dp8393x_readl(void *opaque, hwaddr addr)
>  {
>      uint32_t v;
>      v = dp8393x_readw(opaque, addr);
> @@ -630,7 +630,7 @@ static uint32_t dp8393x_readl(void *opaque, target_phys_addr_t addr)
>      return v;
>  }
>  
> -static void dp8393x_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
> +static void dp8393x_writew(void *opaque, hwaddr addr, uint32_t val)
>  {
>      dp8393xState *s = opaque;
>      int reg;
> @@ -644,7 +644,7 @@ static void dp8393x_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
>      write_register(s, reg, (uint16_t)val);
>  }
>  
> -static void dp8393x_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
> +static void dp8393x_writeb(void *opaque, hwaddr addr, uint32_t val)
>  {
>      uint16_t old_val = dp8393x_readw(opaque, addr & ~0x1);
>  
> @@ -659,7 +659,7 @@ static void dp8393x_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
>      dp8393x_writew(opaque, addr & ~0x1, val);
>  }
>  
> -static void dp8393x_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
> +static void dp8393x_writel(void *opaque, hwaddr addr, uint32_t val)
>  {
>      dp8393x_writew(opaque, addr, val & 0xffff);
>      dp8393x_writew(opaque, addr + 2, (val >> 16) & 0xffff);
> @@ -879,10 +879,10 @@ static void nic_cleanup(NetClientState *nc)
>      .cleanup = nic_cleanup,
>  };
>  
> -void dp83932_init(NICInfo *nd, target_phys_addr_t base, int it_shift,
> +void dp83932_init(NICInfo *nd, hwaddr base, int it_shift,
>                    MemoryRegion *address_space,
>                    qemu_irq irq, void* mem_opaque,
> -                  void (*memory_rw)(void *opaque, target_phys_addr_t addr, uint8_t *buf, int len, int is_write))
> +                  void (*memory_rw)(void *opaque, hwaddr addr, uint8_t *buf, int len, int is_write))
>  {
>      dp8393xState *s;
>  
> diff --git a/hw/ds1225y.c b/hw/ds1225y.c
> index 2cd355b..4b3f69b 100644
> --- a/hw/ds1225y.c
> +++ b/hw/ds1225y.c
> @@ -34,7 +34,7 @@
>      uint8_t *contents;
>  } NvRamState;
>  
> -static uint64_t nvram_read(void *opaque, target_phys_addr_t addr, unsigned size)
> +static uint64_t nvram_read(void *opaque, hwaddr addr, unsigned size)
>  {
>      NvRamState *s = opaque;
>      uint32_t val;
> @@ -44,7 +44,7 @@ static uint64_t nvram_read(void *opaque, target_phys_addr_t addr, unsigned size)
>      return val;
>  }
>  
> -static void nvram_write(void *opaque, target_phys_addr_t addr, uint64_t val,
> +static void nvram_write(void *opaque, hwaddr addr, uint64_t val,
>                          unsigned size)
>  {
>      NvRamState *s = opaque;
> diff --git a/hw/dummy_m68k.c b/hw/dummy_m68k.c
> index f436a0c..20f790b 100644
> --- a/hw/dummy_m68k.c
> +++ b/hw/dummy_m68k.c
> @@ -26,7 +26,7 @@ static void dummy_m68k_init(QEMUMachineInitArgs *args)
>      MemoryRegion *ram = g_new(MemoryRegion, 1);
>      int kernel_size;
>      uint64_t elf_entry;
> -    target_phys_addr_t entry;
> +    hwaddr entry;
>  
>      if (!cpu_model)
>          cpu_model = "cfv4e";
> diff --git a/hw/e1000.c b/hw/e1000.c
> index 63fee10..e4f1ffe 100644
> --- a/hw/e1000.c
> +++ b/hw/e1000.c
> @@ -1011,7 +1011,7 @@ static void (*macreg_writeops[])(E1000State *, int, uint32_t) = {
>  enum { NWRITEOPS = ARRAY_SIZE(macreg_writeops) };
>  
>  static void
> -e1000_mmio_write(void *opaque, target_phys_addr_t addr, uint64_t val,
> +e1000_mmio_write(void *opaque, hwaddr addr, uint64_t val,
>                   unsigned size)
>  {
>      E1000State *s = opaque;
> @@ -1028,7 +1028,7 @@ static void (*macreg_writeops[])(E1000State *, int, uint32_t) = {
>  }
>  
>  static uint64_t
> -e1000_mmio_read(void *opaque, target_phys_addr_t addr, unsigned size)
> +e1000_mmio_read(void *opaque, hwaddr addr, unsigned size)
>  {
>      E1000State *s = opaque;
>      unsigned int index = (addr & 0x1ffff) >> 2;
> @@ -1051,7 +1051,7 @@ static void (*macreg_writeops[])(E1000State *, int, uint32_t) = {
>      },
>  };
>  
> -static uint64_t e1000_io_read(void *opaque, target_phys_addr_t addr,
> +static uint64_t e1000_io_read(void *opaque, hwaddr addr,
>                                unsigned size)
>  {
>      E1000State *s = opaque;
> @@ -1060,7 +1060,7 @@ static uint64_t e1000_io_read(void *opaque, target_phys_addr_t addr,
>      return 0;
>  }
>  
> -static void e1000_io_write(void *opaque, target_phys_addr_t addr,
> +static void e1000_io_write(void *opaque, hwaddr addr,
>                             uint64_t val, unsigned size)
>  {
>      E1000State *s = opaque;
> diff --git a/hw/eccmemctl.c b/hw/eccmemctl.c
> index fe1cd90..000bd08 100644
> --- a/hw/eccmemctl.c
> +++ b/hw/eccmemctl.c
> @@ -129,7 +129,7 @@
>      uint32_t version;
>  } ECCState;
>  
> -static void ecc_mem_write(void *opaque, target_phys_addr_t addr, uint64_t val,
> +static void ecc_mem_write(void *opaque, hwaddr addr, uint64_t val,
>                            unsigned size)
>  {
>      ECCState *s = opaque;
> @@ -172,7 +172,7 @@ static void ecc_mem_write(void *opaque, target_phys_addr_t addr, uint64_t val,
>      }
>  }
>  
> -static uint64_t ecc_mem_read(void *opaque, target_phys_addr_t addr,
> +static uint64_t ecc_mem_read(void *opaque, hwaddr addr,
>                               unsigned size)
>  {
>      ECCState *s = opaque;
> @@ -229,7 +229,7 @@ static uint64_t ecc_mem_read(void *opaque, target_phys_addr_t addr,
>      },
>  };
>  
> -static void ecc_diag_mem_write(void *opaque, target_phys_addr_t addr,
> +static void ecc_diag_mem_write(void *opaque, hwaddr addr,
>                                 uint64_t val, unsigned size)
>  {
>      ECCState *s = opaque;
> @@ -238,7 +238,7 @@ static void ecc_diag_mem_write(void *opaque, target_phys_addr_t addr,
>      s->diag[addr & ECC_DIAG_MASK] = val;
>  }
>  
> -static uint64_t ecc_diag_mem_read(void *opaque, target_phys_addr_t addr,
> +static uint64_t ecc_diag_mem_read(void *opaque, hwaddr addr,
>                                    unsigned size)
>  {
>      ECCState *s = opaque;
> diff --git a/hw/eepro100.c b/hw/eepro100.c
> index 5b23116..a189474 100644
> --- a/hw/eepro100.c
> +++ b/hw/eepro100.c
> @@ -1578,7 +1578,7 @@ static void eepro100_write4(EEPRO100State * s, uint32_t addr, uint32_t val)
>      }
>  }
>  
> -static uint64_t eepro100_read(void *opaque, target_phys_addr_t addr,
> +static uint64_t eepro100_read(void *opaque, hwaddr addr,
>                                unsigned size)
>  {
>      EEPRO100State *s = opaque;
> @@ -1591,7 +1591,7 @@ static uint64_t eepro100_read(void *opaque, target_phys_addr_t addr,
>      }
>  }
>  
> -static void eepro100_write(void *opaque, target_phys_addr_t addr,
> +static void eepro100_write(void *opaque, hwaddr addr,
>                             uint64_t data, unsigned size)
>  {
>      EEPRO100State *s = opaque;
> diff --git a/hw/elf_ops.h b/hw/elf_ops.h
> index 731a983..531a425 100644
> --- a/hw/elf_ops.h
> +++ b/hw/elf_ops.h
> @@ -62,7 +62,7 @@ static struct elf_shdr *glue(find_section, SZ)(struct elf_shdr *shdr_table,
>  
>  static int glue(symfind, SZ)(const void *s0, const void *s1)
>  {
> -    target_phys_addr_t addr = *(target_phys_addr_t *)s0;
> +    hwaddr addr = *(hwaddr *)s0;
>      struct elf_sym *sym = (struct elf_sym *)s1;
>      int result = 0;
>      if (addr < sym->st_value) {
> @@ -74,7 +74,7 @@ static int glue(symfind, SZ)(const void *s0, const void *s1)
>  }
>  
>  static const char *glue(lookup_symbol, SZ)(struct syminfo *s,
> -                                           target_phys_addr_t orig_addr)
> +                                           hwaddr orig_addr)
>  {
>      struct elf_sym *syms = glue(s->disas_symtab.elf, SZ);
>      struct elf_sym *sym;
> diff --git a/hw/empty_slot.c b/hw/empty_slot.c
> index 099c85e..23978eb 100644
> --- a/hw/empty_slot.c
> +++ b/hw/empty_slot.c
> @@ -28,14 +28,14 @@
>      uint64_t size;
>  } EmptySlot;
>  
> -static uint64_t empty_slot_read(void *opaque, target_phys_addr_t addr,
> +static uint64_t empty_slot_read(void *opaque, hwaddr addr,
>                                  unsigned size)
>  {
>      DPRINTF("read from " TARGET_FMT_plx "\n", addr);
>      return 0;
>  }
>  
> -static void empty_slot_write(void *opaque, target_phys_addr_t addr,
> +static void empty_slot_write(void *opaque, hwaddr addr,
>                               uint64_t val, unsigned size)
>  {
>      DPRINTF("write 0x%x to " TARGET_FMT_plx "\n", (unsigned)val, addr);
> @@ -47,7 +47,7 @@ static void empty_slot_write(void *opaque, target_phys_addr_t addr,
>      .endianness = DEVICE_NATIVE_ENDIAN,
>  };
>  
> -void empty_slot_init(target_phys_addr_t addr, uint64_t slot_size)
> +void empty_slot_init(hwaddr addr, uint64_t slot_size)
>  {
>      if (slot_size > 0) {
>          /* Only empty slots larger than 0 byte need handling. */
> diff --git a/hw/empty_slot.h b/hw/empty_slot.h
> index 78dc91d..4e9e460 100644
> --- a/hw/empty_slot.h
> +++ b/hw/empty_slot.h
> @@ -1,2 +1,2 @@
>  /* empty_slot.c */
> -void empty_slot_init(target_phys_addr_t addr, uint64_t slot_size);
> +void empty_slot_init(hwaddr addr, uint64_t slot_size);
> diff --git a/hw/escc.c b/hw/escc.c
> index e1f5e73..a356613 100644
> --- a/hw/escc.c
> +++ b/hw/escc.c
> @@ -463,7 +463,7 @@ static void escc_update_parameters(ChannelState *s)
>      qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp);
>  }
>  
> -static void escc_mem_write(void *opaque, target_phys_addr_t addr,
> +static void escc_mem_write(void *opaque, hwaddr addr,
>                             uint64_t val, unsigned size)
>  {
>      SerialState *serial = opaque;
> @@ -565,7 +565,7 @@ static void escc_mem_write(void *opaque, target_phys_addr_t addr,
>      }
>  }
>  
> -static uint64_t escc_mem_read(void *opaque, target_phys_addr_t addr,
> +static uint64_t escc_mem_read(void *opaque, hwaddr addr,
>                                unsigned size)
>  {
>      SerialState *serial = opaque;
> @@ -683,7 +683,7 @@ static void serial_event(void *opaque, int event)
>      }
>  };
>  
> -MemoryRegion *escc_init(target_phys_addr_t base, qemu_irq irqA, qemu_irq irqB,
> +MemoryRegion *escc_init(hwaddr base, qemu_irq irqA, qemu_irq irqB,
>                CharDriverState *chrA, CharDriverState *chrB,
>                int clock, int it_shift)
>  {
> @@ -846,7 +846,7 @@ static void sunmouse_event(void *opaque,
>      put_queue(s, 0);
>  }
>  
> -void slavio_serial_ms_kbd_init(target_phys_addr_t base, qemu_irq irq,
> +void slavio_serial_ms_kbd_init(hwaddr base, qemu_irq irq,
>                                 int disabled, int clock, int it_shift)
>  {
>      DeviceState *dev;
> diff --git a/hw/escc.h b/hw/escc.h
> index d1da46f..def2894 100644
> --- a/hw/escc.h
> +++ b/hw/escc.h
> @@ -1,8 +1,8 @@
>  /* escc.c */
>  #define ESCC_SIZE 4
> -MemoryRegion *escc_init(target_phys_addr_t base, qemu_irq irqA, qemu_irq irqB,
> +MemoryRegion *escc_init(hwaddr base, qemu_irq irqA, qemu_irq irqB,
>                CharDriverState *chrA, CharDriverState *chrB,
>                int clock, int it_shift);
>  
> -void slavio_serial_ms_kbd_init(target_phys_addr_t base, qemu_irq irq,
> +void slavio_serial_ms_kbd_init(hwaddr base, qemu_irq irq,
>                                 int disabled, int clock, int it_shift);
> diff --git a/hw/esp-pci.c b/hw/esp-pci.c
> index 170e007..d9a8e59 100644
> --- a/hw/esp-pci.c
> +++ b/hw/esp-pci.c
> @@ -159,7 +159,7 @@ static uint32_t esp_pci_dma_read(PCIESPState *pci, uint32_t saddr)
>      return val;
>  }
>  
> -static void esp_pci_io_write(void *opaque, target_phys_addr_t addr,
> +static void esp_pci_io_write(void *opaque, hwaddr addr,
>                               uint64_t val, unsigned int size)
>  {
>      PCIESPState *pci = opaque;
> @@ -202,7 +202,7 @@ static void esp_pci_io_write(void *opaque, target_phys_addr_t addr,
>      }
>  }
>  
> -static uint64_t esp_pci_io_read(void *opaque, target_phys_addr_t addr,
> +static uint64_t esp_pci_io_read(void *opaque, hwaddr addr,
>                                  unsigned int size)
>  {
>      PCIESPState *pci = opaque;
> diff --git a/hw/esp.c b/hw/esp.c
> index 84a4e74..6d01624 100644
> --- a/hw/esp.c
> +++ b/hw/esp.c
> @@ -550,7 +550,7 @@ void esp_reg_write(ESPState *s, uint32_t saddr, uint64_t val)
>      s->wregs[saddr] = val;
>  }
>  
> -static bool esp_mem_accepts(void *opaque, target_phys_addr_t addr,
> +static bool esp_mem_accepts(void *opaque, hwaddr addr,
>                              unsigned size, bool is_write)
>  {
>      return (size == 1) || (is_write && size == 4);
> @@ -585,7 +585,7 @@ static bool esp_mem_accepts(void *opaque, target_phys_addr_t addr,
>      ESPState esp;
>  } SysBusESPState;
>  
> -static void sysbus_esp_mem_write(void *opaque, target_phys_addr_t addr,
> +static void sysbus_esp_mem_write(void *opaque, hwaddr addr,
>                                   uint64_t val, unsigned int size)
>  {
>      SysBusESPState *sysbus = opaque;
> @@ -595,7 +595,7 @@ static void sysbus_esp_mem_write(void *opaque, target_phys_addr_t addr,
>      esp_reg_write(&sysbus->esp, saddr, val);
>  }
>  
> -static uint64_t sysbus_esp_mem_read(void *opaque, target_phys_addr_t addr,
> +static uint64_t sysbus_esp_mem_read(void *opaque, hwaddr addr,
>                                      unsigned int size)
>  {
>      SysBusESPState *sysbus = opaque;
> @@ -612,7 +612,7 @@ static uint64_t sysbus_esp_mem_read(void *opaque, target_phys_addr_t addr,
>      .valid.accepts = esp_mem_accepts,
>  };
>  
> -void esp_init(target_phys_addr_t espaddr, int it_shift,
> +void esp_init(hwaddr espaddr, int it_shift,
>                ESPDMAMemoryReadWriteFunc dma_memory_read,
>                ESPDMAMemoryReadWriteFunc dma_memory_write,
>                void *dma_opaque, qemu_irq irq, qemu_irq *reset,
> diff --git a/hw/esp.h b/hw/esp.h
> index fa855e2..f15cc7b 100644
> --- a/hw/esp.h
> +++ b/hw/esp.h
> @@ -6,7 +6,7 @@
>  /* esp.c */
>  #define ESP_MAX_DEVS 7
>  typedef void (*ESPDMAMemoryReadWriteFunc)(void *opaque, uint8_t *buf, int len);
> -void esp_init(target_phys_addr_t espaddr, int it_shift,
> +void esp_init(hwaddr espaddr, int it_shift,
>                ESPDMAMemoryReadWriteFunc dma_memory_read,
>                ESPDMAMemoryReadWriteFunc dma_memory_write,
>                void *dma_opaque, qemu_irq irq, qemu_irq *reset,
> diff --git a/hw/etraxfs.h b/hw/etraxfs.h
> index c62f94b..725bb9e 100644
> --- a/hw/etraxfs.h
> +++ b/hw/etraxfs.h
> @@ -29,7 +29,7 @@ qemu_irq *cris_pic_init_cpu(CPUCRISState *env);
>  
>  /* Instantiate an ETRAXFS Ethernet MAC.  */
>  static inline DeviceState *
> -etraxfs_eth_init(NICInfo *nd, target_phys_addr_t base, int phyaddr,
> +etraxfs_eth_init(NICInfo *nd, hwaddr base, int phyaddr,
>                   void *dma_out, void *dma_in)
>  {
>      DeviceState *dev;
> diff --git a/hw/etraxfs_dma.c b/hw/etraxfs_dma.c
> index 332525c..49221ab 100644
> --- a/hw/etraxfs_dma.c
> +++ b/hw/etraxfs_dma.c
> @@ -212,7 +212,7 @@ static inline int channel_en(struct fs_dma_ctrl *ctrl, int c)
>  		&& ctrl->channels[c].client;
>  }
>  
> -static inline int fs_channel(target_phys_addr_t addr)
> +static inline int fs_channel(hwaddr addr)
>  {
>  	/* Every channel has a 0x2000 ctrl register map.  */
>  	return addr >> 13;
> @@ -221,7 +221,7 @@ static inline int fs_channel(target_phys_addr_t addr)
>  #ifdef USE_THIS_DEAD_CODE
>  static void channel_load_g(struct fs_dma_ctrl *ctrl, int c)
>  {
> -	target_phys_addr_t addr = channel_reg(ctrl, c, RW_GROUP);
> +	hwaddr addr = channel_reg(ctrl, c, RW_GROUP);
>  
>  	/* Load and decode. FIXME: handle endianness.  */
>  	cpu_physical_memory_read (addr, 
> @@ -253,7 +253,7 @@ static void dump_d(int ch, struct dma_descr_data *d)
>  
>  static void channel_load_c(struct fs_dma_ctrl *ctrl, int c)
>  {
> -	target_phys_addr_t addr = channel_reg(ctrl, c, RW_GROUP_DOWN);
> +	hwaddr addr = channel_reg(ctrl, c, RW_GROUP_DOWN);
>  
>  	/* Load and decode. FIXME: handle endianness.  */
>  	cpu_physical_memory_read (addr, 
> @@ -270,7 +270,7 @@ static void channel_load_c(struct fs_dma_ctrl *ctrl, int c)
>  
>  static void channel_load_d(struct fs_dma_ctrl *ctrl, int c)
>  {
> -	target_phys_addr_t addr = channel_reg(ctrl, c, RW_SAVED_DATA);
> +	hwaddr addr = channel_reg(ctrl, c, RW_SAVED_DATA);
>  
>  	/* Load and decode. FIXME: handle endianness.  */
>  	D(printf("%s ch=%d addr=" TARGET_FMT_plx "\n", __func__, c, addr));
> @@ -284,7 +284,7 @@ static void channel_load_d(struct fs_dma_ctrl *ctrl, int c)
>  
>  static void channel_store_c(struct fs_dma_ctrl *ctrl, int c)
>  {
> -	target_phys_addr_t addr = channel_reg(ctrl, c, RW_GROUP_DOWN);
> +	hwaddr addr = channel_reg(ctrl, c, RW_GROUP_DOWN);
>  
>  	/* Encode and store. FIXME: handle endianness.  */
>  	D(printf("%s ch=%d addr=" TARGET_FMT_plx "\n", __func__, c, addr));
> @@ -296,7 +296,7 @@ static void channel_store_c(struct fs_dma_ctrl *ctrl, int c)
>  
>  static void channel_store_d(struct fs_dma_ctrl *ctrl, int c)
>  {
> -	target_phys_addr_t addr = channel_reg(ctrl, c, RW_SAVED_DATA);
> +	hwaddr addr = channel_reg(ctrl, c, RW_SAVED_DATA);
>  
>  	/* Encode and store. FIXME: handle endianness.  */
>  	D(printf("%s ch=%d addr=" TARGET_FMT_plx "\n", __func__, c, addr));
> @@ -573,14 +573,14 @@ static inline int channel_in_run(struct fs_dma_ctrl *ctrl, int c)
>  		return 0;
>  }
>  
> -static uint32_t dma_rinvalid (void *opaque, target_phys_addr_t addr)
> +static uint32_t dma_rinvalid (void *opaque, hwaddr addr)
>  {
>          hw_error("Unsupported short raccess. reg=" TARGET_FMT_plx "\n", addr);
>          return 0;
>  }
>  
>  static uint64_t
> -dma_read(void *opaque, target_phys_addr_t addr, unsigned int size)
> +dma_read(void *opaque, hwaddr addr, unsigned int size)
>  {
>          struct fs_dma_ctrl *ctrl = opaque;
>  	int c;
> @@ -612,7 +612,7 @@ static uint32_t dma_rinvalid (void *opaque, target_phys_addr_t addr)
>  }
>  
>  static void
> -dma_winvalid (void *opaque, target_phys_addr_t addr, uint32_t value)
> +dma_winvalid (void *opaque, hwaddr addr, uint32_t value)
>  {
>          hw_error("Unsupported short waccess. reg=" TARGET_FMT_plx "\n", addr);
>  }
> @@ -627,7 +627,7 @@ static uint32_t dma_rinvalid (void *opaque, target_phys_addr_t addr)
>  }
>  
>  static void
> -dma_write(void *opaque, target_phys_addr_t addr,
> +dma_write(void *opaque, hwaddr addr,
>  	  uint64_t val64, unsigned int size)
>  {
>          struct fs_dma_ctrl *ctrl = opaque;
> @@ -762,7 +762,7 @@ static void DMA_run(void *opaque)
>          qemu_bh_schedule_idle(etraxfs_dmac->bh);
>  }
>  
> -void *etraxfs_dmac_init(target_phys_addr_t base, int nr_channels)
> +void *etraxfs_dmac_init(hwaddr base, int nr_channels)
>  {
>  	struct fs_dma_ctrl *ctrl = NULL;
>  
> diff --git a/hw/etraxfs_dma.h b/hw/etraxfs_dma.h
> index 021c52a..3fef80f 100644
> --- a/hw/etraxfs_dma.h
> +++ b/hw/etraxfs_dma.h
> @@ -20,7 +20,7 @@ struct etraxfs_dma_client
>  	} client;
>  };
>  
> -void *etraxfs_dmac_init(target_phys_addr_t base, int nr_channels);
> +void *etraxfs_dmac_init(hwaddr base, int nr_channels);
>  void etraxfs_dmac_connect(void *opaque, int channel, qemu_irq *line,
>  			  int input);
>  void etraxfs_dmac_connect_client(void *opaque, int c, 
> diff --git a/hw/etraxfs_eth.c b/hw/etraxfs_eth.c
> index b124f5b..3d42426 100644
> --- a/hw/etraxfs_eth.c
> +++ b/hw/etraxfs_eth.c
> @@ -374,7 +374,7 @@ static void eth_validate_duplex(struct fs_eth *eth)
>  }
>  
>  static uint64_t
> -eth_read(void *opaque, target_phys_addr_t addr, unsigned int size)
> +eth_read(void *opaque, hwaddr addr, unsigned int size)
>  {
>  	struct fs_eth *eth = opaque;
>  	uint32_t r = 0;
> @@ -418,7 +418,7 @@ static void eth_update_ma(struct fs_eth *eth, int ma)
>  }
>  
>  static void
> -eth_write(void *opaque, target_phys_addr_t addr,
> +eth_write(void *opaque, hwaddr addr,
>            uint64_t val64, unsigned int size)
>  {
>  	struct fs_eth *eth = opaque;
> diff --git a/hw/etraxfs_pic.c b/hw/etraxfs_pic.c
> index dc27f88..62a62a3 100644
> --- a/hw/etraxfs_pic.c
> +++ b/hw/etraxfs_pic.c
> @@ -79,7 +79,7 @@ static void pic_update(struct etrax_pic *fs)
>  }
>  
>  static uint64_t
> -pic_read(void *opaque, target_phys_addr_t addr, unsigned int size)
> +pic_read(void *opaque, hwaddr addr, unsigned int size)
>  {
>      struct etrax_pic *fs = opaque;
>      uint32_t rval;
> @@ -89,7 +89,7 @@ static void pic_update(struct etrax_pic *fs)
>      return rval;
>  }
>  
> -static void pic_write(void *opaque, target_phys_addr_t addr,
> +static void pic_write(void *opaque, hwaddr addr,
>                        uint64_t value, unsigned int size)
>  {
>      struct etrax_pic *fs = opaque;
> diff --git a/hw/etraxfs_ser.c b/hw/etraxfs_ser.c
> index 5f16b17..ee0d72b 100644
> --- a/hw/etraxfs_ser.c
> +++ b/hw/etraxfs_ser.c
> @@ -75,7 +75,7 @@ static void ser_update_irq(struct etrax_serial *s)
>  }
>  
>  static uint64_t
> -ser_read(void *opaque, target_phys_addr_t addr, unsigned int size)
> +ser_read(void *opaque, hwaddr addr, unsigned int size)
>  {
>      struct etrax_serial *s = opaque;
>      D(CPUCRISState *env = s->env);
> @@ -110,7 +110,7 @@ static void ser_update_irq(struct etrax_serial *s)
>  }
>  
>  static void
> -ser_write(void *opaque, target_phys_addr_t addr,
> +ser_write(void *opaque, hwaddr addr,
>            uint64_t val64, unsigned int size)
>  {
>      struct etrax_serial *s = opaque;
> diff --git a/hw/etraxfs_timer.c b/hw/etraxfs_timer.c
> index 9076a49..f5601dc 100644
> --- a/hw/etraxfs_timer.c
> +++ b/hw/etraxfs_timer.c
> @@ -75,7 +75,7 @@ struct etrax_timer {
>  };
>  
>  static uint64_t
> -timer_read(void *opaque, target_phys_addr_t addr, unsigned int size)
> +timer_read(void *opaque, hwaddr addr, unsigned int size)
>  {
>      struct etrax_timer *t = opaque;
>      uint32_t r = 0;
> @@ -242,7 +242,7 @@ static inline void timer_watchdog_update(struct etrax_timer *t, uint32_t value)
>  }
>  
>  static void
> -timer_write(void *opaque, target_phys_addr_t addr,
> +timer_write(void *opaque, hwaddr addr,
>              uint64_t val64, unsigned int size)
>  {
>      struct etrax_timer *t = opaque;
> diff --git a/hw/exynos4210.h b/hw/exynos4210.h
> index a43ba3a..777f0f5 100644
> --- a/hw/exynos4210.h
> +++ b/hw/exynos4210.h
> @@ -128,7 +128,7 @@ void exynos4210_combiner_get_gpioin(Exynos4210Irq *irqs, DeviceState *dev,
>  /*
>   * exynos4210 UART
>   */
> -DeviceState *exynos4210_uart_create(target_phys_addr_t addr,
> +DeviceState *exynos4210_uart_create(hwaddr addr,
>                                      int fifo_size,
>                                      int channel,
>                                      CharDriverState *chr,
> diff --git a/hw/exynos4210_combiner.c b/hw/exynos4210_combiner.c
> index 60b33c7..84d36ed 100644
> --- a/hw/exynos4210_combiner.c
> +++ b/hw/exynos4210_combiner.c
> @@ -174,7 +174,7 @@ void exynos4210_combiner_get_gpioin(Exynos4210Irq *irqs, DeviceState *dev,
>  }
>  
>  static uint64_t
> -exynos4210_combiner_read(void *opaque, target_phys_addr_t offset, unsigned size)
> +exynos4210_combiner_read(void *opaque, hwaddr offset, unsigned size)
>  {
>      struct Exynos4210CombinerState *s =
>              (struct Exynos4210CombinerState *)opaque;
> @@ -266,7 +266,7 @@ static void exynos4210_combiner_update(void *opaque, uint8_t group_n)
>      }
>  }
>  
> -static void exynos4210_combiner_write(void *opaque, target_phys_addr_t offset,
> +static void exynos4210_combiner_write(void *opaque, hwaddr offset,
>          uint64_t val, unsigned size)
>  {
>      struct Exynos4210CombinerState *s =
> diff --git a/hw/exynos4210_fimd.c b/hw/exynos4210_fimd.c
> index 3313f00..7cb2c31 100644
> --- a/hw/exynos4210_fimd.c
> +++ b/hw/exynos4210_fimd.c
> @@ -290,7 +290,7 @@ struct Exynos4210fimdWindow {
>      uint16_t virtpage_offsize;       /* VIDWADD2 register */
>      MemoryRegionSection mem_section; /* RAM fragment containing framebuffer */
>      uint8_t *host_fb_addr;           /* Host pointer to window's framebuffer */
> -    target_phys_addr_t fb_len;       /* Framebuffer length */
> +    hwaddr fb_len;       /* Framebuffer length */
>  };
>  
>  typedef struct {
> @@ -1110,7 +1110,7 @@ static inline int fimd_get_buffer_id(Exynos4210fimdWindow *w)
>  static void fimd_update_memory_section(Exynos4210fimdState *s, unsigned win)
>  {
>      Exynos4210fimdWindow *w = &s->window[win];
> -    target_phys_addr_t fb_start_addr, fb_mapped_len;
> +    hwaddr fb_start_addr, fb_mapped_len;
>  
>      if (!s->enabled || !(w->wincon & FIMD_WINCON_ENWIN) ||
>              FIMD_WINDOW_PROTECTED(s->shadowcon, win)) {
> @@ -1243,7 +1243,7 @@ static void exynos4210_fimd_update(void *opaque)
>      Exynos4210fimdState *s = (Exynos4210fimdState *)opaque;
>      Exynos4210fimdWindow *w;
>      int i, line;
> -    target_phys_addr_t fb_line_addr, inc_size;
> +    hwaddr fb_line_addr, inc_size;
>      int scrn_height;
>      int first_line = -1, last_line = -1, scrn_width;
>      bool blend = false;
> @@ -1348,7 +1348,7 @@ static void exynos4210_fimd_reset(DeviceState *d)
>      s->hueoffset = 0x01800080;
>  }
>  
> -static void exynos4210_fimd_write(void *opaque, target_phys_addr_t offset,
> +static void exynos4210_fimd_write(void *opaque, hwaddr offset,
>                                uint64_t val, unsigned size)
>  {
>      Exynos4210fimdState *s = (Exynos4210fimdState *)opaque;
> @@ -1649,7 +1649,7 @@ static void exynos4210_fimd_write(void *opaque, target_phys_addr_t offset,
>      }
>  }
>  
> -static uint64_t exynos4210_fimd_read(void *opaque, target_phys_addr_t offset,
> +static uint64_t exynos4210_fimd_read(void *opaque, hwaddr offset,
>                                    unsigned size)
>  {
>      Exynos4210fimdState *s = (Exynos4210fimdState *)opaque;
> diff --git a/hw/exynos4210_i2c.c b/hw/exynos4210_i2c.c
> index 3f72a5c..1e11d9b 100644
> --- a/hw/exynos4210_i2c.c
> +++ b/hw/exynos4210_i2c.c
> @@ -129,7 +129,7 @@ static void exynos4210_i2c_data_send(void *opaque)
>      exynos4210_i2c_raise_interrupt(s);
>  }
>  
> -static uint64_t exynos4210_i2c_read(void *opaque, target_phys_addr_t offset,
> +static uint64_t exynos4210_i2c_read(void *opaque, hwaddr offset,
>                                   unsigned size)
>  {
>      Exynos4210I2CState *s = (Exynos4210I2CState *)opaque;
> @@ -168,7 +168,7 @@ static uint64_t exynos4210_i2c_read(void *opaque, target_phys_addr_t offset,
>      return value;
>  }
>  
> -static void exynos4210_i2c_write(void *opaque, target_phys_addr_t offset,
> +static void exynos4210_i2c_write(void *opaque, hwaddr offset,
>                                uint64_t value, unsigned size)
>  {
>      Exynos4210I2CState *s = (Exynos4210I2CState *)opaque;
> diff --git a/hw/exynos4210_mct.c b/hw/exynos4210_mct.c
> index 6f94ce2..e79cd6a 100644
> --- a/hw/exynos4210_mct.c
> +++ b/hw/exynos4210_mct.c
> @@ -985,7 +985,7 @@ static void exynos4210_mct_reset(DeviceState *d)
>  }
>  
>  /* Multi Core Timer read */
> -static uint64_t exynos4210_mct_read(void *opaque, target_phys_addr_t offset,
> +static uint64_t exynos4210_mct_read(void *opaque, hwaddr offset,
>          unsigned size)
>  {
>      Exynos4210MCTState *s = (Exynos4210MCTState *)opaque;
> @@ -1098,7 +1098,7 @@ static uint64_t exynos4210_mct_read(void *opaque, target_phys_addr_t offset,
>  }
>  
>  /* MCT write */
> -static void exynos4210_mct_write(void *opaque, target_phys_addr_t offset,
> +static void exynos4210_mct_write(void *opaque, hwaddr offset,
>          uint64_t value, unsigned size)
>  {
>      Exynos4210MCTState *s = (Exynos4210MCTState *)opaque;
> diff --git a/hw/exynos4210_pmu.c b/hw/exynos4210_pmu.c
> index c12d750..a22b8f1 100644
> --- a/hw/exynos4210_pmu.c
> +++ b/hw/exynos4210_pmu.c
> @@ -392,7 +392,7 @@
>      uint32_t reg[PMU_NUM_OF_REGISTERS];
>  } Exynos4210PmuState;
>  
> -static uint64_t exynos4210_pmu_read(void *opaque, target_phys_addr_t offset,
> +static uint64_t exynos4210_pmu_read(void *opaque, hwaddr offset,
>                                      unsigned size)
>  {
>      Exynos4210PmuState *s = (Exynos4210PmuState *)opaque;
> @@ -411,7 +411,7 @@ static uint64_t exynos4210_pmu_read(void *opaque, target_phys_addr_t offset,
>      return 0;
>  }
>  
> -static void exynos4210_pmu_write(void *opaque, target_phys_addr_t offset,
> +static void exynos4210_pmu_write(void *opaque, hwaddr offset,
>                                   uint64_t val, unsigned size)
>  {
>      Exynos4210PmuState *s = (Exynos4210PmuState *)opaque;
> diff --git a/hw/exynos4210_pwm.c b/hw/exynos4210_pwm.c
> index 0c22828..5e2872f 100644
> --- a/hw/exynos4210_pwm.c
> +++ b/hw/exynos4210_pwm.c
> @@ -208,7 +208,7 @@ static void exynos4210_pwm_tick(void *opaque)
>  /*
>   * PWM Read
>   */
> -static uint64_t exynos4210_pwm_read(void *opaque, target_phys_addr_t offset,
> +static uint64_t exynos4210_pwm_read(void *opaque, hwaddr offset,
>          unsigned size)
>  {
>      Exynos4210PWMState *s = (Exynos4210PWMState *)opaque;
> @@ -259,7 +259,7 @@ static uint64_t exynos4210_pwm_read(void *opaque, target_phys_addr_t offset,
>  /*
>   * PWM Write
>   */
> -static void exynos4210_pwm_write(void *opaque, target_phys_addr_t offset,
> +static void exynos4210_pwm_write(void *opaque, hwaddr offset,
>          uint64_t value, unsigned size)
>  {
>      Exynos4210PWMState *s = (Exynos4210PWMState *)opaque;
> diff --git a/hw/exynos4210_rtc.c b/hw/exynos4210_rtc.c
> index 42a4ddc..c4fbd49 100644
> --- a/hw/exynos4210_rtc.c
> +++ b/hw/exynos4210_rtc.c
> @@ -299,7 +299,7 @@ static void exynos4210_rtc_1Hz_tick(void *opaque)
>  /*
>   * RTC Read
>   */
> -static uint64_t exynos4210_rtc_read(void *opaque, target_phys_addr_t offset,
> +static uint64_t exynos4210_rtc_read(void *opaque, hwaddr offset,
>          unsigned size)
>  {
>      uint32_t value = 0;
> @@ -376,7 +376,7 @@ static uint64_t exynos4210_rtc_read(void *opaque, target_phys_addr_t offset,
>  /*
>   * RTC Write
>   */
> -static void exynos4210_rtc_write(void *opaque, target_phys_addr_t offset,
> +static void exynos4210_rtc_write(void *opaque, hwaddr offset,
>          uint64_t value, unsigned size)
>  {
>      Exynos4210RTCState *s = (Exynos4210RTCState *)opaque;
> diff --git a/hw/exynos4210_uart.c b/hw/exynos4210_uart.c
> index ccc4780..20dcd9f 100644
> --- a/hw/exynos4210_uart.c
> +++ b/hw/exynos4210_uart.c
> @@ -96,7 +96,7 @@
>  
>  typedef struct Exynos4210UartReg {
>      const char         *name; /* the only reason is the debug output */
> -    target_phys_addr_t  offset;
> +    hwaddr  offset;
>      uint32_t            reset_value;
>  } Exynos4210UartReg;
>  
> @@ -184,7 +184,7 @@
>  
>  #if DEBUG_UART
>  /* Used only for debugging inside PRINT_DEBUG_... macros */
> -static const char *exynos4210_uart_regname(target_phys_addr_t  offset)
> +static const char *exynos4210_uart_regname(hwaddr  offset)
>  {
>  
>      int regs_number = sizeof(exynos4210_uart_regs) / sizeof(Exynos4210UartReg);
> @@ -348,7 +348,7 @@ static void exynos4210_uart_update_parameters(Exynos4210UartState *s)
>                  s->channel, speed, parity, data_bits, stop_bits);
>  }
>  
> -static void exynos4210_uart_write(void *opaque, target_phys_addr_t offset,
> +static void exynos4210_uart_write(void *opaque, hwaddr offset,
>                                 uint64_t val, unsigned size)
>  {
>      Exynos4210UartState *s = (Exynos4210UartState *)opaque;
> @@ -423,7 +423,7 @@ static void exynos4210_uart_write(void *opaque, target_phys_addr_t offset,
>          break;
>      }
>  }
> -static uint64_t exynos4210_uart_read(void *opaque, target_phys_addr_t offset,
> +static uint64_t exynos4210_uart_read(void *opaque, hwaddr offset,
>                                    unsigned size)
>  {
>      Exynos4210UartState *s = (Exynos4210UartState *)opaque;
> @@ -581,7 +581,7 @@ static void exynos4210_uart_reset(DeviceState *dev)
>      }
>  };
>  
> -DeviceState *exynos4210_uart_create(target_phys_addr_t addr,
> +DeviceState *exynos4210_uart_create(hwaddr addr,
>                                   int fifo_size,
>                                   int channel,
>                                   CharDriverState *chr,
> @@ -617,7 +617,7 @@ DeviceState *exynos4210_uart_create(target_phys_addr_t addr,
>  
>      bus = sysbus_from_qdev(dev);
>      qdev_init_nofail(dev);
> -    if (addr != (target_phys_addr_t)-1) {
> +    if (addr != (hwaddr)-1) {
>          sysbus_mmio_map(bus, 0, addr);
>      }
>      sysbus_connect_irq(bus, 0, irq);
> diff --git a/hw/fdc.c b/hw/fdc.c
> index 25a49e3..bf8c1d9 100644
> --- a/hw/fdc.c
> +++ b/hw/fdc.c
> @@ -626,13 +626,13 @@ static void fdctrl_write (void *opaque, uint32_t reg, uint32_t value)
>      }
>  }
>  
> -static uint64_t fdctrl_read_mem (void *opaque, target_phys_addr_t reg,
> +static uint64_t fdctrl_read_mem (void *opaque, hwaddr reg,
>                                   unsigned ize)
>  {
>      return fdctrl_read(opaque, (uint32_t)reg);
>  }
>  
> -static void fdctrl_write_mem (void *opaque, target_phys_addr_t reg,
> +static void fdctrl_write_mem (void *opaque, hwaddr reg,
>                                uint64_t value, unsigned size)
>  {
>      fdctrl_write(opaque, (uint32_t)reg, value);
> @@ -2032,7 +2032,7 @@ ISADevice *fdctrl_init_isa(ISABus *bus, DriveInfo **fds)
>  }
>  
>  void fdctrl_init_sysbus(qemu_irq irq, int dma_chann,
> -                        target_phys_addr_t mmio_base, DriveInfo **fds)
> +                        hwaddr mmio_base, DriveInfo **fds)
>  {
>      FDCtrl *fdctrl;
>      DeviceState *dev;
> @@ -2053,7 +2053,7 @@ void fdctrl_init_sysbus(qemu_irq irq, int dma_chann,
>      sysbus_mmio_map(&sys->busdev, 0, mmio_base);
>  }
>  
> -void sun4m_fdctrl_init(qemu_irq irq, target_phys_addr_t io_base,
> +void sun4m_fdctrl_init(qemu_irq irq, hwaddr io_base,
>                         DriveInfo **fds, qemu_irq *fdc_tc)
>  {
>      DeviceState *dev;
> diff --git a/hw/fdc.h b/hw/fdc.h
> index b5c9f31..a8f6f7c 100644
> --- a/hw/fdc.h
> +++ b/hw/fdc.h
> @@ -15,8 +15,8 @@ typedef enum FDriveType {
>  
>  ISADevice *fdctrl_init_isa(ISABus *bus, DriveInfo **fds);
>  void fdctrl_init_sysbus(qemu_irq irq, int dma_chann,
> -                        target_phys_addr_t mmio_base, DriveInfo **fds);
> -void sun4m_fdctrl_init(qemu_irq irq, target_phys_addr_t io_base,
> +                        hwaddr mmio_base, DriveInfo **fds);
> +void sun4m_fdctrl_init(qemu_irq irq, hwaddr io_base,
>                         DriveInfo **fds, qemu_irq *fdc_tc);
>  
>  FDriveType isa_fdc_get_drive_type(ISADevice *fdc, int i);
> diff --git a/hw/flash.h b/hw/flash.h
> index 9c9e526..d790f3c 100644
> --- a/hw/flash.h
> +++ b/hw/flash.h
> @@ -5,18 +5,18 @@
>  typedef struct pflash_t pflash_t;
>  
>  /* pflash_cfi01.c */
> -pflash_t *pflash_cfi01_register(target_phys_addr_t base,
> +pflash_t *pflash_cfi01_register(hwaddr base,
>                                  DeviceState *qdev, const char *name,
> -                                target_phys_addr_t size,
> +                                hwaddr size,
>                                  BlockDriverState *bs,
>                                  uint32_t sector_len, int nb_blocs, int width,
>                                  uint16_t id0, uint16_t id1,
>                                  uint16_t id2, uint16_t id3, int be);
>  
>  /* pflash_cfi02.c */
> -pflash_t *pflash_cfi02_register(target_phys_addr_t base,
> +pflash_t *pflash_cfi02_register(hwaddr base,
>                                  DeviceState *qdev, const char *name,
> -                                target_phys_addr_t size,
> +                                hwaddr size,
>                                  BlockDriverState *bs, uint32_t sector_len,
>                                  int nb_blocs, int nb_mappings, int width,
>                                  uint16_t id0, uint16_t id1,
> diff --git a/hw/framebuffer.c b/hw/framebuffer.c
> index 27fa6f5..fa0f786 100644
> --- a/hw/framebuffer.c
> +++ b/hw/framebuffer.c
> @@ -26,7 +26,7 @@
>  void framebuffer_update_display(
>      DisplayState *ds,
>      MemoryRegion *address_space,
> -    target_phys_addr_t base,
> +    hwaddr base,
>      int cols, /* Width in pixels.  */
>      int rows, /* Height in pixels.  */
>      int src_width, /* Length of source line, in bytes.  */
> @@ -38,7 +38,7 @@ void framebuffer_update_display(
>      int *first_row, /* Input and output.  */
>      int *last_row /* Output only */)
>  {
> -    target_phys_addr_t src_len;
> +    hwaddr src_len;
>      uint8_t *dest;
>      uint8_t *src;
>      uint8_t *src_base;
> diff --git a/hw/framebuffer.h b/hw/framebuffer.h
> index 527a6b8..46e375b 100644
> --- a/hw/framebuffer.h
> +++ b/hw/framebuffer.h
> @@ -10,7 +10,7 @@ typedef void (*drawfn)(void *, uint8_t *, const uint8_t *, int, int);
>  void framebuffer_update_display(
>      DisplayState *ds,
>      MemoryRegion *address_space,
> -    target_phys_addr_t base,
> +    hwaddr base,
>      int cols,
>      int rows,
>      int src_width,
> diff --git a/hw/fw_cfg.c b/hw/fw_cfg.c
> index dcde1a9..2b92cda 100644
> --- a/hw/fw_cfg.c
> +++ b/hw/fw_cfg.c
> @@ -258,37 +258,37 @@ static uint8_t fw_cfg_read(FWCfgState *s)
>      return ret;
>  }
>  
> -static uint64_t fw_cfg_data_mem_read(void *opaque, target_phys_addr_t addr,
> +static uint64_t fw_cfg_data_mem_read(void *opaque, hwaddr addr,
>                                       unsigned size)
>  {
>      return fw_cfg_read(opaque);
>  }
>  
> -static void fw_cfg_data_mem_write(void *opaque, target_phys_addr_t addr,
> +static void fw_cfg_data_mem_write(void *opaque, hwaddr addr,
>                                    uint64_t value, unsigned size)
>  {
>      fw_cfg_write(opaque, (uint8_t)value);
>  }
>  
> -static void fw_cfg_ctl_mem_write(void *opaque, target_phys_addr_t addr,
> +static void fw_cfg_ctl_mem_write(void *opaque, hwaddr addr,
>                                   uint64_t value, unsigned size)
>  {
>      fw_cfg_select(opaque, (uint16_t)value);
>  }
>  
> -static bool fw_cfg_ctl_mem_valid(void *opaque, target_phys_addr_t addr,
> +static bool fw_cfg_ctl_mem_valid(void *opaque, hwaddr addr,
>                                   unsigned size, bool is_write)
>  {
>      return is_write && size == 2;
>  }
>  
> -static uint64_t fw_cfg_comb_read(void *opaque, target_phys_addr_t addr,
> +static uint64_t fw_cfg_comb_read(void *opaque, hwaddr addr,
>                                   unsigned size)
>  {
>      return fw_cfg_read(opaque);
>  }
>  
> -static void fw_cfg_comb_write(void *opaque, target_phys_addr_t addr,
> +static void fw_cfg_comb_write(void *opaque, hwaddr addr,
>                                uint64_t value, unsigned size)
>  {
>      switch (size) {
> @@ -301,7 +301,7 @@ static void fw_cfg_comb_write(void *opaque, target_phys_addr_t addr,
>      }
>  }
>  
> -static bool fw_cfg_comb_valid(void *opaque, target_phys_addr_t addr,
> +static bool fw_cfg_comb_valid(void *opaque, hwaddr addr,
>                                    unsigned size, bool is_write)
>  {
>      return (size == 1) || (is_write && size == 2);
> @@ -494,7 +494,7 @@ static void fw_cfg_machine_ready(struct Notifier *n, void *data)
>  }
>  
>  FWCfgState *fw_cfg_init(uint32_t ctl_port, uint32_t data_port,
> -                        target_phys_addr_t ctl_addr, target_phys_addr_t data_addr)
> +                        hwaddr ctl_addr, hwaddr data_addr)
>  {
>      DeviceState *dev;
>      SysBusDevice *d;
> diff --git a/hw/fw_cfg.h b/hw/fw_cfg.h
> index 856bf91..619a394 100644
> --- a/hw/fw_cfg.h
> +++ b/hw/fw_cfg.h
> @@ -63,7 +63,7 @@ int fw_cfg_add_callback(FWCfgState *s, uint16_t key, FWCfgCallback callback,
>  int fw_cfg_add_file(FWCfgState *s, const char *filename, uint8_t *data,
>                      uint32_t len);
>  FWCfgState *fw_cfg_init(uint32_t ctl_port, uint32_t data_port,
> -                        target_phys_addr_t crl_addr, target_phys_addr_t data_addr);
> +                        hwaddr crl_addr, hwaddr data_addr);
>  
>  #endif /* NO_QEMU_PROTOS */
>  
> diff --git a/hw/g364fb.c b/hw/g364fb.c
> index 059e622..f7b4bf5 100644
> --- a/hw/g364fb.c
> +++ b/hw/g364fb.c
> @@ -362,7 +362,7 @@ static void g364fb_screen_dump(void *opaque, const char *filename, bool cswitch,
>  
>  /* called for accesses to io ports */
>  static uint64_t g364fb_ctrl_read(void *opaque,
> -                                 target_phys_addr_t addr,
> +                                 hwaddr addr,
>                                   unsigned int size)
>  {
>      G364State *s = opaque;
> @@ -424,7 +424,7 @@ static void g364_invalidate_cursor_position(G364State *s)
>  }
>  
>  static void g364fb_ctrl_write(void *opaque,
> -                              target_phys_addr_t addr,
> +                              hwaddr addr,
>                                uint64_t val,
>                                unsigned int size)
>  {
> diff --git a/hw/grlib.h b/hw/grlib.h
> index e1c4137..35c22f5 100644
> --- a/hw/grlib.h
> +++ b/hw/grlib.h
> @@ -41,7 +41,7 @@ void grlib_irqmp_set_irq(void *opaque, int irq, int level);
>  void grlib_irqmp_ack(DeviceState *dev, int intno);
>  
>  static inline
> -DeviceState *grlib_irqmp_create(target_phys_addr_t   base,
> +DeviceState *grlib_irqmp_create(hwaddr   base,
>                                  CPUSPARCState            *env,
>                                  qemu_irq           **cpu_irqs,
>                                  uint32_t             nr_irqs,
> @@ -73,7 +73,7 @@ DeviceState *grlib_irqmp_create(target_phys_addr_t   base,
>  /* GPTimer */
>  
>  static inline
> -DeviceState *grlib_gptimer_create(target_phys_addr_t  base,
> +DeviceState *grlib_gptimer_create(hwaddr  base,
>                                    uint32_t            nr_timers,
>                                    uint32_t            freq,
>                                    qemu_irq           *cpu_irqs,
> @@ -103,7 +103,7 @@ DeviceState *grlib_gptimer_create(target_phys_addr_t  base,
>  /* APB UART */
>  
>  static inline
> -DeviceState *grlib_apbuart_create(target_phys_addr_t  base,
> +DeviceState *grlib_apbuart_create(hwaddr  base,
>                                    CharDriverState    *serial,
>                                    qemu_irq            irq)
>  {
> diff --git a/hw/grlib_apbuart.c b/hw/grlib_apbuart.c
> index 73fc989..0865764 100644
> --- a/hw/grlib_apbuart.c
> +++ b/hw/grlib_apbuart.c
> @@ -151,7 +151,7 @@ static void grlib_apbuart_event(void *opaque, int event)
>  }
>  
>  
> -static uint64_t grlib_apbuart_read(void *opaque, target_phys_addr_t addr,
> +static uint64_t grlib_apbuart_read(void *opaque, hwaddr addr,
>                                     unsigned size)
>  {
>      UART     *uart = opaque;
> @@ -181,7 +181,7 @@ static uint64_t grlib_apbuart_read(void *opaque, target_phys_addr_t addr,
>      }
>  }
>  
> -static void grlib_apbuart_write(void *opaque, target_phys_addr_t addr,
> +static void grlib_apbuart_write(void *opaque, hwaddr addr,
>                                  uint64_t value, unsigned size)
>  {
>      UART          *uart = opaque;
> diff --git a/hw/grlib_gptimer.c b/hw/grlib_gptimer.c
> index 41770a9..2fdccfb 100644
> --- a/hw/grlib_gptimer.c
> +++ b/hw/grlib_gptimer.c
> @@ -155,11 +155,11 @@ static void grlib_gptimer_hit(void *opaque)
>      }
>  }
>  
> -static uint64_t grlib_gptimer_read(void *opaque, target_phys_addr_t addr,
> +static uint64_t grlib_gptimer_read(void *opaque, hwaddr addr,
>                                     unsigned size)
>  {
>      GPTimerUnit        *unit  = opaque;
> -    target_phys_addr_t  timer_addr;
> +    hwaddr  timer_addr;
>      int                 id;
>      uint32_t            value = 0;
>  
> @@ -214,11 +214,11 @@ static uint64_t grlib_gptimer_read(void *opaque, target_phys_addr_t addr,
>      return 0;
>  }
>  
> -static void grlib_gptimer_write(void *opaque, target_phys_addr_t addr,
> +static void grlib_gptimer_write(void *opaque, hwaddr addr,
>                                  uint64_t value, unsigned size)
>  {
>      GPTimerUnit        *unit = opaque;
> -    target_phys_addr_t  timer_addr;
> +    hwaddr  timer_addr;
>      int                 id;
>  
>      addr &= 0xff;
> diff --git a/hw/grlib_irqmp.c b/hw/grlib_irqmp.c
> index 0f6e65c..23a6a02 100644
> --- a/hw/grlib_irqmp.c
> +++ b/hw/grlib_irqmp.c
> @@ -162,7 +162,7 @@ void grlib_irqmp_set_irq(void *opaque, int irq, int level)
>      }
>  }
>  
> -static uint64_t grlib_irqmp_read(void *opaque, target_phys_addr_t addr,
> +static uint64_t grlib_irqmp_read(void *opaque, hwaddr addr,
>                                   unsigned size)
>  {
>      IRQMP      *irqmp = opaque;
> @@ -226,7 +226,7 @@ static uint64_t grlib_irqmp_read(void *opaque, target_phys_addr_t addr,
>      return 0;
>  }
>  
> -static void grlib_irqmp_write(void *opaque, target_phys_addr_t addr,
> +static void grlib_irqmp_write(void *opaque, hwaddr addr,
>                                uint64_t value, unsigned size)
>  {
>      IRQMP      *irqmp = opaque;
> diff --git a/hw/gt64xxx.c b/hw/gt64xxx.c
> index e95e664..95d491d 100644
> --- a/hw/gt64xxx.c
> +++ b/hw/gt64xxx.c
> @@ -225,8 +225,8 @@
>  #define GT_PCI1_SERR1MASK    	(0xca8 >> 2)
>  
>  #define PCI_MAPPING_ENTRY(regname)            \
> -    target_phys_addr_t regname ##_start;      \
> -    target_phys_addr_t regname ##_length;     \
> +    hwaddr regname ##_start;      \
> +    hwaddr regname ##_length;     \
>      MemoryRegion regname ##_mem
>  
>  #define TYPE_GT64120_PCI_HOST_BRIDGE "gt64120"
> @@ -245,11 +245,11 @@
>  /* Adjust range to avoid touching space which isn't mappable via PCI */
>  /* XXX: Hardcoded values for Malta: 0x1e000000 - 0x1f100000
>                                      0x1fc00000 - 0x1fd00000  */
> -static void check_reserved_space (target_phys_addr_t *start,
> -                                  target_phys_addr_t *length)
> +static void check_reserved_space (hwaddr *start,
> +                                  hwaddr *length)
>  {
> -    target_phys_addr_t begin = *start;
> -    target_phys_addr_t end = *start + *length;
> +    hwaddr begin = *start;
> +    hwaddr end = *start + *length;
>  
>      if (end >= 0x1e000000LL && end < 0x1f100000LL)
>          end = 0x1e000000LL;
> @@ -271,8 +271,8 @@ static void check_reserved_space (target_phys_addr_t *start,
>  
>  static void gt64120_isd_mapping(GT64120State *s)
>  {
> -    target_phys_addr_t start = s->regs[GT_ISD] << 21;
> -    target_phys_addr_t length = 0x1000;
> +    hwaddr start = s->regs[GT_ISD] << 21;
> +    hwaddr length = 0x1000;
>  
>      if (s->ISD_length) {
>          memory_region_del_subregion(get_system_memory(), &s->ISD_mem);
> @@ -311,7 +311,7 @@ static void gt64120_pci_mapping(GT64120State *s)
>      }
>  }
>  
> -static void gt64120_writel (void *opaque, target_phys_addr_t addr,
> +static void gt64120_writel (void *opaque, hwaddr addr,
>                              uint64_t val, unsigned size)
>  {
>      GT64120State *s = opaque;
> @@ -594,7 +594,7 @@ static void gt64120_writel (void *opaque, target_phys_addr_t addr,
>  }
>  
>  static uint64_t gt64120_readl (void *opaque,
> -                               target_phys_addr_t addr, unsigned size)
> +                               hwaddr addr, unsigned size)
>  {
>      GT64120State *s = opaque;
>      PCIHostState *phb = PCI_HOST_BRIDGE(s);
> diff --git a/hw/heathrow_pic.c b/hw/heathrow_pic.c
> index 16f48d1..b9ec8e7 100644
> --- a/hw/heathrow_pic.c
> +++ b/hw/heathrow_pic.c
> @@ -63,7 +63,7 @@ static void heathrow_pic_update(HeathrowPICS *s)
>      }
>  }
>  
> -static void pic_write(void *opaque, target_phys_addr_t addr,
> +static void pic_write(void *opaque, hwaddr addr,
>                        uint64_t value, unsigned size)
>  {
>      HeathrowPICS *s = opaque;
> @@ -91,7 +91,7 @@ static void pic_write(void *opaque, target_phys_addr_t addr,
>      }
>  }
>  
> -static uint64_t pic_read(void *opaque, target_phys_addr_t addr,
> +static uint64_t pic_read(void *opaque, hwaddr addr,
>                           unsigned size)
>  {
>      HeathrowPICS *s = opaque;
> diff --git a/hw/highbank.c b/hw/highbank.c
> index 15036b6..afbb005 100644
> --- a/hw/highbank.c
> +++ b/hw/highbank.c
> @@ -79,7 +79,7 @@ static void hb_reset_secondary(ARMCPU *cpu, const struct arm_boot_info *info)
>  }
>  
>  #define NUM_REGS      0x200
> -static void hb_regs_write(void *opaque, target_phys_addr_t offset,
> +static void hb_regs_write(void *opaque, hwaddr offset,
>                            uint64_t value, unsigned size)
>  {
>      uint32_t *regs = opaque;
> @@ -95,7 +95,7 @@ static void hb_regs_write(void *opaque, target_phys_addr_t offset,
>      regs[offset/4] = value;
>  }
>  
> -static uint64_t hb_regs_read(void *opaque, target_phys_addr_t offset,
> +static uint64_t hb_regs_read(void *opaque, hwaddr offset,
>                               unsigned size)
>  {
>      uint32_t *regs = opaque;
> diff --git a/hw/hpet.c b/hw/hpet.c
> index fd3ddca..50ac067 100644
> --- a/hw/hpet.c
> +++ b/hw/hpet.c
> @@ -370,20 +370,20 @@ static void hpet_del_timer(HPETTimer *t)
>  }
>  
>  #ifdef HPET_DEBUG
> -static uint32_t hpet_ram_readb(void *opaque, target_phys_addr_t addr)
> +static uint32_t hpet_ram_readb(void *opaque, hwaddr addr)
>  {
>      printf("qemu: hpet_read b at %" PRIx64 "\n", addr);
>      return 0;
>  }
>  
> -static uint32_t hpet_ram_readw(void *opaque, target_phys_addr_t addr)
> +static uint32_t hpet_ram_readw(void *opaque, hwaddr addr)
>  {
>      printf("qemu: hpet_read w at %" PRIx64 "\n", addr);
>      return 0;
>  }
>  #endif
>  
> -static uint64_t hpet_ram_read(void *opaque, target_phys_addr_t addr,
> +static uint64_t hpet_ram_read(void *opaque, hwaddr addr,
>                                unsigned size)
>  {
>      HPETState *s = opaque;
> @@ -455,7 +455,7 @@ static uint64_t hpet_ram_read(void *opaque, target_phys_addr_t addr,
>      return 0;
>  }
>  
> -static void hpet_ram_write(void *opaque, target_phys_addr_t addr,
> +static void hpet_ram_write(void *opaque, hwaddr addr,
>                             uint64_t value, unsigned size)
>  {
>      int i;
> diff --git a/hw/i82378.c b/hw/i82378.c
> index 2123c14..99f35d4 100644
> --- a/hw/i82378.c
> +++ b/hw/i82378.c
> @@ -59,7 +59,7 @@
>      },
>  };
>  
> -static void i82378_io_write(void *opaque, target_phys_addr_t addr,
> +static void i82378_io_write(void *opaque, hwaddr addr,
>                              uint64_t value, unsigned int size)
>  {
>      switch (size) {
> @@ -83,7 +83,7 @@ static void i82378_io_write(void *opaque, target_phys_addr_t addr,
>      }
>  }
>  
> -static uint64_t i82378_io_read(void *opaque, target_phys_addr_t addr,
> +static uint64_t i82378_io_read(void *opaque, hwaddr addr,
>                                 unsigned int size)
>  {
>      DPRINTF("%s: " TARGET_FMT_plx "\n", __func__, addr);
> @@ -105,7 +105,7 @@ static uint64_t i82378_io_read(void *opaque, target_phys_addr_t addr,
>      .endianness = DEVICE_LITTLE_ENDIAN,
>  };
>  
> -static void i82378_mem_write(void *opaque, target_phys_addr_t addr,
> +static void i82378_mem_write(void *opaque, hwaddr addr,
>                               uint64_t value, unsigned int size)
>  {
>      switch (size) {
> @@ -129,7 +129,7 @@ static void i82378_mem_write(void *opaque, target_phys_addr_t addr,
>      }
>  }
>  
> -static uint64_t i82378_mem_read(void *opaque, target_phys_addr_t addr,
> +static uint64_t i82378_mem_read(void *opaque, hwaddr addr,
>                                  unsigned int size)
>  {
>      DPRINTF("%s: " TARGET_FMT_plx "\n", __func__, addr);
> diff --git a/hw/i8259.c b/hw/i8259.c
> index 53daf78..af0ba4d 100644
> --- a/hw/i8259.c
> +++ b/hw/i8259.c
> @@ -235,7 +235,7 @@ static void pic_reset(DeviceState *dev)
>      pic_init_reset(s);
>  }
>  
> -static void pic_ioport_write(void *opaque, target_phys_addr_t addr64,
> +static void pic_ioport_write(void *opaque, hwaddr addr64,
>                               uint64_t val64, unsigned size)
>  {
>      PICCommonState *s = opaque;
> @@ -329,7 +329,7 @@ static void pic_ioport_write(void *opaque, target_phys_addr_t addr64,
>      }
>  }
>  
> -static uint64_t pic_ioport_read(void *opaque, target_phys_addr_t addr,
> +static uint64_t pic_ioport_read(void *opaque, hwaddr addr,
>                                  unsigned size)
>  {
>      PICCommonState *s = opaque;
> @@ -366,14 +366,14 @@ int pic_get_output(DeviceState *d)
>      return (pic_get_irq(s) >= 0);
>  }
>  
> -static void elcr_ioport_write(void *opaque, target_phys_addr_t addr,
> +static void elcr_ioport_write(void *opaque, hwaddr addr,
>                                uint64_t val, unsigned size)
>  {
>      PICCommonState *s = opaque;
>      s->elcr = val & s->elcr_mask;
>  }
>  
> -static uint64_t elcr_ioport_read(void *opaque, target_phys_addr_t addr,
> +static uint64_t elcr_ioport_read(void *opaque, hwaddr addr,
>                                   unsigned size)
>  {
>      PICCommonState *s = opaque;
> diff --git a/hw/ide.h b/hw/ide.h
> index 2db4079..add742c 100644
> --- a/hw/ide.h
> +++ b/hw/ide.h
> @@ -24,7 +24,7 @@ MemoryRegion *pmac_ide_init (DriveInfo **hd_table, qemu_irq irq,
>  		   void *dbdma, int channel, qemu_irq dma_irq);
>  
>  /* ide-mmio.c */
> -void mmio_ide_init (target_phys_addr_t membase, target_phys_addr_t membase2,
> +void mmio_ide_init (hwaddr membase, hwaddr membase2,
>                      MemoryRegion *address_space,
>                      qemu_irq irq, int shift,
>                      DriveInfo *hd0, DriveInfo *hd1);
> diff --git a/hw/ide/ahci.c b/hw/ide/ahci.c
> index 68671bc..67562db 100644
> --- a/hw/ide/ahci.c
> +++ b/hw/ide/ahci.c
> @@ -174,7 +174,7 @@ static void ahci_trigger_irq(AHCIState *s, AHCIDevice *d,
>  
>  static void map_page(uint8_t **ptr, uint64_t addr, uint32_t wanted)
>  {
> -    target_phys_addr_t len = wanted;
> +    hwaddr len = wanted;
>  
>      if (*ptr) {
>          cpu_physical_memory_unmap(*ptr, len, 1, len);
> @@ -279,7 +279,7 @@ static void  ahci_port_write(AHCIState *s, int port, int offset, uint32_t val)
>      }
>  }
>  
> -static uint64_t ahci_mem_read(void *opaque, target_phys_addr_t addr,
> +static uint64_t ahci_mem_read(void *opaque, hwaddr addr,
>                                unsigned size)
>  {
>      AHCIState *s = opaque;
> @@ -317,7 +317,7 @@ static uint64_t ahci_mem_read(void *opaque, target_phys_addr_t addr,
>  
>  
>  
> -static void ahci_mem_write(void *opaque, target_phys_addr_t addr,
> +static void ahci_mem_write(void *opaque, hwaddr addr,
>                             uint64_t val, unsigned size)
>  {
>      AHCIState *s = opaque;
> @@ -373,7 +373,7 @@ static void ahci_mem_write(void *opaque, target_phys_addr_t addr,
>      .endianness = DEVICE_LITTLE_ENDIAN,
>  };
>  
> -static uint64_t ahci_idp_read(void *opaque, target_phys_addr_t addr,
> +static uint64_t ahci_idp_read(void *opaque, hwaddr addr,
>                                unsigned size)
>  {
>      AHCIState *s = opaque;
> @@ -389,7 +389,7 @@ static uint64_t ahci_idp_read(void *opaque, target_phys_addr_t addr,
>      }
>  }
>  
> -static void ahci_idp_write(void *opaque, target_phys_addr_t addr,
> +static void ahci_idp_write(void *opaque, hwaddr addr,
>                             uint64_t val, unsigned size)
>  {
>      AHCIState *s = opaque;
> diff --git a/hw/ide/cmd646.c b/hw/ide/cmd646.c
> index e0b9443..804db60 100644
> --- a/hw/ide/cmd646.c
> +++ b/hw/ide/cmd646.c
> @@ -43,7 +43,7 @@
>  
>  static void cmd646_update_irq(PCIIDEState *d);
>  
> -static uint64_t cmd646_cmd_read(void *opaque, target_phys_addr_t addr,
> +static uint64_t cmd646_cmd_read(void *opaque, hwaddr addr,
>                                  unsigned size)
>  {
>      CMD646BAR *cmd646bar = opaque;
> @@ -54,7 +54,7 @@ static uint64_t cmd646_cmd_read(void *opaque, target_phys_addr_t addr,
>      return ide_status_read(cmd646bar->bus, addr + 2);
>  }
>  
> -static void cmd646_cmd_write(void *opaque, target_phys_addr_t addr,
> +static void cmd646_cmd_write(void *opaque, hwaddr addr,
>                               uint64_t data, unsigned size)
>  {
>      CMD646BAR *cmd646bar = opaque;
> @@ -71,7 +71,7 @@ static void cmd646_cmd_write(void *opaque, target_phys_addr_t addr,
>      .endianness = DEVICE_LITTLE_ENDIAN,
>  };
>  
> -static uint64_t cmd646_data_read(void *opaque, target_phys_addr_t addr,
> +static uint64_t cmd646_data_read(void *opaque, hwaddr addr,
>                                   unsigned size)
>  {
>      CMD646BAR *cmd646bar = opaque;
> @@ -88,7 +88,7 @@ static uint64_t cmd646_data_read(void *opaque, target_phys_addr_t addr,
>      return ((uint64_t)1 << (size * 8)) - 1;
>  }
>  
> -static void cmd646_data_write(void *opaque, target_phys_addr_t addr,
> +static void cmd646_data_write(void *opaque, hwaddr addr,
>                               uint64_t data, unsigned size)
>  {
>      CMD646BAR *cmd646bar = opaque;
> @@ -121,7 +121,7 @@ static void setup_cmd646_bar(PCIIDEState *d, int bus_num)
>      memory_region_init_io(&bar->data, &cmd646_data_ops, bar, "cmd646-data", 8);
>  }
>  
> -static uint64_t bmdma_read(void *opaque, target_phys_addr_t addr,
> +static uint64_t bmdma_read(void *opaque, hwaddr addr,
>                             unsigned size)
>  {
>      BMDMAState *bm = opaque;
> @@ -159,7 +159,7 @@ static uint64_t bmdma_read(void *opaque, target_phys_addr_t addr,
>      return val;
>  }
>  
> -static void bmdma_write(void *opaque, target_phys_addr_t addr,
> +static void bmdma_write(void *opaque, hwaddr addr,
>                          uint64_t val, unsigned size)
>  {
>      BMDMAState *bm = opaque;
> diff --git a/hw/ide/macio.c b/hw/ide/macio.c
> index f228725..720af6e 100644
> --- a/hw/ide/macio.c
> +++ b/hw/ide/macio.c
> @@ -198,7 +198,7 @@ static void pmac_ide_flush(DBDMA_io *io)
>  
>  /* PowerMac IDE memory IO */
>  static void pmac_ide_writeb (void *opaque,
> -                             target_phys_addr_t addr, uint32_t val)
> +                             hwaddr addr, uint32_t val)
>  {
>      MACIOIDEState *d = opaque;
>  
> @@ -216,7 +216,7 @@ static void pmac_ide_writeb (void *opaque,
>      }
>  }
>  
> -static uint32_t pmac_ide_readb (void *opaque,target_phys_addr_t addr)
> +static uint32_t pmac_ide_readb (void *opaque,hwaddr addr)
>  {
>      uint8_t retval;
>      MACIOIDEState *d = opaque;
> @@ -238,7 +238,7 @@ static uint32_t pmac_ide_readb (void *opaque,target_phys_addr_t addr)
>  }
>  
>  static void pmac_ide_writew (void *opaque,
> -                             target_phys_addr_t addr, uint32_t val)
> +                             hwaddr addr, uint32_t val)
>  {
>      MACIOIDEState *d = opaque;
>  
> @@ -249,7 +249,7 @@ static void pmac_ide_writew (void *opaque,
>      }
>  }
>  
> -static uint32_t pmac_ide_readw (void *opaque,target_phys_addr_t addr)
> +static uint32_t pmac_ide_readw (void *opaque,hwaddr addr)
>  {
>      uint16_t retval;
>      MACIOIDEState *d = opaque;
> @@ -265,7 +265,7 @@ static uint32_t pmac_ide_readw (void *opaque,target_phys_addr_t addr)
>  }
>  
>  static void pmac_ide_writel (void *opaque,
> -                             target_phys_addr_t addr, uint32_t val)
> +                             hwaddr addr, uint32_t val)
>  {
>      MACIOIDEState *d = opaque;
>  
> @@ -276,7 +276,7 @@ static void pmac_ide_writel (void *opaque,
>      }
>  }
>  
> -static uint32_t pmac_ide_readl (void *opaque,target_phys_addr_t addr)
> +static uint32_t pmac_ide_readl (void *opaque,hwaddr addr)
>  {
>      uint32_t retval;
>      MACIOIDEState *d = opaque;
> diff --git a/hw/ide/mmio.c b/hw/ide/mmio.c
> index fcfb09e..bcb26c8 100644
> --- a/hw/ide/mmio.c
> +++ b/hw/ide/mmio.c
> @@ -47,7 +47,7 @@ static void mmio_ide_reset(void *opaque)
>      ide_bus_reset(&s->bus);
>  }
>  
> -static uint64_t mmio_ide_read(void *opaque, target_phys_addr_t addr,
> +static uint64_t mmio_ide_read(void *opaque, hwaddr addr,
>                                unsigned size)
>  {
>      MMIOState *s = opaque;
> @@ -58,7 +58,7 @@ static uint64_t mmio_ide_read(void *opaque, target_phys_addr_t addr,
>          return ide_data_readw(&s->bus, 0);
>  }
>  
> -static void mmio_ide_write(void *opaque, target_phys_addr_t addr,
> +static void mmio_ide_write(void *opaque, hwaddr addr,
>                             uint64_t val, unsigned size)
>  {
>      MMIOState *s = opaque;
> @@ -75,14 +75,14 @@ static void mmio_ide_write(void *opaque, target_phys_addr_t addr,
>      .endianness = DEVICE_NATIVE_ENDIAN,
>  };
>  
> -static uint64_t mmio_ide_status_read(void *opaque, target_phys_addr_t addr,
> +static uint64_t mmio_ide_status_read(void *opaque, hwaddr addr,
>                                       unsigned size)
>  {
>      MMIOState *s= opaque;
>      return ide_status_read(&s->bus, 0);
>  }
>  
> -static void mmio_ide_cmd_write(void *opaque, target_phys_addr_t addr,
> +static void mmio_ide_cmd_write(void *opaque, hwaddr addr,
>                                 uint64_t val, unsigned size)
>  {
>      MMIOState *s = opaque;
> @@ -107,7 +107,7 @@ static void mmio_ide_cmd_write(void *opaque, target_phys_addr_t addr,
>      }
>  };
>  
> -void mmio_ide_init (target_phys_addr_t membase, target_phys_addr_t membase2,
> +void mmio_ide_init (hwaddr membase, hwaddr membase2,
>                      MemoryRegion *address_space,
>                      qemu_irq irq, int shift,
>                      DriveInfo *hd0, DriveInfo *hd1)
> diff --git a/hw/ide/pci.c b/hw/ide/pci.c
> index 644533f..bcdd70e 100644
> --- a/hw/ide/pci.c
> +++ b/hw/ide/pci.c
> @@ -327,7 +327,7 @@ void bmdma_cmd_writeb(BMDMAState *bm, uint32_t val)
>      bm->cmd = val & 0x09;
>  }
>  
> -static uint64_t bmdma_addr_read(void *opaque, target_phys_addr_t addr,
> +static uint64_t bmdma_addr_read(void *opaque, hwaddr addr,
>                                  unsigned width)
>  {
>      BMDMAState *bm = opaque;
> @@ -341,7 +341,7 @@ static uint64_t bmdma_addr_read(void *opaque, target_phys_addr_t addr,
>      return data;
>  }
>  
> -static void bmdma_addr_write(void *opaque, target_phys_addr_t addr,
> +static void bmdma_addr_write(void *opaque, hwaddr addr,
>                               uint64_t data, unsigned width)
>  {
>      BMDMAState *bm = opaque;
> diff --git a/hw/ide/piix.c b/hw/ide/piix.c
> index 4ded9ee..9431bad 100644
> --- a/hw/ide/piix.c
> +++ b/hw/ide/piix.c
> @@ -33,7 +33,7 @@
>  
>  #include <hw/ide/pci.h>
>  
> -static uint64_t bmdma_read(void *opaque, target_phys_addr_t addr, unsigned size)
> +static uint64_t bmdma_read(void *opaque, hwaddr addr, unsigned size)
>  {
>      BMDMAState *bm = opaque;
>      uint32_t val;
> @@ -59,7 +59,7 @@ static uint64_t bmdma_read(void *opaque, target_phys_addr_t addr, unsigned size)
>      return val;
>  }
>  
> -static void bmdma_write(void *opaque, target_phys_addr_t addr,
> +static void bmdma_write(void *opaque, hwaddr addr,
>                          uint64_t val, unsigned size)
>  {
>      BMDMAState *bm = opaque;
> diff --git a/hw/ide/via.c b/hw/ide/via.c
> index b20e4f0..efda173 100644
> --- a/hw/ide/via.c
> +++ b/hw/ide/via.c
> @@ -33,7 +33,7 @@
>  
>  #include <hw/ide/pci.h>
>  
> -static uint64_t bmdma_read(void *opaque, target_phys_addr_t addr,
> +static uint64_t bmdma_read(void *opaque, hwaddr addr,
>                             unsigned size)
>  {
>      BMDMAState *bm = opaque;
> @@ -60,7 +60,7 @@ static uint64_t bmdma_read(void *opaque, target_phys_addr_t addr,
>      return val;
>  }
>  
> -static void bmdma_write(void *opaque, target_phys_addr_t addr,
> +static void bmdma_write(void *opaque, hwaddr addr,
>                          uint64_t val, unsigned size)
>  {
>      BMDMAState *bm = opaque;
> diff --git a/hw/imx.h b/hw/imx.h
> index ccf586f..ea9e093 100644
> --- a/hw/imx.h
> +++ b/hw/imx.h
> @@ -11,7 +11,7 @@
>  #ifndef IMX_H
>  #define IMX_H
>  
> -void imx_serial_create(int uart, const target_phys_addr_t addr, qemu_irq irq);
> +void imx_serial_create(int uart, const hwaddr addr, qemu_irq irq);
>  
>  typedef enum  {
>      NOCLK,
> @@ -23,10 +23,10 @@ typedef enum  {
>  
>  uint32_t imx_clock_frequency(DeviceState *s, IMXClk clock);
>  
> -void imx_timerp_create(const target_phys_addr_t addr,
> +void imx_timerp_create(const hwaddr addr,
>                        qemu_irq irq,
>                        DeviceState *ccm);
> -void imx_timerg_create(const target_phys_addr_t addr,
> +void imx_timerg_create(const hwaddr addr,
>                        qemu_irq irq,
>                        DeviceState *ccm);
>  
> diff --git a/hw/imx_avic.c b/hw/imx_avic.c
> index b1a8fe6..8109793 100644
> --- a/hw/imx_avic.c
> +++ b/hw/imx_avic.c
> @@ -152,7 +152,7 @@ static void imx_avic_set_irq(void *opaque, int irq, int level)
>  
>  
>  static uint64_t imx_avic_read(void *opaque,
> -                             target_phys_addr_t offset, unsigned size)
> +                             hwaddr offset, unsigned size)
>  {
>      IMXAVICState *s = (IMXAVICState *)opaque;
>  
> @@ -259,7 +259,7 @@ static uint64_t imx_avic_read(void *opaque,
>      }
>  }
>  
> -static void imx_avic_write(void *opaque, target_phys_addr_t offset,
> +static void imx_avic_write(void *opaque, hwaddr offset,
>                            uint64_t val, unsigned size)
>  {
>      IMXAVICState *s = (IMXAVICState *)opaque;
> diff --git a/hw/imx_ccm.c b/hw/imx_ccm.c
> index 10952c6..f2e623c 100644
> --- a/hw/imx_ccm.c
> +++ b/hw/imx_ccm.c
> @@ -191,7 +191,7 @@ static void imx_ccm_reset(DeviceState *dev)
>      update_clocks(s);
>  }
>  
> -static uint64_t imx_ccm_read(void *opaque, target_phys_addr_t offset,
> +static uint64_t imx_ccm_read(void *opaque, hwaddr offset,
>                                  unsigned size)
>  {
>      IMXCCMState *s = (IMXCCMState *)opaque;
> @@ -232,7 +232,7 @@ static uint64_t imx_ccm_read(void *opaque, target_phys_addr_t offset,
>      return 0;
>  }
>  
> -static void imx_ccm_write(void *opaque, target_phys_addr_t offset,
> +static void imx_ccm_write(void *opaque, hwaddr offset,
>                            uint64_t value, unsigned size)
>  {
>      IMXCCMState *s = (IMXCCMState *)opaque;
> diff --git a/hw/imx_serial.c b/hw/imx_serial.c
> index d4eae43..dcd125f 100644
> --- a/hw/imx_serial.c
> +++ b/hw/imx_serial.c
> @@ -183,7 +183,7 @@ static void imx_serial_reset_at_boot(DeviceState *dev)
>  
>  }
>  
> -static uint64_t imx_serial_read(void *opaque, target_phys_addr_t offset,
> +static uint64_t imx_serial_read(void *opaque, hwaddr offset,
>                                  unsigned size)
>  {
>      IMXSerialState *s = (IMXSerialState *)opaque;
> @@ -244,7 +244,7 @@ static uint64_t imx_serial_read(void *opaque, target_phys_addr_t offset,
>      }
>  }
>  
> -static void imx_serial_write(void *opaque, target_phys_addr_t offset,
> +static void imx_serial_write(void *opaque, hwaddr offset,
>                        uint64_t value, unsigned size)
>  {
>      IMXSerialState *s = (IMXSerialState *)opaque;
> @@ -401,7 +401,7 @@ static int imx_serial_init(SysBusDevice *dev)
>      return 0;
>  }
>  
> -void imx_serial_create(int uart, const target_phys_addr_t addr, qemu_irq irq)
> +void imx_serial_create(int uart, const hwaddr addr, qemu_irq irq)
>  {
>      DeviceState *dev;
>      SysBusDevice *bus;
> @@ -427,7 +427,7 @@ void imx_serial_create(int uart, const target_phys_addr_t addr, qemu_irq irq)
>      qdev_prop_set_chr(dev, "chardev", chr);
>      bus = sysbus_from_qdev(dev);
>      qdev_init_nofail(dev);
> -    if (addr != (target_phys_addr_t)-1) {
> +    if (addr != (hwaddr)-1) {
>          sysbus_mmio_map(bus, 0, addr);
>      }
>      sysbus_connect_irq(bus, 0, irq);
> diff --git a/hw/imx_timer.c b/hw/imx_timer.c
> index c28c537..33f33fb 100644
> --- a/hw/imx_timer.c
> +++ b/hw/imx_timer.c
> @@ -194,7 +194,7 @@ static void imx_timerg_reload(IMXTimerGState *s, uint32_t timeout)
>      ptimer_set_count(s->timer, diff_cnt);
>  }
>  
> -static uint64_t imx_timerg_read(void *opaque, target_phys_addr_t offset,
> +static uint64_t imx_timerg_read(void *opaque, hwaddr offset,
>                                  unsigned size)
>  {
>      IMXTimerGState *s = (IMXTimerGState *)opaque;
> @@ -251,7 +251,7 @@ static void imx_timerg_reset(DeviceState *dev)
>      imx_timerg_set_freq(s);
>  }
>  
> -static void imx_timerg_write(void *opaque, target_phys_addr_t offset,
> +static void imx_timerg_write(void *opaque, hwaddr offset,
>                               uint64_t value, unsigned size)
>  {
>      IMXTimerGState *s = (IMXTimerGState *)opaque;
> @@ -468,7 +468,7 @@ static void imx_timerp_reset(DeviceState *dev)
>      ptimer_set_count(s->timer, TIMER_MAX);
>  }
>  
> -static uint64_t imx_timerp_read(void *opaque, target_phys_addr_t offset,
> +static uint64_t imx_timerp_read(void *opaque, hwaddr offset,
>                                  unsigned size)
>  {
>      IMXTimerPState *s = (IMXTimerPState *)opaque;
> @@ -517,7 +517,7 @@ static void set_timerp_freq(IMXTimerPState *s)
>      }
>  }
>  
> -static void imx_timerp_write(void *opaque, target_phys_addr_t offset,
> +static void imx_timerp_write(void *opaque, hwaddr offset,
>                               uint64_t value, unsigned size)
>  {
>      IMXTimerPState *s = (IMXTimerPState *)opaque;
> @@ -580,7 +580,7 @@ static void imx_timerp_tick(void *opaque)
>      imx_timerp_update(s);
>  }
>  
> -void imx_timerp_create(const target_phys_addr_t addr,
> +void imx_timerp_create(const hwaddr addr,
>                                qemu_irq irq,
>                                DeviceState *ccm)
>  {
> @@ -634,7 +634,7 @@ static int imx_timerp_init(SysBusDevice *dev)
>  }
>  
>  
> -void imx_timerg_create(const target_phys_addr_t addr,
> +void imx_timerg_create(const hwaddr addr,
>                                qemu_irq irq,
>                                DeviceState *ccm)
>  {
> diff --git a/hw/integratorcp.c b/hw/integratorcp.c
> index ac0ea83..77807c3 100644
> --- a/hw/integratorcp.c
> +++ b/hw/integratorcp.c
> @@ -38,7 +38,7 @@
>     0xe, 4, 0x1c, 1, 2, 0x20, 0xc0, 0, 0, 0, 0, 0x30, 0x28, 0x30, 0x28, 0x40
>  };
>  
> -static uint64_t integratorcm_read(void *opaque, target_phys_addr_t offset,
> +static uint64_t integratorcm_read(void *opaque, hwaddr offset,
>                                    unsigned size)
>  {
>      integratorcm_state *s = (integratorcm_state *)opaque;
> @@ -141,7 +141,7 @@ static void integratorcm_update(integratorcm_state *s)
>          hw_error("Core module interrupt\n");
>  }
>  
> -static void integratorcm_write(void *opaque, target_phys_addr_t offset,
> +static void integratorcm_write(void *opaque, hwaddr offset,
>                                 uint64_t value, unsigned size)
>  {
>      integratorcm_state *s = (integratorcm_state *)opaque;
> @@ -295,7 +295,7 @@ static void icp_pic_set_irq(void *opaque, int irq, int level)
>      icp_pic_update(s);
>  }
>  
> -static uint64_t icp_pic_read(void *opaque, target_phys_addr_t offset,
> +static uint64_t icp_pic_read(void *opaque, hwaddr offset,
>                               unsigned size)
>  {
>      icp_pic_state *s = (icp_pic_state *)opaque;
> @@ -324,7 +324,7 @@ static uint64_t icp_pic_read(void *opaque, target_phys_addr_t offset,
>      }
>  }
>  
> -static void icp_pic_write(void *opaque, target_phys_addr_t offset,
> +static void icp_pic_write(void *opaque, hwaddr offset,
>                            uint64_t value, unsigned size)
>  {
>      icp_pic_state *s = (icp_pic_state *)opaque;
> @@ -381,7 +381,7 @@ static int icp_pic_init(SysBusDevice *dev)
>  
>  /* CP control registers.  */
>  
> -static uint64_t icp_control_read(void *opaque, target_phys_addr_t offset,
> +static uint64_t icp_control_read(void *opaque, hwaddr offset,
>                                   unsigned size)
>  {
>      switch (offset >> 2) {
> @@ -399,7 +399,7 @@ static uint64_t icp_control_read(void *opaque, target_phys_addr_t offset,
>      }
>  }
>  
> -static void icp_control_write(void *opaque, target_phys_addr_t offset,
> +static void icp_control_write(void *opaque, hwaddr offset,
>                            uint64_t value, unsigned size)
>  {
>      switch (offset >> 2) {
> @@ -419,7 +419,7 @@ static void icp_control_write(void *opaque, target_phys_addr_t offset,
>      .endianness = DEVICE_NATIVE_ENDIAN,
>  };
>  
> -static void icp_control_init(target_phys_addr_t base)
> +static void icp_control_init(hwaddr base)
>  {
>      MemoryRegion *io;
>  
> diff --git a/hw/intel-hda.c b/hw/intel-hda.c
> index d8e1b23..a68c368 100644
> --- a/hw/intel-hda.c
> +++ b/hw/intel-hda.c
> @@ -206,9 +206,9 @@ struct IntelHDAReg {
>  
>  /* --------------------------------------------------------------------- */
>  
> -static target_phys_addr_t intel_hda_addr(uint32_t lbase, uint32_t ubase)
> +static hwaddr intel_hda_addr(uint32_t lbase, uint32_t ubase)
>  {
> -    target_phys_addr_t addr;
> +    hwaddr addr;
>  
>      addr = ((uint64_t)ubase << 32) | lbase;
>      return addr;
> @@ -295,7 +295,7 @@ static int intel_hda_send_command(IntelHDAState *d, uint32_t verb)
>  
>  static void intel_hda_corb_run(IntelHDAState *d)
>  {
> -    target_phys_addr_t addr;
> +    hwaddr addr;
>      uint32_t rp, verb;
>  
>      if (d->ics & ICH6_IRS_BUSY) {
> @@ -332,7 +332,7 @@ static void intel_hda_response(HDACodecDevice *dev, bool solicited, uint32_t res
>  {
>      HDACodecBus *bus = DO_UPCAST(HDACodecBus, qbus, dev->qdev.parent_bus);
>      IntelHDAState *d = container_of(bus, IntelHDAState, codecs);
> -    target_phys_addr_t addr;
> +    hwaddr addr;
>      uint32_t wp, ex;
>  
>      if (d->ics & ICH6_IRS_BUSY) {
> @@ -381,7 +381,7 @@ static bool intel_hda_xfer(HDACodecDevice *dev, uint32_t stnr, bool output,
>  {
>      HDACodecBus *bus = DO_UPCAST(HDACodecBus, qbus, dev->qdev.parent_bus);
>      IntelHDAState *d = container_of(bus, IntelHDAState, codecs);
> -    target_phys_addr_t addr;
> +    hwaddr addr;
>      uint32_t s, copy, left;
>      IntelHDAStream *st;
>      bool irq = false;
> @@ -453,7 +453,7 @@ static bool intel_hda_xfer(HDACodecDevice *dev, uint32_t stnr, bool output,
>  
>  static void intel_hda_parse_bdl(IntelHDAState *d, IntelHDAStream *st)
>  {
> -    target_phys_addr_t addr;
> +    hwaddr addr;
>      uint8_t buf[16];
>      uint32_t i;
>  
> @@ -890,7 +890,7 @@ static void intel_hda_set_st_ctl(IntelHDAState *d, const IntelHDAReg *reg, uint3
>  
>  };
>  
> -static const IntelHDAReg *intel_hda_reg_find(IntelHDAState *d, target_phys_addr_t addr)
> +static const IntelHDAReg *intel_hda_reg_find(IntelHDAState *d, hwaddr addr)
>  {
>      const IntelHDAReg *reg;
>  
> @@ -1033,7 +1033,7 @@ static void intel_hda_regs_reset(IntelHDAState *d)
>  
>  /* --------------------------------------------------------------------- */
>  
> -static void intel_hda_mmio_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
> +static void intel_hda_mmio_writeb(void *opaque, hwaddr addr, uint32_t val)
>  {
>      IntelHDAState *d = opaque;
>      const IntelHDAReg *reg = intel_hda_reg_find(d, addr);
> @@ -1041,7 +1041,7 @@ static void intel_hda_mmio_writeb(void *opaque, target_phys_addr_t addr, uint32_
>      intel_hda_reg_write(d, reg, val, 0xff);
>  }
>  
> -static void intel_hda_mmio_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
> +static void intel_hda_mmio_writew(void *opaque, hwaddr addr, uint32_t val)
>  {
>      IntelHDAState *d = opaque;
>      const IntelHDAReg *reg = intel_hda_reg_find(d, addr);
> @@ -1049,7 +1049,7 @@ static void intel_hda_mmio_writew(void *opaque, target_phys_addr_t addr, uint32_
>      intel_hda_reg_write(d, reg, val, 0xffff);
>  }
>  
> -static void intel_hda_mmio_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
> +static void intel_hda_mmio_writel(void *opaque, hwaddr addr, uint32_t val)
>  {
>      IntelHDAState *d = opaque;
>      const IntelHDAReg *reg = intel_hda_reg_find(d, addr);
> @@ -1057,7 +1057,7 @@ static void intel_hda_mmio_writel(void *opaque, target_phys_addr_t addr, uint32_
>      intel_hda_reg_write(d, reg, val, 0xffffffff);
>  }
>  
> -static uint32_t intel_hda_mmio_readb(void *opaque, target_phys_addr_t addr)
> +static uint32_t intel_hda_mmio_readb(void *opaque, hwaddr addr)
>  {
>      IntelHDAState *d = opaque;
>      const IntelHDAReg *reg = intel_hda_reg_find(d, addr);
> @@ -1065,7 +1065,7 @@ static uint32_t intel_hda_mmio_readb(void *opaque, target_phys_addr_t addr)
>      return intel_hda_reg_read(d, reg, 0xff);
>  }
>  
> -static uint32_t intel_hda_mmio_readw(void *opaque, target_phys_addr_t addr)
> +static uint32_t intel_hda_mmio_readw(void *opaque, hwaddr addr)
>  {
>      IntelHDAState *d = opaque;
>      const IntelHDAReg *reg = intel_hda_reg_find(d, addr);
> @@ -1073,7 +1073,7 @@ static uint32_t intel_hda_mmio_readw(void *opaque, target_phys_addr_t addr)
>      return intel_hda_reg_read(d, reg, 0xffff);
>  }
>  
> -static uint32_t intel_hda_mmio_readl(void *opaque, target_phys_addr_t addr)
> +static uint32_t intel_hda_mmio_readl(void *opaque, hwaddr addr)
>  {
>      IntelHDAState *d = opaque;
>      const IntelHDAReg *reg = intel_hda_reg_find(d, addr);
> diff --git a/hw/ioapic.c b/hw/ioapic.c
> index e2e4796..7273095 100644
> --- a/hw/ioapic.c
> +++ b/hw/ioapic.c
> @@ -139,7 +139,7 @@ void ioapic_eoi_broadcast(int vector)
>  }
>  
>  static uint64_t
> -ioapic_mem_read(void *opaque, target_phys_addr_t addr, unsigned int size)
> +ioapic_mem_read(void *opaque, hwaddr addr, unsigned int size)
>  {
>      IOAPICCommonState *s = opaque;
>      int index;
> @@ -181,7 +181,7 @@ void ioapic_eoi_broadcast(int vector)
>  }
>  
>  static void
> -ioapic_mem_write(void *opaque, target_phys_addr_t addr, uint64_t val,
> +ioapic_mem_write(void *opaque, hwaddr addr, uint64_t val,
>                   unsigned int size)
>  {
>      IOAPICCommonState *s = opaque;
> diff --git a/hw/isa-bus.c b/hw/isa-bus.c
> index 214f194..685fdc0 100644
> --- a/hw/isa-bus.c
> +++ b/hw/isa-bus.c
> @@ -24,7 +24,7 @@
>  #include "exec-memory.h"
>  
>  static ISABus *isabus;
> -target_phys_addr_t isa_mem_base = 0;
> +hwaddr isa_mem_base = 0;
>  
>  static void isabus_dev_print(Monitor *mon, DeviceState *dev, int indent);
>  static char *isabus_get_fw_dev_path(DeviceState *dev);
> diff --git a/hw/isa.h b/hw/isa.h
> index 8fb498a..f9382e8 100644
> --- a/hw/isa.h
> +++ b/hw/isa.h
> @@ -84,10 +84,10 @@ static inline ISABus *isa_bus_from_device(ISADevice *d)
>      return DO_UPCAST(ISABus, qbus, d->qdev.parent_bus);
>  }
>  
> -extern target_phys_addr_t isa_mem_base;
> +extern hwaddr isa_mem_base;
>  
> -void isa_mmio_setup(MemoryRegion *mr, target_phys_addr_t size);
> -void isa_mmio_init(target_phys_addr_t base, target_phys_addr_t size);
> +void isa_mmio_setup(MemoryRegion *mr, hwaddr size);
> +void isa_mmio_init(hwaddr base, hwaddr size);
>  
>  /* dma.c */
>  int DMA_get_channel_mode (int nchan);
> diff --git a/hw/isa_mmio.c b/hw/isa_mmio.c
> index fd755ab..1405396 100644
> --- a/hw/isa_mmio.c
> +++ b/hw/isa_mmio.c
> @@ -26,35 +26,35 @@
>  #include "isa.h"
>  #include "exec-memory.h"
>  
> -static void isa_mmio_writeb (void *opaque, target_phys_addr_t addr,
> +static void isa_mmio_writeb (void *opaque, hwaddr addr,
>                                    uint32_t val)
>  {
>      cpu_outb(addr & IOPORTS_MASK, val);
>  }
>  
> -static void isa_mmio_writew(void *opaque, target_phys_addr_t addr,
> +static void isa_mmio_writew(void *opaque, hwaddr addr,
>                                 uint32_t val)
>  {
>      cpu_outw(addr & IOPORTS_MASK, val);
>  }
>  
> -static void isa_mmio_writel(void *opaque, target_phys_addr_t addr,
> +static void isa_mmio_writel(void *opaque, hwaddr addr,
>                                 uint32_t val)
>  {
>      cpu_outl(addr & IOPORTS_MASK, val);
>  }
>  
> -static uint32_t isa_mmio_readb (void *opaque, target_phys_addr_t addr)
> +static uint32_t isa_mmio_readb (void *opaque, hwaddr addr)
>  {
>      return cpu_inb(addr & IOPORTS_MASK);
>  }
>  
> -static uint32_t isa_mmio_readw(void *opaque, target_phys_addr_t addr)
> +static uint32_t isa_mmio_readw(void *opaque, hwaddr addr)
>  {
>      return cpu_inw(addr & IOPORTS_MASK);
>  }
>  
> -static uint32_t isa_mmio_readl(void *opaque, target_phys_addr_t addr)
> +static uint32_t isa_mmio_readl(void *opaque, hwaddr addr)
>  {
>      return cpu_inl(addr & IOPORTS_MASK);
>  }
> @@ -67,12 +67,12 @@ static uint32_t isa_mmio_readl(void *opaque, target_phys_addr_t addr)
>      .endianness = DEVICE_LITTLE_ENDIAN,
>  };
>  
> -void isa_mmio_setup(MemoryRegion *mr, target_phys_addr_t size)
> +void isa_mmio_setup(MemoryRegion *mr, hwaddr size)
>  {
>      memory_region_init_io(mr, &isa_mmio_ops, NULL, "isa-mmio", size);
>  }
>  
> -void isa_mmio_init(target_phys_addr_t base, target_phys_addr_t size)
> +void isa_mmio_init(hwaddr base, hwaddr size)
>  {
>      MemoryRegion *mr = g_malloc(sizeof(*mr));
>  
> diff --git a/hw/ivshmem.c b/hw/ivshmem.c
> index 5c4ccb8..f6dbb21 100644
> --- a/hw/ivshmem.c
> +++ b/hw/ivshmem.c
> @@ -163,7 +163,7 @@ static uint32_t ivshmem_IntrStatus_read(IVShmemState *s)
>      return ret;
>  }
>  
> -static void ivshmem_io_write(void *opaque, target_phys_addr_t addr,
> +static void ivshmem_io_write(void *opaque, hwaddr addr,
>                               uint64_t val, unsigned size)
>  {
>      IVShmemState *s = opaque;
> @@ -202,7 +202,7 @@ static void ivshmem_io_write(void *opaque, target_phys_addr_t addr,
>      }
>  }
>  
> -static uint64_t ivshmem_io_read(void *opaque, target_phys_addr_t addr,
> +static uint64_t ivshmem_io_read(void *opaque, hwaddr addr,
>                                  unsigned size)
>  {
>  
> diff --git a/hw/jazz_led.c b/hw/jazz_led.c
> index 6486523..a6a90ab 100644
> --- a/hw/jazz_led.c
> +++ b/hw/jazz_led.c
> @@ -39,7 +39,7 @@
>      screen_state_t state;
>  } LedState;
>  
> -static uint64_t jazz_led_read(void *opaque, target_phys_addr_t addr,
> +static uint64_t jazz_led_read(void *opaque, hwaddr addr,
>                                unsigned int size)
>  {
>      LedState *s = opaque;
> @@ -51,7 +51,7 @@ static uint64_t jazz_led_read(void *opaque, target_phys_addr_t addr,
>      return val;
>  }
>  
> -static void jazz_led_write(void *opaque, target_phys_addr_t addr,
> +static void jazz_led_write(void *opaque, hwaddr addr,
>                             uint64_t val, unsigned int size)
>  {
>      LedState *s = opaque;
> diff --git a/hw/kvm/apic.c b/hw/kvm/apic.c
> index 80e3e48..dbac7ff 100644
> --- a/hw/kvm/apic.c
> +++ b/hw/kvm/apic.c
> @@ -146,13 +146,13 @@ static void kvm_apic_external_nmi(APICCommonState *s)
>      run_on_cpu(s->cpu_env, do_inject_external_nmi, s);
>  }
>  
> -static uint64_t kvm_apic_mem_read(void *opaque, target_phys_addr_t addr,
> +static uint64_t kvm_apic_mem_read(void *opaque, hwaddr addr,
>                                    unsigned size)
>  {
>      return ~(uint64_t)0;
>  }
>  
> -static void kvm_apic_mem_write(void *opaque, target_phys_addr_t addr,
> +static void kvm_apic_mem_write(void *opaque, hwaddr addr,
>                                 uint64_t data, unsigned size)
>  {
>      MSIMessage msg = { .address = addr, .data = data };
> diff --git a/hw/kvm/pci-assign.c b/hw/kvm/pci-assign.c
> index 7a0998c..bfffbab 100644
> --- a/hw/kvm/pci-assign.c
> +++ b/hw/kvm/pci-assign.c
> @@ -133,7 +133,7 @@
>      int msi_virq_nr;
>      int *msi_virq;
>      MSIXTableEntry *msix_table;
> -    target_phys_addr_t msix_table_addr;
> +    hwaddr msix_table_addr;
>      uint16_t msix_max;
>      MemoryRegion mmio;
>      char *configfd_name;
> @@ -147,7 +147,7 @@
>  static void assigned_dev_unregister_msix_mmio(AssignedDevice *dev);
>  
>  static uint64_t assigned_dev_ioport_rw(AssignedDevRegion *dev_region,
> -                                       target_phys_addr_t addr, int size,
> +                                       hwaddr addr, int size,
>                                         uint64_t *data)
>  {
>      uint64_t val = 0;
> @@ -206,19 +206,19 @@ static uint64_t assigned_dev_ioport_rw(AssignedDevRegion *dev_region,
>      return val;
>  }
>  
> -static void assigned_dev_ioport_write(void *opaque, target_phys_addr_t addr,
> +static void assigned_dev_ioport_write(void *opaque, hwaddr addr,
>                                        uint64_t data, unsigned size)
>  {
>      assigned_dev_ioport_rw(opaque, addr, size, &data);
>  }
>  
>  static uint64_t assigned_dev_ioport_read(void *opaque,
> -                                         target_phys_addr_t addr, unsigned size)
> +                                         hwaddr addr, unsigned size)
>  {
>      return assigned_dev_ioport_rw(opaque, addr, size, NULL);
>  }
>  
> -static uint32_t slow_bar_readb(void *opaque, target_phys_addr_t addr)
> +static uint32_t slow_bar_readb(void *opaque, hwaddr addr)
>  {
>      AssignedDevRegion *d = opaque;
>      uint8_t *in = d->u.r_virtbase + addr;
> @@ -230,7 +230,7 @@ static uint32_t slow_bar_readb(void *opaque, target_phys_addr_t addr)
>      return r;
>  }
>  
> -static uint32_t slow_bar_readw(void *opaque, target_phys_addr_t addr)
> +static uint32_t slow_bar_readw(void *opaque, hwaddr addr)
>  {
>      AssignedDevRegion *d = opaque;
>      uint16_t *in = (uint16_t *)(d->u.r_virtbase + addr);
> @@ -242,7 +242,7 @@ static uint32_t slow_bar_readw(void *opaque, target_phys_addr_t addr)
>      return r;
>  }
>  
> -static uint32_t slow_bar_readl(void *opaque, target_phys_addr_t addr)
> +static uint32_t slow_bar_readl(void *opaque, hwaddr addr)
>  {
>      AssignedDevRegion *d = opaque;
>      uint32_t *in = (uint32_t *)(d->u.r_virtbase + addr);
> @@ -254,7 +254,7 @@ static uint32_t slow_bar_readl(void *opaque, target_phys_addr_t addr)
>      return r;
>  }
>  
> -static void slow_bar_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
> +static void slow_bar_writeb(void *opaque, hwaddr addr, uint32_t val)
>  {
>      AssignedDevRegion *d = opaque;
>      uint8_t *out = d->u.r_virtbase + addr;
> @@ -263,7 +263,7 @@ static void slow_bar_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
>      *out = val;
>  }
>  
> -static void slow_bar_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
> +static void slow_bar_writew(void *opaque, hwaddr addr, uint32_t val)
>  {
>      AssignedDevRegion *d = opaque;
>      uint16_t *out = (uint16_t *)(d->u.r_virtbase + addr);
> @@ -272,7 +272,7 @@ static void slow_bar_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
>      *out = val;
>  }
>  
> -static void slow_bar_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
> +static void slow_bar_writel(void *opaque, hwaddr addr, uint32_t val)
>  {
>      AssignedDevRegion *d = opaque;
>      uint32_t *out = (uint32_t *)(d->u.r_virtbase + addr);
> @@ -1499,7 +1499,7 @@ static int assigned_device_pci_cap_init(PCIDevice *pci_dev)
>  }
>  
>  static uint64_t
> -assigned_dev_msix_mmio_read(void *opaque, target_phys_addr_t addr,
> +assigned_dev_msix_mmio_read(void *opaque, hwaddr addr,
>                              unsigned size)
>  {
>      AssignedDevice *adev = opaque;
> @@ -1510,7 +1510,7 @@ static int assigned_device_pci_cap_init(PCIDevice *pci_dev)
>      return val;
>  }
>  
> -static void assigned_dev_msix_mmio_write(void *opaque, target_phys_addr_t addr,
> +static void assigned_dev_msix_mmio_write(void *opaque, hwaddr addr,
>                                           uint64_t val, unsigned size)
>  {
>      AssignedDevice *adev = opaque;
> diff --git a/hw/kvmvapic.c b/hw/kvmvapic.c
> index 5d83625..5e0a7c9 100644
> --- a/hw/kvmvapic.c
> +++ b/hw/kvmvapic.c
> @@ -144,7 +144,7 @@ static void update_guest_rom_state(VAPICROMState *s)
>  
>  static int find_real_tpr_addr(VAPICROMState *s, CPUX86State *env)
>  {
> -    target_phys_addr_t paddr;
> +    hwaddr paddr;
>      target_ulong addr;
>  
>      if (s->state == VAPIC_ACTIVE) {
> @@ -269,7 +269,7 @@ static int evaluate_tpr_instruction(VAPICROMState *s, CPUX86State *env,
>  
>  static int update_rom_mapping(VAPICROMState *s, CPUX86State *env, target_ulong ip)
>  {
> -    target_phys_addr_t paddr;
> +    hwaddr paddr;
>      uint32_t rom_state_vaddr;
>      uint32_t pos, patch, offset;
>  
> @@ -350,14 +350,14 @@ static int get_kpcr_number(CPUX86State *env)
>  static int vapic_enable(VAPICROMState *s, CPUX86State *env)
>  {
>      int cpu_number = get_kpcr_number(env);
> -    target_phys_addr_t vapic_paddr;
> +    hwaddr vapic_paddr;
>      static const uint8_t enabled = 1;
>  
>      if (cpu_number < 0) {
>          return -1;
>      }
>      vapic_paddr = s->vapic_paddr +
> -        (((target_phys_addr_t)cpu_number) << VAPIC_CPU_SHIFT);
> +        (((hwaddr)cpu_number) << VAPIC_CPU_SHIFT);
>      cpu_physical_memory_rw(vapic_paddr + offsetof(VAPICState, enabled),
>                             (void *)&enabled, sizeof(enabled), 1);
>      apic_enable_vapic(env->apic_state, vapic_paddr);
> @@ -384,7 +384,7 @@ static void patch_call(VAPICROMState *s, CPUX86State *env, target_ulong ip,
>  
>  static void patch_instruction(VAPICROMState *s, CPUX86State *env, target_ulong ip)
>  {
> -    target_phys_addr_t paddr;
> +    hwaddr paddr;
>      VAPICHandlers *handlers;
>      uint8_t opcode[2];
>      uint32_t imm32;
> @@ -500,7 +500,7 @@ static void vapic_reset(DeviceState *dev)
>   */
>  static int patch_hypercalls(VAPICROMState *s)
>  {
> -    target_phys_addr_t rom_paddr = s->rom_state_paddr & ROM_BLOCK_MASK;
> +    hwaddr rom_paddr = s->rom_state_paddr & ROM_BLOCK_MASK;
>      static const uint8_t vmcall_pattern[] = { /* vmcall */
>          0xb8, 0x1, 0, 0, 0, 0xf, 0x1, 0xc1
>      };
> @@ -557,7 +557,7 @@ static int patch_hypercalls(VAPICROMState *s)
>   */
>  static void vapic_map_rom_writable(VAPICROMState *s)
>  {
> -    target_phys_addr_t rom_paddr = s->rom_state_paddr & ROM_BLOCK_MASK;
> +    hwaddr rom_paddr = s->rom_state_paddr & ROM_BLOCK_MASK;
>      MemoryRegionSection section;
>      MemoryRegion *as;
>      size_t rom_size;
> @@ -603,11 +603,11 @@ static int vapic_prepare(VAPICROMState *s)
>      return 0;
>  }
>  
> -static void vapic_write(void *opaque, target_phys_addr_t addr, uint64_t data,
> +static void vapic_write(void *opaque, hwaddr addr, uint64_t data,
>                          unsigned int size)
>  {
>      CPUX86State *env = cpu_single_env;
> -    target_phys_addr_t rom_paddr;
> +    hwaddr rom_paddr;
>      VAPICROMState *s = opaque;
>  
>      cpu_synchronize_state(env);
> diff --git a/hw/lan9118.c b/hw/lan9118.c
> index ceaf96f..f724e1c 100644
> --- a/hw/lan9118.c
> +++ b/hw/lan9118.c
> @@ -1000,7 +1000,7 @@ static void lan9118_tick(void *opaque)
>      lan9118_update(s);
>  }
>  
> -static void lan9118_writel(void *opaque, target_phys_addr_t offset,
> +static void lan9118_writel(void *opaque, hwaddr offset,
>                             uint64_t val, unsigned size)
>  {
>      lan9118_state *s = (lan9118_state *)opaque;
> @@ -1134,7 +1134,7 @@ static void lan9118_writel(void *opaque, target_phys_addr_t offset,
>      lan9118_update(s);
>  }
>  
> -static void lan9118_writew(void *opaque, target_phys_addr_t offset,
> +static void lan9118_writew(void *opaque, hwaddr offset,
>                             uint32_t val)
>  {
>      lan9118_state *s = (lan9118_state *)opaque;
> @@ -1161,7 +1161,7 @@ static void lan9118_writew(void *opaque, target_phys_addr_t offset,
>      }
>  }
>  
> -static void lan9118_16bit_mode_write(void *opaque, target_phys_addr_t offset,
> +static void lan9118_16bit_mode_write(void *opaque, hwaddr offset,
>                                       uint64_t val, unsigned size)
>  {
>      switch (size) {
> @@ -1176,7 +1176,7 @@ static void lan9118_16bit_mode_write(void *opaque, target_phys_addr_t offset,
>      hw_error("lan9118_write: Bad size 0x%x\n", size);
>  }
>  
> -static uint64_t lan9118_readl(void *opaque, target_phys_addr_t offset,
> +static uint64_t lan9118_readl(void *opaque, hwaddr offset,
>                                unsigned size)
>  {
>      lan9118_state *s = (lan9118_state *)opaque;
> @@ -1250,7 +1250,7 @@ static uint64_t lan9118_readl(void *opaque, target_phys_addr_t offset,
>      return 0;
>  }
>  
> -static uint32_t lan9118_readw(void *opaque, target_phys_addr_t offset)
> +static uint32_t lan9118_readw(void *opaque, hwaddr offset)
>  {
>      lan9118_state *s = (lan9118_state *)opaque;
>      uint32_t val;
> @@ -1278,7 +1278,7 @@ static uint32_t lan9118_readw(void *opaque, target_phys_addr_t offset)
>      return val;
>  }
>  
> -static uint64_t lan9118_16bit_mode_read(void *opaque, target_phys_addr_t offset,
> +static uint64_t lan9118_16bit_mode_read(void *opaque, hwaddr offset,
>                                          unsigned size)
>  {
>      switch (size) {
> diff --git a/hw/lance.c b/hw/lance.c
> index 9b98bb8..a3e6dd9 100644
> --- a/hw/lance.c
> +++ b/hw/lance.c
> @@ -55,7 +55,7 @@ static void parent_lance_reset(void *opaque, int irq, int level)
>          pcnet_h_reset(&d->state);
>  }
>  
> -static void lance_mem_write(void *opaque, target_phys_addr_t addr,
> +static void lance_mem_write(void *opaque, hwaddr addr,
>                              uint64_t val, unsigned size)
>  {
>      SysBusPCNetState *d = opaque;
> @@ -64,7 +64,7 @@ static void lance_mem_write(void *opaque, target_phys_addr_t addr,
>      pcnet_ioport_writew(&d->state, addr, val & 0xffff);
>  }
>  
> -static uint64_t lance_mem_read(void *opaque, target_phys_addr_t addr,
> +static uint64_t lance_mem_read(void *opaque, hwaddr addr,
>                                 unsigned size)
>  {
>      SysBusPCNetState *d = opaque;
> diff --git a/hw/lm32_boards.c b/hw/lm32_boards.c
> index c5a62c8..772cb8b 100644
> --- a/hw/lm32_boards.c
> +++ b/hw/lm32_boards.c
> @@ -32,12 +32,12 @@
>  
>  typedef struct {
>      LM32CPU *cpu;
> -    target_phys_addr_t bootstrap_pc;
> -    target_phys_addr_t flash_base;
> -    target_phys_addr_t hwsetup_base;
> -    target_phys_addr_t initrd_base;
> +    hwaddr bootstrap_pc;
> +    hwaddr flash_base;
> +    hwaddr hwsetup_base;
> +    hwaddr initrd_base;
>      size_t initrd_size;
> -    target_phys_addr_t cmdline_base;
> +    hwaddr cmdline_base;
>  } ResetInfo;
>  
>  static void cpu_irq_handler(void *opaque, int irq, int level)
> @@ -83,14 +83,14 @@ static void lm32_evr_init(QEMUMachineInitArgs *args)
>      int i;
>  
>      /* memory map */
> -    target_phys_addr_t flash_base  = 0x04000000;
> +    hwaddr flash_base  = 0x04000000;
>      size_t flash_sector_size       = 256 * 1024;
>      size_t flash_size              = 32 * 1024 * 1024;
> -    target_phys_addr_t ram_base    = 0x08000000;
> +    hwaddr ram_base    = 0x08000000;
>      size_t ram_size                = 64 * 1024 * 1024;
> -    target_phys_addr_t timer0_base = 0x80002000;
> -    target_phys_addr_t uart0_base  = 0x80006000;
> -    target_phys_addr_t timer1_base = 0x8000a000;
> +    hwaddr timer0_base = 0x80002000;
> +    hwaddr uart0_base  = 0x80006000;
> +    hwaddr timer1_base = 0x8000a000;
>      int uart0_irq                  = 0;
>      int timer0_irq                 = 1;
>      int timer1_irq                 = 3;
> @@ -174,22 +174,22 @@ static void lm32_uclinux_init(QEMUMachineInitArgs *args)
>      int i;
>  
>      /* memory map */
> -    target_phys_addr_t flash_base   = 0x04000000;
> +    hwaddr flash_base   = 0x04000000;
>      size_t flash_sector_size        = 256 * 1024;
>      size_t flash_size               = 32 * 1024 * 1024;
> -    target_phys_addr_t ram_base     = 0x08000000;
> +    hwaddr ram_base     = 0x08000000;
>      size_t ram_size                 = 64 * 1024 * 1024;
> -    target_phys_addr_t uart0_base   = 0x80000000;
> -    target_phys_addr_t timer0_base  = 0x80002000;
> -    target_phys_addr_t timer1_base  = 0x80010000;
> -    target_phys_addr_t timer2_base  = 0x80012000;
> +    hwaddr uart0_base   = 0x80000000;
> +    hwaddr timer0_base  = 0x80002000;
> +    hwaddr timer1_base  = 0x80010000;
> +    hwaddr timer2_base  = 0x80012000;
>      int uart0_irq                   = 0;
>      int timer0_irq                  = 1;
>      int timer1_irq                  = 20;
>      int timer2_irq                  = 21;
> -    target_phys_addr_t hwsetup_base = 0x0bffe000;
> -    target_phys_addr_t cmdline_base = 0x0bfff000;
> -    target_phys_addr_t initrd_base  = 0x08400000;
> +    hwaddr hwsetup_base = 0x0bffe000;
> +    hwaddr cmdline_base = 0x0bfff000;
> +    hwaddr initrd_base  = 0x08400000;
>      size_t initrd_max               = 0x01000000;
>  
>      reset_info = g_malloc0(sizeof(ResetInfo));
> diff --git a/hw/lm32_hwsetup.h b/hw/lm32_hwsetup.h
> index 70dc61f..853e9ab 100644
> --- a/hw/lm32_hwsetup.h
> +++ b/hw/lm32_hwsetup.h
> @@ -71,7 +71,7 @@ static inline void hwsetup_free(HWSetup *hw)
>  }
>  
>  static inline void hwsetup_create_rom(HWSetup *hw,
> -        target_phys_addr_t base)
> +        hwaddr base)
>  {
>      rom_add_blob("hwsetup", hw->data, TARGET_PAGE_SIZE, base);
>  }
> diff --git a/hw/lm32_sys.c b/hw/lm32_sys.c
> index bbe03c4..a7887d1 100644
> --- a/hw/lm32_sys.c
> +++ b/hw/lm32_sys.c
> @@ -61,7 +61,7 @@ static void copy_testname(LM32SysState *s)
>      s->testname[MAX_TESTNAME_LEN - 1] = '\0';
>  }
>  
> -static void sys_write(void *opaque, target_phys_addr_t addr,
> +static void sys_write(void *opaque, hwaddr addr,
>                        uint64_t value, unsigned size)
>  {
>      LM32SysState *s = opaque;
> @@ -91,7 +91,7 @@ static void sys_write(void *opaque, target_phys_addr_t addr,
>      }
>  }
>  
> -static bool sys_ops_accepts(void *opaque, target_phys_addr_t addr,
> +static bool sys_ops_accepts(void *opaque, hwaddr addr,
>                              unsigned size, bool is_write)
>  {
>      return is_write && size == 4;
> diff --git a/hw/lm32_timer.c b/hw/lm32_timer.c
> index e9450a0..a8be9cc 100644
> --- a/hw/lm32_timer.c
> +++ b/hw/lm32_timer.c
> @@ -72,7 +72,7 @@ static void timer_update_irq(LM32TimerState *s)
>      qemu_set_irq(s->irq, state);
>  }
>  
> -static uint64_t timer_read(void *opaque, target_phys_addr_t addr, unsigned size)
> +static uint64_t timer_read(void *opaque, hwaddr addr, unsigned size)
>  {
>      LM32TimerState *s = opaque;
>      uint32_t r = 0;
> @@ -97,7 +97,7 @@ static uint64_t timer_read(void *opaque, target_phys_addr_t addr, unsigned size)
>      return r;
>  }
>  
> -static void timer_write(void *opaque, target_phys_addr_t addr,
> +static void timer_write(void *opaque, hwaddr addr,
>                          uint64_t value, unsigned size)
>  {
>      LM32TimerState *s = opaque;
> diff --git a/hw/lm32_uart.c b/hw/lm32_uart.c
> index 57066e2..adb9287 100644
> --- a/hw/lm32_uart.c
> +++ b/hw/lm32_uart.c
> @@ -125,7 +125,7 @@ static void uart_update_irq(LM32UartState *s)
>      qemu_set_irq(s->irq, irq);
>  }
>  
> -static uint64_t uart_read(void *opaque, target_phys_addr_t addr,
> +static uint64_t uart_read(void *opaque, hwaddr addr,
>                            unsigned size)
>  {
>      LM32UartState *s = opaque;
> @@ -160,7 +160,7 @@ static uint64_t uart_read(void *opaque, target_phys_addr_t addr,
>      return r;
>  }
>  
> -static void uart_write(void *opaque, target_phys_addr_t addr,
> +static void uart_write(void *opaque, hwaddr addr,
>                         uint64_t value, unsigned size)
>  {
>      LM32UartState *s = opaque;
> diff --git a/hw/lm4549.c b/hw/lm4549.c
> index e0137d5..b3c2d5f 100644
> --- a/hw/lm4549.c
> +++ b/hw/lm4549.c
> @@ -150,7 +150,7 @@ static void lm4549_audio_out_callback(void *opaque, int free)
>      }
>  }
>  
> -uint32_t lm4549_read(lm4549_state *s, target_phys_addr_t offset)
> +uint32_t lm4549_read(lm4549_state *s, hwaddr offset)
>  {
>      uint16_t *regfile = s->regfile;
>      uint32_t value = 0;
> @@ -165,7 +165,7 @@ uint32_t lm4549_read(lm4549_state *s, target_phys_addr_t offset)
>  }
>  
>  void lm4549_write(lm4549_state *s,
> -                  target_phys_addr_t offset, uint32_t value)
> +                  hwaddr offset, uint32_t value)
>  {
>      uint16_t *regfile = s->regfile;
>  
> diff --git a/hw/lm4549.h b/hw/lm4549.h
> index 5948780..812a7a4 100644
> --- a/hw/lm4549.h
> +++ b/hw/lm4549.h
> @@ -36,8 +36,8 @@ extern const VMStateDescription vmstate_lm4549_state;
>  
>  
>  void lm4549_init(lm4549_state *s, lm4549_callback data_req, void *opaque);
> -uint32_t lm4549_read(lm4549_state *s, target_phys_addr_t offset);
> -void lm4549_write(lm4549_state *s, target_phys_addr_t offset, uint32_t value);
> +uint32_t lm4549_read(lm4549_state *s, hwaddr offset);
> +void lm4549_write(lm4549_state *s, hwaddr offset, uint32_t value);
>  uint32_t lm4549_write_samples(lm4549_state *s, uint32_t left, uint32_t right);
>  
>  #endif /* #ifndef HW_LM4549_H */
> diff --git a/hw/loader.c b/hw/loader.c
> index 33acc2f..ba01ca6 100644
> --- a/hw/loader.c
> +++ b/hw/loader.c
> @@ -88,7 +88,7 @@ int load_image(const char *filename, uint8_t *addr)
>  
>  /* read()-like version */
>  ssize_t read_targphys(const char *name,
> -                      int fd, target_phys_addr_t dst_addr, size_t nbytes)
> +                      int fd, hwaddr dst_addr, size_t nbytes)
>  {
>      uint8_t *buf;
>      ssize_t did;
> @@ -103,7 +103,7 @@ ssize_t read_targphys(const char *name,
>  
>  /* return the size or -1 if error */
>  int load_image_targphys(const char *filename,
> -                        target_phys_addr_t addr, uint64_t max_sz)
> +                        hwaddr addr, uint64_t max_sz)
>  {
>      int size;
>  
> @@ -117,7 +117,7 @@ int load_image_targphys(const char *filename,
>      return size;
>  }
>  
> -void pstrcpy_targphys(const char *name, target_phys_addr_t dest, int buf_size,
> +void pstrcpy_targphys(const char *name, hwaddr dest, int buf_size,
>                        const char *source)
>  {
>      const char *nulp;
> @@ -179,8 +179,8 @@ static void bswap_ahdr(struct exec *e)
>       : (_N_SEGMENT_ROUND (_N_TXTENDADDR(x, target_page_size), target_page_size)))
>  
>  
> -int load_aout(const char *filename, target_phys_addr_t addr, int max_sz,
> -              int bswap_needed, target_phys_addr_t target_page_size)
> +int load_aout(const char *filename, hwaddr addr, int max_sz,
> +              int bswap_needed, hwaddr target_page_size)
>  {
>      int fd;
>      ssize_t size, ret;
> @@ -434,8 +434,8 @@ static ssize_t gunzip(void *dst, size_t dstlen, uint8_t *src,
>  }
>  
>  /* Load a U-Boot image.  */
> -int load_uimage(const char *filename, target_phys_addr_t *ep,
> -                target_phys_addr_t *loadaddr, int *is_linux)
> +int load_uimage(const char *filename, hwaddr *ep,
> +                hwaddr *loadaddr, int *is_linux)
>  {
>      int fd;
>      int size;
> @@ -539,7 +539,7 @@ struct Rom {
>      char *fw_dir;
>      char *fw_file;
>  
> -    target_phys_addr_t addr;
> +    hwaddr addr;
>      QTAILQ_ENTRY(Rom) next;
>  };
>  
> @@ -565,7 +565,7 @@ static void rom_insert(Rom *rom)
>  }
>  
>  int rom_add_file(const char *file, const char *fw_dir,
> -                 target_phys_addr_t addr, int32_t bootindex)
> +                 hwaddr addr, int32_t bootindex)
>  {
>      Rom *rom;
>      int rc, fd = -1;
> @@ -633,7 +633,7 @@ int rom_add_file(const char *file, const char *fw_dir,
>  }
>  
>  int rom_add_blob(const char *name, const void *blob, size_t len,
> -                 target_phys_addr_t addr)
> +                 hwaddr addr)
>  {
>      Rom *rom;
>  
> @@ -679,7 +679,7 @@ static void rom_reset(void *unused)
>  
>  int rom_load_all(void)
>  {
> -    target_phys_addr_t addr = 0;
> +    hwaddr addr = 0;
>      MemoryRegionSection section;
>      Rom *rom;
>  
> @@ -709,7 +709,7 @@ void rom_set_fw(void *f)
>      fw_cfg = f;
>  }
>  
> -static Rom *find_rom(target_phys_addr_t addr)
> +static Rom *find_rom(hwaddr addr)
>  {
>      Rom *rom;
>  
> @@ -733,9 +733,9 @@ static Rom *find_rom(target_phys_addr_t addr)
>   * a ROM between addr and addr + size is copied. Note that this can involve
>   * multiple ROMs, which need not start at addr and need not end at addr + size.
>   */
> -int rom_copy(uint8_t *dest, target_phys_addr_t addr, size_t size)
> +int rom_copy(uint8_t *dest, hwaddr addr, size_t size)
>  {
> -    target_phys_addr_t end = addr + size;
> +    hwaddr end = addr + size;
>      uint8_t *s, *d = dest;
>      size_t l = 0;
>      Rom *rom;
> @@ -768,7 +768,7 @@ int rom_copy(uint8_t *dest, target_phys_addr_t addr, size_t size)
>      return (d + l) - dest;
>  }
>  
> -void *rom_ptr(target_phys_addr_t addr)
> +void *rom_ptr(hwaddr addr)
>  {
>      Rom *rom;
>  
> diff --git a/hw/loader.h b/hw/loader.h
> index 6da291e..26480ad 100644
> --- a/hw/loader.h
> +++ b/hw/loader.h
> @@ -4,32 +4,32 @@
>  /* loader.c */
>  int get_image_size(const char *filename);
>  int load_image(const char *filename, uint8_t *addr); /* deprecated */
> -int load_image_targphys(const char *filename, target_phys_addr_t,
> +int load_image_targphys(const char *filename, hwaddr,
>                          uint64_t max_sz);
>  int load_elf(const char *filename, uint64_t (*translate_fn)(void *, uint64_t),
>               void *translate_opaque, uint64_t *pentry, uint64_t *lowaddr,
>               uint64_t *highaddr, int big_endian, int elf_machine,
>               int clear_lsb);
> -int load_aout(const char *filename, target_phys_addr_t addr, int max_sz,
> -              int bswap_needed, target_phys_addr_t target_page_size);
> -int load_uimage(const char *filename, target_phys_addr_t *ep,
> -                target_phys_addr_t *loadaddr, int *is_linux);
> +int load_aout(const char *filename, hwaddr addr, int max_sz,
> +              int bswap_needed, hwaddr target_page_size);
> +int load_uimage(const char *filename, hwaddr *ep,
> +                hwaddr *loadaddr, int *is_linux);
>  
>  ssize_t read_targphys(const char *name,
> -                      int fd, target_phys_addr_t dst_addr, size_t nbytes);
> +                      int fd, hwaddr dst_addr, size_t nbytes);
>  void pstrcpy_targphys(const char *name,
> -                      target_phys_addr_t dest, int buf_size,
> +                      hwaddr dest, int buf_size,
>                        const char *source);
>  
>  
>  int rom_add_file(const char *file, const char *fw_dir,
> -                 target_phys_addr_t addr, int32_t bootindex);
> +                 hwaddr addr, int32_t bootindex);
>  int rom_add_blob(const char *name, const void *blob, size_t len,
> -                 target_phys_addr_t addr);
> +                 hwaddr addr);
>  int rom_load_all(void);
>  void rom_set_fw(void *f);
> -int rom_copy(uint8_t *dest, target_phys_addr_t addr, size_t size);
> -void *rom_ptr(target_phys_addr_t addr);
> +int rom_copy(uint8_t *dest, hwaddr addr, size_t size);
> +void *rom_ptr(hwaddr addr);
>  void do_info_roms(Monitor *mon);
>  
>  #define rom_add_file_fixed(_f, _a, _i)          \
> diff --git a/hw/lsi53c895a.c b/hw/lsi53c895a.c
> index 34afe96..04f2fae 100644
> --- a/hw/lsi53c895a.c
> +++ b/hw/lsi53c895a.c
> @@ -1878,7 +1878,7 @@ static void lsi_reg_writeb(LSIState *s, int offset, uint8_t val)
>  #undef CASE_SET_REG32
>  }
>  
> -static void lsi_mmio_write(void *opaque, target_phys_addr_t addr,
> +static void lsi_mmio_write(void *opaque, hwaddr addr,
>                             uint64_t val, unsigned size)
>  {
>      LSIState *s = opaque;
> @@ -1886,7 +1886,7 @@ static void lsi_mmio_write(void *opaque, target_phys_addr_t addr,
>      lsi_reg_writeb(s, addr & 0xff, val);
>  }
>  
> -static uint64_t lsi_mmio_read(void *opaque, target_phys_addr_t addr,
> +static uint64_t lsi_mmio_read(void *opaque, hwaddr addr,
>                                unsigned size)
>  {
>      LSIState *s = opaque;
> @@ -1904,7 +1904,7 @@ static uint64_t lsi_mmio_read(void *opaque, target_phys_addr_t addr,
>      },
>  };
>  
> -static void lsi_ram_write(void *opaque, target_phys_addr_t addr,
> +static void lsi_ram_write(void *opaque, hwaddr addr,
>                            uint64_t val, unsigned size)
>  {
>      LSIState *s = opaque;
> @@ -1920,7 +1920,7 @@ static void lsi_ram_write(void *opaque, target_phys_addr_t addr,
>      s->script_ram[addr >> 2] = newval;
>  }
>  
> -static uint64_t lsi_ram_read(void *opaque, target_phys_addr_t addr,
> +static uint64_t lsi_ram_read(void *opaque, hwaddr addr,
>                               unsigned size)
>  {
>      LSIState *s = opaque;
> @@ -1939,14 +1939,14 @@ static uint64_t lsi_ram_read(void *opaque, target_phys_addr_t addr,
>      .endianness = DEVICE_NATIVE_ENDIAN,
>  };
>  
> -static uint64_t lsi_io_read(void *opaque, target_phys_addr_t addr,
> +static uint64_t lsi_io_read(void *opaque, hwaddr addr,
>                              unsigned size)
>  {
>      LSIState *s = opaque;
>      return lsi_reg_readb(s, addr & 0xff);
>  }
>  
> -static void lsi_io_write(void *opaque, target_phys_addr_t addr,
> +static void lsi_io_write(void *opaque, hwaddr addr,
>                           uint64_t val, unsigned size)
>  {
>      LSIState *s = opaque;
> diff --git a/hw/m48t59.c b/hw/m48t59.c
> index dd6cb37..9eb1a09 100644
> --- a/hw/m48t59.c
> +++ b/hw/m48t59.c
> @@ -522,14 +522,14 @@ static uint32_t NVRAM_readb (void *opaque, uint32_t addr)
>      return retval;
>  }
>  
> -static void nvram_writeb (void *opaque, target_phys_addr_t addr, uint32_t value)
> +static void nvram_writeb (void *opaque, hwaddr addr, uint32_t value)
>  {
>      M48t59State *NVRAM = opaque;
>  
>      m48t59_write(NVRAM, addr, value & 0xff);
>  }
>  
> -static void nvram_writew (void *opaque, target_phys_addr_t addr, uint32_t value)
> +static void nvram_writew (void *opaque, hwaddr addr, uint32_t value)
>  {
>      M48t59State *NVRAM = opaque;
>  
> @@ -537,7 +537,7 @@ static void nvram_writew (void *opaque, target_phys_addr_t addr, uint32_t value)
>      m48t59_write(NVRAM, addr + 1, value & 0xff);
>  }
>  
> -static void nvram_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
> +static void nvram_writel (void *opaque, hwaddr addr, uint32_t value)
>  {
>      M48t59State *NVRAM = opaque;
>  
> @@ -547,7 +547,7 @@ static void nvram_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
>      m48t59_write(NVRAM, addr + 3, value & 0xff);
>  }
>  
> -static uint32_t nvram_readb (void *opaque, target_phys_addr_t addr)
> +static uint32_t nvram_readb (void *opaque, hwaddr addr)
>  {
>      M48t59State *NVRAM = opaque;
>      uint32_t retval;
> @@ -556,7 +556,7 @@ static uint32_t nvram_readb (void *opaque, target_phys_addr_t addr)
>      return retval;
>  }
>  
> -static uint32_t nvram_readw (void *opaque, target_phys_addr_t addr)
> +static uint32_t nvram_readw (void *opaque, hwaddr addr)
>  {
>      M48t59State *NVRAM = opaque;
>      uint32_t retval;
> @@ -566,7 +566,7 @@ static uint32_t nvram_readw (void *opaque, target_phys_addr_t addr)
>      return retval;
>  }
>  
> -static uint32_t nvram_readl (void *opaque, target_phys_addr_t addr)
> +static uint32_t nvram_readl (void *opaque, hwaddr addr)
>  {
>      M48t59State *NVRAM = opaque;
>      uint32_t retval;
> @@ -636,7 +636,7 @@ static void m48t59_reset_sysbus(DeviceState *d)
>  };
>  
>  /* Initialisation routine */
> -M48t59State *m48t59_init(qemu_irq IRQ, target_phys_addr_t mem_base,
> +M48t59State *m48t59_init(qemu_irq IRQ, hwaddr mem_base,
>                           uint32_t io_base, uint16_t size, int model)
>  {
>      DeviceState *dev;
> diff --git a/hw/mac_dbdma.c b/hw/mac_dbdma.c
> index 1791ec1..e551156 100644
> --- a/hw/mac_dbdma.c
> +++ b/hw/mac_dbdma.c
> @@ -699,7 +699,7 @@ void DBDMA_register_channel(void *dbdma, int nchan, qemu_irq irq,
>          ch->flush(&ch->io);
>  }
>  
> -static void dbdma_write(void *opaque, target_phys_addr_t addr,
> +static void dbdma_write(void *opaque, hwaddr addr,
>                          uint64_t value, unsigned size)
>  {
>      int channel = addr >> DBDMA_CHANNEL_SHIFT;
> @@ -749,7 +749,7 @@ static void dbdma_write(void *opaque, target_phys_addr_t addr,
>      }
>  }
>  
> -static uint64_t dbdma_read(void *opaque, target_phys_addr_t addr,
> +static uint64_t dbdma_read(void *opaque, hwaddr addr,
>                             unsigned size)
>  {
>      uint32_t value;
> diff --git a/hw/mac_dbdma.h b/hw/mac_dbdma.h
> index 6d1abe6..bfdb0dd 100644
> --- a/hw/mac_dbdma.h
> +++ b/hw/mac_dbdma.h
> @@ -30,7 +30,7 @@ typedef void (*DBDMA_end)(DBDMA_io *io);
>  struct DBDMA_io {
>      void *opaque;
>      void *channel;
> -    target_phys_addr_t addr;
> +    hwaddr addr;
>      int len;
>      int is_last;
>      int is_dma_out;
> diff --git a/hw/mac_nvram.c b/hw/mac_nvram.c
> index ed0a2b7..a0d14dd 100644
> --- a/hw/mac_nvram.c
> +++ b/hw/mac_nvram.c
> @@ -71,7 +71,7 @@ void macio_nvram_write (void *opaque, uint32_t addr, uint32_t val)
>  }
>  
>  /* macio style NVRAM device */
> -static void macio_nvram_writeb(void *opaque, target_phys_addr_t addr,
> +static void macio_nvram_writeb(void *opaque, hwaddr addr,
>                                 uint64_t value, unsigned size)
>  {
>      MacIONVRAMState *s = opaque;
> @@ -81,7 +81,7 @@ static void macio_nvram_writeb(void *opaque, target_phys_addr_t addr,
>      NVR_DPRINTF("writeb addr %04x val %x\n", (int)addr, value);
>  }
>  
> -static uint64_t macio_nvram_readb(void *opaque, target_phys_addr_t addr,
> +static uint64_t macio_nvram_readb(void *opaque, hwaddr addr,
>                                    unsigned size)
>  {
>      MacIONVRAMState *s = opaque;
> @@ -116,7 +116,7 @@ static void macio_nvram_reset(void *opaque)
>  {
>  }
>  
> -MacIONVRAMState *macio_nvram_init (target_phys_addr_t size,
> +MacIONVRAMState *macio_nvram_init (hwaddr size,
>                                     unsigned int it_shift)
>  {
>      MacIONVRAMState *s;
> @@ -135,7 +135,7 @@ MacIONVRAMState *macio_nvram_init (target_phys_addr_t size,
>  }
>  
>  void macio_nvram_setup_bar(MacIONVRAMState *s, MemoryRegion *bar,
> -                           target_phys_addr_t mem_base)
> +                           hwaddr mem_base)
>  {
>      memory_region_add_subregion(bar, mem_base, &s->mem);
>  }
> diff --git a/hw/mainstone.c b/hw/mainstone.c
> index c0d6034..3266946 100644
> --- a/hw/mainstone.c
> +++ b/hw/mainstone.c
> @@ -101,7 +101,7 @@ static void mainstone_common_init(MemoryRegion *address_space_mem,
>                  const char *cpu_model, enum mainstone_model_e model, int arm_id)
>  {
>      uint32_t sector_len = 256 * 1024;
> -    target_phys_addr_t mainstone_flash_base[] = { MST_FLASH_0, MST_FLASH_1 };
> +    hwaddr mainstone_flash_base[] = { MST_FLASH_0, MST_FLASH_1 };
>      PXA2xxState *mpu;
>      DeviceState *mst_irq;
>      DriveInfo *dinfo;
> diff --git a/hw/marvell_88w8618_audio.c b/hw/marvell_88w8618_audio.c
> index f6f1937..de16cfa 100644
> --- a/hw/marvell_88w8618_audio.c
> +++ b/hw/marvell_88w8618_audio.c
> @@ -138,7 +138,7 @@ static void mv88w8618_audio_clock_update(mv88w8618_audio_state *s)
>      wm8750_set_bclk_in(s->wm, rate);
>  }
>  
> -static uint64_t mv88w8618_audio_read(void *opaque, target_phys_addr_t offset,
> +static uint64_t mv88w8618_audio_read(void *opaque, hwaddr offset,
>                                      unsigned size)
>  {
>      mv88w8618_audio_state *s = opaque;
> @@ -164,7 +164,7 @@ static uint64_t mv88w8618_audio_read(void *opaque, target_phys_addr_t offset,
>      }
>  }
>  
> -static void mv88w8618_audio_write(void *opaque, target_phys_addr_t offset,
> +static void mv88w8618_audio_write(void *opaque, hwaddr offset,
>                                    uint64_t value, unsigned size)
>  {
>      mv88w8618_audio_state *s = opaque;
> diff --git a/hw/mcf.h b/hw/mcf.h
> index 19a8b54..f929910 100644
> --- a/hw/mcf.h
> +++ b/hw/mcf.h
> @@ -5,23 +5,23 @@
>  struct MemoryRegion;
>  
>  /* mcf_uart.c */
> -uint64_t mcf_uart_read(void *opaque, target_phys_addr_t addr,
> +uint64_t mcf_uart_read(void *opaque, hwaddr addr,
>                         unsigned size);
> -void mcf_uart_write(void *opaque, target_phys_addr_t addr,
> +void mcf_uart_write(void *opaque, hwaddr addr,
>                      uint64_t val, unsigned size);
>  void *mcf_uart_init(qemu_irq irq, CharDriverState *chr);
>  void mcf_uart_mm_init(struct MemoryRegion *sysmem,
> -                      target_phys_addr_t base,
> +                      hwaddr base,
>                        qemu_irq irq, CharDriverState *chr);
>  
>  /* mcf_intc.c */
>  qemu_irq *mcf_intc_init(struct MemoryRegion *sysmem,
> -                        target_phys_addr_t base,
> +                        hwaddr base,
>                          CPUM68KState *env);
>  
>  /* mcf_fec.c */
>  void mcf_fec_init(struct MemoryRegion *sysmem, NICInfo *nd,
> -                  target_phys_addr_t base, qemu_irq *irq);
> +                  hwaddr base, qemu_irq *irq);
>  
>  /* mcf5206.c */
>  qemu_irq *mcf5206_init(struct MemoryRegion *sysmem,
> diff --git a/hw/mcf5206.c b/hw/mcf5206.c
> index 27753e2..510d770 100644
> --- a/hw/mcf5206.c
> +++ b/hw/mcf5206.c
> @@ -371,10 +371,10 @@ static void m5206_mbar_write(m5206_mbar_state *s, uint32_t offset,
>    /* 1c0-200 */ 1, 1, 1, 1,  1, 1, 1, 1,  1, 1, 1, 1,  1, 1, 1, 1,
>  };
>  
> -static uint32_t m5206_mbar_readw(void *opaque, target_phys_addr_t offset);
> -static uint32_t m5206_mbar_readl(void *opaque, target_phys_addr_t offset);
> +static uint32_t m5206_mbar_readw(void *opaque, hwaddr offset);
> +static uint32_t m5206_mbar_readl(void *opaque, hwaddr offset);
>  
> -static uint32_t m5206_mbar_readb(void *opaque, target_phys_addr_t offset)
> +static uint32_t m5206_mbar_readb(void *opaque, hwaddr offset)
>  {
>      m5206_mbar_state *s = (m5206_mbar_state *)opaque;
>      offset &= 0x3ff;
> @@ -392,7 +392,7 @@ static uint32_t m5206_mbar_readb(void *opaque, target_phys_addr_t offset)
>      return m5206_mbar_read(s, offset, 1);
>  }
>  
> -static uint32_t m5206_mbar_readw(void *opaque, target_phys_addr_t offset)
> +static uint32_t m5206_mbar_readw(void *opaque, hwaddr offset)
>  {
>      m5206_mbar_state *s = (m5206_mbar_state *)opaque;
>      int width;
> @@ -416,7 +416,7 @@ static uint32_t m5206_mbar_readw(void *opaque, target_phys_addr_t offset)
>      return m5206_mbar_read(s, offset, 2);
>  }
>  
> -static uint32_t m5206_mbar_readl(void *opaque, target_phys_addr_t offset)
> +static uint32_t m5206_mbar_readl(void *opaque, hwaddr offset)
>  {
>      m5206_mbar_state *s = (m5206_mbar_state *)opaque;
>      int width;
> @@ -434,12 +434,12 @@ static uint32_t m5206_mbar_readl(void *opaque, target_phys_addr_t offset)
>      return m5206_mbar_read(s, offset, 4);
>  }
>  
> -static void m5206_mbar_writew(void *opaque, target_phys_addr_t offset,
> +static void m5206_mbar_writew(void *opaque, hwaddr offset,
>                                uint32_t value);
> -static void m5206_mbar_writel(void *opaque, target_phys_addr_t offset,
> +static void m5206_mbar_writel(void *opaque, hwaddr offset,
>                                uint32_t value);
>  
> -static void m5206_mbar_writeb(void *opaque, target_phys_addr_t offset,
> +static void m5206_mbar_writeb(void *opaque, hwaddr offset,
>                                uint32_t value)
>  {
>      m5206_mbar_state *s = (m5206_mbar_state *)opaque;
> @@ -463,7 +463,7 @@ static void m5206_mbar_writeb(void *opaque, target_phys_addr_t offset,
>      m5206_mbar_write(s, offset, value, 1);
>  }
>  
> -static void m5206_mbar_writew(void *opaque, target_phys_addr_t offset,
> +static void m5206_mbar_writew(void *opaque, hwaddr offset,
>                                uint32_t value)
>  {
>      m5206_mbar_state *s = (m5206_mbar_state *)opaque;
> @@ -491,7 +491,7 @@ static void m5206_mbar_writew(void *opaque, target_phys_addr_t offset,
>      m5206_mbar_write(s, offset, value, 2);
>  }
>  
> -static void m5206_mbar_writel(void *opaque, target_phys_addr_t offset,
> +static void m5206_mbar_writel(void *opaque, hwaddr offset,
>                                uint32_t value)
>  {
>      m5206_mbar_state *s = (m5206_mbar_state *)opaque;
> diff --git a/hw/mcf5208.c b/hw/mcf5208.c
> index 688bc3c..b1db549 100644
> --- a/hw/mcf5208.c
> +++ b/hw/mcf5208.c
> @@ -45,7 +45,7 @@ static void m5208_timer_update(m5208_timer_state *s)
>          qemu_irq_lower(s->irq);
>  }
>  
> -static void m5208_timer_write(void *opaque, target_phys_addr_t offset,
> +static void m5208_timer_write(void *opaque, hwaddr offset,
>                                uint64_t value, unsigned size)
>  {
>      m5208_timer_state *s = (m5208_timer_state *)opaque;
> @@ -107,7 +107,7 @@ static void m5208_timer_trigger(void *opaque)
>      m5208_timer_update(s);
>  }
>  
> -static uint64_t m5208_timer_read(void *opaque, target_phys_addr_t addr,
> +static uint64_t m5208_timer_read(void *opaque, hwaddr addr,
>                                   unsigned size)
>  {
>      m5208_timer_state *s = (m5208_timer_state *)opaque;
> @@ -130,7 +130,7 @@ static uint64_t m5208_timer_read(void *opaque, target_phys_addr_t addr,
>      .endianness = DEVICE_NATIVE_ENDIAN,
>  };
>  
> -static uint64_t m5208_sys_read(void *opaque, target_phys_addr_t addr,
> +static uint64_t m5208_sys_read(void *opaque, hwaddr addr,
>                                 unsigned size)
>  {
>      switch (addr) {
> @@ -152,7 +152,7 @@ static uint64_t m5208_sys_read(void *opaque, target_phys_addr_t addr,
>      }
>  }
>  
> -static void m5208_sys_write(void *opaque, target_phys_addr_t addr,
> +static void m5208_sys_write(void *opaque, hwaddr addr,
>                              uint64_t value, unsigned size)
>  {
>      hw_error("m5208_sys_write: Bad offset 0x%x\n", (int)addr);
> @@ -195,7 +195,7 @@ static void mcf5208evb_init(QEMUMachineInitArgs *args)
>      CPUM68KState *env;
>      int kernel_size;
>      uint64_t elf_entry;
> -    target_phys_addr_t entry;
> +    hwaddr entry;
>      qemu_irq *pic;
>      MemoryRegion *address_space_mem = get_system_memory();
>      MemoryRegion *ram = g_new(MemoryRegion, 1);
> diff --git a/hw/mcf_fec.c b/hw/mcf_fec.c
> index 2fec5bc..1ed193c 100644
> --- a/hw/mcf_fec.c
> +++ b/hw/mcf_fec.c
> @@ -216,7 +216,7 @@ static void mcf_fec_reset(mcf_fec_state *s)
>      s->rfsr = 0x500;
>  }
>  
> -static uint64_t mcf_fec_read(void *opaque, target_phys_addr_t addr,
> +static uint64_t mcf_fec_read(void *opaque, hwaddr addr,
>                               unsigned size)
>  {
>      mcf_fec_state *s = (mcf_fec_state *)opaque;
> @@ -254,7 +254,7 @@ static uint64_t mcf_fec_read(void *opaque, target_phys_addr_t addr,
>      }
>  }
>  
> -static void mcf_fec_write(void *opaque, target_phys_addr_t addr,
> +static void mcf_fec_write(void *opaque, hwaddr addr,
>                            uint64_t value, unsigned size)
>  {
>      mcf_fec_state *s = (mcf_fec_state *)opaque;
> @@ -458,7 +458,7 @@ static void mcf_fec_cleanup(NetClientState *nc)
>  };
>  
>  void mcf_fec_init(MemoryRegion *sysmem, NICInfo *nd,
> -                  target_phys_addr_t base, qemu_irq *irq)
> +                  hwaddr base, qemu_irq *irq)
>  {
>      mcf_fec_state *s;
>  
> diff --git a/hw/mcf_intc.c b/hw/mcf_intc.c
> index cc1a5f3..6ef6dac 100644
> --- a/hw/mcf_intc.c
> +++ b/hw/mcf_intc.c
> @@ -43,7 +43,7 @@ static void mcf_intc_update(mcf_intc_state *s)
>      m68k_set_irq_level(s->env, best_level, s->active_vector);
>  }
>  
> -static uint64_t mcf_intc_read(void *opaque, target_phys_addr_t addr,
> +static uint64_t mcf_intc_read(void *opaque, hwaddr addr,
>                                unsigned size)
>  {
>      int offset;
> @@ -76,7 +76,7 @@ static uint64_t mcf_intc_read(void *opaque, target_phys_addr_t addr,
>      }
>  }
>  
> -static void mcf_intc_write(void *opaque, target_phys_addr_t addr,
> +static void mcf_intc_write(void *opaque, hwaddr addr,
>                             uint64_t val, unsigned size)
>  {
>      int offset;
> @@ -138,7 +138,7 @@ static void mcf_intc_reset(mcf_intc_state *s)
>  };
>  
>  qemu_irq *mcf_intc_init(MemoryRegion *sysmem,
> -                        target_phys_addr_t base,
> +                        hwaddr base,
>                          CPUM68KState *env)
>  {
>      mcf_intc_state *s;
> diff --git a/hw/mcf_uart.c b/hw/mcf_uart.c
> index ec6a87f..d1655f8 100644
> --- a/hw/mcf_uart.c
> +++ b/hw/mcf_uart.c
> @@ -66,7 +66,7 @@ static void mcf_uart_update(mcf_uart_state *s)
>      qemu_set_irq(s->irq, (s->isr & s->imr) != 0);
>  }
>  
> -uint64_t mcf_uart_read(void *opaque, target_phys_addr_t addr,
> +uint64_t mcf_uart_read(void *opaque, hwaddr addr,
>                         unsigned size)
>  {
>      mcf_uart_state *s = (mcf_uart_state *)opaque;
> @@ -185,7 +185,7 @@ static void mcf_do_command(mcf_uart_state *s, uint8_t cmd)
>      }
>  }
>  
> -void mcf_uart_write(void *opaque, target_phys_addr_t addr,
> +void mcf_uart_write(void *opaque, hwaddr addr,
>                      uint64_t val, unsigned size)
>  {
>      mcf_uart_state *s = (mcf_uart_state *)opaque;
> @@ -294,7 +294,7 @@ void *mcf_uart_init(qemu_irq irq, CharDriverState *chr)
>  };
>  
>  void mcf_uart_mm_init(MemoryRegion *sysmem,
> -                      target_phys_addr_t base,
> +                      hwaddr base,
>                        qemu_irq irq,
>                        CharDriverState *chr)
>  {
> diff --git a/hw/megasas.c b/hw/megasas.c
> index 0e57740..7a2036e 100644
> --- a/hw/megasas.c
> +++ b/hw/megasas.c
> @@ -59,8 +59,8 @@
>      uint16_t count;
>      uint64_t context;
>  
> -    target_phys_addr_t pa;
> -    target_phys_addr_t pa_size;
> +    hwaddr pa;
> +    hwaddr pa_size;
>      union mfi_frame *frame;
>      SCSIRequest *req;
>      QEMUSGList qsg;
> @@ -277,7 +277,7 @@ static int megasas_build_sense(MegasasCmd *cmd, uint8_t *sense_ptr,
>      uint8_t sense_len)
>  {
>      uint32_t pa_hi = 0, pa_lo;
> -    target_phys_addr_t pa;
> +    hwaddr pa;
>  
>      if (sense_len > cmd->frame->header.sense_len) {
>          sense_len = cmd->frame->header.sense_len;
> @@ -404,7 +404,7 @@ static int megasas_next_index(MegasasState *s, int index, int limit)
>  }
>  
>  static MegasasCmd *megasas_lookup_frame(MegasasState *s,
> -    target_phys_addr_t frame)
> +    hwaddr frame)
>  {
>      MegasasCmd *cmd = NULL;
>      int num = 0, index;
> @@ -424,7 +424,7 @@ static MegasasCmd *megasas_lookup_frame(MegasasState *s,
>  }
>  
>  static MegasasCmd *megasas_next_frame(MegasasState *s,
> -    target_phys_addr_t frame)
> +    hwaddr frame)
>  {
>      MegasasCmd *cmd = NULL;
>      int num = 0, index;
> @@ -452,11 +452,11 @@ static MegasasCmd *megasas_next_frame(MegasasState *s,
>  }
>  
>  static MegasasCmd *megasas_enqueue_frame(MegasasState *s,
> -    target_phys_addr_t frame, uint64_t context, int count)
> +    hwaddr frame, uint64_t context, int count)
>  {
>      MegasasCmd *cmd = NULL;
>      int frame_size = MFI_FRAME_SIZE * 16;
> -    target_phys_addr_t frame_size_p = frame_size;
> +    hwaddr frame_size_p = frame_size;
>  
>      cmd = megasas_next_frame(s, frame);
>      /* All frames busy */
> @@ -561,7 +561,7 @@ static void megasas_abort_command(MegasasCmd *cmd)
>  static int megasas_init_firmware(MegasasState *s, MegasasCmd *cmd)
>  {
>      uint32_t pa_hi, pa_lo;
> -    target_phys_addr_t iq_pa, initq_size;
> +    hwaddr iq_pa, initq_size;
>      struct mfi_init_qinfo *initq;
>      uint32_t flags;
>      int ret = MFI_STAT_OK;
> @@ -1771,7 +1771,7 @@ static void megasas_command_cancel(SCSIRequest *req)
>  static int megasas_handle_abort(MegasasState *s, MegasasCmd *cmd)
>  {
>      uint64_t abort_ctx = le64_to_cpu(cmd->frame->abort.abort_context);
> -    target_phys_addr_t abort_addr, addr_hi, addr_lo;
> +    hwaddr abort_addr, addr_hi, addr_lo;
>      MegasasCmd *abort_cmd;
>  
>      addr_hi = le32_to_cpu(cmd->frame->abort.abort_mfi_addr_hi);
> @@ -1861,7 +1861,7 @@ static void megasas_handle_frame(MegasasState *s, uint64_t frame_addr,
>      }
>  }
>  
> -static uint64_t megasas_mmio_read(void *opaque, target_phys_addr_t addr,
> +static uint64_t megasas_mmio_read(void *opaque, hwaddr addr,
>                                    unsigned size)
>  {
>      MegasasState *s = opaque;
> @@ -1897,7 +1897,7 @@ static uint64_t megasas_mmio_read(void *opaque, target_phys_addr_t addr,
>      return retval;
>  }
>  
> -static void megasas_mmio_write(void *opaque, target_phys_addr_t addr,
> +static void megasas_mmio_write(void *opaque, hwaddr addr,
>                                 uint64_t val, unsigned size)
>  {
>      MegasasState *s = opaque;
> @@ -1977,13 +1977,13 @@ static void megasas_mmio_write(void *opaque, target_phys_addr_t addr,
>      }
>  };
>  
> -static uint64_t megasas_port_read(void *opaque, target_phys_addr_t addr,
> +static uint64_t megasas_port_read(void *opaque, hwaddr addr,
>                                    unsigned size)
>  {
>      return megasas_mmio_read(opaque, addr & 0xff, size);
>  }
>  
> -static void megasas_port_write(void *opaque, target_phys_addr_t addr,
> +static void megasas_port_write(void *opaque, hwaddr addr,
>                                 uint64_t val, unsigned size)
>  {
>      megasas_mmio_write(opaque, addr & 0xff, val, size);
> @@ -1999,7 +1999,7 @@ static void megasas_port_write(void *opaque, target_phys_addr_t addr,
>      }
>  };
>  
> -static uint64_t megasas_queue_read(void *opaque, target_phys_addr_t addr,
> +static uint64_t megasas_queue_read(void *opaque, hwaddr addr,
>                                     unsigned size)
>  {
>      return 0;
> diff --git a/hw/microblaze_boot.c b/hw/microblaze_boot.c
> index 1030e9c..02c349c 100644
> --- a/hw/microblaze_boot.c
> +++ b/hw/microblaze_boot.c
> @@ -55,7 +55,7 @@ static void main_cpu_reset(void *opaque)
>      }
>  }
>  
> -static int microblaze_load_dtb(target_phys_addr_t addr,
> +static int microblaze_load_dtb(hwaddr addr,
>                                        uint32_t ramsize,
>                                        const char *kernel_cmdline,
>                                        const char *dtb_filename)
> @@ -100,7 +100,7 @@ static uint64_t translate_kernel_address(void *opaque, uint64_t addr)
>      return addr - 0x30000000LL;
>  }
>  
> -void microblaze_load_kernel(MicroBlazeCPU *cpu, target_phys_addr_t ddr_base,
> +void microblaze_load_kernel(MicroBlazeCPU *cpu, hwaddr ddr_base,
>                              uint32_t ramsize, const char *dtb_filename,
>                              void (*machine_cpu_reset)(MicroBlazeCPU *))
>  {
> @@ -149,7 +149,7 @@ void microblaze_load_kernel(MicroBlazeCPU *cpu, target_phys_addr_t ddr_base,
>  
>          /* If it wasn't an ELF image, try an u-boot image.  */
>          if (kernel_size < 0) {
> -            target_phys_addr_t uentry, loadaddr;
> +            hwaddr uentry, loadaddr;
>  
>              kernel_size = load_uimage(kernel_filename, &uentry, &loadaddr, 0);
>              boot_info.bootstrap_pc = uentry;
> diff --git a/hw/microblaze_boot.h b/hw/microblaze_boot.h
> index c9a3064..c1cf836 100644
> --- a/hw/microblaze_boot.h
> +++ b/hw/microblaze_boot.h
> @@ -3,7 +3,7 @@
>  
>  #include "hw.h"
>  
> -void microblaze_load_kernel(MicroBlazeCPU *cpu, target_phys_addr_t ddr_base,
> +void microblaze_load_kernel(MicroBlazeCPU *cpu, hwaddr ddr_base,
>                              uint32_t ramsize, const char *dtb_filename,
>                              void (*machine_cpu_reset)(MicroBlazeCPU *));
>  
> diff --git a/hw/milkymist-ac97.c b/hw/milkymist-ac97.c
> index 4414f39..d87656c 100644
> --- a/hw/milkymist-ac97.c
> +++ b/hw/milkymist-ac97.c
> @@ -83,7 +83,7 @@ static void update_voices(MilkymistAC97State *s)
>      }
>  }
>  
> -static uint64_t ac97_read(void *opaque, target_phys_addr_t addr,
> +static uint64_t ac97_read(void *opaque, hwaddr addr,
>                            unsigned size)
>  {
>      MilkymistAC97State *s = opaque;
> @@ -115,7 +115,7 @@ static uint64_t ac97_read(void *opaque, target_phys_addr_t addr,
>      return r;
>  }
>  
> -static void ac97_write(void *opaque, target_phys_addr_t addr, uint64_t value,
> +static void ac97_write(void *opaque, hwaddr addr, uint64_t value,
>                         unsigned size)
>  {
>      MilkymistAC97State *s = opaque;
> diff --git a/hw/milkymist-hpdmc.c b/hw/milkymist-hpdmc.c
> index 2da0293..5d120a4 100644
> --- a/hw/milkymist-hpdmc.c
> +++ b/hw/milkymist-hpdmc.c
> @@ -48,7 +48,7 @@ struct MilkymistHpdmcState {
>  };
>  typedef struct MilkymistHpdmcState MilkymistHpdmcState;
>  
> -static uint64_t hpdmc_read(void *opaque, target_phys_addr_t addr,
> +static uint64_t hpdmc_read(void *opaque, hwaddr addr,
>                             unsigned size)
>  {
>      MilkymistHpdmcState *s = opaque;
> @@ -74,7 +74,7 @@ static uint64_t hpdmc_read(void *opaque, target_phys_addr_t addr,
>      return r;
>  }
>  
> -static void hpdmc_write(void *opaque, target_phys_addr_t addr, uint64_t value,
> +static void hpdmc_write(void *opaque, hwaddr addr, uint64_t value,
>                          unsigned size)
>  {
>      MilkymistHpdmcState *s = opaque;
> diff --git a/hw/milkymist-hw.h b/hw/milkymist-hw.h
> index 9f358a7..96b2a7f 100644
> --- a/hw/milkymist-hw.h
> +++ b/hw/milkymist-hw.h
> @@ -4,7 +4,7 @@
>  #include "qdev.h"
>  #include "qdev-addr.h"
>  
> -static inline DeviceState *milkymist_uart_create(target_phys_addr_t base,
> +static inline DeviceState *milkymist_uart_create(hwaddr base,
>          qemu_irq irq)
>  {
>      DeviceState *dev;
> @@ -17,7 +17,7 @@ static inline DeviceState *milkymist_uart_create(target_phys_addr_t base,
>      return dev;
>  }
>  
> -static inline DeviceState *milkymist_hpdmc_create(target_phys_addr_t base)
> +static inline DeviceState *milkymist_hpdmc_create(hwaddr base)
>  {
>      DeviceState *dev;
>  
> @@ -28,7 +28,7 @@ static inline DeviceState *milkymist_hpdmc_create(target_phys_addr_t base)
>      return dev;
>  }
>  
> -static inline DeviceState *milkymist_memcard_create(target_phys_addr_t base)
> +static inline DeviceState *milkymist_memcard_create(hwaddr base)
>  {
>      DeviceState *dev;
>  
> @@ -39,7 +39,7 @@ static inline DeviceState *milkymist_memcard_create(target_phys_addr_t base)
>      return dev;
>  }
>  
> -static inline DeviceState *milkymist_vgafb_create(target_phys_addr_t base,
> +static inline DeviceState *milkymist_vgafb_create(hwaddr base,
>          uint32_t fb_offset, uint32_t fb_mask)
>  {
>      DeviceState *dev;
> @@ -53,7 +53,7 @@ static inline DeviceState *milkymist_vgafb_create(target_phys_addr_t base,
>      return dev;
>  }
>  
> -static inline DeviceState *milkymist_sysctl_create(target_phys_addr_t base,
> +static inline DeviceState *milkymist_sysctl_create(hwaddr base,
>          qemu_irq gpio_irq, qemu_irq timer0_irq, qemu_irq timer1_irq,
>          uint32_t freq_hz, uint32_t system_id, uint32_t capabilities,
>          uint32_t gpio_strappings)
> @@ -74,7 +74,7 @@ static inline DeviceState *milkymist_sysctl_create(target_phys_addr_t base,
>      return dev;
>  }
>  
> -static inline DeviceState *milkymist_pfpu_create(target_phys_addr_t base,
> +static inline DeviceState *milkymist_pfpu_create(hwaddr base,
>          qemu_irq irq)
>  {
>      DeviceState *dev;
> @@ -97,7 +97,7 @@ static const int glx_fbconfig_attr[] = {
>  };
>  #endif
>  
> -static inline DeviceState *milkymist_tmu2_create(target_phys_addr_t base,
> +static inline DeviceState *milkymist_tmu2_create(hwaddr base,
>          qemu_irq irq)
>  {
>  #ifdef CONFIG_OPENGL
> @@ -152,7 +152,7 @@ static inline DeviceState *milkymist_tmu2_create(target_phys_addr_t base,
>  #endif
>  }
>  
> -static inline DeviceState *milkymist_ac97_create(target_phys_addr_t base,
> +static inline DeviceState *milkymist_ac97_create(hwaddr base,
>          qemu_irq crrequest_irq, qemu_irq crreply_irq, qemu_irq dmar_irq,
>          qemu_irq dmaw_irq)
>  {
> @@ -169,7 +169,7 @@ static inline DeviceState *milkymist_ac97_create(target_phys_addr_t base,
>      return dev;
>  }
>  
> -static inline DeviceState *milkymist_minimac_create(target_phys_addr_t base,
> +static inline DeviceState *milkymist_minimac_create(hwaddr base,
>          qemu_irq rx_irq, qemu_irq tx_irq)
>  {
>      DeviceState *dev;
> @@ -185,8 +185,8 @@ static inline DeviceState *milkymist_minimac_create(target_phys_addr_t base,
>      return dev;
>  }
>  
> -static inline DeviceState *milkymist_minimac2_create(target_phys_addr_t base,
> -        target_phys_addr_t buffers_base, qemu_irq rx_irq, qemu_irq tx_irq)
> +static inline DeviceState *milkymist_minimac2_create(hwaddr base,
> +        hwaddr buffers_base, qemu_irq rx_irq, qemu_irq tx_irq)
>  {
>      DeviceState *dev;
>  
> @@ -202,7 +202,7 @@ static inline DeviceState *milkymist_minimac2_create(target_phys_addr_t base,
>      return dev;
>  }
>  
> -static inline DeviceState *milkymist_softusb_create(target_phys_addr_t base,
> +static inline DeviceState *milkymist_softusb_create(hwaddr base,
>          qemu_irq irq, uint32_t pmem_base, uint32_t pmem_size,
>          uint32_t dmem_base, uint32_t dmem_size)
>  {
> diff --git a/hw/milkymist-memcard.c b/hw/milkymist-memcard.c
> index 3515c3c..ca5df56 100644
> --- a/hw/milkymist-memcard.c
> +++ b/hw/milkymist-memcard.c
> @@ -117,7 +117,7 @@ static void memcard_sd_command(MilkymistMemcardState *s)
>      }
>  }
>  
> -static uint64_t memcard_read(void *opaque, target_phys_addr_t addr,
> +static uint64_t memcard_read(void *opaque, hwaddr addr,
>                               unsigned size)
>  {
>      MilkymistMemcardState *s = opaque;
> @@ -166,7 +166,7 @@ static uint64_t memcard_read(void *opaque, target_phys_addr_t addr,
>      return r;
>  }
>  
> -static void memcard_write(void *opaque, target_phys_addr_t addr, uint64_t value,
> +static void memcard_write(void *opaque, hwaddr addr, uint64_t value,
>                            unsigned size)
>  {
>      MilkymistMemcardState *s = opaque;
> diff --git a/hw/milkymist-minimac2.c b/hw/milkymist-minimac2.c
> index b483a02..b204e5f 100644
> --- a/hw/milkymist-minimac2.c
> +++ b/hw/milkymist-minimac2.c
> @@ -96,7 +96,7 @@ struct MilkymistMinimac2State {
>      NICState *nic;
>      NICConf conf;
>      char *phy_model;
> -    target_phys_addr_t buffers_base;
> +    hwaddr buffers_base;
>      MemoryRegion buffers;
>      MemoryRegion regs_region;
>  
> @@ -323,7 +323,7 @@ static ssize_t minimac2_rx(NetClientState *nc, const uint8_t *buf, size_t size)
>  }
>  
>  static uint64_t
> -minimac2_read(void *opaque, target_phys_addr_t addr, unsigned size)
> +minimac2_read(void *opaque, hwaddr addr, unsigned size)
>  {
>      MilkymistMinimac2State *s = opaque;
>      uint32_t r = 0;
> @@ -352,7 +352,7 @@ static ssize_t minimac2_rx(NetClientState *nc, const uint8_t *buf, size_t size)
>  }
>  
>  static void
> -minimac2_write(void *opaque, target_phys_addr_t addr, uint64_t value,
> +minimac2_write(void *opaque, hwaddr addr, uint64_t value,
>                 unsigned size)
>  {
>      MilkymistMinimac2State *s = opaque;
> diff --git a/hw/milkymist-pfpu.c b/hw/milkymist-pfpu.c
> index 0f9ff4a..450bab9 100644
> --- a/hw/milkymist-pfpu.c
> +++ b/hw/milkymist-pfpu.c
> @@ -131,7 +131,7 @@ struct MilkymistPFPUState {
>  };
>  typedef struct MilkymistPFPUState MilkymistPFPUState;
>  
> -static inline target_phys_addr_t
> +static inline hwaddr
>  get_dma_address(uint32_t base, uint32_t x, uint32_t y)
>  {
>      return base + 8 * (128 * y + x);
> @@ -225,7 +225,7 @@ static int pfpu_decode_insn(MilkymistPFPUState *s)
>      {
>          uint32_t a = cpu_to_be32(s->gp_regs[reg_a]);
>          uint32_t b = cpu_to_be32(s->gp_regs[reg_b]);
> -        target_phys_addr_t dma_ptr =
> +        hwaddr dma_ptr =
>              get_dma_address(s->regs[R_MESHBASE],
>                      s->gp_regs[GPR_X], s->gp_regs[GPR_Y]);
>          cpu_physical_memory_write(dma_ptr, (uint8_t *)&a, 4);
> @@ -380,7 +380,7 @@ static inline int get_microcode_address(MilkymistPFPUState *s, uint32_t addr)
>      return (512 * s->regs[R_CODEPAGE]) + addr - MICROCODE_BEGIN;
>  }
>  
> -static uint64_t pfpu_read(void *opaque, target_phys_addr_t addr,
> +static uint64_t pfpu_read(void *opaque, hwaddr addr,
>                            unsigned size)
>  {
>      MilkymistPFPUState *s = opaque;
> @@ -420,7 +420,7 @@ static uint64_t pfpu_read(void *opaque, target_phys_addr_t addr,
>      return r;
>  }
>  
> -static void pfpu_write(void *opaque, target_phys_addr_t addr, uint64_t value,
> +static void pfpu_write(void *opaque, hwaddr addr, uint64_t value,
>                         unsigned size)
>  {
>      MilkymistPFPUState *s = opaque;
> diff --git a/hw/milkymist-softusb.c b/hw/milkymist-softusb.c
> index ecc2be9..b162b88 100644
> --- a/hw/milkymist-softusb.c
> +++ b/hw/milkymist-softusb.c
> @@ -71,7 +71,7 @@ struct MilkymistSoftUsbState {
>  };
>  typedef struct MilkymistSoftUsbState MilkymistSoftUsbState;
>  
> -static uint64_t softusb_read(void *opaque, target_phys_addr_t addr,
> +static uint64_t softusb_read(void *opaque, hwaddr addr,
>                               unsigned size)
>  {
>      MilkymistSoftUsbState *s = opaque;
> @@ -95,7 +95,7 @@ static uint64_t softusb_read(void *opaque, target_phys_addr_t addr,
>  }
>  
>  static void
> -softusb_write(void *opaque, target_phys_addr_t addr, uint64_t value,
> +softusb_write(void *opaque, hwaddr addr, uint64_t value,
>                unsigned size)
>  {
>      MilkymistSoftUsbState *s = opaque;
> diff --git a/hw/milkymist-sysctl.c b/hw/milkymist-sysctl.c
> index 8878d2b..f951ef9 100644
> --- a/hw/milkymist-sysctl.c
> +++ b/hw/milkymist-sysctl.c
> @@ -89,7 +89,7 @@ static void sysctl_icap_write(MilkymistSysctlState *s, uint32_t value)
>      }
>  }
>  
> -static uint64_t sysctl_read(void *opaque, target_phys_addr_t addr,
> +static uint64_t sysctl_read(void *opaque, hwaddr addr,
>                              unsigned size)
>  {
>      MilkymistSysctlState *s = opaque;
> @@ -134,7 +134,7 @@ static uint64_t sysctl_read(void *opaque, target_phys_addr_t addr,
>      return r;
>  }
>  
> -static void sysctl_write(void *opaque, target_phys_addr_t addr, uint64_t value,
> +static void sysctl_write(void *opaque, hwaddr addr, uint64_t value,
>                           unsigned size)
>  {
>      MilkymistSysctlState *s = opaque;
> diff --git a/hw/milkymist-tmu2.c b/hw/milkymist-tmu2.c
> index 210ceed..3f9a684 100644
> --- a/hw/milkymist-tmu2.c
> +++ b/hw/milkymist-tmu2.c
> @@ -182,9 +182,9 @@ static void tmu2_start(MilkymistTMU2State *s)
>      GLXPbuffer pbuffer;
>      GLuint texture;
>      void *fb;
> -    target_phys_addr_t fb_len;
> +    hwaddr fb_len;
>      void *mesh;
> -    target_phys_addr_t mesh_len;
> +    hwaddr mesh_len;
>      float m;
>  
>      trace_milkymist_tmu2_start();
> @@ -310,7 +310,7 @@ static void tmu2_start(MilkymistTMU2State *s)
>      qemu_irq_pulse(s->irq);
>  }
>  
> -static uint64_t tmu2_read(void *opaque, target_phys_addr_t addr,
> +static uint64_t tmu2_read(void *opaque, hwaddr addr,
>                            unsigned size)
>  {
>      MilkymistTMU2State *s = opaque;
> @@ -372,7 +372,7 @@ static void tmu2_check_registers(MilkymistTMU2State *s)
>      }
>  }
>  
> -static void tmu2_write(void *opaque, target_phys_addr_t addr, uint64_t value,
> +static void tmu2_write(void *opaque, hwaddr addr, uint64_t value,
>                         unsigned size)
>  {
>      MilkymistTMU2State *s = opaque;
> diff --git a/hw/milkymist-uart.c b/hw/milkymist-uart.c
> index 291fe3c..aefa8c7 100644
> --- a/hw/milkymist-uart.c
> +++ b/hw/milkymist-uart.c
> @@ -78,7 +78,7 @@ static void uart_update_irq(MilkymistUartState *s)
>      }
>  }
>  
> -static uint64_t uart_read(void *opaque, target_phys_addr_t addr,
> +static uint64_t uart_read(void *opaque, hwaddr addr,
>                            unsigned size)
>  {
>      MilkymistUartState *s = opaque;
> @@ -107,7 +107,7 @@ static uint64_t uart_read(void *opaque, target_phys_addr_t addr,
>      return r;
>  }
>  
> -static void uart_write(void *opaque, target_phys_addr_t addr, uint64_t value,
> +static void uart_write(void *opaque, hwaddr addr, uint64_t value,
>                         unsigned size)
>  {
>      MilkymistUartState *s = opaque;
> diff --git a/hw/milkymist-vgafb.c b/hw/milkymist-vgafb.c
> index cd4365d..8d36bc1 100644
> --- a/hw/milkymist-vgafb.c
> +++ b/hw/milkymist-vgafb.c
> @@ -155,7 +155,7 @@ static void vgafb_resize(MilkymistVgafbState *s)
>      s->invalidate = 1;
>  }
>  
> -static uint64_t vgafb_read(void *opaque, target_phys_addr_t addr,
> +static uint64_t vgafb_read(void *opaque, hwaddr addr,
>                             unsigned size)
>  {
>      MilkymistVgafbState *s = opaque;
> @@ -193,7 +193,7 @@ static uint64_t vgafb_read(void *opaque, target_phys_addr_t addr,
>      return r;
>  }
>  
> -static void vgafb_write(void *opaque, target_phys_addr_t addr, uint64_t value,
> +static void vgafb_write(void *opaque, hwaddr addr, uint64_t value,
>                          unsigned size)
>  {
>      MilkymistVgafbState *s = opaque;
> diff --git a/hw/milkymist.c b/hw/milkymist.c
> index ca9ed43..4c8111a 100644
> --- a/hw/milkymist.c
> +++ b/hw/milkymist.c
> @@ -38,11 +38,11 @@
>  
>  typedef struct {
>      LM32CPU *cpu;
> -    target_phys_addr_t bootstrap_pc;
> -    target_phys_addr_t flash_base;
> -    target_phys_addr_t initrd_base;
> +    hwaddr bootstrap_pc;
> +    hwaddr flash_base;
> +    hwaddr initrd_base;
>      size_t initrd_size;
> -    target_phys_addr_t cmdline_base;
> +    hwaddr cmdline_base;
>  } ResetInfo;
>  
>  static void cpu_irq_handler(void *opaque, int irq, int level)
> @@ -91,14 +91,14 @@ static void main_cpu_reset(void *opaque)
>      ResetInfo *reset_info;
>  
>      /* memory map */
> -    target_phys_addr_t flash_base   = 0x00000000;
> +    hwaddr flash_base   = 0x00000000;
>      size_t flash_sector_size        = 128 * 1024;
>      size_t flash_size               = 32 * 1024 * 1024;
> -    target_phys_addr_t sdram_base   = 0x40000000;
> +    hwaddr sdram_base   = 0x40000000;
>      size_t sdram_size               = 128 * 1024 * 1024;
>  
> -    target_phys_addr_t initrd_base  = sdram_base + 0x1002000;
> -    target_phys_addr_t cmdline_base = sdram_base + 0x1000000;
> +    hwaddr initrd_base  = sdram_base + 0x1002000;
> +    hwaddr cmdline_base = sdram_base + 0x1000000;
>      size_t initrd_max = sdram_size - 0x1002000;
>  
>      reset_info = g_malloc0(sizeof(ResetInfo));
> diff --git a/hw/mips.h b/hw/mips.h
> index a7e6d4c..f7e9b7e 100644
> --- a/hw/mips.h
> +++ b/hw/mips.h
> @@ -12,7 +12,7 @@ PCIBus *bonito_init(qemu_irq *pic);
>  
>  /* rc4030.c */
>  typedef struct rc4030DMAState *rc4030_dma;
> -void rc4030_dma_memory_rw(void *opaque, target_phys_addr_t addr, uint8_t *buf, int len, int is_write);
> +void rc4030_dma_memory_rw(void *opaque, hwaddr addr, uint8_t *buf, int len, int is_write);
>  void rc4030_dma_read(void *dma, uint8_t *buf, int len);
>  void rc4030_dma_write(void *dma, uint8_t *buf, int len);
>  
> @@ -21,9 +21,9 @@ void *rc4030_init(qemu_irq timer, qemu_irq jazz_bus,
>                    MemoryRegion *sysmem);
>  
>  /* dp8393x.c */
> -void dp83932_init(NICInfo *nd, target_phys_addr_t base, int it_shift,
> +void dp83932_init(NICInfo *nd, hwaddr base, int it_shift,
>                    MemoryRegion *address_space,
>                    qemu_irq irq, void* mem_opaque,
> -                  void (*memory_rw)(void *opaque, target_phys_addr_t addr, uint8_t *buf, int len, int is_write));
> +                  void (*memory_rw)(void *opaque, hwaddr addr, uint8_t *buf, int len, int is_write));
>  
>  #endif
> diff --git a/hw/mips_jazz.c b/hw/mips_jazz.c
> index 6bd231d..0847427 100644
> --- a/hw/mips_jazz.c
> +++ b/hw/mips_jazz.c
> @@ -56,12 +56,12 @@ static void main_cpu_reset(void *opaque)
>      cpu_reset(CPU(cpu));
>  }
>  
> -static uint64_t rtc_read(void *opaque, target_phys_addr_t addr, unsigned size)
> +static uint64_t rtc_read(void *opaque, hwaddr addr, unsigned size)
>  {
>      return cpu_inw(0x71);
>  }
>  
> -static void rtc_write(void *opaque, target_phys_addr_t addr,
> +static void rtc_write(void *opaque, hwaddr addr,
>                        uint64_t val, unsigned size)
>  {
>      cpu_outw(0x71, val & 0xff);
> @@ -73,7 +73,7 @@ static void rtc_write(void *opaque, target_phys_addr_t addr,
>      .endianness = DEVICE_NATIVE_ENDIAN,
>  };
>  
> -static uint64_t dma_dummy_read(void *opaque, target_phys_addr_t addr,
> +static uint64_t dma_dummy_read(void *opaque, hwaddr addr,
>                                 unsigned size)
>  {
>      /* Nothing to do. That is only to ensure that
> @@ -81,7 +81,7 @@ static uint64_t dma_dummy_read(void *opaque, target_phys_addr_t addr,
>      return 0xff;
>  }
>  
> -static void dma_dummy_write(void *opaque, target_phys_addr_t addr,
> +static void dma_dummy_write(void *opaque, hwaddr addr,
>                              uint64_t val, unsigned size)
>  {
>      /* Nothing to do. That is only to ensure that
> diff --git a/hw/mips_malta.c b/hw/mips_malta.c
> index 22ec8b9..0571d58 100644
> --- a/hw/mips_malta.c
> +++ b/hw/mips_malta.c
> @@ -231,7 +231,7 @@ static void eeprom24c0x_write(int scl, int sda)
>      eeprom.sda = sda;
>  }
>  
> -static uint64_t malta_fpga_read(void *opaque, target_phys_addr_t addr,
> +static uint64_t malta_fpga_read(void *opaque, hwaddr addr,
>                                  unsigned size)
>  {
>      MaltaFPGAState *s = opaque;
> @@ -319,7 +319,7 @@ static uint64_t malta_fpga_read(void *opaque, target_phys_addr_t addr,
>      return val;
>  }
>  
> -static void malta_fpga_write(void *opaque, target_phys_addr_t addr,
> +static void malta_fpga_write(void *opaque, hwaddr addr,
>                               uint64_t val, unsigned size)
>  {
>      MaltaFPGAState *s = opaque;
> @@ -441,7 +441,7 @@ static void malta_fpga_led_init(CharDriverState *chr)
>  }
>  
>  static MaltaFPGAState *malta_fpga_init(MemoryRegion *address_space,
> -         target_phys_addr_t base, qemu_irq uart_irq, CharDriverState *uart_chr)
> +         hwaddr base, qemu_irq uart_irq, CharDriverState *uart_chr)
>  {
>      MaltaFPGAState *s;
>  
> diff --git a/hw/mips_r4k.c b/hw/mips_r4k.c
> index 539577b..325098a 100644
> --- a/hw/mips_r4k.c
> +++ b/hw/mips_r4k.c
> @@ -44,7 +44,7 @@
>      const char *initrd_filename;
>  } loaderparams;
>  
> -static void mips_qemu_write (void *opaque, target_phys_addr_t addr,
> +static void mips_qemu_write (void *opaque, hwaddr addr,
>                               uint64_t val, unsigned size)
>  {
>      if ((addr & 0xffff) == 0 && val == 42)
> @@ -53,7 +53,7 @@ static void mips_qemu_write (void *opaque, target_phys_addr_t addr,
>          qemu_system_shutdown_request ();
>  }
>  
> -static uint64_t mips_qemu_read (void *opaque, target_phys_addr_t addr,
> +static uint64_t mips_qemu_read (void *opaque, hwaddr addr,
>                                  unsigned size)
>  {
>      return 0;
> diff --git a/hw/mipsnet.c b/hw/mipsnet.c
> index 28063b1..bece332 100644
> --- a/hw/mipsnet.c
> +++ b/hw/mipsnet.c
> @@ -96,7 +96,7 @@ static ssize_t mipsnet_receive(NetClientState *nc, const uint8_t *buf, size_t si
>      return size;
>  }
>  
> -static uint64_t mipsnet_ioport_read(void *opaque, target_phys_addr_t addr,
> +static uint64_t mipsnet_ioport_read(void *opaque, hwaddr addr,
>                                      unsigned int size)
>  {
>      MIPSnetState *s = opaque;
> @@ -142,7 +142,7 @@ static uint64_t mipsnet_ioport_read(void *opaque, target_phys_addr_t addr,
>      return ret;
>  }
>  
> -static void mipsnet_ioport_write(void *opaque, target_phys_addr_t addr,
> +static void mipsnet_ioport_write(void *opaque, hwaddr addr,
>                                   uint64_t val, unsigned int size)
>  {
>      MIPSnetState *s = opaque;
> diff --git a/hw/mpc8544_guts.c b/hw/mpc8544_guts.c
> index 13b0ddd..873cb8c 100644
> --- a/hw/mpc8544_guts.c
> +++ b/hw/mpc8544_guts.c
> @@ -58,7 +58,7 @@ struct GutsState {
>  
>  typedef struct GutsState GutsState;
>  
> -static uint64_t mpc8544_guts_read(void *opaque, target_phys_addr_t addr,
> +static uint64_t mpc8544_guts_read(void *opaque, hwaddr addr,
>                                    unsigned size)
>  {
>      uint32_t value = 0;
> @@ -80,7 +80,7 @@ static uint64_t mpc8544_guts_read(void *opaque, target_phys_addr_t addr,
>      return value;
>  }
>  
> -static void mpc8544_guts_write(void *opaque, target_phys_addr_t addr,
> +static void mpc8544_guts_write(void *opaque, hwaddr addr,
>                                 uint64_t value, unsigned size)
>  {
>      addr &= MPC8544_GUTS_MMIO_SIZE - 1;
> diff --git a/hw/msix.c b/hw/msix.c
> index b623cb5..136ef09 100644
> --- a/hw/msix.c
> +++ b/hw/msix.c
> @@ -157,7 +157,7 @@ void msix_write_config(PCIDevice *dev, uint32_t addr,
>      }
>  }
>  
> -static uint64_t msix_table_mmio_read(void *opaque, target_phys_addr_t addr,
> +static uint64_t msix_table_mmio_read(void *opaque, hwaddr addr,
>                                       unsigned size)
>  {
>      PCIDevice *dev = opaque;
> @@ -165,7 +165,7 @@ static uint64_t msix_table_mmio_read(void *opaque, target_phys_addr_t addr,
>      return pci_get_long(dev->msix_table + addr);
>  }
>  
> -static void msix_table_mmio_write(void *opaque, target_phys_addr_t addr,
> +static void msix_table_mmio_write(void *opaque, hwaddr addr,
>                                    uint64_t val, unsigned size)
>  {
>      PCIDevice *dev = opaque;
> @@ -188,7 +188,7 @@ static void msix_table_mmio_write(void *opaque, target_phys_addr_t addr,
>      },
>  };
>  
> -static uint64_t msix_pba_mmio_read(void *opaque, target_phys_addr_t addr,
> +static uint64_t msix_pba_mmio_read(void *opaque, hwaddr addr,
>                                     unsigned size)
>  {
>      PCIDevice *dev = opaque;
> diff --git a/hw/mst_fpga.c b/hw/mst_fpga.c
> index 024192d..fb4b739 100644
> --- a/hw/mst_fpga.c
> +++ b/hw/mst_fpga.c
> @@ -91,7 +91,7 @@
>  
>  
>  static uint64_t
> -mst_fpga_readb(void *opaque, target_phys_addr_t addr, unsigned size)
> +mst_fpga_readb(void *opaque, hwaddr addr, unsigned size)
>  {
>  	mst_irq_state *s = (mst_irq_state *) opaque;
>  
> @@ -128,7 +128,7 @@
>  }
>  
>  static void
> -mst_fpga_writeb(void *opaque, target_phys_addr_t addr, uint64_t value,
> +mst_fpga_writeb(void *opaque, hwaddr addr, uint64_t value,
>  		unsigned size)
>  {
>  	mst_irq_state *s = (mst_irq_state *) opaque;
> diff --git a/hw/multiboot.c b/hw/multiboot.c
> index b1e04c5..09ec5b2 100644
> --- a/hw/multiboot.c
> +++ b/hw/multiboot.c
> @@ -80,15 +80,15 @@ enum {
>      /* buffer holding kernel, cmdlines and mb_infos */
>      void *mb_buf;
>      /* address in target */
> -    target_phys_addr_t mb_buf_phys;
> +    hwaddr mb_buf_phys;
>      /* size of mb_buf in bytes */
>      unsigned mb_buf_size;
>      /* offset of mb-info's in bytes */
> -    target_phys_addr_t offset_mbinfo;
> +    hwaddr offset_mbinfo;
>      /* offset in buffer for cmdlines in bytes */
> -    target_phys_addr_t offset_cmdlines;
> +    hwaddr offset_cmdlines;
>      /* offset of modules in bytes */
> -    target_phys_addr_t offset_mods;
> +    hwaddr offset_mods;
>      /* available slots for mb modules infos */
>      int mb_mods_avail;
>      /* currently used slots of mb modules */
> @@ -97,7 +97,7 @@ enum {
>  
>  static uint32_t mb_add_cmdline(MultibootState *s, const char *cmdline)
>  {
> -    target_phys_addr_t p = s->offset_cmdlines;
> +    hwaddr p = s->offset_cmdlines;
>      char *b = (char *)s->mb_buf + p;
>  
>      get_opt_value(b, strlen(cmdline) + 1, cmdline);
> @@ -106,8 +106,8 @@ static uint32_t mb_add_cmdline(MultibootState *s, const char *cmdline)
>  }
>  
>  static void mb_add_mod(MultibootState *s,
> -                       target_phys_addr_t start, target_phys_addr_t end,
> -                       target_phys_addr_t cmdline_phys)
> +                       hwaddr start, hwaddr end,
> +                       hwaddr cmdline_phys)
>  {
>      char *p;
>      assert(s->mb_mods_count < s->mb_mods_avail);
> @@ -276,7 +276,7 @@ int load_multiboot(void *fw_cfg,
>              *next_initrd = '\0';
>              /* if a space comes after the module filename, treat everything
>                 after that as parameters */
> -            target_phys_addr_t c = mb_add_cmdline(&mbs, initrd_filename);
> +            hwaddr c = mb_add_cmdline(&mbs, initrd_filename);
>              if ((next_space = strchr(initrd_filename, ' ')))
>                  *next_space = '\0';
>              mb_debug("multiboot loading module: %s\n", initrd_filename);
> diff --git a/hw/musicpal.c b/hw/musicpal.c
> index 159d3c3..beec76b 100644
> --- a/hw/musicpal.c
> +++ b/hw/musicpal.c
> @@ -266,7 +266,7 @@ static void eth_send(mv88w8618_eth_state *s, int queue_index)
>      } while (desc_addr != s->tx_queue[queue_index]);
>  }
>  
> -static uint64_t mv88w8618_eth_read(void *opaque, target_phys_addr_t offset,
> +static uint64_t mv88w8618_eth_read(void *opaque, hwaddr offset,
>                                     unsigned size)
>  {
>      mv88w8618_eth_state *s = opaque;
> @@ -308,7 +308,7 @@ static uint64_t mv88w8618_eth_read(void *opaque, target_phys_addr_t offset,
>      }
>  }
>  
> -static void mv88w8618_eth_write(void *opaque, target_phys_addr_t offset,
> +static void mv88w8618_eth_write(void *opaque, hwaddr offset,
>                                  uint64_t value, unsigned size)
>  {
>      mv88w8618_eth_state *s = opaque;
> @@ -540,7 +540,7 @@ static void musicpal_lcd_gpio_brigthness_in(void *opaque, int irq, int level)
>      s->brightness |= level << irq;
>  }
>  
> -static uint64_t musicpal_lcd_read(void *opaque, target_phys_addr_t offset,
> +static uint64_t musicpal_lcd_read(void *opaque, hwaddr offset,
>                                    unsigned size)
>  {
>      musicpal_lcd_state *s = opaque;
> @@ -554,7 +554,7 @@ static uint64_t musicpal_lcd_read(void *opaque, target_phys_addr_t offset,
>      }
>  }
>  
> -static void musicpal_lcd_write(void *opaque, target_phys_addr_t offset,
> +static void musicpal_lcd_write(void *opaque, hwaddr offset,
>                                 uint64_t value, unsigned size)
>  {
>      musicpal_lcd_state *s = opaque;
> @@ -682,7 +682,7 @@ static void mv88w8618_pic_set_irq(void *opaque, int irq, int level)
>      mv88w8618_pic_update(s);
>  }
>  
> -static uint64_t mv88w8618_pic_read(void *opaque, target_phys_addr_t offset,
> +static uint64_t mv88w8618_pic_read(void *opaque, hwaddr offset,
>                                     unsigned size)
>  {
>      mv88w8618_pic_state *s = opaque;
> @@ -696,7 +696,7 @@ static uint64_t mv88w8618_pic_read(void *opaque, target_phys_addr_t offset,
>      }
>  }
>  
> -static void mv88w8618_pic_write(void *opaque, target_phys_addr_t offset,
> +static void mv88w8618_pic_write(void *opaque, hwaddr offset,
>                                  uint64_t value, unsigned size)
>  {
>      mv88w8618_pic_state *s = opaque;
> @@ -815,7 +815,7 @@ static void mv88w8618_timer_init(SysBusDevice *dev, mv88w8618_timer_state *s,
>      s->ptimer = ptimer_init(bh);
>  }
>  
> -static uint64_t mv88w8618_pit_read(void *opaque, target_phys_addr_t offset,
> +static uint64_t mv88w8618_pit_read(void *opaque, hwaddr offset,
>                                     unsigned size)
>  {
>      mv88w8618_pit_state *s = opaque;
> @@ -831,7 +831,7 @@ static uint64_t mv88w8618_pit_read(void *opaque, target_phys_addr_t offset,
>      }
>  }
>  
> -static void mv88w8618_pit_write(void *opaque, target_phys_addr_t offset,
> +static void mv88w8618_pit_write(void *opaque, hwaddr offset,
>                                  uint64_t value, unsigned size)
>  {
>      mv88w8618_pit_state *s = opaque;
> @@ -957,7 +957,7 @@ static void mv88w8618_pit_class_init(ObjectClass *klass, void *data)
>  } mv88w8618_flashcfg_state;
>  
>  static uint64_t mv88w8618_flashcfg_read(void *opaque,
> -                                        target_phys_addr_t offset,
> +                                        hwaddr offset,
>                                          unsigned size)
>  {
>      mv88w8618_flashcfg_state *s = opaque;
> @@ -971,7 +971,7 @@ static uint64_t mv88w8618_flashcfg_read(void *opaque,
>      }
>  }
>  
> -static void mv88w8618_flashcfg_write(void *opaque, target_phys_addr_t offset,
> +static void mv88w8618_flashcfg_write(void *opaque, hwaddr offset,
>                                       uint64_t value, unsigned size)
>  {
>      mv88w8618_flashcfg_state *s = opaque;
> @@ -1032,7 +1032,7 @@ static void mv88w8618_flashcfg_class_init(ObjectClass *klass, void *data)
>  
>  #define MP_BOARD_REVISION       0x31
>  
> -static uint64_t musicpal_misc_read(void *opaque, target_phys_addr_t offset,
> +static uint64_t musicpal_misc_read(void *opaque, hwaddr offset,
>                                     unsigned size)
>  {
>      switch (offset) {
> @@ -1044,7 +1044,7 @@ static uint64_t musicpal_misc_read(void *opaque, target_phys_addr_t offset,
>      }
>  }
>  
> -static void musicpal_misc_write(void *opaque, target_phys_addr_t offset,
> +static void musicpal_misc_write(void *opaque, hwaddr offset,
>                                  uint64_t value, unsigned size)
>  {
>  }
> @@ -1068,7 +1068,7 @@ static void musicpal_misc_init(SysBusDevice *dev)
>  #define MP_WLAN_MAGIC1          0x11c
>  #define MP_WLAN_MAGIC2          0x124
>  
> -static uint64_t mv88w8618_wlan_read(void *opaque, target_phys_addr_t offset,
> +static uint64_t mv88w8618_wlan_read(void *opaque, hwaddr offset,
>                                      unsigned size)
>  {
>      switch (offset) {
> @@ -1084,7 +1084,7 @@ static uint64_t mv88w8618_wlan_read(void *opaque, target_phys_addr_t offset,
>      }
>  }
>  
> -static void mv88w8618_wlan_write(void *opaque, target_phys_addr_t offset,
> +static void mv88w8618_wlan_write(void *opaque, hwaddr offset,
>                                   uint64_t value, unsigned size)
>  {
>  }
> @@ -1202,7 +1202,7 @@ static void musicpal_gpio_pin_event(void *opaque, int pin, int level)
>      }
>  }
>  
> -static uint64_t musicpal_gpio_read(void *opaque, target_phys_addr_t offset,
> +static uint64_t musicpal_gpio_read(void *opaque, hwaddr offset,
>                                     unsigned size)
>  {
>      musicpal_gpio_state *s = opaque;
> @@ -1241,7 +1241,7 @@ static uint64_t musicpal_gpio_read(void *opaque, target_phys_addr_t offset,
>      }
>  }
>  
> -static void musicpal_gpio_write(void *opaque, target_phys_addr_t offset,
> +static void musicpal_gpio_write(void *opaque, hwaddr offset,
>                                  uint64_t value, unsigned size)
>  {
>      musicpal_gpio_state *s = opaque;
> diff --git a/hw/ne2000.c b/hw/ne2000.c
> index 15605c4..d3dd9a6 100644
> --- a/hw/ne2000.c
> +++ b/hw/ne2000.c
> @@ -652,7 +652,7 @@ static int ne2000_post_load(void* opaque, int version_id)
>      }
>  };
>  
> -static uint64_t ne2000_read(void *opaque, target_phys_addr_t addr,
> +static uint64_t ne2000_read(void *opaque, hwaddr addr,
>                              unsigned size)
>  {
>      NE2000State *s = opaque;
> @@ -671,7 +671,7 @@ static uint64_t ne2000_read(void *opaque, target_phys_addr_t addr,
>      return ((uint64_t)1 << (size * 8)) - 1;
>  }
>  
> -static void ne2000_write(void *opaque, target_phys_addr_t addr,
> +static void ne2000_write(void *opaque, hwaddr addr,
>                           uint64_t data, unsigned size)
>  {
>      NE2000State *s = opaque;
> diff --git a/hw/nvram.h b/hw/nvram.h
> index 8924da4..a4a1db4 100644
> --- a/hw/nvram.h
> +++ b/hw/nvram.h
> @@ -36,7 +36,7 @@ uint32_t m48t59_read (void *private, uint32_t addr);
>  void m48t59_toggle_lock (void *private, int lock);
>  M48t59State *m48t59_init_isa(ISABus *bus, uint32_t io_base, uint16_t size,
>                               int type);
> -M48t59State *m48t59_init(qemu_irq IRQ, target_phys_addr_t mem_base,
> +M48t59State *m48t59_init(qemu_irq IRQ, hwaddr mem_base,
>                           uint32_t io_base, uint16_t size, int type);
>  void m48t59_set_addr (void *opaque, uint32_t addr);
>  
> diff --git a/hw/omap.h b/hw/omap.h
> index 413851b..8bd7c73 100644
> --- a/hw/omap.h
> +++ b/hw/omap.h
> @@ -65,7 +65,7 @@ void omap_clk_reparent(omap_clk clk, omap_clk parent);
>  /* OMAP2 l4 Interconnect */
>  struct omap_l4_s;
>  struct omap_l4_region_s {
> -    target_phys_addr_t offset;
> +    hwaddr offset;
>      size_t size;
>      int access;
>  };
> @@ -80,13 +80,13 @@ struct omap_target_agent_s {
>      struct omap_l4_s *bus;
>      int regions;
>      const struct omap_l4_region_s *start;
> -    target_phys_addr_t base;
> +    hwaddr base;
>      uint32_t component;
>      uint32_t control;
>      uint32_t status;
>  };
>  struct omap_l4_s *omap_l4_init(MemoryRegion *address_space,
> -                               target_phys_addr_t base, int ta_num);
> +                               hwaddr base, int ta_num);
>  
>  struct omap_target_agent_s;
>  struct omap_target_agent_s *omap_l4ta_get(
> @@ -94,23 +94,23 @@ struct omap_target_agent_s *omap_l4ta_get(
>      const struct omap_l4_region_s *regions,
>      const struct omap_l4_agent_info_s *agents,
>      int cs);
> -target_phys_addr_t omap_l4_attach(struct omap_target_agent_s *ta,
> +hwaddr omap_l4_attach(struct omap_target_agent_s *ta,
>                                           int region, MemoryRegion *mr);
> -target_phys_addr_t omap_l4_region_base(struct omap_target_agent_s *ta,
> +hwaddr omap_l4_region_base(struct omap_target_agent_s *ta,
>                                         int region);
> -target_phys_addr_t omap_l4_region_size(struct omap_target_agent_s *ta,
> +hwaddr omap_l4_region_size(struct omap_target_agent_s *ta,
>                                         int region);
>  
>  /* OMAP2 SDRAM controller */
>  struct omap_sdrc_s;
>  struct omap_sdrc_s *omap_sdrc_init(MemoryRegion *sysmem,
> -                                   target_phys_addr_t base);
> +                                   hwaddr base);
>  void omap_sdrc_reset(struct omap_sdrc_s *s);
>  
>  /* OMAP2 general purpose memory controller */
>  struct omap_gpmc_s;
>  struct omap_gpmc_s *omap_gpmc_init(struct omap_mpu_state_s *mpu,
> -                                   target_phys_addr_t base,
> +                                   hwaddr base,
>                                     qemu_irq irq, qemu_irq drq);
>  void omap_gpmc_reset(struct omap_gpmc_s *s);
>  void omap_gpmc_attach(struct omap_gpmc_s *s, int cs, MemoryRegion *iomem);
> @@ -433,11 +433,11 @@ enum omap_dma_model {
>  };
>  
>  struct soc_dma_s;
> -struct soc_dma_s *omap_dma_init(target_phys_addr_t base, qemu_irq *irqs,
> +struct soc_dma_s *omap_dma_init(hwaddr base, qemu_irq *irqs,
>                  MemoryRegion *sysmem,
>                  qemu_irq lcd_irq, struct omap_mpu_state_s *mpu, omap_clk clk,
>                  enum omap_dma_model model);
> -struct soc_dma_s *omap_dma4_init(target_phys_addr_t base, qemu_irq *irqs,
> +struct soc_dma_s *omap_dma4_init(hwaddr base, qemu_irq *irqs,
>                  MemoryRegion *sysmem,
>                  struct omap_mpu_state_s *mpu, int fifo,
>                  int chans, omap_clk iclk, omap_clk fclk);
> @@ -469,10 +469,10 @@ typedef enum {
>  /* Only used in OMAP DMA 3.x gigacells */
>  struct omap_dma_lcd_channel_s {
>      enum omap_dma_port src;
> -    target_phys_addr_t src_f1_top;
> -    target_phys_addr_t src_f1_bottom;
> -    target_phys_addr_t src_f2_top;
> -    target_phys_addr_t src_f2_bottom;
> +    hwaddr src_f1_top;
> +    hwaddr src_f1_bottom;
> +    hwaddr src_f2_top;
> +    hwaddr src_f2_bottom;
>  
>      /* Used in OMAP DMA 3.2 gigacell */
>      unsigned char brust_f1;
> @@ -508,7 +508,7 @@ struct omap_dma_lcd_channel_s {
>      int dual;
>  
>      int current_frame;
> -    target_phys_addr_t phys_framebuffer[2];
> +    hwaddr phys_framebuffer[2];
>      qemu_irq irq;
>      struct omap_mpu_state_s *mpu;
>  } *omap_dma_get_lcdch(struct soc_dma_s *s);
> @@ -659,7 +659,7 @@ struct omap_synctimer_s *omap_synctimer_init(struct omap_target_agent_s *ta,
>  void omap_synctimer_reset(struct omap_synctimer_s *s);
>  
>  struct omap_uart_s;
> -struct omap_uart_s *omap_uart_init(target_phys_addr_t base,
> +struct omap_uart_s *omap_uart_init(hwaddr base,
>                  qemu_irq irq, omap_clk fclk, omap_clk iclk,
>                  qemu_irq txdma, qemu_irq rxdma,
>                  const char *label, CharDriverState *chr);
> @@ -728,7 +728,7 @@ void omap_tap_init(struct omap_target_agent_s *ta,
>  struct omap_lcd_panel_s;
>  void omap_lcdc_reset(struct omap_lcd_panel_s *s);
>  struct omap_lcd_panel_s *omap_lcdc_init(MemoryRegion *sysmem,
> -                                        target_phys_addr_t base,
> +                                        hwaddr base,
>                                          qemu_irq irq,
>                                          struct omap_dma_lcd_channel_s *dma,
>                                          omap_clk clk);
> @@ -744,7 +744,7 @@ struct omap_dss_s;
>  void omap_dss_reset(struct omap_dss_s *s);
>  struct omap_dss_s *omap_dss_init(struct omap_target_agent_s *ta,
>                  MemoryRegion *sysmem,
> -                target_phys_addr_t l3_base,
> +                hwaddr l3_base,
>                  qemu_irq irq, qemu_irq drq,
>                  omap_clk fck1, omap_clk fck2, omap_clk ck54m,
>                  omap_clk ick1, omap_clk ick2);
> @@ -752,7 +752,7 @@ void omap_rfbi_attach(struct omap_dss_s *s, int cs, struct rfbi_chip_s *chip);
>  
>  /* omap_mmc.c */
>  struct omap_mmc_s;
> -struct omap_mmc_s *omap_mmc_init(target_phys_addr_t base,
> +struct omap_mmc_s *omap_mmc_init(hwaddr base,
>                  MemoryRegion *sysmem,
>                  BlockDriverState *bd,
>                  qemu_irq irq, qemu_irq dma[], omap_clk clk);
> @@ -829,11 +829,11 @@ struct omap_mpu_state_s {
>  
>      struct omap_dma_port_if_s {
>          uint32_t (*read[3])(struct omap_mpu_state_s *s,
> -                        target_phys_addr_t offset);
> +                        hwaddr offset);
>          void (*write[3])(struct omap_mpu_state_s *s,
> -                        target_phys_addr_t offset, uint32_t value);
> +                        hwaddr offset, uint32_t value);
>          int (*addr_valid)(struct omap_mpu_state_s *s,
> -                        target_phys_addr_t addr);
> +                        hwaddr addr);
>      } port[__omap_dma_port_last];
>  
>      unsigned long sdram_size;
> @@ -942,16 +942,16 @@ struct omap_mpu_state_s *omap2420_mpu_init(MemoryRegion *sysmem,
>                  unsigned long sdram_size,
>                  const char *core);
>  
> -#define OMAP_FMT_plx "%#08" TARGET_PRIxPHYS
> +#define OMAP_FMT_plx "%#08" HWADDR_PRIx
>  
> -uint32_t omap_badwidth_read8(void *opaque, target_phys_addr_t addr);
> -void omap_badwidth_write8(void *opaque, target_phys_addr_t addr,
> +uint32_t omap_badwidth_read8(void *opaque, hwaddr addr);
> +void omap_badwidth_write8(void *opaque, hwaddr addr,
>                  uint32_t value);
> -uint32_t omap_badwidth_read16(void *opaque, target_phys_addr_t addr);
> -void omap_badwidth_write16(void *opaque, target_phys_addr_t addr,
> +uint32_t omap_badwidth_read16(void *opaque, hwaddr addr);
> +void omap_badwidth_write16(void *opaque, hwaddr addr,
>                  uint32_t value);
> -uint32_t omap_badwidth_read32(void *opaque, target_phys_addr_t addr);
> -void omap_badwidth_write32(void *opaque, target_phys_addr_t addr,
> +uint32_t omap_badwidth_read32(void *opaque, hwaddr addr);
> +void omap_badwidth_write32(void *opaque, hwaddr addr,
>                  uint32_t value);
>  
>  void omap_mpu_wakeup(void *opaque, int irq, int req);
> diff --git a/hw/omap1.c b/hw/omap1.c
> index ad60cc4..4d5815e 100644
> --- a/hw/omap1.c
> +++ b/hw/omap1.c
> @@ -26,7 +26,7 @@
>  #include "sysbus.h"
>  
>  /* Should signal the TCMI/GPMC */
> -uint32_t omap_badwidth_read8(void *opaque, target_phys_addr_t addr)
> +uint32_t omap_badwidth_read8(void *opaque, hwaddr addr)
>  {
>      uint8_t ret;
>  
> @@ -35,7 +35,7 @@ uint32_t omap_badwidth_read8(void *opaque, target_phys_addr_t addr)
>      return ret;
>  }
>  
> -void omap_badwidth_write8(void *opaque, target_phys_addr_t addr,
> +void omap_badwidth_write8(void *opaque, hwaddr addr,
>                  uint32_t value)
>  {
>      uint8_t val8 = value;
> @@ -44,7 +44,7 @@ void omap_badwidth_write8(void *opaque, target_phys_addr_t addr,
>      cpu_physical_memory_write(addr, (void *) &val8, 1);
>  }
>  
> -uint32_t omap_badwidth_read16(void *opaque, target_phys_addr_t addr)
> +uint32_t omap_badwidth_read16(void *opaque, hwaddr addr)
>  {
>      uint16_t ret;
>  
> @@ -53,7 +53,7 @@ uint32_t omap_badwidth_read16(void *opaque, target_phys_addr_t addr)
>      return ret;
>  }
>  
> -void omap_badwidth_write16(void *opaque, target_phys_addr_t addr,
> +void omap_badwidth_write16(void *opaque, hwaddr addr,
>                  uint32_t value)
>  {
>      uint16_t val16 = value;
> @@ -62,7 +62,7 @@ void omap_badwidth_write16(void *opaque, target_phys_addr_t addr,
>      cpu_physical_memory_write(addr, (void *) &val16, 2);
>  }
>  
> -uint32_t omap_badwidth_read32(void *opaque, target_phys_addr_t addr)
> +uint32_t omap_badwidth_read32(void *opaque, hwaddr addr)
>  {
>      uint32_t ret;
>  
> @@ -71,7 +71,7 @@ uint32_t omap_badwidth_read32(void *opaque, target_phys_addr_t addr)
>      return ret;
>  }
>  
> -void omap_badwidth_write32(void *opaque, target_phys_addr_t addr,
> +void omap_badwidth_write32(void *opaque, hwaddr addr,
>                  uint32_t value)
>  {
>      OMAP_32B_REG(addr);
> @@ -176,7 +176,7 @@ static void omap_timer_clk_setup(struct omap_mpu_timer_s *timer)
>      timer->rate = omap_clk_getrate(timer->clk);
>  }
>  
> -static uint64_t omap_mpu_timer_read(void *opaque, target_phys_addr_t addr,
> +static uint64_t omap_mpu_timer_read(void *opaque, hwaddr addr,
>                                      unsigned size)
>  {
>      struct omap_mpu_timer_s *s = (struct omap_mpu_timer_s *) opaque;
> @@ -200,7 +200,7 @@ static uint64_t omap_mpu_timer_read(void *opaque, target_phys_addr_t addr,
>      return 0;
>  }
>  
> -static void omap_mpu_timer_write(void *opaque, target_phys_addr_t addr,
> +static void omap_mpu_timer_write(void *opaque, hwaddr addr,
>                                   uint64_t value, unsigned size)
>  {
>      struct omap_mpu_timer_s *s = (struct omap_mpu_timer_s *) opaque;
> @@ -251,7 +251,7 @@ static void omap_mpu_timer_reset(struct omap_mpu_timer_s *s)
>  }
>  
>  static struct omap_mpu_timer_s *omap_mpu_timer_init(MemoryRegion *system_memory,
> -                target_phys_addr_t base,
> +                hwaddr base,
>                  qemu_irq irq, omap_clk clk)
>  {
>      struct omap_mpu_timer_s *s = (struct omap_mpu_timer_s *)
> @@ -282,7 +282,7 @@ struct omap_watchdog_timer_s {
>      int reset;
>  };
>  
> -static uint64_t omap_wd_timer_read(void *opaque, target_phys_addr_t addr,
> +static uint64_t omap_wd_timer_read(void *opaque, hwaddr addr,
>                                     unsigned size)
>  {
>      struct omap_watchdog_timer_s *s = (struct omap_watchdog_timer_s *) opaque;
> @@ -307,7 +307,7 @@ static uint64_t omap_wd_timer_read(void *opaque, target_phys_addr_t addr,
>      return 0;
>  }
>  
> -static void omap_wd_timer_write(void *opaque, target_phys_addr_t addr,
> +static void omap_wd_timer_write(void *opaque, hwaddr addr,
>                                  uint64_t value, unsigned size)
>  {
>      struct omap_watchdog_timer_s *s = (struct omap_watchdog_timer_s *) opaque;
> @@ -380,7 +380,7 @@ static void omap_wd_timer_reset(struct omap_watchdog_timer_s *s)
>  }
>  
>  static struct omap_watchdog_timer_s *omap_wd_timer_init(MemoryRegion *memory,
> -                target_phys_addr_t base,
> +                hwaddr base,
>                  qemu_irq irq, omap_clk clk)
>  {
>      struct omap_watchdog_timer_s *s = (struct omap_watchdog_timer_s *)
> @@ -405,7 +405,7 @@ struct omap_32khz_timer_s {
>      MemoryRegion iomem;
>  };
>  
> -static uint64_t omap_os_timer_read(void *opaque, target_phys_addr_t addr,
> +static uint64_t omap_os_timer_read(void *opaque, hwaddr addr,
>                                     unsigned size)
>  {
>      struct omap_32khz_timer_s *s = (struct omap_32khz_timer_s *) opaque;
> @@ -432,7 +432,7 @@ static uint64_t omap_os_timer_read(void *opaque, target_phys_addr_t addr,
>      return 0;
>  }
>  
> -static void omap_os_timer_write(void *opaque, target_phys_addr_t addr,
> +static void omap_os_timer_write(void *opaque, hwaddr addr,
>                                  uint64_t value, unsigned size)
>  {
>      struct omap_32khz_timer_s *s = (struct omap_32khz_timer_s *) opaque;
> @@ -486,7 +486,7 @@ static void omap_os_timer_reset(struct omap_32khz_timer_s *s)
>  }
>  
>  static struct omap_32khz_timer_s *omap_os_timer_init(MemoryRegion *memory,
> -                target_phys_addr_t base,
> +                hwaddr base,
>                  qemu_irq irq, omap_clk clk)
>  {
>      struct omap_32khz_timer_s *s = (struct omap_32khz_timer_s *)
> @@ -506,7 +506,7 @@ static struct omap_32khz_timer_s *omap_os_timer_init(MemoryRegion *memory,
>  }
>  
>  /* Ultra Low-Power Device Module */
> -static uint64_t omap_ulpd_pm_read(void *opaque, target_phys_addr_t addr,
> +static uint64_t omap_ulpd_pm_read(void *opaque, hwaddr addr,
>                                    unsigned size)
>  {
>      struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
> @@ -573,7 +573,7 @@ static inline void omap_ulpd_req_update(struct omap_mpu_state_s *s,
>          omap_clk_canidle(omap_findclk(s, "usb_clk0"), (~value >> 3) & 1);
>  }
>  
> -static void omap_ulpd_pm_write(void *opaque, target_phys_addr_t addr,
> +static void omap_ulpd_pm_write(void *opaque, hwaddr addr,
>                                 uint64_t value, unsigned size)
>  {
>      struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
> @@ -726,7 +726,7 @@ static void omap_ulpd_pm_reset(struct omap_mpu_state_s *mpu)
>  }
>  
>  static void omap_ulpd_pm_init(MemoryRegion *system_memory,
> -                target_phys_addr_t base,
> +                hwaddr base,
>                  struct omap_mpu_state_s *mpu)
>  {
>      memory_region_init_io(&mpu->ulpd_pm_iomem, &omap_ulpd_pm_ops, mpu,
> @@ -736,7 +736,7 @@ static void omap_ulpd_pm_init(MemoryRegion *system_memory,
>  }
>  
>  /* OMAP Pin Configuration */
> -static uint64_t omap_pin_cfg_read(void *opaque, target_phys_addr_t addr,
> +static uint64_t omap_pin_cfg_read(void *opaque, hwaddr addr,
>                                    unsigned size)
>  {
>      struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
> @@ -843,7 +843,7 @@ static inline void omap_pin_modconf1_update(struct omap_mpu_state_s *s,
>           omap_clk_onoff(omap_findclk(s, "usb_hhc_ck"), (value >> 9) & 1);
>  }
>  
> -static void omap_pin_cfg_write(void *opaque, target_phys_addr_t addr,
> +static void omap_pin_cfg_write(void *opaque, hwaddr addr,
>                                 uint64_t value, unsigned size)
>  {
>      struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
> @@ -944,7 +944,7 @@ static void omap_pin_cfg_reset(struct omap_mpu_state_s *mpu)
>  }
>  
>  static void omap_pin_cfg_init(MemoryRegion *system_memory,
> -                target_phys_addr_t base,
> +                hwaddr base,
>                  struct omap_mpu_state_s *mpu)
>  {
>      memory_region_init_io(&mpu->pin_cfg_iomem, &omap_pin_cfg_ops, mpu,
> @@ -954,7 +954,7 @@ static void omap_pin_cfg_init(MemoryRegion *system_memory,
>  }
>  
>  /* Device Identification, Die Identification */
> -static uint64_t omap_id_read(void *opaque, target_phys_addr_t addr,
> +static uint64_t omap_id_read(void *opaque, hwaddr addr,
>                               unsigned size)
>  {
>      struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
> @@ -1001,7 +1001,7 @@ static uint64_t omap_id_read(void *opaque, target_phys_addr_t addr,
>      return 0;
>  }
>  
> -static void omap_id_write(void *opaque, target_phys_addr_t addr,
> +static void omap_id_write(void *opaque, hwaddr addr,
>                            uint64_t value, unsigned size)
>  {
>      if (size != 4) {
> @@ -1035,7 +1035,7 @@ static void omap_id_init(MemoryRegion *memory, struct omap_mpu_state_s *mpu)
>  }
>  
>  /* MPUI Control (Dummy) */
> -static uint64_t omap_mpui_read(void *opaque, target_phys_addr_t addr,
> +static uint64_t omap_mpui_read(void *opaque, hwaddr addr,
>                                 unsigned size)
>  {
>      struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
> @@ -1068,7 +1068,7 @@ static uint64_t omap_mpui_read(void *opaque, target_phys_addr_t addr,
>      return 0;
>  }
>  
> -static void omap_mpui_write(void *opaque, target_phys_addr_t addr,
> +static void omap_mpui_write(void *opaque, hwaddr addr,
>                              uint64_t value, unsigned size)
>  {
>      struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
> @@ -1109,7 +1109,7 @@ static void omap_mpui_reset(struct omap_mpu_state_s *s)
>      s->mpui_ctrl = 0x0003ff1b;
>  }
>  
> -static void omap_mpui_init(MemoryRegion *memory, target_phys_addr_t base,
> +static void omap_mpui_init(MemoryRegion *memory, hwaddr base,
>                  struct omap_mpu_state_s *mpu)
>  {
>      memory_region_init_io(&mpu->mpui_iomem, &omap_mpui_ops, mpu,
> @@ -1131,7 +1131,7 @@ struct omap_tipb_bridge_s {
>      uint16_t enh_control;
>  };
>  
> -static uint64_t omap_tipb_bridge_read(void *opaque, target_phys_addr_t addr,
> +static uint64_t omap_tipb_bridge_read(void *opaque, hwaddr addr,
>                                        unsigned size)
>  {
>      struct omap_tipb_bridge_s *s = (struct omap_tipb_bridge_s *) opaque;
> @@ -1161,7 +1161,7 @@ static uint64_t omap_tipb_bridge_read(void *opaque, target_phys_addr_t addr,
>      return 0;
>  }
>  
> -static void omap_tipb_bridge_write(void *opaque, target_phys_addr_t addr,
> +static void omap_tipb_bridge_write(void *opaque, hwaddr addr,
>                                     uint64_t value, unsigned size)
>  {
>      struct omap_tipb_bridge_s *s = (struct omap_tipb_bridge_s *) opaque;
> @@ -1215,7 +1215,7 @@ static void omap_tipb_bridge_reset(struct omap_tipb_bridge_s *s)
>  }
>  
>  static struct omap_tipb_bridge_s *omap_tipb_bridge_init(
> -    MemoryRegion *memory, target_phys_addr_t base,
> +    MemoryRegion *memory, hwaddr base,
>      qemu_irq abort_irq, omap_clk clk)
>  {
>      struct omap_tipb_bridge_s *s = (struct omap_tipb_bridge_s *)
> @@ -1232,7 +1232,7 @@ static struct omap_tipb_bridge_s *omap_tipb_bridge_init(
>  }
>  
>  /* Dummy Traffic Controller's Memory Interface */
> -static uint64_t omap_tcmi_read(void *opaque, target_phys_addr_t addr,
> +static uint64_t omap_tcmi_read(void *opaque, hwaddr addr,
>                                 unsigned size)
>  {
>      struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
> @@ -1270,7 +1270,7 @@ static uint64_t omap_tcmi_read(void *opaque, target_phys_addr_t addr,
>      return 0;
>  }
>  
> -static void omap_tcmi_write(void *opaque, target_phys_addr_t addr,
> +static void omap_tcmi_write(void *opaque, hwaddr addr,
>                              uint64_t value, unsigned size)
>  {
>      struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
> @@ -1330,7 +1330,7 @@ static void omap_tcmi_reset(struct omap_mpu_state_s *mpu)
>      mpu->tcmi_regs[0x40 >> 2] = 0x00000000;
>  }
>  
> -static void omap_tcmi_init(MemoryRegion *memory, target_phys_addr_t base,
> +static void omap_tcmi_init(MemoryRegion *memory, hwaddr base,
>                  struct omap_mpu_state_s *mpu)
>  {
>      memory_region_init_io(&mpu->tcmi_iomem, &omap_tcmi_ops, mpu,
> @@ -1346,7 +1346,7 @@ struct dpll_ctl_s {
>      omap_clk dpll;
>  };
>  
> -static uint64_t omap_dpll_read(void *opaque, target_phys_addr_t addr,
> +static uint64_t omap_dpll_read(void *opaque, hwaddr addr,
>                                 unsigned size)
>  {
>      struct dpll_ctl_s *s = (struct dpll_ctl_s *) opaque;
> @@ -1362,7 +1362,7 @@ static uint64_t omap_dpll_read(void *opaque, target_phys_addr_t addr,
>      return 0;
>  }
>  
> -static void omap_dpll_write(void *opaque, target_phys_addr_t addr,
> +static void omap_dpll_write(void *opaque, hwaddr addr,
>                              uint64_t value, unsigned size)
>  {
>      struct dpll_ctl_s *s = (struct dpll_ctl_s *) opaque;
> @@ -1412,7 +1412,7 @@ static void omap_dpll_reset(struct dpll_ctl_s *s)
>  }
>  
>  static struct dpll_ctl_s  *omap_dpll_init(MemoryRegion *memory,
> -                           target_phys_addr_t base, omap_clk clk)
> +                           hwaddr base, omap_clk clk)
>  {
>      struct dpll_ctl_s *s = g_malloc0(sizeof(*s));
>      memory_region_init_io(&s->iomem, &omap_dpll_ops, s, "omap-dpll", 0x100);
> @@ -1425,7 +1425,7 @@ static struct dpll_ctl_s  *omap_dpll_init(MemoryRegion *memory,
>  }
>  
>  /* MPU Clock/Reset/Power Mode Control */
> -static uint64_t omap_clkm_read(void *opaque, target_phys_addr_t addr,
> +static uint64_t omap_clkm_read(void *opaque, hwaddr addr,
>                                 unsigned size)
>  {
>      struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
> @@ -1627,7 +1627,7 @@ static inline void omap_clkm_ckout1_update(struct omap_mpu_state_s *s,
>      }
>  }
>  
> -static void omap_clkm_write(void *opaque, target_phys_addr_t addr,
> +static void omap_clkm_write(void *opaque, hwaddr addr,
>                              uint64_t value, unsigned size)
>  {
>      struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
> @@ -1714,7 +1714,7 @@ static void omap_clkm_write(void *opaque, target_phys_addr_t addr,
>      .endianness = DEVICE_NATIVE_ENDIAN,
>  };
>  
> -static uint64_t omap_clkdsp_read(void *opaque, target_phys_addr_t addr,
> +static uint64_t omap_clkdsp_read(void *opaque, hwaddr addr,
>                                   unsigned size)
>  {
>      struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
> @@ -1758,7 +1758,7 @@ static inline void omap_clkdsp_idlect2_update(struct omap_mpu_state_s *s,
>      SET_ONOFF("dspxor_ck", 1);				/* EN_XORPCK */
>  }
>  
> -static void omap_clkdsp_write(void *opaque, target_phys_addr_t addr,
> +static void omap_clkdsp_write(void *opaque, hwaddr addr,
>                                uint64_t value, unsigned size)
>  {
>      struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
> @@ -1823,8 +1823,8 @@ static void omap_clkm_reset(struct omap_mpu_state_s *s)
>      s->clkm.dsp_rstct2 = 0x0000;
>  }
>  
> -static void omap_clkm_init(MemoryRegion *memory, target_phys_addr_t mpu_base,
> -                target_phys_addr_t dsp_base, struct omap_mpu_state_s *s)
> +static void omap_clkm_init(MemoryRegion *memory, hwaddr mpu_base,
> +                hwaddr dsp_base, struct omap_mpu_state_s *s)
>  {
>      memory_region_init_io(&s->clkm_iomem, &omap_clkm_ops, s,
>                            "omap-clkm", 0x100);
> @@ -1903,7 +1903,7 @@ static void omap_mpuio_kbd_update(struct omap_mpuio_s *s)
>      s->row_latch = ~rows;
>  }
>  
> -static uint64_t omap_mpuio_read(void *opaque, target_phys_addr_t addr,
> +static uint64_t omap_mpuio_read(void *opaque, hwaddr addr,
>                                  unsigned size)
>  {
>      struct omap_mpuio_s *s = (struct omap_mpuio_s *) opaque;
> @@ -1963,7 +1963,7 @@ static uint64_t omap_mpuio_read(void *opaque, target_phys_addr_t addr,
>      return 0;
>  }
>  
> -static void omap_mpuio_write(void *opaque, target_phys_addr_t addr,
> +static void omap_mpuio_write(void *opaque, hwaddr addr,
>                               uint64_t value, unsigned size)
>  {
>      struct omap_mpuio_s *s = (struct omap_mpuio_s *) opaque;
> @@ -2072,7 +2072,7 @@ static void omap_mpuio_onoff(void *opaque, int line, int on)
>  }
>  
>  static struct omap_mpuio_s *omap_mpuio_init(MemoryRegion *memory,
> -                target_phys_addr_t base,
> +                hwaddr base,
>                  qemu_irq kbd_int, qemu_irq gpio_int, qemu_irq wakeup,
>                  omap_clk clk)
>  {
> @@ -2159,7 +2159,7 @@ static void omap_uwire_transfer_start(struct omap_uwire_s *s)
>      }
>  }
>  
> -static uint64_t omap_uwire_read(void *opaque, target_phys_addr_t addr,
> +static uint64_t omap_uwire_read(void *opaque, hwaddr addr,
>                                  unsigned size)
>  {
>      struct omap_uwire_s *s = (struct omap_uwire_s *) opaque;
> @@ -2193,7 +2193,7 @@ static uint64_t omap_uwire_read(void *opaque, target_phys_addr_t addr,
>      return 0;
>  }
>  
> -static void omap_uwire_write(void *opaque, target_phys_addr_t addr,
> +static void omap_uwire_write(void *opaque, hwaddr addr,
>                               uint64_t value, unsigned size)
>  {
>      struct omap_uwire_s *s = (struct omap_uwire_s *) opaque;
> @@ -2263,7 +2263,7 @@ static void omap_uwire_reset(struct omap_uwire_s *s)
>  }
>  
>  static struct omap_uwire_s *omap_uwire_init(MemoryRegion *system_memory,
> -                                            target_phys_addr_t base,
> +                                            hwaddr base,
>                                              qemu_irq txirq, qemu_irq rxirq,
>                                              qemu_irq dma,
>                                              omap_clk clk)
> @@ -2312,7 +2312,7 @@ static void omap_pwl_update(struct omap_pwl_s *s)
>      }
>  }
>  
> -static uint64_t omap_pwl_read(void *opaque, target_phys_addr_t addr,
> +static uint64_t omap_pwl_read(void *opaque, hwaddr addr,
>                                unsigned size)
>  {
>      struct omap_pwl_s *s = (struct omap_pwl_s *) opaque;
> @@ -2332,7 +2332,7 @@ static uint64_t omap_pwl_read(void *opaque, target_phys_addr_t addr,
>      return 0;
>  }
>  
> -static void omap_pwl_write(void *opaque, target_phys_addr_t addr,
> +static void omap_pwl_write(void *opaque, hwaddr addr,
>                             uint64_t value, unsigned size)
>  {
>      struct omap_pwl_s *s = (struct omap_pwl_s *) opaque;
> @@ -2381,7 +2381,7 @@ static void omap_pwl_clk_update(void *opaque, int line, int on)
>  }
>  
>  static struct omap_pwl_s *omap_pwl_init(MemoryRegion *system_memory,
> -                                        target_phys_addr_t base,
> +                                        hwaddr base,
>                                          omap_clk clk)
>  {
>      struct omap_pwl_s *s = g_malloc0(sizeof(*s));
> @@ -2405,7 +2405,7 @@ struct omap_pwt_s {
>      omap_clk clk;
>  };
>  
> -static uint64_t omap_pwt_read(void *opaque, target_phys_addr_t addr,
> +static uint64_t omap_pwt_read(void *opaque, hwaddr addr,
>                                unsigned size)
>  {
>      struct omap_pwt_s *s = (struct omap_pwt_s *) opaque;
> @@ -2427,7 +2427,7 @@ static uint64_t omap_pwt_read(void *opaque, target_phys_addr_t addr,
>      return 0;
>  }
>  
> -static void omap_pwt_write(void *opaque, target_phys_addr_t addr,
> +static void omap_pwt_write(void *opaque, hwaddr addr,
>                             uint64_t value, unsigned size)
>  {
>      struct omap_pwt_s *s = (struct omap_pwt_s *) opaque;
> @@ -2488,7 +2488,7 @@ static void omap_pwt_reset(struct omap_pwt_s *s)
>  }
>  
>  static struct omap_pwt_s *omap_pwt_init(MemoryRegion *system_memory,
> -                                        target_phys_addr_t base,
> +                                        hwaddr base,
>                                          omap_clk clk)
>  {
>      struct omap_pwt_s *s = g_malloc0(sizeof(*s));
> @@ -2536,7 +2536,7 @@ static void omap_rtc_alarm_update(struct omap_rtc_s *s)
>          printf("%s: conversion failed\n", __FUNCTION__);
>  }
>  
> -static uint64_t omap_rtc_read(void *opaque, target_phys_addr_t addr,
> +static uint64_t omap_rtc_read(void *opaque, hwaddr addr,
>                                unsigned size)
>  {
>      struct omap_rtc_s *s = (struct omap_rtc_s *) opaque;
> @@ -2618,7 +2618,7 @@ static uint64_t omap_rtc_read(void *opaque, target_phys_addr_t addr,
>      return 0;
>  }
>  
> -static void omap_rtc_write(void *opaque, target_phys_addr_t addr,
> +static void omap_rtc_write(void *opaque, hwaddr addr,
>                             uint64_t value, unsigned size)
>  {
>      struct omap_rtc_s *s = (struct omap_rtc_s *) opaque;
> @@ -2901,7 +2901,7 @@ static void omap_rtc_reset(struct omap_rtc_s *s)
>  }
>  
>  static struct omap_rtc_s *omap_rtc_init(MemoryRegion *system_memory,
> -                                        target_phys_addr_t base,
> +                                        hwaddr base,
>                                          qemu_irq timerirq, qemu_irq alarmirq,
>                                          omap_clk clk)
>  {
> @@ -3129,7 +3129,7 @@ static void omap_mcbsp_req_update(struct omap_mcbsp_s *s)
>          omap_mcbsp_rx_stop(s);
>  }
>  
> -static uint64_t omap_mcbsp_read(void *opaque, target_phys_addr_t addr,
> +static uint64_t omap_mcbsp_read(void *opaque, hwaddr addr,
>                                  unsigned size)
>  {
>      struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque;
> @@ -3227,7 +3227,7 @@ static uint64_t omap_mcbsp_read(void *opaque, target_phys_addr_t addr,
>      return 0;
>  }
>  
> -static void omap_mcbsp_writeh(void *opaque, target_phys_addr_t addr,
> +static void omap_mcbsp_writeh(void *opaque, hwaddr addr,
>                  uint32_t value)
>  {
>      struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque;
> @@ -3365,7 +3365,7 @@ static void omap_mcbsp_writeh(void *opaque, target_phys_addr_t addr,
>      OMAP_BAD_REG(addr);
>  }
>  
> -static void omap_mcbsp_writew(void *opaque, target_phys_addr_t addr,
> +static void omap_mcbsp_writew(void *opaque, hwaddr addr,
>                  uint32_t value)
>  {
>      struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque;
> @@ -3396,7 +3396,7 @@ static void omap_mcbsp_writew(void *opaque, target_phys_addr_t addr,
>      omap_badwidth_write16(opaque, addr, value);
>  }
>  
> -static void omap_mcbsp_write(void *opaque, target_phys_addr_t addr,
> +static void omap_mcbsp_write(void *opaque, hwaddr addr,
>                               uint64_t value, unsigned size)
>  {
>      switch (size) {
> @@ -3432,7 +3432,7 @@ static void omap_mcbsp_reset(struct omap_mcbsp_s *s)
>  }
>  
>  static struct omap_mcbsp_s *omap_mcbsp_init(MemoryRegion *system_memory,
> -                                            target_phys_addr_t base,
> +                                            hwaddr base,
>                                              qemu_irq txirq, qemu_irq rxirq,
>                                              qemu_irq *dma, omap_clk clk)
>  {
> @@ -3547,7 +3547,7 @@ static void omap_lpg_reset(struct omap_lpg_s *s)
>      omap_lpg_update(s);
>  }
>  
> -static uint64_t omap_lpg_read(void *opaque, target_phys_addr_t addr,
> +static uint64_t omap_lpg_read(void *opaque, hwaddr addr,
>                                unsigned size)
>  {
>      struct omap_lpg_s *s = (struct omap_lpg_s *) opaque;
> @@ -3569,7 +3569,7 @@ static uint64_t omap_lpg_read(void *opaque, target_phys_addr_t addr,
>      return 0;
>  }
>  
> -static void omap_lpg_write(void *opaque, target_phys_addr_t addr,
> +static void omap_lpg_write(void *opaque, hwaddr addr,
>                             uint64_t value, unsigned size)
>  {
>      struct omap_lpg_s *s = (struct omap_lpg_s *) opaque;
> @@ -3613,7 +3613,7 @@ static void omap_lpg_clk_update(void *opaque, int line, int on)
>  }
>  
>  static struct omap_lpg_s *omap_lpg_init(MemoryRegion *system_memory,
> -                                        target_phys_addr_t base, omap_clk clk)
> +                                        hwaddr base, omap_clk clk)
>  {
>      struct omap_lpg_s *s = (struct omap_lpg_s *)
>              g_malloc0(sizeof(struct omap_lpg_s));
> @@ -3631,7 +3631,7 @@ static struct omap_lpg_s *omap_lpg_init(MemoryRegion *system_memory,
>  }
>  
>  /* MPUI Peripheral Bridge configuration */
> -static uint64_t omap_mpui_io_read(void *opaque, target_phys_addr_t addr,
> +static uint64_t omap_mpui_io_read(void *opaque, hwaddr addr,
>                                    unsigned size)
>  {
>      if (size != 2) {
> @@ -3645,7 +3645,7 @@ static uint64_t omap_mpui_io_read(void *opaque, target_phys_addr_t addr,
>      return 0;
>  }
>  
> -static void omap_mpui_io_write(void *opaque, target_phys_addr_t addr,
> +static void omap_mpui_io_write(void *opaque, hwaddr addr,
>                                 uint64_t value, unsigned size)
>  {
>      /* FIXME: infinite loop */
> @@ -3706,8 +3706,8 @@ static void omap1_mpu_reset(void *opaque)
>  }
>  
>  static const struct omap_map_s {
> -    target_phys_addr_t phys_dsp;
> -    target_phys_addr_t phys_mpu;
> +    hwaddr phys_dsp;
> +    hwaddr phys_mpu;
>      uint32_t size;
>      const char *name;
>  } omap15xx_dsp_mm[] = {
> @@ -3778,38 +3778,38 @@ void omap_mpu_wakeup(void *opaque, int irq, int req)
>  
>  /* DMA ports for OMAP1 */
>  static int omap_validate_emiff_addr(struct omap_mpu_state_s *s,
> -                target_phys_addr_t addr)
> +                hwaddr addr)
>  {
>      return range_covers_byte(OMAP_EMIFF_BASE, s->sdram_size, addr);
>  }
>  
>  static int omap_validate_emifs_addr(struct omap_mpu_state_s *s,
> -                target_phys_addr_t addr)
> +                hwaddr addr)
>  {
>      return range_covers_byte(OMAP_EMIFS_BASE, OMAP_EMIFF_BASE - OMAP_EMIFS_BASE,
>                               addr);
>  }
>  
>  static int omap_validate_imif_addr(struct omap_mpu_state_s *s,
> -                target_phys_addr_t addr)
> +                hwaddr addr)
>  {
>      return range_covers_byte(OMAP_IMIF_BASE, s->sram_size, addr);
>  }
>  
>  static int omap_validate_tipb_addr(struct omap_mpu_state_s *s,
> -                target_phys_addr_t addr)
> +                hwaddr addr)
>  {
>      return range_covers_byte(0xfffb0000, 0xffff0000 - 0xfffb0000, addr);
>  }
>  
>  static int omap_validate_local_addr(struct omap_mpu_state_s *s,
> -                target_phys_addr_t addr)
> +                hwaddr addr)
>  {
>      return range_covers_byte(OMAP_LOCALBUS_BASE, 0x1000000, addr);
>  }
>  
>  static int omap_validate_tipb_mpui_addr(struct omap_mpu_state_s *s,
> -                target_phys_addr_t addr)
> +                hwaddr addr)
>  {
>      return range_covers_byte(0xe1010000, 0xe1020004 - 0xe1010000, addr);
>  }
> diff --git a/hw/omap2.c b/hw/omap2.c
> index 4278dd1..96aba71 100644
> --- a/hw/omap2.c
> +++ b/hw/omap2.c
> @@ -324,7 +324,7 @@ static void omap_eac_reset(struct omap_eac_s *s)
>      omap_eac_interrupt_update(s);
>  }
>  
> -static uint64_t omap_eac_read(void *opaque, target_phys_addr_t addr,
> +static uint64_t omap_eac_read(void *opaque, hwaddr addr,
>                                unsigned size)
>  {
>      struct omap_eac_s *s = (struct omap_eac_s *) opaque;
> @@ -440,7 +440,7 @@ static uint64_t omap_eac_read(void *opaque, target_phys_addr_t addr,
>      return 0;
>  }
>  
> -static void omap_eac_write(void *opaque, target_phys_addr_t addr,
> +static void omap_eac_write(void *opaque, hwaddr addr,
>                             uint64_t value, unsigned size)
>  {
>      struct omap_eac_s *s = (struct omap_eac_s *) opaque;
> @@ -644,7 +644,7 @@ static void omap_sti_reset(struct omap_sti_s *s)
>      omap_sti_interrupt_update(s);
>  }
>  
> -static uint64_t omap_sti_read(void *opaque, target_phys_addr_t addr,
> +static uint64_t omap_sti_read(void *opaque, hwaddr addr,
>                                unsigned size)
>  {
>      struct omap_sti_s *s = (struct omap_sti_s *) opaque;
> @@ -685,7 +685,7 @@ static uint64_t omap_sti_read(void *opaque, target_phys_addr_t addr,
>      return 0;
>  }
>  
> -static void omap_sti_write(void *opaque, target_phys_addr_t addr,
> +static void omap_sti_write(void *opaque, hwaddr addr,
>                             uint64_t value, unsigned size)
>  {
>      struct omap_sti_s *s = (struct omap_sti_s *) opaque;
> @@ -741,14 +741,14 @@ static void omap_sti_write(void *opaque, target_phys_addr_t addr,
>      .endianness = DEVICE_NATIVE_ENDIAN,
>  };
>  
> -static uint64_t omap_sti_fifo_read(void *opaque, target_phys_addr_t addr,
> +static uint64_t omap_sti_fifo_read(void *opaque, hwaddr addr,
>                                     unsigned size)
>  {
>      OMAP_BAD_REG(addr);
>      return 0;
>  }
>  
> -static void omap_sti_fifo_write(void *opaque, target_phys_addr_t addr,
> +static void omap_sti_fifo_write(void *opaque, hwaddr addr,
>                                  uint64_t value, unsigned size)
>  {
>      struct omap_sti_s *s = (struct omap_sti_s *) opaque;
> @@ -780,7 +780,7 @@ static void omap_sti_fifo_write(void *opaque, target_phys_addr_t addr,
>  
>  static struct omap_sti_s *omap_sti_init(struct omap_target_agent_s *ta,
>                  MemoryRegion *sysmem,
> -                target_phys_addr_t channel_base, qemu_irq irq, omap_clk clk,
> +                hwaddr channel_base, qemu_irq irq, omap_clk clk,
>                  CharDriverState *chr)
>  {
>      struct omap_sti_s *s = (struct omap_sti_s *)
> @@ -1040,7 +1040,7 @@ static void omap_prcm_int_update(struct omap_prcm_s *s, int dom)
>      /* XXX or is the mask applied before PRCM_IRQSTATUS_* ? */
>  }
>  
> -static uint64_t omap_prcm_read(void *opaque, target_phys_addr_t addr,
> +static uint64_t omap_prcm_read(void *opaque, hwaddr addr,
>                                 unsigned size)
>  {
>      struct omap_prcm_s *s = (struct omap_prcm_s *) opaque;
> @@ -1352,7 +1352,7 @@ static void omap_prcm_dpll_update(struct omap_prcm_s *s)
>      }
>  }
>  
> -static void omap_prcm_write(void *opaque, target_phys_addr_t addr,
> +static void omap_prcm_write(void *opaque, hwaddr addr,
>                              uint64_t value, unsigned size)
>  {
>      struct omap_prcm_s *s = (struct omap_prcm_s *) opaque;
> @@ -1832,7 +1832,7 @@ struct omap_sysctl_s {
>      uint32_t msuspendmux[5];
>  };
>  
> -static uint32_t omap_sysctl_read8(void *opaque, target_phys_addr_t addr)
> +static uint32_t omap_sysctl_read8(void *opaque, hwaddr addr)
>  {
>  
>      struct omap_sysctl_s *s = (struct omap_sysctl_s *) opaque;
> @@ -1857,7 +1857,7 @@ static uint32_t omap_sysctl_read8(void *opaque, target_phys_addr_t addr)
>      return 0;
>  }
>  
> -static uint32_t omap_sysctl_read(void *opaque, target_phys_addr_t addr)
> +static uint32_t omap_sysctl_read(void *opaque, hwaddr addr)
>  {
>      struct omap_sysctl_s *s = (struct omap_sysctl_s *) opaque;
>  
> @@ -1957,7 +1957,7 @@ static uint32_t omap_sysctl_read(void *opaque, target_phys_addr_t addr)
>      return 0;
>  }
>  
> -static void omap_sysctl_write8(void *opaque, target_phys_addr_t addr,
> +static void omap_sysctl_write8(void *opaque, hwaddr addr,
>                  uint32_t value)
>  {
>      struct omap_sysctl_s *s = (struct omap_sysctl_s *) opaque;
> @@ -1981,7 +1981,7 @@ static void omap_sysctl_write8(void *opaque, target_phys_addr_t addr,
>      }
>  }
>  
> -static void omap_sysctl_write(void *opaque, target_phys_addr_t addr,
> +static void omap_sysctl_write(void *opaque, hwaddr addr,
>                  uint32_t value)
>  {
>      struct omap_sysctl_s *s = (struct omap_sysctl_s *) opaque;
> @@ -2226,7 +2226,7 @@ static void omap2_mpu_reset(void *opaque)
>  }
>  
>  static int omap2_validate_addr(struct omap_mpu_state_s *s,
> -                target_phys_addr_t addr)
> +                hwaddr addr)
>  {
>      return 1;
>  }
> diff --git a/hw/omap_dma.c b/hw/omap_dma.c
> index 389cb78..e619c7b 100644
> --- a/hw/omap_dma.c
> +++ b/hw/omap_dma.c
> @@ -31,7 +31,7 @@ struct omap_dma_channel_s {
>      int endian_lock[2];
>      int translate[2];
>      enum omap_dma_port port[2];
> -    target_phys_addr_t addr[2];
> +    hwaddr addr[2];
>      omap_dma_addressing_t mode[2];
>      uint32_t elements;
>      uint16_t frames;
> @@ -78,7 +78,7 @@ struct omap_dma_channel_s {
>      struct omap_dma_channel_s *sibling;
>  
>      struct omap_dma_reg_set_s {
> -        target_phys_addr_t src, dest;
> +        hwaddr src, dest;
>          int frame;
>          int element;
>          int pck_element;
> @@ -914,7 +914,7 @@ static int omap_dma_ch_reg_write(struct omap_dma_s *s,
>          break;
>  
>      case 0x06:	/* SYS_DMA_CSR_CH0 */
> -        OMAP_RO_REG((target_phys_addr_t) reg);
> +        OMAP_RO_REG((hwaddr) reg);
>          break;
>  
>      case 0x08:	/* SYS_DMA_CSSA_L_CH0 */
> @@ -954,7 +954,7 @@ static int omap_dma_ch_reg_write(struct omap_dma_s *s,
>          break;
>  
>      case 0x18:	/* SYS_DMA_CPC_CH0 or DMA_CSAC */
> -        OMAP_RO_REG((target_phys_addr_t) reg);
> +        OMAP_RO_REG((hwaddr) reg);
>          break;
>  
>      case 0x1c:	/* DMA_CDEI */
> @@ -1446,7 +1446,7 @@ static int omap_dma_sys_read(struct omap_dma_s *s, int offset,
>      return 0;
>  }
>  
> -static uint64_t omap_dma_read(void *opaque, target_phys_addr_t addr,
> +static uint64_t omap_dma_read(void *opaque, hwaddr addr,
>                                unsigned size)
>  {
>      struct omap_dma_s *s = (struct omap_dma_s *) opaque;
> @@ -1494,7 +1494,7 @@ static uint64_t omap_dma_read(void *opaque, target_phys_addr_t addr,
>      return 0;
>  }
>  
> -static void omap_dma_write(void *opaque, target_phys_addr_t addr,
> +static void omap_dma_write(void *opaque, hwaddr addr,
>                             uint64_t value, unsigned size)
>  {
>      struct omap_dma_s *s = (struct omap_dma_s *) opaque;
> @@ -1618,7 +1618,7 @@ static void omap_dma_setcaps(struct omap_dma_s *s)
>      }
>  }
>  
> -struct soc_dma_s *omap_dma_init(target_phys_addr_t base, qemu_irq *irqs,
> +struct soc_dma_s *omap_dma_init(hwaddr base, qemu_irq *irqs,
>                  MemoryRegion *sysmem,
>                  qemu_irq lcd_irq, struct omap_mpu_state_s *mpu, omap_clk clk,
>                  enum omap_dma_model model)
> @@ -1692,7 +1692,7 @@ static void omap_dma_interrupts_4_update(struct omap_dma_s *s)
>          qemu_irq_raise(s->irq[3]);
>  }
>  
> -static uint64_t omap_dma4_read(void *opaque, target_phys_addr_t addr,
> +static uint64_t omap_dma4_read(void *opaque, hwaddr addr,
>                                 unsigned size)
>  {
>      struct omap_dma_s *s = (struct omap_dma_s *) opaque;
> @@ -1842,7 +1842,7 @@ static uint64_t omap_dma4_read(void *opaque, target_phys_addr_t addr,
>      }
>  }
>  
> -static void omap_dma4_write(void *opaque, target_phys_addr_t addr,
> +static void omap_dma4_write(void *opaque, hwaddr addr,
>                              uint64_t value, unsigned size)
>  {
>      struct omap_dma_s *s = (struct omap_dma_s *) opaque;
> @@ -1988,12 +1988,12 @@ static void omap_dma4_write(void *opaque, target_phys_addr_t addr,
>          break;
>  
>      case 0x1c:	/* DMA4_CSSA */
> -        ch->addr[0] = (target_phys_addr_t) (uint32_t) value;
> +        ch->addr[0] = (hwaddr) (uint32_t) value;
>          ch->set_update = 1;
>          break;
>  
>      case 0x20:	/* DMA4_CDSA */
> -        ch->addr[1] = (target_phys_addr_t) (uint32_t) value;
> +        ch->addr[1] = (hwaddr) (uint32_t) value;
>          ch->set_update = 1;
>          break;
>  
> @@ -2040,7 +2040,7 @@ static void omap_dma4_write(void *opaque, target_phys_addr_t addr,
>      .endianness = DEVICE_NATIVE_ENDIAN,
>  };
>  
> -struct soc_dma_s *omap_dma4_init(target_phys_addr_t base, qemu_irq *irqs,
> +struct soc_dma_s *omap_dma4_init(hwaddr base, qemu_irq *irqs,
>                  MemoryRegion *sysmem,
>                  struct omap_mpu_state_s *mpu, int fifo,
>                  int chans, omap_clk iclk, omap_clk fclk)
> diff --git a/hw/omap_dss.c b/hw/omap_dss.c
> index 86ed6ea..1e83726 100644
> --- a/hw/omap_dss.c
> +++ b/hw/omap_dss.c
> @@ -60,7 +60,7 @@ struct omap_dss_s {
>              int nx;
>              int ny;
>  
> -            target_phys_addr_t addr[3];
> +            hwaddr addr[3];
>  
>              uint32_t attr;
>              uint32_t tresh;
> @@ -168,7 +168,7 @@ void omap_dss_reset(struct omap_dss_s *s)
>      omap_dispc_interrupt_update(s);
>  }
>  
> -static uint64_t omap_diss_read(void *opaque, target_phys_addr_t addr,
> +static uint64_t omap_diss_read(void *opaque, hwaddr addr,
>                                 unsigned size)
>  {
>      struct omap_dss_s *s = (struct omap_dss_s *) opaque;
> @@ -206,7 +206,7 @@ static uint64_t omap_diss_read(void *opaque, target_phys_addr_t addr,
>      return 0;
>  }
>  
> -static void omap_diss_write(void *opaque, target_phys_addr_t addr,
> +static void omap_diss_write(void *opaque, hwaddr addr,
>                              uint64_t value, unsigned size)
>  {
>      struct omap_dss_s *s = (struct omap_dss_s *) opaque;
> @@ -246,7 +246,7 @@ static void omap_diss_write(void *opaque, target_phys_addr_t addr,
>      .endianness = DEVICE_NATIVE_ENDIAN,
>  };
>  
> -static uint64_t omap_disc_read(void *opaque, target_phys_addr_t addr,
> +static uint64_t omap_disc_read(void *opaque, hwaddr addr,
>                                 unsigned size)
>  {
>      struct omap_dss_s *s = (struct omap_dss_s *) opaque;
> @@ -371,7 +371,7 @@ static uint64_t omap_disc_read(void *opaque, target_phys_addr_t addr,
>      return 0;
>  }
>  
> -static void omap_disc_write(void *opaque, target_phys_addr_t addr,
> +static void omap_disc_write(void *opaque, hwaddr addr,
>                              uint64_t value, unsigned size)
>  {
>      struct omap_dss_s *s = (struct omap_dss_s *) opaque;
> @@ -502,11 +502,11 @@ static void omap_disc_write(void *opaque, target_phys_addr_t addr,
>          s->dispc.invalidate = 1;
>          break;
>      case 0x080:	/* DISPC_GFX_BA0 */
> -        s->dispc.l[0].addr[0] = (target_phys_addr_t) value;
> +        s->dispc.l[0].addr[0] = (hwaddr) value;
>          s->dispc.invalidate = 1;
>          break;
>      case 0x084:	/* DISPC_GFX_BA1 */
> -        s->dispc.l[0].addr[1] = (target_phys_addr_t) value;
> +        s->dispc.l[0].addr[1] = (hwaddr) value;
>          s->dispc.invalidate = 1;
>          break;
>      case 0x088:	/* DISPC_GFX_POSITION */
> @@ -543,7 +543,7 @@ static void omap_disc_write(void *opaque, target_phys_addr_t addr,
>          s->dispc.l[0].wininc = value;
>          break;
>      case 0x0b8:	/* DISPC_GFX_TABLE_BA */
> -        s->dispc.l[0].addr[2] = (target_phys_addr_t) value;
> +        s->dispc.l[0].addr[2] = (hwaddr) value;
>          s->dispc.invalidate = 1;
>          break;
>  
> @@ -602,11 +602,11 @@ static void omap_rfbi_transfer_stop(struct omap_dss_s *s)
>  static void omap_rfbi_transfer_start(struct omap_dss_s *s)
>  {
>      void *data;
> -    target_phys_addr_t len;
> -    target_phys_addr_t data_addr;
> +    hwaddr len;
> +    hwaddr data_addr;
>      int pitch;
>      static void *bounce_buffer;
> -    static target_phys_addr_t bounce_len;
> +    static hwaddr bounce_len;
>  
>      if (!s->rfbi.enable || s->rfbi.busy)
>          return;
> @@ -663,7 +663,7 @@ static void omap_rfbi_transfer_start(struct omap_dss_s *s)
>      omap_dispc_interrupt_update(s);
>  }
>  
> -static uint64_t omap_rfbi_read(void *opaque, target_phys_addr_t addr,
> +static uint64_t omap_rfbi_read(void *opaque, hwaddr addr,
>                                 unsigned size)
>  {
>      struct omap_dss_s *s = (struct omap_dss_s *) opaque;
> @@ -730,7 +730,7 @@ static uint64_t omap_rfbi_read(void *opaque, target_phys_addr_t addr,
>      return 0;
>  }
>  
> -static void omap_rfbi_write(void *opaque, target_phys_addr_t addr,
> +static void omap_rfbi_write(void *opaque, hwaddr addr,
>                              uint64_t value, unsigned size)
>  {
>      struct omap_dss_s *s = (struct omap_dss_s *) opaque;
> @@ -864,7 +864,7 @@ static void omap_rfbi_write(void *opaque, target_phys_addr_t addr,
>      .endianness = DEVICE_NATIVE_ENDIAN,
>  };
>  
> -static uint64_t omap_venc_read(void *opaque, target_phys_addr_t addr,
> +static uint64_t omap_venc_read(void *opaque, hwaddr addr,
>                                 unsigned size)
>  {
>      if (size != 4) {
> @@ -924,7 +924,7 @@ static uint64_t omap_venc_read(void *opaque, target_phys_addr_t addr,
>      return 0;
>  }
>  
> -static void omap_venc_write(void *opaque, target_phys_addr_t addr,
> +static void omap_venc_write(void *opaque, hwaddr addr,
>                              uint64_t value, unsigned size)
>  {
>      if (size != 4) {
> @@ -986,7 +986,7 @@ static void omap_venc_write(void *opaque, target_phys_addr_t addr,
>      .endianness = DEVICE_NATIVE_ENDIAN,
>  };
>  
> -static uint64_t omap_im3_read(void *opaque, target_phys_addr_t addr,
> +static uint64_t omap_im3_read(void *opaque, hwaddr addr,
>                                unsigned size)
>  {
>      if (size != 4) {
> @@ -1012,7 +1012,7 @@ static uint64_t omap_im3_read(void *opaque, target_phys_addr_t addr,
>      return 0;
>  }
>  
> -static void omap_im3_write(void *opaque, target_phys_addr_t addr,
> +static void omap_im3_write(void *opaque, hwaddr addr,
>                             uint64_t value, unsigned size)
>  {
>      if (size != 4) {
> @@ -1041,7 +1041,7 @@ static void omap_im3_write(void *opaque, target_phys_addr_t addr,
>  
>  struct omap_dss_s *omap_dss_init(struct omap_target_agent_s *ta,
>                  MemoryRegion *sysmem,
> -                target_phys_addr_t l3_base,
> +                hwaddr l3_base,
>                  qemu_irq irq, qemu_irq drq,
>                  omap_clk fck1, omap_clk fck2, omap_clk ck54m,
>                  omap_clk ick1, omap_clk ick2)
> diff --git a/hw/omap_gpio.c b/hw/omap_gpio.c
> index 201ff77..2565532 100644
> --- a/hw/omap_gpio.c
> +++ b/hw/omap_gpio.c
> @@ -61,7 +61,7 @@ static void omap_gpio_set(void *opaque, int line, int level)
>      }
>  }
>  
> -static uint64_t omap_gpio_read(void *opaque, target_phys_addr_t addr,
> +static uint64_t omap_gpio_read(void *opaque, hwaddr addr,
>                                 unsigned size)
>  {
>      struct omap_gpio_s *s = (struct omap_gpio_s *) opaque;
> @@ -99,7 +99,7 @@ static uint64_t omap_gpio_read(void *opaque, target_phys_addr_t addr,
>      return 0;
>  }
>  
> -static void omap_gpio_write(void *opaque, target_phys_addr_t addr,
> +static void omap_gpio_write(void *opaque, hwaddr addr,
>                              uint64_t value, unsigned size)
>  {
>      struct omap_gpio_s *s = (struct omap_gpio_s *) opaque;
> @@ -300,7 +300,7 @@ static void omap2_gpio_module_reset(struct omap2_gpio_s *s)
>      s->delay = 0;
>  }
>  
> -static uint32_t omap2_gpio_module_read(void *opaque, target_phys_addr_t addr)
> +static uint32_t omap2_gpio_module_read(void *opaque, hwaddr addr)
>  {
>      struct omap2_gpio_s *s = (struct omap2_gpio_s *) opaque;
>  
> @@ -372,7 +372,7 @@ static uint32_t omap2_gpio_module_read(void *opaque, target_phys_addr_t addr)
>      return 0;
>  }
>  
> -static void omap2_gpio_module_write(void *opaque, target_phys_addr_t addr,
> +static void omap2_gpio_module_write(void *opaque, hwaddr addr,
>                  uint32_t value)
>  {
>      struct omap2_gpio_s *s = (struct omap2_gpio_s *) opaque;
> @@ -514,12 +514,12 @@ static void omap2_gpio_module_write(void *opaque, target_phys_addr_t addr,
>      }
>  }
>  
> -static uint32_t omap2_gpio_module_readp(void *opaque, target_phys_addr_t addr)
> +static uint32_t omap2_gpio_module_readp(void *opaque, hwaddr addr)
>  {
>      return omap2_gpio_module_read(opaque, addr & ~3) >> ((addr & 3) << 3);
>  }
>  
> -static void omap2_gpio_module_writep(void *opaque, target_phys_addr_t addr,
> +static void omap2_gpio_module_writep(void *opaque, hwaddr addr,
>                  uint32_t value)
>  {
>      uint32_t cur = 0;
> @@ -604,7 +604,7 @@ static void omap2_gpif_reset(DeviceState *dev)
>      s->gpo = 0;
>  }
>  
> -static uint64_t omap2_gpif_top_read(void *opaque, target_phys_addr_t addr,
> +static uint64_t omap2_gpif_top_read(void *opaque, hwaddr addr,
>                                      unsigned size)
>  {
>      struct omap2_gpif_s *s = (struct omap2_gpif_s *) opaque;
> @@ -633,7 +633,7 @@ static uint64_t omap2_gpif_top_read(void *opaque, target_phys_addr_t addr,
>      return 0;
>  }
>  
> -static void omap2_gpif_top_write(void *opaque, target_phys_addr_t addr,
> +static void omap2_gpif_top_write(void *opaque, hwaddr addr,
>                                   uint64_t value, unsigned size)
>  {
>      struct omap2_gpif_s *s = (struct omap2_gpif_s *) opaque;
> diff --git a/hw/omap_gpmc.c b/hw/omap_gpmc.c
> index 2fc4137..1f7c5bc 100644
> --- a/hw/omap_gpmc.c
> +++ b/hw/omap_gpmc.c
> @@ -121,7 +121,7 @@ static void omap_gpmc_dma_update(struct omap_gpmc_s *s, int value)
>   * all addresses in the region behave like accesses to the relevant
>   * GPMC_NAND_DATA_i register (which is actually implemented to call these)
>   */
> -static uint64_t omap_nand_read(void *opaque, target_phys_addr_t addr,
> +static uint64_t omap_nand_read(void *opaque, hwaddr addr,
>                                 unsigned size)
>  {
>      struct omap_gpmc_cs_file_s *f = (struct omap_gpmc_cs_file_s *)opaque;
> @@ -200,7 +200,7 @@ static void omap_nand_setio(DeviceState *dev, uint64_t value,
>      }
>  }
>  
> -static void omap_nand_write(void *opaque, target_phys_addr_t addr,
> +static void omap_nand_write(void *opaque, hwaddr addr,
>                              uint64_t value, unsigned size)
>  {
>      struct omap_gpmc_cs_file_s *f = (struct omap_gpmc_cs_file_s *)opaque;
> @@ -281,7 +281,7 @@ static void fill_prefetch_fifo(struct omap_gpmc_s *s)
>   * engine is enabled -- all addresses in the region behave alike:
>   * data is read or written to the FIFO.
>   */
> -static uint64_t omap_gpmc_prefetch_read(void *opaque, target_phys_addr_t addr,
> +static uint64_t omap_gpmc_prefetch_read(void *opaque, hwaddr addr,
>                                          unsigned size)
>  {
>      struct omap_gpmc_s *s = (struct omap_gpmc_s *) opaque;
> @@ -311,7 +311,7 @@ static uint64_t omap_gpmc_prefetch_read(void *opaque, target_phys_addr_t addr,
>      return data;
>  }
>  
> -static void omap_gpmc_prefetch_write(void *opaque, target_phys_addr_t addr,
> +static void omap_gpmc_prefetch_write(void *opaque, hwaddr addr,
>                                       uint64_t value, unsigned size)
>  {
>      struct omap_gpmc_s *s = (struct omap_gpmc_s *) opaque;
> @@ -484,7 +484,7 @@ void omap_gpmc_reset(struct omap_gpmc_s *s)
>          ecc_reset(&s->ecc[i]);
>  }
>  
> -static int gpmc_wordaccess_only(target_phys_addr_t addr)
> +static int gpmc_wordaccess_only(hwaddr addr)
>  {
>      /* Return true if the register offset is to a register that
>       * only permits word width accesses.
> @@ -502,7 +502,7 @@ static int gpmc_wordaccess_only(target_phys_addr_t addr)
>      return 1;
>  }
>  
> -static uint64_t omap_gpmc_read(void *opaque, target_phys_addr_t addr,
> +static uint64_t omap_gpmc_read(void *opaque, hwaddr addr,
>                                 unsigned size)
>  {
>      struct omap_gpmc_s *s = (struct omap_gpmc_s *) opaque;
> @@ -614,7 +614,7 @@ static uint64_t omap_gpmc_read(void *opaque, target_phys_addr_t addr,
>      return 0;
>  }
>  
> -static void omap_gpmc_write(void *opaque, target_phys_addr_t addr,
> +static void omap_gpmc_write(void *opaque, hwaddr addr,
>                              uint64_t value, unsigned size)
>  {
>      struct omap_gpmc_s *s = (struct omap_gpmc_s *) opaque;
> @@ -819,7 +819,7 @@ static void omap_gpmc_write(void *opaque, target_phys_addr_t addr,
>  };
>  
>  struct omap_gpmc_s *omap_gpmc_init(struct omap_mpu_state_s *mpu,
> -                                   target_phys_addr_t base,
> +                                   hwaddr base,
>                                     qemu_irq irq, qemu_irq drq)
>  {
>      int cs;
> diff --git a/hw/omap_gptimer.c b/hw/omap_gptimer.c
> index 7a14519..e39da74 100644
> --- a/hw/omap_gptimer.c
> +++ b/hw/omap_gptimer.c
> @@ -258,7 +258,7 @@ void omap_gp_timer_reset(struct omap_gp_timer_s *s)
>      omap_gp_timer_update(s);
>  }
>  
> -static uint32_t omap_gp_timer_readw(void *opaque, target_phys_addr_t addr)
> +static uint32_t omap_gp_timer_readw(void *opaque, hwaddr addr)
>  {
>      struct omap_gp_timer_s *s = (struct omap_gp_timer_s *) opaque;
>  
> @@ -324,7 +324,7 @@ static uint32_t omap_gp_timer_readw(void *opaque, target_phys_addr_t addr)
>      return 0;
>  }
>  
> -static uint32_t omap_gp_timer_readh(void *opaque, target_phys_addr_t addr)
> +static uint32_t omap_gp_timer_readh(void *opaque, hwaddr addr)
>  {
>      struct omap_gp_timer_s *s = (struct omap_gp_timer_s *) opaque;
>      uint32_t ret;
> @@ -338,7 +338,7 @@ static uint32_t omap_gp_timer_readh(void *opaque, target_phys_addr_t addr)
>      }
>  }
>  
> -static void omap_gp_timer_write(void *opaque, target_phys_addr_t addr,
> +static void omap_gp_timer_write(void *opaque, hwaddr addr,
>                  uint32_t value)
>  {
>      struct omap_gp_timer_s *s = (struct omap_gp_timer_s *) opaque;
> @@ -438,7 +438,7 @@ static void omap_gp_timer_write(void *opaque, target_phys_addr_t addr,
>      }
>  }
>  
> -static void omap_gp_timer_writeh(void *opaque, target_phys_addr_t addr,
> +static void omap_gp_timer_writeh(void *opaque, hwaddr addr,
>                  uint32_t value)
>  {
>      struct omap_gp_timer_s *s = (struct omap_gp_timer_s *) opaque;
> diff --git a/hw/omap_i2c.c b/hw/omap_i2c.c
> index 20bc82e..ba08e64 100644
> --- a/hw/omap_i2c.c
> +++ b/hw/omap_i2c.c
> @@ -149,7 +149,7 @@ static void omap_i2c_reset(DeviceState *dev)
>      s->test = 0;
>  }
>  
> -static uint32_t omap_i2c_read(void *opaque, target_phys_addr_t addr)
> +static uint32_t omap_i2c_read(void *opaque, hwaddr addr)
>  {
>      OMAPI2CState *s = opaque;
>      int offset = addr & OMAP_MPUI_REG_MASK;
> @@ -248,7 +248,7 @@ static uint32_t omap_i2c_read(void *opaque, target_phys_addr_t addr)
>      return 0;
>  }
>  
> -static void omap_i2c_write(void *opaque, target_phys_addr_t addr,
> +static void omap_i2c_write(void *opaque, hwaddr addr,
>                  uint32_t value)
>  {
>      OMAPI2CState *s = opaque;
> @@ -390,7 +390,7 @@ static void omap_i2c_write(void *opaque, target_phys_addr_t addr,
>      }
>  }
>  
> -static void omap_i2c_writeb(void *opaque, target_phys_addr_t addr,
> +static void omap_i2c_writeb(void *opaque, hwaddr addr,
>                  uint32_t value)
>  {
>      OMAPI2CState *s = opaque;
> diff --git a/hw/omap_intc.c b/hw/omap_intc.c
> index 5076e07..61e0daf 100644
> --- a/hw/omap_intc.c
> +++ b/hw/omap_intc.c
> @@ -145,7 +145,7 @@ static void omap_set_intr_noedge(void *opaque, int irq, int req)
>          bank->irqs = (bank->inputs &= ~(1 << n)) | bank->swi;
>  }
>  
> -static uint64_t omap_inth_read(void *opaque, target_phys_addr_t addr,
> +static uint64_t omap_inth_read(void *opaque, hwaddr addr,
>                                 unsigned size)
>  {
>      struct omap_intr_handler_s *s = (struct omap_intr_handler_s *) opaque;
> @@ -223,7 +223,7 @@ static uint64_t omap_inth_read(void *opaque, target_phys_addr_t addr,
>      return 0;
>  }
>  
> -static void omap_inth_write(void *opaque, target_phys_addr_t addr,
> +static void omap_inth_write(void *opaque, hwaddr addr,
>                              uint64_t value, unsigned size)
>  {
>      struct omap_intr_handler_s *s = (struct omap_intr_handler_s *) opaque;
> @@ -396,7 +396,7 @@ static void omap_intc_class_init(ObjectClass *klass, void *data)
>      .class_init    = omap_intc_class_init,
>  };
>  
> -static uint64_t omap2_inth_read(void *opaque, target_phys_addr_t addr,
> +static uint64_t omap2_inth_read(void *opaque, hwaddr addr,
>                                  unsigned size)
>  {
>      struct omap_intr_handler_s *s = (struct omap_intr_handler_s *) opaque;
> @@ -477,7 +477,7 @@ static uint64_t omap2_inth_read(void *opaque, target_phys_addr_t addr,
>      return 0;
>  }
>  
> -static void omap2_inth_write(void *opaque, target_phys_addr_t addr,
> +static void omap2_inth_write(void *opaque, hwaddr addr,
>                               uint64_t value, unsigned size)
>  {
>      struct omap_intr_handler_s *s = (struct omap_intr_handler_s *) opaque;
> diff --git a/hw/omap_l4.c b/hw/omap_l4.c
> index dbad7f6..09e983f 100644
> --- a/hw/omap_l4.c
> +++ b/hw/omap_l4.c
> @@ -22,13 +22,13 @@
>  
>  struct omap_l4_s {
>      MemoryRegion *address_space;
> -    target_phys_addr_t base;
> +    hwaddr base;
>      int ta_num;
>      struct omap_target_agent_s ta[0];
>  };
>  
>  struct omap_l4_s *omap_l4_init(MemoryRegion *address_space,
> -                               target_phys_addr_t base, int ta_num)
> +                               hwaddr base, int ta_num)
>  {
>      struct omap_l4_s *bus = g_malloc0(
>                      sizeof(*bus) + ta_num * sizeof(*bus->ta));
> @@ -40,19 +40,19 @@ struct omap_l4_s *omap_l4_init(MemoryRegion *address_space,
>      return bus;
>  }
>  
> -target_phys_addr_t omap_l4_region_base(struct omap_target_agent_s *ta,
> +hwaddr omap_l4_region_base(struct omap_target_agent_s *ta,
>                                         int region)
>  {
>      return ta->bus->base + ta->start[region].offset;
>  }
>  
> -target_phys_addr_t omap_l4_region_size(struct omap_target_agent_s *ta,
> +hwaddr omap_l4_region_size(struct omap_target_agent_s *ta,
>                                         int region)
>  {
>      return ta->start[region].size;
>  }
>  
> -static uint64_t omap_l4ta_read(void *opaque, target_phys_addr_t addr,
> +static uint64_t omap_l4ta_read(void *opaque, hwaddr addr,
>                                 unsigned size)
>  {
>      struct omap_target_agent_s *s = (struct omap_target_agent_s *) opaque;
> @@ -76,7 +76,7 @@ static uint64_t omap_l4ta_read(void *opaque, target_phys_addr_t addr,
>      return 0;
>  }
>  
> -static void omap_l4ta_write(void *opaque, target_phys_addr_t addr,
> +static void omap_l4ta_write(void *opaque, hwaddr addr,
>                              uint64_t value, unsigned size)
>  {
>      struct omap_target_agent_s *s = (struct omap_target_agent_s *) opaque;
> @@ -143,10 +143,10 @@ struct omap_target_agent_s *omap_l4ta_get(struct omap_l4_s *bus,
>      return ta;
>  }
>  
> -target_phys_addr_t omap_l4_attach(struct omap_target_agent_s *ta,
> +hwaddr omap_l4_attach(struct omap_target_agent_s *ta,
>                                           int region, MemoryRegion *mr)
>  {
> -    target_phys_addr_t base;
> +    hwaddr base;
>  
>      if (region < 0 || region >= ta->regions) {
>          fprintf(stderr, "%s: bad io region (%i)\n", __FUNCTION__, region);
> diff --git a/hw/omap_lcdc.c b/hw/omap_lcdc.c
> index e2ba108..bf177c2 100644
> --- a/hw/omap_lcdc.c
> +++ b/hw/omap_lcdc.c
> @@ -117,7 +117,7 @@ static void omap_update_display(void *opaque)
>      draw_line_func draw_line;
>      int size, height, first, last;
>      int width, linesize, step, bpp, frame_offset;
> -    target_phys_addr_t frame_base;
> +    hwaddr frame_base;
>  
>      if (!omap_lcd || omap_lcd->plm == 1 ||
>                      !omap_lcd->enable || !ds_get_bits_per_pixel(omap_lcd->state))
> @@ -359,7 +359,7 @@ static void omap_lcd_update(struct omap_lcd_panel_s *s) {
>      }
>  }
>  
> -static uint64_t omap_lcdc_read(void *opaque, target_phys_addr_t addr,
> +static uint64_t omap_lcdc_read(void *opaque, hwaddr addr,
>                                 unsigned size)
>  {
>      struct omap_lcd_panel_s *s = (struct omap_lcd_panel_s *) opaque;
> @@ -392,7 +392,7 @@ static uint64_t omap_lcdc_read(void *opaque, target_phys_addr_t addr,
>      return 0;
>  }
>  
> -static void omap_lcdc_write(void *opaque, target_phys_addr_t addr,
> +static void omap_lcdc_write(void *opaque, hwaddr addr,
>                              uint64_t value, unsigned size)
>  {
>      struct omap_lcd_panel_s *s = (struct omap_lcd_panel_s *) opaque;
> @@ -465,7 +465,7 @@ void omap_lcdc_reset(struct omap_lcd_panel_s *s)
>  }
>  
>  struct omap_lcd_panel_s *omap_lcdc_init(MemoryRegion *sysmem,
> -                                        target_phys_addr_t base,
> +                                        hwaddr base,
>                                          qemu_irq irq,
>                                          struct omap_dma_lcd_channel_s *dma,
>                                          omap_clk clk)
> diff --git a/hw/omap_mmc.c b/hw/omap_mmc.c
> index aec0285..7ecd9bd 100644
> --- a/hw/omap_mmc.c
> +++ b/hw/omap_mmc.c
> @@ -306,7 +306,7 @@ void omap_mmc_reset(struct omap_mmc_s *host)
>      host->clkdiv = 0;
>  }
>  
> -static uint64_t omap_mmc_read(void *opaque, target_phys_addr_t offset,
> +static uint64_t omap_mmc_read(void *opaque, hwaddr offset,
>                                unsigned size)
>  {
>      uint16_t i;
> @@ -399,7 +399,7 @@ static uint64_t omap_mmc_read(void *opaque, target_phys_addr_t offset,
>      return 0;
>  }
>  
> -static void omap_mmc_write(void *opaque, target_phys_addr_t offset,
> +static void omap_mmc_write(void *opaque, hwaddr offset,
>                             uint64_t value, unsigned size)
>  {
>      int i;
> @@ -572,7 +572,7 @@ static void omap_mmc_cover_cb(void *opaque, int line, int level)
>      }
>  }
>  
> -struct omap_mmc_s *omap_mmc_init(target_phys_addr_t base,
> +struct omap_mmc_s *omap_mmc_init(hwaddr base,
>                  MemoryRegion *sysmem,
>                  BlockDriverState *bd,
>                  qemu_irq irq, qemu_irq dma[], omap_clk clk)
> diff --git a/hw/omap_sdrc.c b/hw/omap_sdrc.c
> index 784e326..b0f3b8e 100644
> --- a/hw/omap_sdrc.c
> +++ b/hw/omap_sdrc.c
> @@ -31,7 +31,7 @@ void omap_sdrc_reset(struct omap_sdrc_s *s)
>      s->config = 0x10;
>  }
>  
> -static uint64_t omap_sdrc_read(void *opaque, target_phys_addr_t addr,
> +static uint64_t omap_sdrc_read(void *opaque, hwaddr addr,
>                                 unsigned size)
>  {
>      struct omap_sdrc_s *s = (struct omap_sdrc_s *) opaque;
> @@ -86,7 +86,7 @@ static uint64_t omap_sdrc_read(void *opaque, target_phys_addr_t addr,
>      return 0;
>  }
>  
> -static void omap_sdrc_write(void *opaque, target_phys_addr_t addr,
> +static void omap_sdrc_write(void *opaque, hwaddr addr,
>                              uint64_t value, unsigned size)
>  {
>      struct omap_sdrc_s *s = (struct omap_sdrc_s *) opaque;
> @@ -154,7 +154,7 @@ static void omap_sdrc_write(void *opaque, target_phys_addr_t addr,
>  };
>  
>  struct omap_sdrc_s *omap_sdrc_init(MemoryRegion *sysmem,
> -                                   target_phys_addr_t base)
> +                                   hwaddr base)
>  {
>      struct omap_sdrc_s *s = (struct omap_sdrc_s *)
>              g_malloc0(sizeof(struct omap_sdrc_s));
> diff --git a/hw/omap_spi.c b/hw/omap_spi.c
> index 8f2b697..42d5149 100644
> --- a/hw/omap_spi.c
> +++ b/hw/omap_spi.c
> @@ -130,7 +130,7 @@ void omap_mcspi_reset(struct omap_mcspi_s *s)
>      omap_mcspi_interrupt_update(s);
>  }
>  
> -static uint64_t omap_mcspi_read(void *opaque, target_phys_addr_t addr,
> +static uint64_t omap_mcspi_read(void *opaque, hwaddr addr,
>                                  unsigned size)
>  {
>      struct omap_mcspi_s *s = (struct omap_mcspi_s *) opaque;
> @@ -204,7 +204,7 @@ static uint64_t omap_mcspi_read(void *opaque, target_phys_addr_t addr,
>      return 0;
>  }
>  
> -static void omap_mcspi_write(void *opaque, target_phys_addr_t addr,
> +static void omap_mcspi_write(void *opaque, hwaddr addr,
>                               uint64_t value, unsigned size)
>  {
>      struct omap_mcspi_s *s = (struct omap_mcspi_s *) opaque;
> diff --git a/hw/omap_sx1.c b/hw/omap_sx1.c
> index ad17487..eb2bf05 100644
> --- a/hw/omap_sx1.c
> +++ b/hw/omap_sx1.c
> @@ -59,7 +59,7 @@
>   * - 1 RTC
>   */
>  
> -static uint64_t static_read(void *opaque, target_phys_addr_t offset,
> +static uint64_t static_read(void *opaque, hwaddr offset,
>                              unsigned size)
>  {
>      uint32_t *val = (uint32_t *) opaque;
> @@ -68,7 +68,7 @@ static uint64_t static_read(void *opaque, target_phys_addr_t offset,
>      return *val >> ((offset & mask) << 3);
>  }
>  
> -static void static_write(void *opaque, target_phys_addr_t offset,
> +static void static_write(void *opaque, hwaddr offset,
>                           uint64_t value, unsigned size)
>  {
>  #ifdef SPY
> diff --git a/hw/omap_synctimer.c b/hw/omap_synctimer.c
> index 367f26e..7031a88 100644
> --- a/hw/omap_synctimer.c
> +++ b/hw/omap_synctimer.c
> @@ -36,7 +36,7 @@ void omap_synctimer_reset(struct omap_synctimer_s *s)
>      s->val = omap_synctimer_read(s);
>  }
>  
> -static uint32_t omap_synctimer_readw(void *opaque, target_phys_addr_t addr)
> +static uint32_t omap_synctimer_readw(void *opaque, hwaddr addr)
>  {
>      struct omap_synctimer_s *s = (struct omap_synctimer_s *) opaque;
>  
> @@ -52,7 +52,7 @@ static uint32_t omap_synctimer_readw(void *opaque, target_phys_addr_t addr)
>      return 0;
>  }
>  
> -static uint32_t omap_synctimer_readh(void *opaque, target_phys_addr_t addr)
> +static uint32_t omap_synctimer_readh(void *opaque, hwaddr addr)
>  {
>      struct omap_synctimer_s *s = (struct omap_synctimer_s *) opaque;
>      uint32_t ret;
> @@ -66,7 +66,7 @@ static uint32_t omap_synctimer_readh(void *opaque, target_phys_addr_t addr)
>      }
>  }
>  
> -static void omap_synctimer_write(void *opaque, target_phys_addr_t addr,
> +static void omap_synctimer_write(void *opaque, hwaddr addr,
>                  uint32_t value)
>  {
>      OMAP_BAD_REG(addr);
> diff --git a/hw/omap_tap.c b/hw/omap_tap.c
> index 0277c73..e273e97 100644
> --- a/hw/omap_tap.c
> +++ b/hw/omap_tap.c
> @@ -22,7 +22,7 @@
>  #include "omap.h"
>  
>  /* TEST-Chip-level TAP */
> -static uint64_t omap_tap_read(void *opaque, target_phys_addr_t addr,
> +static uint64_t omap_tap_read(void *opaque, hwaddr addr,
>                                unsigned size)
>  {
>      struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
> @@ -91,7 +91,7 @@ static uint64_t omap_tap_read(void *opaque, target_phys_addr_t addr,
>      return 0;
>  }
>  
> -static void omap_tap_write(void *opaque, target_phys_addr_t addr,
> +static void omap_tap_write(void *opaque, hwaddr addr,
>                             uint64_t value, unsigned size)
>  {
>      if (size != 4) {
> diff --git a/hw/omap_uart.c b/hw/omap_uart.c
> index 1c16a54..92f2702 100644
> --- a/hw/omap_uart.c
> +++ b/hw/omap_uart.c
> @@ -26,7 +26,7 @@
>  /* UARTs */
>  struct omap_uart_s {
>      MemoryRegion iomem;
> -    target_phys_addr_t base;
> +    hwaddr base;
>      SerialState *serial; /* TODO */
>      struct omap_target_agent_s *ta;
>      omap_clk fclk;
> @@ -50,7 +50,7 @@ void omap_uart_reset(struct omap_uart_s *s)
>      s->clksel = 0;
>  }
>  
> -struct omap_uart_s *omap_uart_init(target_phys_addr_t base,
> +struct omap_uart_s *omap_uart_init(hwaddr base,
>                  qemu_irq irq, omap_clk fclk, omap_clk iclk,
>                  qemu_irq txdma, qemu_irq rxdma,
>                  const char *label, CharDriverState *chr)
> @@ -68,7 +68,7 @@ struct omap_uart_s *omap_uart_init(target_phys_addr_t base,
>      return s;
>  }
>  
> -static uint64_t omap_uart_read(void *opaque, target_phys_addr_t addr,
> +static uint64_t omap_uart_read(void *opaque, hwaddr addr,
>                                 unsigned size)
>  {
>      struct omap_uart_s *s = (struct omap_uart_s *) opaque;
> @@ -106,7 +106,7 @@ static uint64_t omap_uart_read(void *opaque, target_phys_addr_t addr,
>      return 0;
>  }
>  
> -static void omap_uart_write(void *opaque, target_phys_addr_t addr,
> +static void omap_uart_write(void *opaque, hwaddr addr,
>                              uint64_t value, unsigned size)
>  {
>      struct omap_uart_s *s = (struct omap_uart_s *) opaque;
> @@ -164,7 +164,7 @@ struct omap_uart_s *omap2_uart_init(MemoryRegion *sysmem,
>                  qemu_irq txdma, qemu_irq rxdma,
>                  const char *label, CharDriverState *chr)
>  {
> -    target_phys_addr_t base = omap_l4_attach(ta, 0, NULL);
> +    hwaddr base = omap_l4_attach(ta, 0, NULL);
>      struct omap_uart_s *s = omap_uart_init(base, irq,
>                      fclk, iclk, txdma, rxdma, label, chr);
>  
> diff --git a/hw/onenand.c b/hw/onenand.c
> index 0f7b755..1803e4c 100644
> --- a/hw/onenand.c
> +++ b/hw/onenand.c
> @@ -42,7 +42,7 @@
>          uint16_t ver;
>      } id;
>      int shift;
> -    target_phys_addr_t base;
> +    hwaddr base;
>      qemu_irq intr;
>      qemu_irq rdy;
>      BlockDriverState *bdrv;
> @@ -588,7 +588,7 @@ static void onenand_command(OneNANDState *s)
>      onenand_intr_update(s);
>  }
>  
> -static uint64_t onenand_read(void *opaque, target_phys_addr_t addr,
> +static uint64_t onenand_read(void *opaque, hwaddr addr,
>                               unsigned size)
>  {
>      OneNANDState *s = (OneNANDState *) opaque;
> @@ -653,7 +653,7 @@ static uint64_t onenand_read(void *opaque, target_phys_addr_t addr,
>      return 0;
>  }
>  
> -static void onenand_write(void *opaque, target_phys_addr_t addr,
> +static void onenand_write(void *opaque, hwaddr addr,
>                            uint64_t value, unsigned size)
>  {
>      OneNANDState *s = (OneNANDState *) opaque;
> @@ -760,7 +760,7 @@ static int onenand_initfn(SysBusDevice *dev)
>      OneNANDState *s = (OneNANDState *)dev;
>      uint32_t size = 1 << (24 + ((s->id.dev >> 4) & 7));
>      void *ram;
> -    s->base = (target_phys_addr_t)-1;
> +    s->base = (hwaddr)-1;
>      s->rdy = NULL;
>      s->blocks = size >> BLOCK_SHIFT;
>      s->secs = size >> 9;
> diff --git a/hw/opencores_eth.c b/hw/opencores_eth.c
> index 8c15969..b2780b9 100644
> --- a/hw/opencores_eth.c
> +++ b/hw/opencores_eth.c
> @@ -528,7 +528,7 @@ static void open_eth_check_start_xmit(OpenEthState *s)
>  }
>  
>  static uint64_t open_eth_reg_read(void *opaque,
> -        target_phys_addr_t addr, unsigned int size)
> +        hwaddr addr, unsigned int size)
>  {
>      static uint32_t (*reg_read[REG_MAX])(OpenEthState *s) = {
>      };
> @@ -620,7 +620,7 @@ static void open_eth_mii_tx_host_write(OpenEthState *s, uint32_t val)
>  }
>  
>  static void open_eth_reg_write(void *opaque,
> -        target_phys_addr_t addr, uint64_t val, unsigned int size)
> +        hwaddr addr, uint64_t val, unsigned int size)
>  {
>      static void (*reg_write[REG_MAX])(OpenEthState *s, uint32_t val) = {
>          [MODER] = open_eth_moder_host_write,
> @@ -644,7 +644,7 @@ static void open_eth_reg_write(void *opaque,
>  }
>  
>  static uint64_t open_eth_desc_read(void *opaque,
> -        target_phys_addr_t addr, unsigned int size)
> +        hwaddr addr, unsigned int size)
>  {
>      OpenEthState *s = opaque;
>      uint64_t v = 0;
> @@ -656,7 +656,7 @@ static uint64_t open_eth_desc_read(void *opaque,
>  }
>  
>  static void open_eth_desc_write(void *opaque,
> -        target_phys_addr_t addr, uint64_t val, unsigned int size)
> +        hwaddr addr, uint64_t val, unsigned int size)
>  {
>      OpenEthState *s = opaque;
>  
> diff --git a/hw/openpic.c b/hw/openpic.c
> index b9d8568..8b3784a 100644
> --- a/hw/openpic.c
> +++ b/hw/openpic.c
> @@ -178,9 +178,9 @@ static int get_current_cpu(void)
>    return cpu_single_env->cpu_index;
>  }
>  
> -static uint32_t openpic_cpu_read_internal(void *opaque, target_phys_addr_t addr,
> +static uint32_t openpic_cpu_read_internal(void *opaque, hwaddr addr,
>                                            int idx);
> -static void openpic_cpu_write_internal(void *opaque, target_phys_addr_t addr,
> +static void openpic_cpu_write_internal(void *opaque, hwaddr addr,
>                                         uint32_t val, int idx);
>  
>  enum {
> @@ -596,7 +596,7 @@ static void write_mailbox_register (openpic_t *opp, int n_mbx,
>  #endif
>  #endif /* 0 : Code provision for Intel model */
>  
> -static void openpic_gbl_write (void *opaque, target_phys_addr_t addr, uint32_t val)
> +static void openpic_gbl_write (void *opaque, hwaddr addr, uint32_t val)
>  {
>      openpic_t *opp = opaque;
>      IRQ_dst_t *dst;
> @@ -662,7 +662,7 @@ static void openpic_gbl_write (void *opaque, target_phys_addr_t addr, uint32_t v
>      }
>  }
>  
> -static uint32_t openpic_gbl_read (void *opaque, target_phys_addr_t addr)
> +static uint32_t openpic_gbl_read (void *opaque, hwaddr addr)
>  {
>      openpic_t *opp = opaque;
>      uint32_t retval;
> @@ -826,7 +826,7 @@ static uint32_t openpic_src_read (void *opaque, uint32_t addr)
>      return retval;
>  }
>  
> -static void openpic_cpu_write_internal(void *opaque, target_phys_addr_t addr,
> +static void openpic_cpu_write_internal(void *opaque, hwaddr addr,
>                                         uint32_t val, int idx)
>  {
>      openpic_t *opp = opaque;
> @@ -886,12 +886,12 @@ static void openpic_cpu_write_internal(void *opaque, target_phys_addr_t addr,
>      }
>  }
>  
> -static void openpic_cpu_write(void *opaque, target_phys_addr_t addr, uint32_t val)
> +static void openpic_cpu_write(void *opaque, hwaddr addr, uint32_t val)
>  {
>      openpic_cpu_write_internal(opaque, addr, val, (addr & 0x1f000) >> 12);
>  }
>  
> -static uint32_t openpic_cpu_read_internal(void *opaque, target_phys_addr_t addr,
> +static uint32_t openpic_cpu_read_internal(void *opaque, hwaddr addr,
>                                            int idx)
>  {
>      openpic_t *opp = opaque;
> @@ -970,18 +970,18 @@ static uint32_t openpic_cpu_read_internal(void *opaque, target_phys_addr_t addr,
>      return retval;
>  }
>  
> -static uint32_t openpic_cpu_read(void *opaque, target_phys_addr_t addr)
> +static uint32_t openpic_cpu_read(void *opaque, hwaddr addr)
>  {
>      return openpic_cpu_read_internal(opaque, addr, (addr & 0x1f000) >> 12);
>  }
>  
>  static void openpic_buggy_write (void *opaque,
> -                                 target_phys_addr_t addr, uint32_t val)
> +                                 hwaddr addr, uint32_t val)
>  {
>      printf("Invalid OPENPIC write access !\n");
>  }
>  
> -static uint32_t openpic_buggy_read (void *opaque, target_phys_addr_t addr)
> +static uint32_t openpic_buggy_read (void *opaque, hwaddr addr)
>  {
>      printf("Invalid OPENPIC read access !\n");
>  
> @@ -989,7 +989,7 @@ static uint32_t openpic_buggy_read (void *opaque, target_phys_addr_t addr)
>  }
>  
>  static void openpic_writel (void *opaque,
> -                            target_phys_addr_t addr, uint32_t val)
> +                            hwaddr addr, uint32_t val)
>  {
>      openpic_t *opp = opaque;
>  
> @@ -1010,7 +1010,7 @@ static void openpic_writel (void *opaque,
>      }
>  }
>  
> -static uint32_t openpic_readl (void *opaque,target_phys_addr_t addr)
> +static uint32_t openpic_readl (void *opaque,hwaddr addr)
>  {
>      openpic_t *opp = opaque;
>      uint32_t retval;
> @@ -1034,7 +1034,7 @@ static uint32_t openpic_readl (void *opaque,target_phys_addr_t addr)
>      return retval;
>  }
>  
> -static uint64_t openpic_read(void *opaque, target_phys_addr_t addr,
> +static uint64_t openpic_read(void *opaque, hwaddr addr,
>                               unsigned size)
>  {
>      openpic_t *opp = opaque;
> @@ -1045,7 +1045,7 @@ static uint64_t openpic_read(void *opaque, target_phys_addr_t addr,
>      }
>  }
>  
> -static void openpic_write(void *opaque, target_phys_addr_t addr,
> +static void openpic_write(void *opaque, hwaddr addr,
>                            uint64_t data, unsigned size)
>  {
>      openpic_t *opp = opaque;
> @@ -1300,7 +1300,7 @@ static void mpic_reset (void *opaque)
>      mpp->glbc = 0x00000000;
>  }
>  
> -static void mpic_timer_write (void *opaque, target_phys_addr_t addr, uint32_t val)
> +static void mpic_timer_write (void *opaque, hwaddr addr, uint32_t val)
>  {
>      openpic_t *mpp = opaque;
>      int idx, cpu;
> @@ -1333,7 +1333,7 @@ static void mpic_timer_write (void *opaque, target_phys_addr_t addr, uint32_t va
>      }
>  }
>  
> -static uint32_t mpic_timer_read (void *opaque, target_phys_addr_t addr)
> +static uint32_t mpic_timer_read (void *opaque, hwaddr addr)
>  {
>      openpic_t *mpp = opaque;
>      uint32_t retval;
> @@ -1368,7 +1368,7 @@ static uint32_t mpic_timer_read (void *opaque, target_phys_addr_t addr)
>      return retval;
>  }
>  
> -static void mpic_src_ext_write (void *opaque, target_phys_addr_t addr,
> +static void mpic_src_ext_write (void *opaque, hwaddr addr,
>                                  uint32_t val)
>  {
>      openpic_t *mpp = opaque;
> @@ -1390,7 +1390,7 @@ static void mpic_src_ext_write (void *opaque, target_phys_addr_t addr,
>      }
>  }
>  
> -static uint32_t mpic_src_ext_read (void *opaque, target_phys_addr_t addr)
> +static uint32_t mpic_src_ext_read (void *opaque, hwaddr addr)
>  {
>      openpic_t *mpp = opaque;
>      uint32_t retval;
> @@ -1416,7 +1416,7 @@ static uint32_t mpic_src_ext_read (void *opaque, target_phys_addr_t addr)
>      return retval;
>  }
>  
> -static void mpic_src_int_write (void *opaque, target_phys_addr_t addr,
> +static void mpic_src_int_write (void *opaque, hwaddr addr,
>                                  uint32_t val)
>  {
>      openpic_t *mpp = opaque;
> @@ -1438,7 +1438,7 @@ static void mpic_src_int_write (void *opaque, target_phys_addr_t addr,
>      }
>  }
>  
> -static uint32_t mpic_src_int_read (void *opaque, target_phys_addr_t addr)
> +static uint32_t mpic_src_int_read (void *opaque, hwaddr addr)
>  {
>      openpic_t *mpp = opaque;
>      uint32_t retval;
> @@ -1464,7 +1464,7 @@ static uint32_t mpic_src_int_read (void *opaque, target_phys_addr_t addr)
>      return retval;
>  }
>  
> -static void mpic_src_msg_write (void *opaque, target_phys_addr_t addr,
> +static void mpic_src_msg_write (void *opaque, hwaddr addr,
>                                  uint32_t val)
>  {
>      openpic_t *mpp = opaque;
> @@ -1486,7 +1486,7 @@ static void mpic_src_msg_write (void *opaque, target_phys_addr_t addr,
>      }
>  }
>  
> -static uint32_t mpic_src_msg_read (void *opaque, target_phys_addr_t addr)
> +static uint32_t mpic_src_msg_read (void *opaque, hwaddr addr)
>  {
>      openpic_t *mpp = opaque;
>      uint32_t retval;
> @@ -1512,7 +1512,7 @@ static uint32_t mpic_src_msg_read (void *opaque, target_phys_addr_t addr)
>      return retval;
>  }
>  
> -static void mpic_src_msi_write (void *opaque, target_phys_addr_t addr,
> +static void mpic_src_msi_write (void *opaque, hwaddr addr,
>                                  uint32_t val)
>  {
>      openpic_t *mpp = opaque;
> @@ -1533,7 +1533,7 @@ static void mpic_src_msi_write (void *opaque, target_phys_addr_t addr,
>          }
>      }
>  }
> -static uint32_t mpic_src_msi_read (void *opaque, target_phys_addr_t addr)
> +static uint32_t mpic_src_msi_read (void *opaque, hwaddr addr)
>  {
>      openpic_t *mpp = opaque;
>      uint32_t retval;
> @@ -1657,7 +1657,7 @@ static uint32_t mpic_src_msi_read (void *opaque, target_phys_addr_t addr)
>      .endianness = DEVICE_BIG_ENDIAN,
>  };
>  
> -qemu_irq *mpic_init (MemoryRegion *address_space, target_phys_addr_t base,
> +qemu_irq *mpic_init (MemoryRegion *address_space, hwaddr base,
>                       int nb_cpus, qemu_irq **irqs, qemu_irq irq_out)
>  {
>      openpic_t    *mpp;
> @@ -1665,7 +1665,7 @@ qemu_irq *mpic_init (MemoryRegion *address_space, target_phys_addr_t base,
>      struct {
>          const char             *name;
>          MemoryRegionOps const  *ops;
> -        target_phys_addr_t      start_addr;
> +        hwaddr      start_addr;
>          ram_addr_t              size;
>      } const list[] = {
>          {"glb", &mpic_glb_ops, MPIC_GLB_REG_START, MPIC_GLB_REG_SIZE},
> diff --git a/hw/openpic.h b/hw/openpic.h
> index 8556030..f50a1e4 100644
> --- a/hw/openpic.h
> +++ b/hw/openpic.h
> @@ -13,6 +13,6 @@ enum {
>  
>  qemu_irq *openpic_init (MemoryRegion **pmem, int nb_cpus,
>                          qemu_irq **irqs, qemu_irq irq_out);
> -qemu_irq *mpic_init (MemoryRegion *address_space, target_phys_addr_t base,
> +qemu_irq *mpic_init (MemoryRegion *address_space, hwaddr base,
>                       int nb_cpus, qemu_irq **irqs, qemu_irq irq_out);
>  #endif /* __OPENPIC_H__ */
> diff --git a/hw/openrisc_sim.c b/hw/openrisc_sim.c
> index 7327740..23c66df 100644
> --- a/hw/openrisc_sim.c
> +++ b/hw/openrisc_sim.c
> @@ -39,8 +39,8 @@ static void main_cpu_reset(void *opaque)
>  }
>  
>  static void openrisc_sim_net_init(MemoryRegion *address_space,
> -                                  target_phys_addr_t base,
> -                                  target_phys_addr_t descriptors,
> +                                  hwaddr base,
> +                                  hwaddr descriptors,
>                                    qemu_irq irq, NICInfo *nd)
>  {
>      DeviceState *dev;
> @@ -64,7 +64,7 @@ static void cpu_openrisc_load_kernel(ram_addr_t ram_size,
>  {
>      long kernel_size;
>      uint64_t elf_entry;
> -    target_phys_addr_t entry;
> +    hwaddr entry;
>  
>      if (kernel_filename && !qtest_enabled()) {
>          kernel_size = load_elf(kernel_filename, NULL, NULL,
> diff --git a/hw/palm.c b/hw/palm.c
> index 032b8d6..d263051 100644
> --- a/hw/palm.c
> +++ b/hw/palm.c
> @@ -27,25 +27,25 @@
>  #include "loader.h"
>  #include "exec-memory.h"
>  
> -static uint32_t static_readb(void *opaque, target_phys_addr_t offset)
> +static uint32_t static_readb(void *opaque, hwaddr offset)
>  {
>      uint32_t *val = (uint32_t *) opaque;
>      return *val >> ((offset & 3) << 3);
>  }
>  
> -static uint32_t static_readh(void *opaque, target_phys_addr_t offset)
> +static uint32_t static_readh(void *opaque, hwaddr offset)
>  {
>      uint32_t *val = (uint32_t *) opaque;
>      return *val >> ((offset & 1) << 3);
>  }
>  
> -static uint32_t static_readw(void *opaque, target_phys_addr_t offset)
> +static uint32_t static_readw(void *opaque, hwaddr offset)
>  {
>      uint32_t *val = (uint32_t *) opaque;
>      return *val >> ((offset & 0) << 3);
>  }
>  
> -static void static_write(void *opaque, target_phys_addr_t offset,
> +static void static_write(void *opaque, hwaddr offset,
>                  uint32_t value)
>  {
>  #ifdef SPY
> diff --git a/hw/parallel.c b/hw/parallel.c
> index 219f384..c4705bc 100644
> --- a/hw/parallel.c
> +++ b/hw/parallel.c
> @@ -511,7 +511,7 @@ static int parallel_isa_initfn(ISADevice *dev)
>  }
>  
>  /* Memory mapped interface */
> -static uint32_t parallel_mm_readb (void *opaque, target_phys_addr_t addr)
> +static uint32_t parallel_mm_readb (void *opaque, hwaddr addr)
>  {
>      ParallelState *s = opaque;
>  
> @@ -519,14 +519,14 @@ static uint32_t parallel_mm_readb (void *opaque, target_phys_addr_t addr)
>  }
>  
>  static void parallel_mm_writeb (void *opaque,
> -                                target_phys_addr_t addr, uint32_t value)
> +                                hwaddr addr, uint32_t value)
>  {
>      ParallelState *s = opaque;
>  
>      parallel_ioport_write_sw(s, addr >> s->it_shift, value & 0xFF);
>  }
>  
> -static uint32_t parallel_mm_readw (void *opaque, target_phys_addr_t addr)
> +static uint32_t parallel_mm_readw (void *opaque, hwaddr addr)
>  {
>      ParallelState *s = opaque;
>  
> @@ -534,14 +534,14 @@ static uint32_t parallel_mm_readw (void *opaque, target_phys_addr_t addr)
>  }
>  
>  static void parallel_mm_writew (void *opaque,
> -                                target_phys_addr_t addr, uint32_t value)
> +                                hwaddr addr, uint32_t value)
>  {
>      ParallelState *s = opaque;
>  
>      parallel_ioport_write_sw(s, addr >> s->it_shift, value & 0xFFFF);
>  }
>  
> -static uint32_t parallel_mm_readl (void *opaque, target_phys_addr_t addr)
> +static uint32_t parallel_mm_readl (void *opaque, hwaddr addr)
>  {
>      ParallelState *s = opaque;
>  
> @@ -549,7 +549,7 @@ static uint32_t parallel_mm_readl (void *opaque, target_phys_addr_t addr)
>  }
>  
>  static void parallel_mm_writel (void *opaque,
> -                                target_phys_addr_t addr, uint32_t value)
> +                                hwaddr addr, uint32_t value)
>  {
>      ParallelState *s = opaque;
>  
> @@ -566,7 +566,7 @@ static void parallel_mm_writel (void *opaque,
>  
>  /* If fd is zero, it means that the parallel device uses the console */
>  bool parallel_mm_init(MemoryRegion *address_space,
> -                      target_phys_addr_t base, int it_shift, qemu_irq irq,
> +                      hwaddr base, int it_shift, qemu_irq irq,
>                        CharDriverState *chr)
>  {
>      ParallelState *s;
> diff --git a/hw/pc.c b/hw/pc.c
> index 805e8ca..16de04c 100644
> --- a/hw/pc.c
> +++ b/hw/pc.c
> @@ -638,13 +638,13 @@ static void load_linux(void *fw_cfg,
>                         const char *kernel_filename,
>  		       const char *initrd_filename,
>  		       const char *kernel_cmdline,
> -                       target_phys_addr_t max_ram_size)
> +                       hwaddr max_ram_size)
>  {
>      uint16_t protocol;
>      int setup_size, kernel_size, initrd_size = 0, cmdline_size;
>      uint32_t initrd_max;
>      uint8_t header[8192], *setup, *kernel, *initrd_data;
> -    target_phys_addr_t real_addr, prot_addr, cmdline_addr, initrd_addr = 0;
> +    hwaddr real_addr, prot_addr, cmdline_addr, initrd_addr = 0;
>      FILE *f;
>      char *vmode;
>  
> diff --git a/hw/pc.h b/hw/pc.h
> index 6cba7ce..e7993ca 100644
> --- a/hw/pc.h
> +++ b/hw/pc.h
> @@ -30,7 +30,7 @@ static inline bool parallel_init(ISABus *bus, int index, CharDriverState *chr)
>  }
>  
>  bool parallel_mm_init(MemoryRegion *address_space,
> -                      target_phys_addr_t base, int it_shift, qemu_irq irq,
> +                      hwaddr base, int it_shift, qemu_irq irq,
>                        CharDriverState *chr);
>  
>  /* i8259.c */
> @@ -68,7 +68,7 @@ void vmmouse_set_data(const uint32_t *data);
>  void i8042_init(qemu_irq kbd_irq, qemu_irq mouse_irq, uint32_t io_base);
>  void i8042_mm_init(qemu_irq kbd_irq, qemu_irq mouse_irq,
>                     MemoryRegion *region, ram_addr_t size,
> -                   target_phys_addr_t mask);
> +                   hwaddr mask);
>  void i8042_isa_mouse_fake_event(void *opaque);
>  void i8042_setup_a20_line(ISADevice *dev, qemu_irq *a20_out);
>  
> @@ -130,10 +130,10 @@ PCIBus *i440fx_init(PCII440FXState **pi440fx_state, int *piix_devfn,
>                      MemoryRegion *address_space_mem,
>                      MemoryRegion *address_space_io,
>                      ram_addr_t ram_size,
> -                    target_phys_addr_t pci_hole_start,
> -                    target_phys_addr_t pci_hole_size,
> -                    target_phys_addr_t pci_hole64_start,
> -                    target_phys_addr_t pci_hole64_size,
> +                    hwaddr pci_hole_start,
> +                    hwaddr pci_hole_size,
> +                    hwaddr pci_hole64_start,
> +                    hwaddr pci_hole64_size,
>                      MemoryRegion *pci_memory,
>                      MemoryRegion *ram_memory);
>  
> @@ -149,8 +149,8 @@ enum vga_retrace_method {
>  
>  extern enum vga_retrace_method vga_retrace_method;
>  
> -int isa_vga_mm_init(target_phys_addr_t vram_base,
> -                    target_phys_addr_t ctrl_base, int it_shift,
> +int isa_vga_mm_init(hwaddr vram_base,
> +                    hwaddr ctrl_base, int it_shift,
>                      MemoryRegion *address_space);
>  
>  /* ne2000.c */
> diff --git a/hw/pc_piix.c b/hw/pc_piix.c
> index bf04a42..47ebc1a 100644
> --- a/hw/pc_piix.c
> +++ b/hw/pc_piix.c
> @@ -195,7 +195,7 @@ static void pc_init1(MemoryRegion *system_memory,
>                                below_4g_mem_size,
>                                0x100000000ULL - below_4g_mem_size,
>                                0x100000000ULL + above_4g_mem_size,
> -                              (sizeof(target_phys_addr_t) == 4
> +                              (sizeof(hwaddr) == 4
>                                 ? 0
>                                 : ((uint64_t)1 << 62)),
>                                pci_memory, ram_memory);
> diff --git a/hw/pc_sysfw.c b/hw/pc_sysfw.c
> index b45f0ac..9d7c5f4 100644
> --- a/hw/pc_sysfw.c
> +++ b/hw/pc_sysfw.c
> @@ -106,7 +106,7 @@ static void pc_system_flash_init(MemoryRegion *rom_memory,
>  {
>      BlockDriverState *bdrv;
>      int64_t size;
> -    target_phys_addr_t phys_addr;
> +    hwaddr phys_addr;
>      int sector_bits, sector_size;
>      pflash_t *system_flash;
>      MemoryRegion *flash_mem;
> diff --git a/hw/pci.c b/hw/pci.c
> index 7eeaac0..d44fd0e 100644
> --- a/hw/pci.c
> +++ b/hw/pci.c
> @@ -987,7 +987,7 @@ static pcibus_t pci_bar_address(PCIDevice *d,
>       * to >4G. Check it. TODO: we might need to support
>       * it in the future for e.g. PAE.
>       */
> -    if (last_addr >= TARGET_PHYS_ADDR_MAX) {
> +    if (last_addr >= HWADDR_MAX) {
>          return PCI_BAR_UNMAPPED;
>      }
>  
> diff --git a/hw/pci_host.c b/hw/pci_host.c
> index 3950e94..68e328c 100644
> --- a/hw/pci_host.c
> +++ b/hw/pci_host.c
> @@ -94,7 +94,7 @@ uint32_t pci_data_read(PCIBus *s, uint32_t addr, int len)
>      return val;
>  }
>  
> -static void pci_host_config_write(void *opaque, target_phys_addr_t addr,
> +static void pci_host_config_write(void *opaque, hwaddr addr,
>                                    uint64_t val, unsigned len)
>  {
>      PCIHostState *s = opaque;
> @@ -107,7 +107,7 @@ static void pci_host_config_write(void *opaque, target_phys_addr_t addr,
>      s->config_reg = val;
>  }
>  
> -static uint64_t pci_host_config_read(void *opaque, target_phys_addr_t addr,
> +static uint64_t pci_host_config_read(void *opaque, hwaddr addr,
>                                       unsigned len)
>  {
>      PCIHostState *s = opaque;
> @@ -118,7 +118,7 @@ static uint64_t pci_host_config_read(void *opaque, target_phys_addr_t addr,
>      return val;
>  }
>  
> -static void pci_host_data_write(void *opaque, target_phys_addr_t addr,
> +static void pci_host_data_write(void *opaque, hwaddr addr,
>                                  uint64_t val, unsigned len)
>  {
>      PCIHostState *s = opaque;
> @@ -129,7 +129,7 @@ static void pci_host_data_write(void *opaque, target_phys_addr_t addr,
>  }
>  
>  static uint64_t pci_host_data_read(void *opaque,
> -                                   target_phys_addr_t addr, unsigned len)
> +                                   hwaddr addr, unsigned len)
>  {
>      PCIHostState *s = opaque;
>      uint32_t val;
> diff --git a/hw/pcie_host.c b/hw/pcie_host.c
> index 28bbe72..9f7f3d3 100644
> --- a/hw/pcie_host.c
> +++ b/hw/pcie_host.c
> @@ -53,7 +53,7 @@ static inline PCIDevice *pcie_dev_find_by_mmcfg_addr(PCIBus *s,
>                             PCIE_MMCFG_DEVFN(mmcfg_addr));
>  }
>  
> -static void pcie_mmcfg_data_write(void *opaque, target_phys_addr_t mmcfg_addr,
> +static void pcie_mmcfg_data_write(void *opaque, hwaddr mmcfg_addr,
>                                    uint64_t val, unsigned len)
>  {
>      PCIExpressHost *e = opaque;
> @@ -76,7 +76,7 @@ static void pcie_mmcfg_data_write(void *opaque, target_phys_addr_t mmcfg_addr,
>  }
>  
>  static uint64_t pcie_mmcfg_data_read(void *opaque,
> -                                     target_phys_addr_t mmcfg_addr,
> +                                     hwaddr mmcfg_addr,
>                                       unsigned len)
>  {
>      PCIExpressHost *e = opaque;
> @@ -105,7 +105,7 @@ static uint64_t pcie_mmcfg_data_read(void *opaque,
>  };
>  
>  /* pcie_host::base_addr == PCIE_BASE_ADDR_UNMAPPED when it isn't mapped. */
> -#define PCIE_BASE_ADDR_UNMAPPED  ((target_phys_addr_t)-1ULL)
> +#define PCIE_BASE_ADDR_UNMAPPED  ((hwaddr)-1ULL)
>  
>  int pcie_host_init(PCIExpressHost *e, uint32_t size)
>  {
> @@ -127,7 +127,7 @@ void pcie_host_mmcfg_unmap(PCIExpressHost *e)
>      }
>  }
>  
> -void pcie_host_mmcfg_map(PCIExpressHost *e, target_phys_addr_t addr)
> +void pcie_host_mmcfg_map(PCIExpressHost *e, hwaddr addr)
>  {
>      e->base_addr = addr;
>      memory_region_add_subregion(get_system_memory(), e->base_addr, &e->mmio);
> @@ -135,7 +135,7 @@ void pcie_host_mmcfg_map(PCIExpressHost *e, target_phys_addr_t addr)
>  
>  void pcie_host_mmcfg_update(PCIExpressHost *e,
>                              int enable,
> -                            target_phys_addr_t addr)
> +                            hwaddr addr)
>  {
>      pcie_host_mmcfg_unmap(e);
>      if (enable) {
> diff --git a/hw/pcie_host.h b/hw/pcie_host.h
> index 0074508..9978b9f 100644
> --- a/hw/pcie_host.h
> +++ b/hw/pcie_host.h
> @@ -30,10 +30,10 @@ struct PCIExpressHost {
>      /* express part */
>  
>      /* base address where MMCONFIG area is mapped. */
> -    target_phys_addr_t  base_addr;
> +    hwaddr  base_addr;
>  
>      /* the size of MMCONFIG area. It's host bridge dependent */
> -    target_phys_addr_t  size;
> +    hwaddr  size;
>  
>      /* MMCONFIG mmio area */
>      MemoryRegion mmio;
> @@ -41,9 +41,9 @@ struct PCIExpressHost {
>  
>  int pcie_host_init(PCIExpressHost *e, uint32_t size);
>  void pcie_host_mmcfg_unmap(PCIExpressHost *e);
> -void pcie_host_mmcfg_map(PCIExpressHost *e, target_phys_addr_t addr);
> +void pcie_host_mmcfg_map(PCIExpressHost *e, hwaddr addr);
>  void pcie_host_mmcfg_update(PCIExpressHost *e,
>                              int enable,
> -                            target_phys_addr_t addr);
> +                            hwaddr addr);
>  
>  #endif /* PCIE_HOST_H */
> diff --git a/hw/pckbd.c b/hw/pckbd.c
> index 69857ba..000c7f0 100644
> --- a/hw/pckbd.c
> +++ b/hw/pckbd.c
> @@ -139,7 +139,7 @@
>      qemu_irq irq_kbd;
>      qemu_irq irq_mouse;
>      qemu_irq *a20_out;
> -    target_phys_addr_t mask;
> +    hwaddr mask;
>  } KBDState;
>  
>  /* update irq and KBD_STAT_[MOUSE_]OBF */
> @@ -380,7 +380,7 @@ static void kbd_reset(void *opaque)
>  };
>  
>  /* Memory mapped interface */
> -static uint32_t kbd_mm_readb (void *opaque, target_phys_addr_t addr)
> +static uint32_t kbd_mm_readb (void *opaque, hwaddr addr)
>  {
>      KBDState *s = opaque;
>  
> @@ -390,7 +390,7 @@ static uint32_t kbd_mm_readb (void *opaque, target_phys_addr_t addr)
>          return kbd_read_data(s, 0) & 0xff;
>  }
>  
> -static void kbd_mm_writeb (void *opaque, target_phys_addr_t addr, uint32_t value)
> +static void kbd_mm_writeb (void *opaque, hwaddr addr, uint32_t value)
>  {
>      KBDState *s = opaque;
>  
> @@ -410,7 +410,7 @@ static void kbd_mm_writeb (void *opaque, target_phys_addr_t addr, uint32_t value
>  
>  void i8042_mm_init(qemu_irq kbd_irq, qemu_irq mouse_irq,
>                     MemoryRegion *region, ram_addr_t size,
> -                   target_phys_addr_t mask)
> +                   hwaddr mask)
>  {
>      KBDState *s = g_malloc0(sizeof(KBDState));
>  
> diff --git a/hw/pcnet-pci.c b/hw/pcnet-pci.c
> index 48fd447..0bf438f 100644
> --- a/hw/pcnet-pci.c
> +++ b/hw/pcnet-pci.c
> @@ -71,7 +71,7 @@ static uint32_t pcnet_aprom_readb(void *opaque, uint32_t addr)
>      return val;
>  }
>  
> -static uint64_t pcnet_ioport_read(void *opaque, target_phys_addr_t addr,
> +static uint64_t pcnet_ioport_read(void *opaque, hwaddr addr,
>                                    unsigned size)
>  {
>      PCNetState *d = opaque;
> @@ -98,7 +98,7 @@ static uint64_t pcnet_ioport_read(void *opaque, target_phys_addr_t addr,
>      return ((uint64_t)1 << (size * 8)) - 1;
>  }
>  
> -static void pcnet_ioport_write(void *opaque, target_phys_addr_t addr,
> +static void pcnet_ioport_write(void *opaque, hwaddr addr,
>                                 uint64_t data, unsigned size)
>  {
>      PCNetState *d = opaque;
> @@ -130,7 +130,7 @@ static void pcnet_ioport_write(void *opaque, target_phys_addr_t addr,
>      .endianness = DEVICE_NATIVE_ENDIAN,
>  };
>  
> -static void pcnet_mmio_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
> +static void pcnet_mmio_writeb(void *opaque, hwaddr addr, uint32_t val)
>  {
>      PCNetState *d = opaque;
>  #ifdef PCNET_DEBUG_IO
> @@ -141,7 +141,7 @@ static void pcnet_mmio_writeb(void *opaque, target_phys_addr_t addr, uint32_t va
>          pcnet_aprom_writeb(d, addr & 0x0f, val);
>  }
>  
> -static uint32_t pcnet_mmio_readb(void *opaque, target_phys_addr_t addr)
> +static uint32_t pcnet_mmio_readb(void *opaque, hwaddr addr)
>  {
>      PCNetState *d = opaque;
>      uint32_t val = -1;
> @@ -154,7 +154,7 @@ static uint32_t pcnet_mmio_readb(void *opaque, target_phys_addr_t addr)
>      return val;
>  }
>  
> -static void pcnet_mmio_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
> +static void pcnet_mmio_writew(void *opaque, hwaddr addr, uint32_t val)
>  {
>      PCNetState *d = opaque;
>  #ifdef PCNET_DEBUG_IO
> @@ -170,7 +170,7 @@ static void pcnet_mmio_writew(void *opaque, target_phys_addr_t addr, uint32_t va
>      }
>  }
>  
> -static uint32_t pcnet_mmio_readw(void *opaque, target_phys_addr_t addr)
> +static uint32_t pcnet_mmio_readw(void *opaque, hwaddr addr)
>  {
>      PCNetState *d = opaque;
>      uint32_t val = -1;
> @@ -189,7 +189,7 @@ static uint32_t pcnet_mmio_readw(void *opaque, target_phys_addr_t addr)
>      return val;
>  }
>  
> -static void pcnet_mmio_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
> +static void pcnet_mmio_writel(void *opaque, hwaddr addr, uint32_t val)
>  {
>      PCNetState *d = opaque;
>  #ifdef PCNET_DEBUG_IO
> @@ -207,7 +207,7 @@ static void pcnet_mmio_writel(void *opaque, target_phys_addr_t addr, uint32_t va
>      }
>  }
>  
> -static uint32_t pcnet_mmio_readl(void *opaque, target_phys_addr_t addr)
> +static uint32_t pcnet_mmio_readl(void *opaque, hwaddr addr)
>  {
>      PCNetState *d = opaque;
>      uint32_t val;
> @@ -252,13 +252,13 @@ static uint32_t pcnet_mmio_readl(void *opaque, target_phys_addr_t addr)
>      .endianness = DEVICE_NATIVE_ENDIAN,
>  };
>  
> -static void pci_physical_memory_write(void *dma_opaque, target_phys_addr_t addr,
> +static void pci_physical_memory_write(void *dma_opaque, hwaddr addr,
>                                        uint8_t *buf, int len, int do_bswap)
>  {
>      pci_dma_write(dma_opaque, addr, buf, len);
>  }
>  
> -static void pci_physical_memory_read(void *dma_opaque, target_phys_addr_t addr,
> +static void pci_physical_memory_read(void *dma_opaque, hwaddr addr,
>                                       uint8_t *buf, int len, int do_bswap)
>  {
>      pci_dma_read(dma_opaque, addr, buf, len);
> diff --git a/hw/pcnet.c b/hw/pcnet.c
> index 40820b3..54eecd0 100644
> --- a/hw/pcnet.c
> +++ b/hw/pcnet.c
> @@ -293,7 +293,7 @@ struct pcnet_RMD {
>          GET_FIELD((R)->msg_length, RMDM, ZEROS))
>  
>  static inline void pcnet_tmd_load(PCNetState *s, struct pcnet_TMD *tmd,
> -                                  target_phys_addr_t addr)
> +                                  hwaddr addr)
>  {
>      if (!BCR_SSIZE32(s)) {
>          struct {
> @@ -323,7 +323,7 @@ static inline void pcnet_tmd_load(PCNetState *s, struct pcnet_TMD *tmd,
>  }
>  
>  static inline void pcnet_tmd_store(PCNetState *s, const struct pcnet_TMD *tmd,
> -                                   target_phys_addr_t addr)
> +                                   hwaddr addr)
>  {
>      if (!BCR_SSIZE32(s)) {
>          struct {
> @@ -359,7 +359,7 @@ static inline void pcnet_tmd_store(PCNetState *s, const struct pcnet_TMD *tmd,
>  }
>  
>  static inline void pcnet_rmd_load(PCNetState *s, struct pcnet_RMD *rmd,
> -                                  target_phys_addr_t addr)
> +                                  hwaddr addr)
>  {
>      if (!BCR_SSIZE32(s)) {
>          struct {
> @@ -389,7 +389,7 @@ static inline void pcnet_rmd_load(PCNetState *s, struct pcnet_RMD *rmd,
>  }
>  
>  static inline void pcnet_rmd_store(PCNetState *s, struct pcnet_RMD *rmd,
> -                                   target_phys_addr_t addr)
> +                                   hwaddr addr)
>  {
>      if (!BCR_SSIZE32(s)) {
>          struct {
> @@ -660,7 +660,7 @@ static inline int ladr_match(PCNetState *s, const uint8_t *buf, int size)
>      return 0;
>  }
>  
> -static inline target_phys_addr_t pcnet_rdra_addr(PCNetState *s, int idx)
> +static inline hwaddr pcnet_rdra_addr(PCNetState *s, int idx)
>  {
>      while (idx < 1) idx += CSR_RCVRL(s);
>      return s->rdra + ((CSR_RCVRL(s) - idx) * (BCR_SWSTYLE(s) ? 16 : 8));
> @@ -898,19 +898,19 @@ static void pcnet_rdte_poll(PCNetState *s)
>      if (s->rdra) {
>          int bad = 0;
>  #if 1
> -        target_phys_addr_t crda = pcnet_rdra_addr(s, CSR_RCVRC(s));
> -        target_phys_addr_t nrda = pcnet_rdra_addr(s, -1 + CSR_RCVRC(s));
> -        target_phys_addr_t nnrd = pcnet_rdra_addr(s, -2 + CSR_RCVRC(s));
> +        hwaddr crda = pcnet_rdra_addr(s, CSR_RCVRC(s));
> +        hwaddr nrda = pcnet_rdra_addr(s, -1 + CSR_RCVRC(s));
> +        hwaddr nnrd = pcnet_rdra_addr(s, -2 + CSR_RCVRC(s));
>  #else
> -        target_phys_addr_t crda = s->rdra +
> +        hwaddr crda = s->rdra +
>              (CSR_RCVRL(s) - CSR_RCVRC(s)) *
>              (BCR_SWSTYLE(s) ? 16 : 8 );
>          int nrdc = CSR_RCVRC(s)<=1 ? CSR_RCVRL(s) : CSR_RCVRC(s)-1;
> -        target_phys_addr_t nrda = s->rdra +
> +        hwaddr nrda = s->rdra +
>              (CSR_RCVRL(s) - nrdc) *
>              (BCR_SWSTYLE(s) ? 16 : 8 );
>          int nnrc = nrdc<=1 ? CSR_RCVRL(s) : nrdc-1;
> -        target_phys_addr_t nnrd = s->rdra +
> +        hwaddr nnrd = s->rdra +
>              (CSR_RCVRL(s) - nnrc) *
>              (BCR_SWSTYLE(s) ? 16 : 8 );
>  #endif
> @@ -970,7 +970,7 @@ static int pcnet_tdte_poll(PCNetState *s)
>  {
>      s->csr[34] = s->csr[35] = 0;
>      if (s->tdra) {
> -        target_phys_addr_t cxda = s->tdra +
> +        hwaddr cxda = s->tdra +
>              (CSR_XMTRL(s) - CSR_XMTRC(s)) *
>              (BCR_SWSTYLE(s) ? 16 : 8);
>          int bad = 0;
> @@ -1050,7 +1050,7 @@ ssize_t pcnet_receive(NetClientState *nc, const uint8_t *buf, size_t size_)
>          if (!(CSR_CRST(s) & 0x8000) && s->rdra) {
>              struct pcnet_RMD rmd;
>              int rcvrc = CSR_RCVRC(s)-1,i;
> -            target_phys_addr_t nrda;
> +            hwaddr nrda;
>              for (i = CSR_RCVRL(s)-1; i > 0; i--, rcvrc--) {
>                  if (rcvrc <= 1)
>                      rcvrc = CSR_RCVRL(s);
> @@ -1078,7 +1078,7 @@ ssize_t pcnet_receive(NetClientState *nc, const uint8_t *buf, size_t size_)
>              CSR_MISSC(s)++;
>          } else {
>              uint8_t *src = s->buffer;
> -            target_phys_addr_t crda = CSR_CRDA(s);
> +            hwaddr crda = CSR_CRDA(s);
>              struct pcnet_RMD rmd;
>              int pktcount = 0;
>  
> @@ -1118,7 +1118,7 @@ ssize_t pcnet_receive(NetClientState *nc, const uint8_t *buf, size_t size_)
>  
>  #define PCNET_RECV_STORE() do {                                 \
>      int count = MIN(4096 - GET_FIELD(rmd.buf_length, RMDL, BCNT),remaining); \
> -    target_phys_addr_t rbadr = PHYSADDR(s, rmd.rbadr);          \
> +    hwaddr rbadr = PHYSADDR(s, rmd.rbadr);          \
>      s->phys_mem_write(s->dma_opaque, rbadr, src, count, CSR_BSWP(s)); \
>      src += count; remaining -= count;                           \
>      SET_FIELD(&rmd.status, RMDS, OWN, 0);                       \
> @@ -1129,7 +1129,7 @@ ssize_t pcnet_receive(NetClientState *nc, const uint8_t *buf, size_t size_)
>              remaining = size;
>              PCNET_RECV_STORE();
>              if ((remaining > 0) && CSR_NRDA(s)) {
> -                target_phys_addr_t nrda = CSR_NRDA(s);
> +                hwaddr nrda = CSR_NRDA(s);
>  #ifdef PCNET_DEBUG_RMD
>                  PRINT_RMD(&rmd);
>  #endif
> @@ -1206,7 +1206,7 @@ void pcnet_set_link_status(NetClientState *nc)
>  
>  static void pcnet_transmit(PCNetState *s)
>  {
> -    target_phys_addr_t xmit_cxda = 0;
> +    hwaddr xmit_cxda = 0;
>      int count = CSR_XMTRL(s)-1;
>      int add_crc = 0;
>  
> diff --git a/hw/pcnet.h b/hw/pcnet.h
> index d0af54a..da8c3bd 100644
> --- a/hw/pcnet.h
> +++ b/hw/pcnet.h
> @@ -42,9 +42,9 @@ struct PCNetState_st {
>      MemoryRegion mmio;
>      uint8_t buffer[4096];
>      qemu_irq irq;
> -    void (*phys_mem_read)(void *dma_opaque, target_phys_addr_t addr,
> +    void (*phys_mem_read)(void *dma_opaque, hwaddr addr,
>                           uint8_t *buf, int len, int do_bswap);
> -    void (*phys_mem_write)(void *dma_opaque, target_phys_addr_t addr,
> +    void (*phys_mem_write)(void *dma_opaque, hwaddr addr,
>                            uint8_t *buf, int len, int do_bswap);
>      void *dma_opaque;
>      int tx_busy;
> diff --git a/hw/pcspk.c b/hw/pcspk.c
> index e430324..ad6491b 100644
> --- a/hw/pcspk.c
> +++ b/hw/pcspk.c
> @@ -121,7 +121,7 @@ int pcspk_audio_init(ISABus *bus)
>      return 0;
>  }
>  
> -static uint64_t pcspk_io_read(void *opaque, target_phys_addr_t addr,
> +static uint64_t pcspk_io_read(void *opaque, hwaddr addr,
>                                unsigned size)
>  {
>      PCSpkState *s = opaque;
> @@ -135,7 +135,7 @@ static uint64_t pcspk_io_read(void *opaque, target_phys_addr_t addr,
>         (ch.out << 5);
>  }
>  
> -static void pcspk_io_write(void *opaque, target_phys_addr_t addr, uint64_t val,
> +static void pcspk_io_write(void *opaque, hwaddr addr, uint64_t val,
>                             unsigned size)
>  {
>      PCSpkState *s = opaque;
> diff --git a/hw/petalogix_ml605_mmu.c b/hw/petalogix_ml605_mmu.c
> index 5b45809..3589a4b 100644
> --- a/hw/petalogix_ml605_mmu.c
> +++ b/hw/petalogix_ml605_mmu.c
> @@ -84,7 +84,7 @@ static void machine_cpu_reset(MicroBlazeCPU *cpu)
>      CPUMBState *env;
>      DriveInfo *dinfo;
>      int i;
> -    target_phys_addr_t ddr_base = MEMORY_BASEADDR;
> +    hwaddr ddr_base = MEMORY_BASEADDR;
>      MemoryRegion *phys_lmb_bram = g_new(MemoryRegion, 1);
>      MemoryRegion *phys_ram = g_new(MemoryRegion, 1);
>      qemu_irq irq[32], *cpu_irq;
> diff --git a/hw/petalogix_s3adsp1800_mmu.c b/hw/petalogix_s3adsp1800_mmu.c
> index 71c32ce..c5fd5e7 100644
> --- a/hw/petalogix_s3adsp1800_mmu.c
> +++ b/hw/petalogix_s3adsp1800_mmu.c
> @@ -66,7 +66,7 @@ static void machine_cpu_reset(MicroBlazeCPU *cpu)
>      CPUMBState *env;
>      DriveInfo *dinfo;
>      int i;
> -    target_phys_addr_t ddr_base = MEMORY_BASEADDR;
> +    hwaddr ddr_base = MEMORY_BASEADDR;
>      MemoryRegion *phys_lmb_bram = g_new(MemoryRegion, 1);
>      MemoryRegion *phys_ram = g_new(MemoryRegion, 1);
>      qemu_irq irq[32], *cpu_irq;
> diff --git a/hw/pflash_cfi01.c b/hw/pflash_cfi01.c
> index 3b437da..5e3a409 100644
> --- a/hw/pflash_cfi01.c
> +++ b/hw/pflash_cfi01.c
> @@ -61,9 +61,9 @@
>  
>  struct pflash_t {
>      BlockDriverState *bs;
> -    target_phys_addr_t base;
> -    target_phys_addr_t sector_len;
> -    target_phys_addr_t total_len;
> +    hwaddr base;
> +    hwaddr sector_len;
> +    hwaddr total_len;
>      int width;
>      int wcycle; /* if 0, the flash is read normally */
>      int bypass;
> @@ -73,7 +73,7 @@ struct pflash_t {
>      uint16_t ident[4];
>      uint8_t cfi_len;
>      uint8_t cfi_table[0x52];
> -    target_phys_addr_t counter;
> +    hwaddr counter;
>      unsigned int writeblock_size;
>      QEMUTimer *timer;
>      MemoryRegion mem;
> @@ -96,10 +96,10 @@ static void pflash_timer (void *opaque)
>      pfl->cmd = 0;
>  }
>  
> -static uint32_t pflash_read (pflash_t *pfl, target_phys_addr_t offset,
> +static uint32_t pflash_read (pflash_t *pfl, hwaddr offset,
>                               int width, int be)
>  {
> -    target_phys_addr_t boff;
> +    hwaddr boff;
>      uint32_t ret;
>      uint8_t *p;
>  
> @@ -211,7 +211,7 @@ static void pflash_update(pflash_t *pfl, int offset,
>      }
>  }
>  
> -static inline void pflash_data_write(pflash_t *pfl, target_phys_addr_t offset,
> +static inline void pflash_data_write(pflash_t *pfl, hwaddr offset,
>                                       uint32_t value, int width, int be)
>  {
>      uint8_t *p = pfl->storage;
> @@ -249,7 +249,7 @@ static inline void pflash_data_write(pflash_t *pfl, target_phys_addr_t offset,
>  
>  }
>  
> -static void pflash_write(pflash_t *pfl, target_phys_addr_t offset,
> +static void pflash_write(pflash_t *pfl, hwaddr offset,
>                           uint32_t value, int width, int be)
>  {
>      uint8_t *p;
> @@ -389,7 +389,7 @@ static void pflash_write(pflash_t *pfl, target_phys_addr_t offset,
>              pfl->status |= 0x80;
>  
>              if (!pfl->counter) {
> -                target_phys_addr_t mask = pfl->writeblock_size - 1;
> +                hwaddr mask = pfl->writeblock_size - 1;
>                  mask = ~mask;
>  
>                  DPRINTF("%s: block write finished\n", __func__);
> @@ -445,57 +445,57 @@ static void pflash_write(pflash_t *pfl, target_phys_addr_t offset,
>  }
>  
>  
> -static uint32_t pflash_readb_be(void *opaque, target_phys_addr_t addr)
> +static uint32_t pflash_readb_be(void *opaque, hwaddr addr)
>  {
>      return pflash_read(opaque, addr, 1, 1);
>  }
>  
> -static uint32_t pflash_readb_le(void *opaque, target_phys_addr_t addr)
> +static uint32_t pflash_readb_le(void *opaque, hwaddr addr)
>  {
>      return pflash_read(opaque, addr, 1, 0);
>  }
>  
> -static uint32_t pflash_readw_be(void *opaque, target_phys_addr_t addr)
> +static uint32_t pflash_readw_be(void *opaque, hwaddr addr)
>  {
>      pflash_t *pfl = opaque;
>  
>      return pflash_read(pfl, addr, 2, 1);
>  }
>  
> -static uint32_t pflash_readw_le(void *opaque, target_phys_addr_t addr)
> +static uint32_t pflash_readw_le(void *opaque, hwaddr addr)
>  {
>      pflash_t *pfl = opaque;
>  
>      return pflash_read(pfl, addr, 2, 0);
>  }
>  
> -static uint32_t pflash_readl_be(void *opaque, target_phys_addr_t addr)
> +static uint32_t pflash_readl_be(void *opaque, hwaddr addr)
>  {
>      pflash_t *pfl = opaque;
>  
>      return pflash_read(pfl, addr, 4, 1);
>  }
>  
> -static uint32_t pflash_readl_le(void *opaque, target_phys_addr_t addr)
> +static uint32_t pflash_readl_le(void *opaque, hwaddr addr)
>  {
>      pflash_t *pfl = opaque;
>  
>      return pflash_read(pfl, addr, 4, 0);
>  }
>  
> -static void pflash_writeb_be(void *opaque, target_phys_addr_t addr,
> +static void pflash_writeb_be(void *opaque, hwaddr addr,
>                               uint32_t value)
>  {
>      pflash_write(opaque, addr, value, 1, 1);
>  }
>  
> -static void pflash_writeb_le(void *opaque, target_phys_addr_t addr,
> +static void pflash_writeb_le(void *opaque, hwaddr addr,
>                               uint32_t value)
>  {
>      pflash_write(opaque, addr, value, 1, 0);
>  }
>  
> -static void pflash_writew_be(void *opaque, target_phys_addr_t addr,
> +static void pflash_writew_be(void *opaque, hwaddr addr,
>                               uint32_t value)
>  {
>      pflash_t *pfl = opaque;
> @@ -503,7 +503,7 @@ static void pflash_writew_be(void *opaque, target_phys_addr_t addr,
>      pflash_write(pfl, addr, value, 2, 1);
>  }
>  
> -static void pflash_writew_le(void *opaque, target_phys_addr_t addr,
> +static void pflash_writew_le(void *opaque, hwaddr addr,
>                               uint32_t value)
>  {
>      pflash_t *pfl = opaque;
> @@ -511,7 +511,7 @@ static void pflash_writew_le(void *opaque, target_phys_addr_t addr,
>      pflash_write(pfl, addr, value, 2, 0);
>  }
>  
> -static void pflash_writel_be(void *opaque, target_phys_addr_t addr,
> +static void pflash_writel_be(void *opaque, hwaddr addr,
>                               uint32_t value)
>  {
>      pflash_t *pfl = opaque;
> @@ -519,7 +519,7 @@ static void pflash_writel_be(void *opaque, target_phys_addr_t addr,
>      pflash_write(pfl, addr, value, 4, 1);
>  }
>  
> -static void pflash_writel_le(void *opaque, target_phys_addr_t addr,
> +static void pflash_writel_le(void *opaque, hwaddr addr,
>                               uint32_t value)
>  {
>      pflash_t *pfl = opaque;
> @@ -543,16 +543,16 @@ static void pflash_writel_le(void *opaque, target_phys_addr_t addr,
>      .endianness = DEVICE_NATIVE_ENDIAN,
>  };
>  
> -pflash_t *pflash_cfi01_register(target_phys_addr_t base,
> +pflash_t *pflash_cfi01_register(hwaddr base,
>                                  DeviceState *qdev, const char *name,
> -                                target_phys_addr_t size,
> +                                hwaddr size,
>                                  BlockDriverState *bs, uint32_t sector_len,
>                                  int nb_blocs, int width,
>                                  uint16_t id0, uint16_t id1,
>                                  uint16_t id2, uint16_t id3, int be)
>  {
>      pflash_t *pfl;
> -    target_phys_addr_t total_len;
> +    hwaddr total_len;
>      int ret;
>  
>      total_len = sector_len * nb_blocs;
> diff --git a/hw/pflash_cfi02.c b/hw/pflash_cfi02.c
> index 39337ec..9f94c06 100644
> --- a/hw/pflash_cfi02.c
> +++ b/hw/pflash_cfi02.c
> @@ -56,7 +56,7 @@
>  
>  struct pflash_t {
>      BlockDriverState *bs;
> -    target_phys_addr_t base;
> +    hwaddr base;
>      uint32_t sector_len;
>      uint32_t chip_len;
>      int mappings;
> @@ -89,7 +89,7 @@ struct pflash_t {
>  static void pflash_setup_mappings(pflash_t *pfl)
>  {
>      unsigned i;
> -    target_phys_addr_t size = memory_region_size(&pfl->orig_mem);
> +    hwaddr size = memory_region_size(&pfl->orig_mem);
>  
>      memory_region_init(&pfl->mem, "pflash", pfl->mappings * size);
>      pfl->mem_mappings = g_new(MemoryRegion, pfl->mappings);
> @@ -122,10 +122,10 @@ static void pflash_timer (void *opaque)
>      pfl->cmd = 0;
>  }
>  
> -static uint32_t pflash_read (pflash_t *pfl, target_phys_addr_t offset,
> +static uint32_t pflash_read (pflash_t *pfl, hwaddr offset,
>                               int width, int be)
>  {
> -    target_phys_addr_t boff;
> +    hwaddr boff;
>      uint32_t ret;
>      uint8_t *p;
>  
> @@ -242,10 +242,10 @@ static void pflash_update(pflash_t *pfl, int offset,
>      }
>  }
>  
> -static void pflash_write (pflash_t *pfl, target_phys_addr_t offset,
> +static void pflash_write (pflash_t *pfl, hwaddr offset,
>                            uint32_t value, int width, int be)
>  {
> -    target_phys_addr_t boff;
> +    hwaddr boff;
>      uint8_t *p;
>      uint8_t cmd;
>  
> @@ -477,57 +477,57 @@ static void pflash_write (pflash_t *pfl, target_phys_addr_t offset,
>  }
>  
>  
> -static uint32_t pflash_readb_be(void *opaque, target_phys_addr_t addr)
> +static uint32_t pflash_readb_be(void *opaque, hwaddr addr)
>  {
>      return pflash_read(opaque, addr, 1, 1);
>  }
>  
> -static uint32_t pflash_readb_le(void *opaque, target_phys_addr_t addr)
> +static uint32_t pflash_readb_le(void *opaque, hwaddr addr)
>  {
>      return pflash_read(opaque, addr, 1, 0);
>  }
>  
> -static uint32_t pflash_readw_be(void *opaque, target_phys_addr_t addr)
> +static uint32_t pflash_readw_be(void *opaque, hwaddr addr)
>  {
>      pflash_t *pfl = opaque;
>  
>      return pflash_read(pfl, addr, 2, 1);
>  }
>  
> -static uint32_t pflash_readw_le(void *opaque, target_phys_addr_t addr)
> +static uint32_t pflash_readw_le(void *opaque, hwaddr addr)
>  {
>      pflash_t *pfl = opaque;
>  
>      return pflash_read(pfl, addr, 2, 0);
>  }
>  
> -static uint32_t pflash_readl_be(void *opaque, target_phys_addr_t addr)
> +static uint32_t pflash_readl_be(void *opaque, hwaddr addr)
>  {
>      pflash_t *pfl = opaque;
>  
>      return pflash_read(pfl, addr, 4, 1);
>  }
>  
> -static uint32_t pflash_readl_le(void *opaque, target_phys_addr_t addr)
> +static uint32_t pflash_readl_le(void *opaque, hwaddr addr)
>  {
>      pflash_t *pfl = opaque;
>  
>      return pflash_read(pfl, addr, 4, 0);
>  }
>  
> -static void pflash_writeb_be(void *opaque, target_phys_addr_t addr,
> +static void pflash_writeb_be(void *opaque, hwaddr addr,
>                               uint32_t value)
>  {
>      pflash_write(opaque, addr, value, 1, 1);
>  }
>  
> -static void pflash_writeb_le(void *opaque, target_phys_addr_t addr,
> +static void pflash_writeb_le(void *opaque, hwaddr addr,
>                               uint32_t value)
>  {
>      pflash_write(opaque, addr, value, 1, 0);
>  }
>  
> -static void pflash_writew_be(void *opaque, target_phys_addr_t addr,
> +static void pflash_writew_be(void *opaque, hwaddr addr,
>                               uint32_t value)
>  {
>      pflash_t *pfl = opaque;
> @@ -535,7 +535,7 @@ static void pflash_writew_be(void *opaque, target_phys_addr_t addr,
>      pflash_write(pfl, addr, value, 2, 1);
>  }
>  
> -static void pflash_writew_le(void *opaque, target_phys_addr_t addr,
> +static void pflash_writew_le(void *opaque, hwaddr addr,
>                               uint32_t value)
>  {
>      pflash_t *pfl = opaque;
> @@ -543,7 +543,7 @@ static void pflash_writew_le(void *opaque, target_phys_addr_t addr,
>      pflash_write(pfl, addr, value, 2, 0);
>  }
>  
> -static void pflash_writel_be(void *opaque, target_phys_addr_t addr,
> +static void pflash_writel_be(void *opaque, hwaddr addr,
>                               uint32_t value)
>  {
>      pflash_t *pfl = opaque;
> @@ -551,7 +551,7 @@ static void pflash_writel_be(void *opaque, target_phys_addr_t addr,
>      pflash_write(pfl, addr, value, 4, 1);
>  }
>  
> -static void pflash_writel_le(void *opaque, target_phys_addr_t addr,
> +static void pflash_writel_le(void *opaque, hwaddr addr,
>                               uint32_t value)
>  {
>      pflash_t *pfl = opaque;
> @@ -575,9 +575,9 @@ static void pflash_writel_le(void *opaque, target_phys_addr_t addr,
>      .endianness = DEVICE_NATIVE_ENDIAN,
>  };
>  
> -pflash_t *pflash_cfi02_register(target_phys_addr_t base,
> +pflash_t *pflash_cfi02_register(hwaddr base,
>                                  DeviceState *qdev, const char *name,
> -                                target_phys_addr_t size,
> +                                hwaddr size,
>                                  BlockDriverState *bs, uint32_t sector_len,
>                                  int nb_blocs, int nb_mappings, int width,
>                                  uint16_t id0, uint16_t id1,
> diff --git a/hw/piix_pci.c b/hw/piix_pci.c
> index 537fc19..4f3b8a8 100644
> --- a/hw/piix_pci.c
> +++ b/hw/piix_pci.c
> @@ -259,10 +259,10 @@ static PCIBus *i440fx_common_init(const char *device_name,
>                                    MemoryRegion *address_space_mem,
>                                    MemoryRegion *address_space_io,
>                                    ram_addr_t ram_size,
> -                                  target_phys_addr_t pci_hole_start,
> -                                  target_phys_addr_t pci_hole_size,
> -                                  target_phys_addr_t pci_hole64_start,
> -                                  target_phys_addr_t pci_hole64_size,
> +                                  hwaddr pci_hole_start,
> +                                  hwaddr pci_hole_size,
> +                                  hwaddr pci_hole64_start,
> +                                  hwaddr pci_hole64_size,
>                                    MemoryRegion *pci_address_space,
>                                    MemoryRegion *ram_memory)
>  {
> @@ -341,10 +341,10 @@ PCIBus *i440fx_init(PCII440FXState **pi440fx_state, int *piix3_devfn,
>                      MemoryRegion *address_space_mem,
>                      MemoryRegion *address_space_io,
>                      ram_addr_t ram_size,
> -                    target_phys_addr_t pci_hole_start,
> -                    target_phys_addr_t pci_hole_size,
> -                    target_phys_addr_t pci_hole64_start,
> -                    target_phys_addr_t pci_hole64_size,
> +                    hwaddr pci_hole_start,
> +                    hwaddr pci_hole_size,
> +                    hwaddr pci_hole64_start,
> +                    hwaddr pci_hole64_size,
>                      MemoryRegion *pci_memory, MemoryRegion *ram_memory)
>  
>  {
> diff --git a/hw/pl011.c b/hw/pl011.c
> index fb22736..1f7ce2f 100644
> --- a/hw/pl011.c
> +++ b/hw/pl011.c
> @@ -54,7 +54,7 @@ static void pl011_update(pl011_state *s)
>      qemu_set_irq(s->irq, flags != 0);
>  }
>  
> -static uint64_t pl011_read(void *opaque, target_phys_addr_t offset,
> +static uint64_t pl011_read(void *opaque, hwaddr offset,
>                             unsigned size)
>  {
>      pl011_state *s = (pl011_state *)opaque;
> @@ -127,7 +127,7 @@ static void pl011_set_read_trigger(pl011_state *s)
>          s->read_trigger = 1;
>  }
>  
> -static void pl011_write(void *opaque, target_phys_addr_t offset,
> +static void pl011_write(void *opaque, hwaddr offset,
>                          uint64_t value, unsigned size)
>  {
>      pl011_state *s = (pl011_state *)opaque;
> diff --git a/hw/pl022.c b/hw/pl022.c
> index e2ae315..fbd7ded 100644
> --- a/hw/pl022.c
> +++ b/hw/pl022.c
> @@ -130,7 +130,7 @@ static void pl022_xfer(pl022_state *s)
>      pl022_update(s);
>  }
>  
> -static uint64_t pl022_read(void *opaque, target_phys_addr_t offset,
> +static uint64_t pl022_read(void *opaque, hwaddr offset,
>                             unsigned size)
>  {
>      pl022_state *s = (pl022_state *)opaque;
> @@ -174,7 +174,7 @@ static uint64_t pl022_read(void *opaque, target_phys_addr_t offset,
>      }
>  }
>  
> -static void pl022_write(void *opaque, target_phys_addr_t offset,
> +static void pl022_write(void *opaque, hwaddr offset,
>                          uint64_t value, unsigned size)
>  {
>      pl022_state *s = (pl022_state *)opaque;
> diff --git a/hw/pl031.c b/hw/pl031.c
> index 6cbaf23..8bf0183 100644
> --- a/hw/pl031.c
> +++ b/hw/pl031.c
> @@ -95,7 +95,7 @@ static void pl031_set_alarm(pl031_state *s)
>      }
>  }
>  
> -static uint64_t pl031_read(void *opaque, target_phys_addr_t offset,
> +static uint64_t pl031_read(void *opaque, hwaddr offset,
>                             unsigned size)
>  {
>      pl031_state *s = (pl031_state *)opaque;
> @@ -133,7 +133,7 @@ static uint64_t pl031_read(void *opaque, target_phys_addr_t offset,
>      return 0;
>  }
>  
> -static void pl031_write(void * opaque, target_phys_addr_t offset,
> +static void pl031_write(void * opaque, hwaddr offset,
>                          uint64_t value, unsigned size)
>  {
>      pl031_state *s = (pl031_state *)opaque;
> diff --git a/hw/pl041.c b/hw/pl041.c
> index 9a6db1b..4436d97 100644
> --- a/hw/pl041.c
> +++ b/hw/pl041.c
> @@ -97,7 +97,7 @@
>  
>  
>  #if defined(PL041_DEBUG_LEVEL)
> -static const char *get_reg_name(target_phys_addr_t offset)
> +static const char *get_reg_name(hwaddr offset)
>  {
>      if (offset <= PL041_dr1_7) {
>          return pl041_regs_name[offset >> 2];
> @@ -327,7 +327,7 @@ static void pl041_request_data(void *opaque)
>      pl041_isr1_update(s);
>  }
>  
> -static uint64_t pl041_read(void *opaque, target_phys_addr_t offset,
> +static uint64_t pl041_read(void *opaque, hwaddr offset,
>                                  unsigned size)
>  {
>      pl041_state *s = (pl041_state *)opaque;
> @@ -361,7 +361,7 @@ static uint64_t pl041_read(void *opaque, target_phys_addr_t offset,
>      return value;
>  }
>  
> -static void pl041_write(void *opaque, target_phys_addr_t offset,
> +static void pl041_write(void *opaque, hwaddr offset,
>                               uint64_t value, unsigned size)
>  {
>      pl041_state *s = (pl041_state *)opaque;
> diff --git a/hw/pl050.c b/hw/pl050.c
> index b13924a..470572e 100644
> --- a/hw/pl050.c
> +++ b/hw/pl050.c
> @@ -58,7 +58,7 @@ static void pl050_update(void *opaque, int level)
>      qemu_set_irq(s->irq, raise);
>  }
>  
> -static uint64_t pl050_read(void *opaque, target_phys_addr_t offset,
> +static uint64_t pl050_read(void *opaque, hwaddr offset,
>                             unsigned size)
>  {
>      pl050_state *s = (pl050_state *)opaque;
> @@ -100,7 +100,7 @@ static uint64_t pl050_read(void *opaque, target_phys_addr_t offset,
>      }
>  }
>  
> -static void pl050_write(void *opaque, target_phys_addr_t offset,
> +static void pl050_write(void *opaque, hwaddr offset,
>                          uint64_t value, unsigned size)
>  {
>      pl050_state *s = (pl050_state *)opaque;
> diff --git a/hw/pl061.c b/hw/pl061.c
> index 2aac7e8..7d182e7 100644
> --- a/hw/pl061.c
> +++ b/hw/pl061.c
> @@ -113,7 +113,7 @@ static void pl061_update(pl061_state *s)
>      /* FIXME: Implement input interrupts.  */
>  }
>  
> -static uint64_t pl061_read(void *opaque, target_phys_addr_t offset,
> +static uint64_t pl061_read(void *opaque, hwaddr offset,
>                             unsigned size)
>  {
>      pl061_state *s = (pl061_state *)opaque;
> @@ -169,7 +169,7 @@ static uint64_t pl061_read(void *opaque, target_phys_addr_t offset,
>      }
>  }
>  
> -static void pl061_write(void *opaque, target_phys_addr_t offset,
> +static void pl061_write(void *opaque, hwaddr offset,
>                          uint64_t value, unsigned size)
>  {
>      pl061_state *s = (pl061_state *)opaque;
> diff --git a/hw/pl080.c b/hw/pl080.c
> index b3cf651..6abe528 100644
> --- a/hw/pl080.c
> +++ b/hw/pl080.c
> @@ -218,7 +218,7 @@ static void pl080_run(pl080_state *s)
>      }
>  }
>  
> -static uint64_t pl080_read(void *opaque, target_phys_addr_t offset,
> +static uint64_t pl080_read(void *opaque, hwaddr offset,
>                             unsigned size)
>  {
>      pl080_state *s = (pl080_state *)opaque;
> @@ -286,7 +286,7 @@ static uint64_t pl080_read(void *opaque, target_phys_addr_t offset,
>      }
>  }
>  
> -static void pl080_write(void *opaque, target_phys_addr_t offset,
> +static void pl080_write(void *opaque, hwaddr offset,
>                          uint64_t value, unsigned size)
>  {
>      pl080_state *s = (pl080_state *)opaque;
> diff --git a/hw/pl110.c b/hw/pl110.c
> index a582640..82486b0 100644
> --- a/hw/pl110.c
> +++ b/hw/pl110.c
> @@ -305,7 +305,7 @@ static void pl110_update(pl110_state *s)
>    /* TODO: Implement interrupts.  */
>  }
>  
> -static uint64_t pl110_read(void *opaque, target_phys_addr_t offset,
> +static uint64_t pl110_read(void *opaque, hwaddr offset,
>                             unsigned size)
>  {
>      pl110_state *s = (pl110_state *)opaque;
> @@ -354,7 +354,7 @@ static uint64_t pl110_read(void *opaque, target_phys_addr_t offset,
>      }
>  }
>  
> -static void pl110_write(void *opaque, target_phys_addr_t offset,
> +static void pl110_write(void *opaque, hwaddr offset,
>                          uint64_t val, unsigned size)
>  {
>      pl110_state *s = (pl110_state *)opaque;
> diff --git a/hw/pl181.c b/hw/pl181.c
> index 5a73473..8a2895c 100644
> --- a/hw/pl181.c
> +++ b/hw/pl181.c
> @@ -285,7 +285,7 @@ static void pl181_fifo_run(pl181_state *s)
>      }
>  }
>  
> -static uint64_t pl181_read(void *opaque, target_phys_addr_t offset,
> +static uint64_t pl181_read(void *opaque, hwaddr offset,
>                             unsigned size)
>  {
>      pl181_state *s = (pl181_state *)opaque;
> @@ -369,7 +369,7 @@ static uint64_t pl181_read(void *opaque, target_phys_addr_t offset,
>      }
>  }
>  
> -static void pl181_write(void *opaque, target_phys_addr_t offset,
> +static void pl181_write(void *opaque, hwaddr offset,
>                          uint64_t value, unsigned size)
>  {
>      pl181_state *s = (pl181_state *)opaque;
> diff --git a/hw/pl190.c b/hw/pl190.c
> index 961da5b..213229b 100644
> --- a/hw/pl190.c
> +++ b/hw/pl190.c
> @@ -85,7 +85,7 @@ static void pl190_update_vectors(pl190_state *s)
>      pl190_update(s);
>  }
>  
> -static uint64_t pl190_read(void *opaque, target_phys_addr_t offset,
> +static uint64_t pl190_read(void *opaque, hwaddr offset,
>                             unsigned size)
>  {
>      pl190_state *s = (pl190_state *)opaque;
> @@ -149,7 +149,7 @@ static uint64_t pl190_read(void *opaque, target_phys_addr_t offset,
>      }
>  }
>  
> -static void pl190_write(void *opaque, target_phys_addr_t offset,
> +static void pl190_write(void *opaque, hwaddr offset,
>                          uint64_t val, unsigned size)
>  {
>      pl190_state *s = (pl190_state *)opaque;
> diff --git a/hw/ppc/e500.c b/hw/ppc/e500.c
> index 846f53a..d655e3f 100644
> --- a/hw/ppc/e500.c
> +++ b/hw/ppc/e500.c
> @@ -108,9 +108,9 @@ static void dt_serial_create(void *fdt, unsigned long long offset,
>  
>  static int ppce500_load_device_tree(CPUPPCState *env,
>                                      PPCE500Params *params,
> -                                    target_phys_addr_t addr,
> -                                    target_phys_addr_t initrd_base,
> -                                    target_phys_addr_t initrd_size)
> +                                    hwaddr addr,
> +                                    hwaddr initrd_base,
> +                                    hwaddr initrd_size)
>  {
>      int ret = -1;
>      uint64_t mem_reg_property[] = { 0, cpu_to_be64(params->ram_size) };
> @@ -346,7 +346,7 @@ static int ppce500_load_device_tree(CPUPPCState *env,
>  }
>  
>  /* Create -kernel TLB entries for BookE.  */
> -static inline target_phys_addr_t booke206_page_size_to_tlb(uint64_t size)
> +static inline hwaddr booke206_page_size_to_tlb(uint64_t size)
>  {
>      return 63 - clz64(size >> 10);
>  }
> @@ -355,7 +355,7 @@ static void mmubooke_create_initial_mapping(CPUPPCState *env)
>  {
>      struct boot_info *bi = env->load_info;
>      ppcmas_tlb_t *tlb = booke206_get_tlbm(env, 1, 0, 0);
> -    target_phys_addr_t size, dt_end;
> +    hwaddr size, dt_end;
>      int ps;
>  
>      /* Our initial TLB entry needs to cover everything from 0 to
> @@ -412,8 +412,8 @@ void ppce500_init(PPCE500Params *params)
>      CPUPPCState *env = NULL;
>      uint64_t elf_entry;
>      uint64_t elf_lowaddr;
> -    target_phys_addr_t entry=0;
> -    target_phys_addr_t loadaddr=UIMAGE_LOAD_BASE;
> +    hwaddr entry=0;
> +    hwaddr loadaddr=UIMAGE_LOAD_BASE;
>      target_long kernel_size=0;
>      target_ulong dt_base = 0;
>      target_ulong initrd_base = 0;
> diff --git a/hw/ppc405.h b/hw/ppc405.h
> index 1f5dc5f..535cbfb 100644
> --- a/hw/ppc405.h
> +++ b/hw/ppc405.h
> @@ -61,20 +61,20 @@ ram_addr_t ppc405_set_bootinfo (CPUPPCState *env, ppc4xx_bd_info_t *bd,
>  
>  CPUPPCState *ppc405cr_init(MemoryRegion *address_space_mem,
>                          MemoryRegion ram_memories[4],
> -                        target_phys_addr_t ram_bases[4],
> -                        target_phys_addr_t ram_sizes[4],
> +                        hwaddr ram_bases[4],
> +                        hwaddr ram_sizes[4],
>                          uint32_t sysclk, qemu_irq **picp,
>                          int do_init);
>  CPUPPCState *ppc405ep_init(MemoryRegion *address_space_mem,
>                          MemoryRegion ram_memories[2],
> -                        target_phys_addr_t ram_bases[2],
> -                        target_phys_addr_t ram_sizes[2],
> +                        hwaddr ram_bases[2],
> +                        hwaddr ram_sizes[2],
>                          uint32_t sysclk, qemu_irq **picp,
>                          int do_init);
>  /* IBM STBxxx microcontrollers */
>  CPUPPCState *ppc_stb025_init (MemoryRegion ram_memories[2],
> -                           target_phys_addr_t ram_bases[2],
> -                           target_phys_addr_t ram_sizes[2],
> +                           hwaddr ram_bases[2],
> +                           hwaddr ram_sizes[2],
>                             uint32_t sysclk, qemu_irq **picp,
>                             ram_addr_t *offsetp);
>  
> diff --git a/hw/ppc405_boards.c b/hw/ppc405_boards.c
> index e848cb0..8dc693f 100644
> --- a/hw/ppc405_boards.c
> +++ b/hw/ppc405_boards.c
> @@ -60,7 +60,7 @@ struct ref405ep_fpga_t {
>      uint8_t reg1;
>  };
>  
> -static uint32_t ref405ep_fpga_readb (void *opaque, target_phys_addr_t addr)
> +static uint32_t ref405ep_fpga_readb (void *opaque, hwaddr addr)
>  {
>      ref405ep_fpga_t *fpga;
>      uint32_t ret;
> @@ -82,7 +82,7 @@ static uint32_t ref405ep_fpga_readb (void *opaque, target_phys_addr_t addr)
>  }
>  
>  static void ref405ep_fpga_writeb (void *opaque,
> -                                  target_phys_addr_t addr, uint32_t value)
> +                                  hwaddr addr, uint32_t value)
>  {
>      ref405ep_fpga_t *fpga;
>  
> @@ -99,7 +99,7 @@ static void ref405ep_fpga_writeb (void *opaque,
>      }
>  }
>  
> -static uint32_t ref405ep_fpga_readw (void *opaque, target_phys_addr_t addr)
> +static uint32_t ref405ep_fpga_readw (void *opaque, hwaddr addr)
>  {
>      uint32_t ret;
>  
> @@ -110,13 +110,13 @@ static uint32_t ref405ep_fpga_readw (void *opaque, target_phys_addr_t addr)
>  }
>  
>  static void ref405ep_fpga_writew (void *opaque,
> -                                  target_phys_addr_t addr, uint32_t value)
> +                                  hwaddr addr, uint32_t value)
>  {
>      ref405ep_fpga_writeb(opaque, addr, (value >> 8) & 0xFF);
>      ref405ep_fpga_writeb(opaque, addr + 1, value & 0xFF);
>  }
>  
> -static uint32_t ref405ep_fpga_readl (void *opaque, target_phys_addr_t addr)
> +static uint32_t ref405ep_fpga_readl (void *opaque, hwaddr addr)
>  {
>      uint32_t ret;
>  
> @@ -129,7 +129,7 @@ static uint32_t ref405ep_fpga_readl (void *opaque, target_phys_addr_t addr)
>  }
>  
>  static void ref405ep_fpga_writel (void *opaque,
> -                                  target_phys_addr_t addr, uint32_t value)
> +                                  hwaddr addr, uint32_t value)
>  {
>      ref405ep_fpga_writeb(opaque, addr, (value >> 24) & 0xFF);
>      ref405ep_fpga_writeb(opaque, addr + 1, (value >> 16) & 0xFF);
> @@ -184,7 +184,7 @@ static void ref405ep_init(QEMUMachineInitArgs *args)
>      MemoryRegion *sram = g_new(MemoryRegion, 1);
>      ram_addr_t bdloc;
>      MemoryRegion *ram_memories = g_malloc(2 * sizeof(*ram_memories));
> -    target_phys_addr_t ram_bases[2], ram_sizes[2];
> +    hwaddr ram_bases[2], ram_sizes[2];
>      target_ulong sram_size;
>      long bios_size;
>      //int phy_addr = 0;
> @@ -389,7 +389,7 @@ struct taihu_cpld_t {
>      uint8_t reg1;
>  };
>  
> -static uint32_t taihu_cpld_readb (void *opaque, target_phys_addr_t addr)
> +static uint32_t taihu_cpld_readb (void *opaque, hwaddr addr)
>  {
>      taihu_cpld_t *cpld;
>      uint32_t ret;
> @@ -411,7 +411,7 @@ static uint32_t taihu_cpld_readb (void *opaque, target_phys_addr_t addr)
>  }
>  
>  static void taihu_cpld_writeb (void *opaque,
> -                               target_phys_addr_t addr, uint32_t value)
> +                               hwaddr addr, uint32_t value)
>  {
>      taihu_cpld_t *cpld;
>  
> @@ -428,7 +428,7 @@ static void taihu_cpld_writeb (void *opaque,
>      }
>  }
>  
> -static uint32_t taihu_cpld_readw (void *opaque, target_phys_addr_t addr)
> +static uint32_t taihu_cpld_readw (void *opaque, hwaddr addr)
>  {
>      uint32_t ret;
>  
> @@ -439,13 +439,13 @@ static uint32_t taihu_cpld_readw (void *opaque, target_phys_addr_t addr)
>  }
>  
>  static void taihu_cpld_writew (void *opaque,
> -                               target_phys_addr_t addr, uint32_t value)
> +                               hwaddr addr, uint32_t value)
>  {
>      taihu_cpld_writeb(opaque, addr, (value >> 8) & 0xFF);
>      taihu_cpld_writeb(opaque, addr + 1, value & 0xFF);
>  }
>  
> -static uint32_t taihu_cpld_readl (void *opaque, target_phys_addr_t addr)
> +static uint32_t taihu_cpld_readl (void *opaque, hwaddr addr)
>  {
>      uint32_t ret;
>  
> @@ -458,7 +458,7 @@ static uint32_t taihu_cpld_readl (void *opaque, target_phys_addr_t addr)
>  }
>  
>  static void taihu_cpld_writel (void *opaque,
> -                               target_phys_addr_t addr, uint32_t value)
> +                               hwaddr addr, uint32_t value)
>  {
>      taihu_cpld_writel(opaque, addr, (value >> 24) & 0xFF);
>      taihu_cpld_writel(opaque, addr + 1, (value >> 16) & 0xFF);
> @@ -504,7 +504,7 @@ static void taihu_405ep_init(QEMUMachineInitArgs *args)
>      MemoryRegion *sysmem = get_system_memory();
>      MemoryRegion *bios;
>      MemoryRegion *ram_memories = g_malloc(2 * sizeof(*ram_memories));
> -    target_phys_addr_t ram_bases[2], ram_sizes[2];
> +    hwaddr ram_bases[2], ram_sizes[2];
>      long bios_size;
>      target_ulong kernel_base, initrd_base;
>      long kernel_size, initrd_size;
> diff --git a/hw/ppc405_uc.c b/hw/ppc405_uc.c
> index e81409d..0f458ef 100644
> --- a/hw/ppc405_uc.c
> +++ b/hw/ppc405_uc.c
> @@ -271,7 +271,7 @@ struct ppc4xx_opba_t {
>      uint8_t pr;
>  };
>  
> -static uint32_t opba_readb (void *opaque, target_phys_addr_t addr)
> +static uint32_t opba_readb (void *opaque, hwaddr addr)
>  {
>      ppc4xx_opba_t *opba;
>      uint32_t ret;
> @@ -296,7 +296,7 @@ static uint32_t opba_readb (void *opaque, target_phys_addr_t addr)
>  }
>  
>  static void opba_writeb (void *opaque,
> -                         target_phys_addr_t addr, uint32_t value)
> +                         hwaddr addr, uint32_t value)
>  {
>      ppc4xx_opba_t *opba;
>  
> @@ -317,7 +317,7 @@ static void opba_writeb (void *opaque,
>      }
>  }
>  
> -static uint32_t opba_readw (void *opaque, target_phys_addr_t addr)
> +static uint32_t opba_readw (void *opaque, hwaddr addr)
>  {
>      uint32_t ret;
>  
> @@ -331,7 +331,7 @@ static uint32_t opba_readw (void *opaque, target_phys_addr_t addr)
>  }
>  
>  static void opba_writew (void *opaque,
> -                         target_phys_addr_t addr, uint32_t value)
> +                         hwaddr addr, uint32_t value)
>  {
>  #ifdef DEBUG_OPBA
>      printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
> @@ -341,7 +341,7 @@ static void opba_writew (void *opaque,
>      opba_writeb(opaque, addr + 1, value);
>  }
>  
> -static uint32_t opba_readl (void *opaque, target_phys_addr_t addr)
> +static uint32_t opba_readl (void *opaque, hwaddr addr)
>  {
>      uint32_t ret;
>  
> @@ -355,7 +355,7 @@ static uint32_t opba_readl (void *opaque, target_phys_addr_t addr)
>  }
>  
>  static void opba_writel (void *opaque,
> -                         target_phys_addr_t addr, uint32_t value)
> +                         hwaddr addr, uint32_t value)
>  {
>  #ifdef DEBUG_OPBA
>      printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
> @@ -382,7 +382,7 @@ static void ppc4xx_opba_reset (void *opaque)
>      opba->pr = 0x11;
>  }
>  
> -static void ppc4xx_opba_init(target_phys_addr_t base)
> +static void ppc4xx_opba_init(hwaddr base)
>  {
>      ppc4xx_opba_t *opba;
>  
> @@ -738,7 +738,7 @@ struct ppc405_gpio_t {
>      uint32_t isr1l;
>  };
>  
> -static uint32_t ppc405_gpio_readb (void *opaque, target_phys_addr_t addr)
> +static uint32_t ppc405_gpio_readb (void *opaque, hwaddr addr)
>  {
>  #ifdef DEBUG_GPIO
>      printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
> @@ -748,7 +748,7 @@ static uint32_t ppc405_gpio_readb (void *opaque, target_phys_addr_t addr)
>  }
>  
>  static void ppc405_gpio_writeb (void *opaque,
> -                                target_phys_addr_t addr, uint32_t value)
> +                                hwaddr addr, uint32_t value)
>  {
>  #ifdef DEBUG_GPIO
>      printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
> @@ -756,7 +756,7 @@ static void ppc405_gpio_writeb (void *opaque,
>  #endif
>  }
>  
> -static uint32_t ppc405_gpio_readw (void *opaque, target_phys_addr_t addr)
> +static uint32_t ppc405_gpio_readw (void *opaque, hwaddr addr)
>  {
>  #ifdef DEBUG_GPIO
>      printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
> @@ -766,7 +766,7 @@ static uint32_t ppc405_gpio_readw (void *opaque, target_phys_addr_t addr)
>  }
>  
>  static void ppc405_gpio_writew (void *opaque,
> -                                target_phys_addr_t addr, uint32_t value)
> +                                hwaddr addr, uint32_t value)
>  {
>  #ifdef DEBUG_GPIO
>      printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
> @@ -774,7 +774,7 @@ static void ppc405_gpio_writew (void *opaque,
>  #endif
>  }
>  
> -static uint32_t ppc405_gpio_readl (void *opaque, target_phys_addr_t addr)
> +static uint32_t ppc405_gpio_readl (void *opaque, hwaddr addr)
>  {
>  #ifdef DEBUG_GPIO
>      printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
> @@ -784,7 +784,7 @@ static uint32_t ppc405_gpio_readl (void *opaque, target_phys_addr_t addr)
>  }
>  
>  static void ppc405_gpio_writel (void *opaque,
> -                                target_phys_addr_t addr, uint32_t value)
> +                                hwaddr addr, uint32_t value)
>  {
>  #ifdef DEBUG_GPIO
>      printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
> @@ -804,7 +804,7 @@ static void ppc405_gpio_reset (void *opaque)
>  {
>  }
>  
> -static void ppc405_gpio_init(target_phys_addr_t base)
> +static void ppc405_gpio_init(hwaddr base)
>  {
>      ppc405_gpio_t *gpio;
>  
> @@ -1010,7 +1010,7 @@ struct ppc4xx_i2c_t {
>      uint8_t directcntl;
>  };
>  
> -static uint32_t ppc4xx_i2c_readb (void *opaque, target_phys_addr_t addr)
> +static uint32_t ppc4xx_i2c_readb (void *opaque, hwaddr addr)
>  {
>      ppc4xx_i2c_t *i2c;
>      uint32_t ret;
> @@ -1078,7 +1078,7 @@ static uint32_t ppc4xx_i2c_readb (void *opaque, target_phys_addr_t addr)
>  }
>  
>  static void ppc4xx_i2c_writeb (void *opaque,
> -                               target_phys_addr_t addr, uint32_t value)
> +                               hwaddr addr, uint32_t value)
>  {
>      ppc4xx_i2c_t *i2c;
>  
> @@ -1137,7 +1137,7 @@ static void ppc4xx_i2c_writeb (void *opaque,
>      }
>  }
>  
> -static uint32_t ppc4xx_i2c_readw (void *opaque, target_phys_addr_t addr)
> +static uint32_t ppc4xx_i2c_readw (void *opaque, hwaddr addr)
>  {
>      uint32_t ret;
>  
> @@ -1151,7 +1151,7 @@ static uint32_t ppc4xx_i2c_readw (void *opaque, target_phys_addr_t addr)
>  }
>  
>  static void ppc4xx_i2c_writew (void *opaque,
> -                               target_phys_addr_t addr, uint32_t value)
> +                               hwaddr addr, uint32_t value)
>  {
>  #ifdef DEBUG_I2C
>      printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
> @@ -1161,7 +1161,7 @@ static void ppc4xx_i2c_writew (void *opaque,
>      ppc4xx_i2c_writeb(opaque, addr + 1, value);
>  }
>  
> -static uint32_t ppc4xx_i2c_readl (void *opaque, target_phys_addr_t addr)
> +static uint32_t ppc4xx_i2c_readl (void *opaque, hwaddr addr)
>  {
>      uint32_t ret;
>  
> @@ -1177,7 +1177,7 @@ static uint32_t ppc4xx_i2c_readl (void *opaque, target_phys_addr_t addr)
>  }
>  
>  static void ppc4xx_i2c_writel (void *opaque,
> -                               target_phys_addr_t addr, uint32_t value)
> +                               hwaddr addr, uint32_t value)
>  {
>  #ifdef DEBUG_I2C
>      printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
> @@ -1213,7 +1213,7 @@ static void ppc4xx_i2c_reset (void *opaque)
>      i2c->directcntl = 0x0F;
>  }
>  
> -static void ppc405_i2c_init(target_phys_addr_t base, qemu_irq irq)
> +static void ppc405_i2c_init(hwaddr base, qemu_irq irq)
>  {
>      ppc4xx_i2c_t *i2c;
>  
> @@ -1245,7 +1245,7 @@ struct ppc4xx_gpt_t {
>      uint32_t mask[5];
>  };
>  
> -static uint32_t ppc4xx_gpt_readb (void *opaque, target_phys_addr_t addr)
> +static uint32_t ppc4xx_gpt_readb (void *opaque, hwaddr addr)
>  {
>  #ifdef DEBUG_GPT
>      printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
> @@ -1255,7 +1255,7 @@ static uint32_t ppc4xx_gpt_readb (void *opaque, target_phys_addr_t addr)
>  }
>  
>  static void ppc4xx_gpt_writeb (void *opaque,
> -                               target_phys_addr_t addr, uint32_t value)
> +                               hwaddr addr, uint32_t value)
>  {
>  #ifdef DEBUG_I2C
>      printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
> @@ -1264,7 +1264,7 @@ static void ppc4xx_gpt_writeb (void *opaque,
>      /* XXX: generate a bus fault */
>  }
>  
> -static uint32_t ppc4xx_gpt_readw (void *opaque, target_phys_addr_t addr)
> +static uint32_t ppc4xx_gpt_readw (void *opaque, hwaddr addr)
>  {
>  #ifdef DEBUG_GPT
>      printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
> @@ -1274,7 +1274,7 @@ static uint32_t ppc4xx_gpt_readw (void *opaque, target_phys_addr_t addr)
>  }
>  
>  static void ppc4xx_gpt_writew (void *opaque,
> -                               target_phys_addr_t addr, uint32_t value)
> +                               hwaddr addr, uint32_t value)
>  {
>  #ifdef DEBUG_I2C
>      printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
> @@ -1335,7 +1335,7 @@ static void ppc4xx_gpt_compute_timer (ppc4xx_gpt_t *gpt)
>      /* XXX: TODO */
>  }
>  
> -static uint32_t ppc4xx_gpt_readl (void *opaque, target_phys_addr_t addr)
> +static uint32_t ppc4xx_gpt_readl (void *opaque, hwaddr addr)
>  {
>      ppc4xx_gpt_t *gpt;
>      uint32_t ret;
> @@ -1391,7 +1391,7 @@ static uint32_t ppc4xx_gpt_readl (void *opaque, target_phys_addr_t addr)
>  }
>  
>  static void ppc4xx_gpt_writel (void *opaque,
> -                               target_phys_addr_t addr, uint32_t value)
> +                               hwaddr addr, uint32_t value)
>  {
>      ppc4xx_gpt_t *gpt;
>      int idx;
> @@ -1488,7 +1488,7 @@ static void ppc4xx_gpt_reset (void *opaque)
>      }
>  }
>  
> -static void ppc4xx_gpt_init(target_phys_addr_t base, qemu_irq irqs[5])
> +static void ppc4xx_gpt_init(hwaddr base, qemu_irq irqs[5])
>  {
>      ppc4xx_gpt_t *gpt;
>      int i;
> @@ -2104,8 +2104,8 @@ static void ppc405cr_cpc_init (CPUPPCState *env, clk_setup_t clk_setup[7],
>  
>  CPUPPCState *ppc405cr_init(MemoryRegion *address_space_mem,
>                          MemoryRegion ram_memories[4],
> -                        target_phys_addr_t ram_bases[4],
> -                        target_phys_addr_t ram_sizes[4],
> +                        hwaddr ram_bases[4],
> +                        hwaddr ram_sizes[4],
>                          uint32_t sysclk, qemu_irq **picp,
>                          int do_init)
>  {
> @@ -2453,8 +2453,8 @@ static void ppc405ep_cpc_init (CPUPPCState *env, clk_setup_t clk_setup[8],
>  
>  CPUPPCState *ppc405ep_init(MemoryRegion *address_space_mem,
>                          MemoryRegion ram_memories[2],
> -                        target_phys_addr_t ram_bases[2],
> -                        target_phys_addr_t ram_sizes[2],
> +                        hwaddr ram_bases[2],
> +                        hwaddr ram_sizes[2],
>                          uint32_t sysclk, qemu_irq **picp,
>                          int do_init)
>  {
> diff --git a/hw/ppc440_bamboo.c b/hw/ppc440_bamboo.c
> index 5616a26..a6b1d51 100644
> --- a/hw/ppc440_bamboo.c
> +++ b/hw/ppc440_bamboo.c
> @@ -49,12 +49,12 @@
>      256<<20, 128<<20, 64<<20, 32<<20, 16<<20, 8<<20, 0
>  };
>  
> -static target_phys_addr_t entry;
> +static hwaddr entry;
>  
> -static int bamboo_load_device_tree(target_phys_addr_t addr,
> +static int bamboo_load_device_tree(hwaddr addr,
>                                       uint32_t ramsize,
> -                                     target_phys_addr_t initrd_base,
> -                                     target_phys_addr_t initrd_size,
> +                                     hwaddr initrd_base,
> +                                     hwaddr initrd_size,
>                                       const char *kernel_cmdline)
>  {
>      int ret = -1;
> @@ -123,7 +123,7 @@ static int bamboo_load_device_tree(target_phys_addr_t addr,
>  /* Create reset TLB entries for BookE, spanning the 32bit addr space.  */
>  static void mmubooke_create_initial_mapping(CPUPPCState *env,
>                                       target_ulong va,
> -                                     target_phys_addr_t pa)
> +                                     hwaddr pa)
>  {
>      ppcemb_tlb_t *tlb = &env->tlb.tlbe[0];
>  
> @@ -168,8 +168,8 @@ static void bamboo_init(QEMUMachineInitArgs *args)
>      MemoryRegion *address_space_mem = get_system_memory();
>      MemoryRegion *ram_memories
>          = g_malloc(PPC440EP_SDRAM_NR_BANKS * sizeof(*ram_memories));
> -    target_phys_addr_t ram_bases[PPC440EP_SDRAM_NR_BANKS];
> -    target_phys_addr_t ram_sizes[PPC440EP_SDRAM_NR_BANKS];
> +    hwaddr ram_bases[PPC440EP_SDRAM_NR_BANKS];
> +    hwaddr ram_sizes[PPC440EP_SDRAM_NR_BANKS];
>      qemu_irq *pic;
>      qemu_irq *irqs;
>      PCIBus *pcibus;
> @@ -177,7 +177,7 @@ static void bamboo_init(QEMUMachineInitArgs *args)
>      CPUPPCState *env;
>      uint64_t elf_entry;
>      uint64_t elf_lowaddr;
> -    target_phys_addr_t loadaddr = 0;
> +    hwaddr loadaddr = 0;
>      target_long initrd_size = 0;
>      DeviceState *dev;
>      int success;
> diff --git a/hw/ppc4xx.h b/hw/ppc4xx.h
> index 5cd78b6..d795ced 100644
> --- a/hw/ppc4xx.h
> +++ b/hw/ppc4xx.h
> @@ -43,22 +43,22 @@ qemu_irq *ppcuic_init (CPUPPCState *env, qemu_irq *irqs,
>  
>  ram_addr_t ppc4xx_sdram_adjust(ram_addr_t ram_size, int nr_banks,
>                                 MemoryRegion ram_memories[],
> -                               target_phys_addr_t ram_bases[],
> -                               target_phys_addr_t ram_sizes[],
> +                               hwaddr ram_bases[],
> +                               hwaddr ram_sizes[],
>                                 const unsigned int sdram_bank_sizes[]);
>  
>  void ppc4xx_sdram_init (CPUPPCState *env, qemu_irq irq, int nbanks,
>                          MemoryRegion ram_memories[],
> -                        target_phys_addr_t *ram_bases,
> -                        target_phys_addr_t *ram_sizes,
> +                        hwaddr *ram_bases,
> +                        hwaddr *ram_sizes,
>                          int do_init);
>  
>  #define TYPE_PPC4xx_PCI_HOST_BRIDGE "ppc4xx-pcihost"
>  
>  PCIBus *ppc4xx_pci_init(CPUPPCState *env, qemu_irq pci_irqs[4],
> -                        target_phys_addr_t config_space,
> -                        target_phys_addr_t int_ack,
> -                        target_phys_addr_t special_cycle,
> -                        target_phys_addr_t registers);
> +                        hwaddr config_space,
> +                        hwaddr int_ack,
> +                        hwaddr special_cycle,
> +                        hwaddr registers);
>  
>  #endif /* !defined(PPC_4XX_H) */
> diff --git a/hw/ppc4xx_devs.c b/hw/ppc4xx_devs.c
> index 41163e6..bac8d87 100644
> --- a/hw/ppc4xx_devs.c
> +++ b/hw/ppc4xx_devs.c
> @@ -326,8 +326,8 @@ struct ppc4xx_sdram_t {
>      int nbanks;
>      MemoryRegion containers[4]; /* used for clipping */
>      MemoryRegion *ram_memories;
> -    target_phys_addr_t ram_bases[4];
> -    target_phys_addr_t ram_sizes[4];
> +    hwaddr ram_bases[4];
> +    hwaddr ram_sizes[4];
>      uint32_t besr0;
>      uint32_t besr1;
>      uint32_t bear;
> @@ -348,11 +348,11 @@ enum {
>  };
>  
>  /* XXX: TOFIX: some patches have made this code become inconsistent:
> - *      there are type inconsistencies, mixing target_phys_addr_t, target_ulong
> + *      there are type inconsistencies, mixing hwaddr, target_ulong
>   *      and uint32_t
>   */
> -static uint32_t sdram_bcr (target_phys_addr_t ram_base,
> -                           target_phys_addr_t ram_size)
> +static uint32_t sdram_bcr (hwaddr ram_base,
> +                           hwaddr ram_size)
>  {
>      uint32_t bcr;
>  
> @@ -389,7 +389,7 @@ static uint32_t sdram_bcr (target_phys_addr_t ram_base,
>      return bcr;
>  }
>  
> -static inline target_phys_addr_t sdram_base(uint32_t bcr)
> +static inline hwaddr sdram_base(uint32_t bcr)
>  {
>      return bcr & 0xFF800000;
>  }
> @@ -646,8 +646,8 @@ static void sdram_reset (void *opaque)
>  
>  void ppc4xx_sdram_init (CPUPPCState *env, qemu_irq irq, int nbanks,
>                          MemoryRegion *ram_memories,
> -                        target_phys_addr_t *ram_bases,
> -                        target_phys_addr_t *ram_sizes,
> +                        hwaddr *ram_bases,
> +                        hwaddr *ram_sizes,
>                          int do_init)
>  {
>      ppc4xx_sdram_t *sdram;
> @@ -656,12 +656,12 @@ void ppc4xx_sdram_init (CPUPPCState *env, qemu_irq irq, int nbanks,
>      sdram->irq = irq;
>      sdram->nbanks = nbanks;
>      sdram->ram_memories = ram_memories;
> -    memset(sdram->ram_bases, 0, 4 * sizeof(target_phys_addr_t));
> +    memset(sdram->ram_bases, 0, 4 * sizeof(hwaddr));
>      memcpy(sdram->ram_bases, ram_bases,
> -           nbanks * sizeof(target_phys_addr_t));
> -    memset(sdram->ram_sizes, 0, 4 * sizeof(target_phys_addr_t));
> +           nbanks * sizeof(hwaddr));
> +    memset(sdram->ram_sizes, 0, 4 * sizeof(hwaddr));
>      memcpy(sdram->ram_sizes, ram_sizes,
> -           nbanks * sizeof(target_phys_addr_t));
> +           nbanks * sizeof(hwaddr));
>      qemu_register_reset(&sdram_reset, sdram);
>      ppc_dcr_register(env, SDRAM0_CFGADDR,
>                       sdram, &dcr_read_sdram, &dcr_write_sdram);
> @@ -680,8 +680,8 @@ void ppc4xx_sdram_init (CPUPPCState *env, qemu_irq irq, int nbanks,
>   * sizes varies by SoC. */
>  ram_addr_t ppc4xx_sdram_adjust(ram_addr_t ram_size, int nr_banks,
>                                 MemoryRegion ram_memories[],
> -                               target_phys_addr_t ram_bases[],
> -                               target_phys_addr_t ram_sizes[],
> +                               hwaddr ram_bases[],
> +                               hwaddr ram_sizes[],
>                                 const unsigned int sdram_bank_sizes[])
>  {
>      ram_addr_t size_left = ram_size;
> diff --git a/hw/ppc4xx_pci.c b/hw/ppc4xx_pci.c
> index a14fd42..d3ad6a0 100644
> --- a/hw/ppc4xx_pci.c
> +++ b/hw/ppc4xx_pci.c
> @@ -92,7 +92,7 @@ struct PPC4xxPCIState {
>  
>  #define PCI_ALL_SIZE        (PCI_REG_BASE + PCI_REG_SIZE)
>  
> -static uint64_t pci4xx_cfgaddr_read(void *opaque, target_phys_addr_t addr,
> +static uint64_t pci4xx_cfgaddr_read(void *opaque, hwaddr addr,
>                                      unsigned size)
>  {
>      PPC4xxPCIState *ppc4xx_pci = opaque;
> @@ -101,7 +101,7 @@ static uint64_t pci4xx_cfgaddr_read(void *opaque, target_phys_addr_t addr,
>      return phb->config_reg;
>  }
>  
> -static void pci4xx_cfgaddr_write(void *opaque, target_phys_addr_t addr,
> +static void pci4xx_cfgaddr_write(void *opaque, hwaddr addr,
>                                    uint64_t value, unsigned size)
>  {
>      PPC4xxPCIState *ppc4xx_pci = opaque;
> @@ -116,7 +116,7 @@ static void pci4xx_cfgaddr_write(void *opaque, target_phys_addr_t addr,
>      .endianness = DEVICE_LITTLE_ENDIAN,
>  };
>  
> -static void ppc4xx_pci_reg_write4(void *opaque, target_phys_addr_t offset,
> +static void ppc4xx_pci_reg_write4(void *opaque, hwaddr offset,
>                                    uint64_t value, unsigned size)
>  {
>      struct PPC4xxPCIState *pci = opaque;
> @@ -184,7 +184,7 @@ static void ppc4xx_pci_reg_write4(void *opaque, target_phys_addr_t offset,
>      }
>  }
>  
> -static uint64_t ppc4xx_pci_reg_read4(void *opaque, target_phys_addr_t offset,
> +static uint64_t ppc4xx_pci_reg_read4(void *opaque, hwaddr offset,
>                                       unsigned size)
>  {
>      struct PPC4xxPCIState *pci = opaque;
> diff --git a/hw/ppc_mac.h b/hw/ppc_mac.h
> index 7d08418..524b236 100644
> --- a/hw/ppc_mac.h
> +++ b/hw/ppc_mac.h
> @@ -71,10 +71,10 @@ PCIBus *pci_pmac_u3_init(qemu_irq *pic,
>  /* Mac NVRAM */
>  typedef struct MacIONVRAMState MacIONVRAMState;
>  
> -MacIONVRAMState *macio_nvram_init (target_phys_addr_t size,
> +MacIONVRAMState *macio_nvram_init (hwaddr size,
>                                     unsigned int it_shift);
>  void macio_nvram_setup_bar(MacIONVRAMState *s, MemoryRegion *bar,
> -                           target_phys_addr_t mem_base);
> +                           hwaddr mem_base);
>  void pmac_format_nvram_partition (MacIONVRAMState *nvr, int len);
>  uint32_t macio_nvram_read (void *opaque, uint32_t addr);
>  void macio_nvram_write (void *opaque, uint32_t addr, uint32_t val);
> diff --git a/hw/ppc_newworld.c b/hw/ppc_newworld.c
> index a265445..15f74f9 100644
> --- a/hw/ppc_newworld.c
> +++ b/hw/ppc_newworld.c
> @@ -82,13 +82,13 @@
>  #endif
>  
>  /* UniN device */
> -static void unin_write(void *opaque, target_phys_addr_t addr, uint64_t value,
> +static void unin_write(void *opaque, hwaddr addr, uint64_t value,
>                         unsigned size)
>  {
>      UNIN_DPRINTF("write addr " TARGET_FMT_plx " val %"PRIx64"\n", addr, value);
>  }
>  
> -static uint64_t unin_read(void *opaque, target_phys_addr_t addr, unsigned size)
> +static uint64_t unin_read(void *opaque, hwaddr addr, unsigned size)
>  {
>      uint32_t value;
>  
> @@ -115,7 +115,7 @@ static uint64_t translate_kernel_address(void *opaque, uint64_t addr)
>      return (addr & 0x0fffffff) + KERNEL_LOAD_ADDR;
>  }
>  
> -static target_phys_addr_t round_page(target_phys_addr_t addr)
> +static hwaddr round_page(hwaddr addr)
>  {
>      return (addr + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK;
>  }
> @@ -143,7 +143,7 @@ static void ppc_core99_init(QEMUMachineInitArgs *args)
>      MemoryRegion *unin_memory = g_new(MemoryRegion, 1);
>      int linux_boot, i;
>      MemoryRegion *ram = g_new(MemoryRegion, 1), *bios = g_new(MemoryRegion, 1);
> -    target_phys_addr_t kernel_base, initrd_base, cmdline_base = 0;
> +    hwaddr kernel_base, initrd_base, cmdline_base = 0;
>      long kernel_size, initrd_size;
>      PCIBus *pci_bus;
>      MacIONVRAMState *nvr;
> diff --git a/hw/ppc_oldworld.c b/hw/ppc_oldworld.c
> index de33408..a4f899d 100644
> --- a/hw/ppc_oldworld.c
> +++ b/hw/ppc_oldworld.c
> @@ -59,7 +59,7 @@ static uint64_t translate_kernel_address(void *opaque, uint64_t addr)
>      return (addr & 0x0fffffff) + KERNEL_LOAD_ADDR;
>  }
>  
> -static target_phys_addr_t round_page(target_phys_addr_t addr)
> +static hwaddr round_page(hwaddr addr)
>  {
>      return (addr + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK;
>  }
> diff --git a/hw/ppc_prep.c b/hw/ppc_prep.c
> index a0d1c3d..085851a 100644
> --- a/hw/ppc_prep.c
> +++ b/hw/ppc_prep.c
> @@ -115,27 +115,27 @@
>  } XCSR;
>  
>  static void PPC_XCSR_writeb (void *opaque,
> -                             target_phys_addr_t addr, uint32_t value)
> +                             hwaddr addr, uint32_t value)
>  {
>      printf("%s: 0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", __func__, addr,
>             value);
>  }
>  
>  static void PPC_XCSR_writew (void *opaque,
> -                             target_phys_addr_t addr, uint32_t value)
> +                             hwaddr addr, uint32_t value)
>  {
>      printf("%s: 0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", __func__, addr,
>             value);
>  }
>  
>  static void PPC_XCSR_writel (void *opaque,
> -                             target_phys_addr_t addr, uint32_t value)
> +                             hwaddr addr, uint32_t value)
>  {
>      printf("%s: 0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", __func__, addr,
>             value);
>  }
>  
> -static uint32_t PPC_XCSR_readb (void *opaque, target_phys_addr_t addr)
> +static uint32_t PPC_XCSR_readb (void *opaque, hwaddr addr)
>  {
>      uint32_t retval = 0;
>  
> @@ -145,7 +145,7 @@ static uint32_t PPC_XCSR_readb (void *opaque, target_phys_addr_t addr)
>      return retval;
>  }
>  
> -static uint32_t PPC_XCSR_readw (void *opaque, target_phys_addr_t addr)
> +static uint32_t PPC_XCSR_readw (void *opaque, hwaddr addr)
>  {
>      uint32_t retval = 0;
>  
> @@ -155,7 +155,7 @@ static uint32_t PPC_XCSR_readw (void *opaque, target_phys_addr_t addr)
>      return retval;
>  }
>  
> -static uint32_t PPC_XCSR_readl (void *opaque, target_phys_addr_t addr)
> +static uint32_t PPC_XCSR_readl (void *opaque, hwaddr addr)
>  {
>      uint32_t retval = 0;
>  
> @@ -343,8 +343,8 @@ static uint32_t PREP_io_800_readb (void *opaque, uint32_t addr)
>      return retval;
>  }
>  
> -static inline target_phys_addr_t prep_IO_address(sysctrl_t *sysctrl,
> -                                                 target_phys_addr_t addr)
> +static inline hwaddr prep_IO_address(sysctrl_t *sysctrl,
> +                                                 hwaddr addr)
>  {
>      if (sysctrl->contiguous_map == 0) {
>          /* 64 KB contiguous space for IOs */
> @@ -357,7 +357,7 @@ static inline target_phys_addr_t prep_IO_address(sysctrl_t *sysctrl,
>      return addr;
>  }
>  
> -static void PPC_prep_io_writeb (void *opaque, target_phys_addr_t addr,
> +static void PPC_prep_io_writeb (void *opaque, hwaddr addr,
>                                  uint32_t value)
>  {
>      sysctrl_t *sysctrl = opaque;
> @@ -366,7 +366,7 @@ static void PPC_prep_io_writeb (void *opaque, target_phys_addr_t addr,
>      cpu_outb(addr, value);
>  }
>  
> -static uint32_t PPC_prep_io_readb (void *opaque, target_phys_addr_t addr)
> +static uint32_t PPC_prep_io_readb (void *opaque, hwaddr addr)
>  {
>      sysctrl_t *sysctrl = opaque;
>      uint32_t ret;
> @@ -377,7 +377,7 @@ static uint32_t PPC_prep_io_readb (void *opaque, target_phys_addr_t addr)
>      return ret;
>  }
>  
> -static void PPC_prep_io_writew (void *opaque, target_phys_addr_t addr,
> +static void PPC_prep_io_writew (void *opaque, hwaddr addr,
>                                  uint32_t value)
>  {
>      sysctrl_t *sysctrl = opaque;
> @@ -387,7 +387,7 @@ static void PPC_prep_io_writew (void *opaque, target_phys_addr_t addr,
>      cpu_outw(addr, value);
>  }
>  
> -static uint32_t PPC_prep_io_readw (void *opaque, target_phys_addr_t addr)
> +static uint32_t PPC_prep_io_readw (void *opaque, hwaddr addr)
>  {
>      sysctrl_t *sysctrl = opaque;
>      uint32_t ret;
> @@ -399,7 +399,7 @@ static uint32_t PPC_prep_io_readw (void *opaque, target_phys_addr_t addr)
>      return ret;
>  }
>  
> -static void PPC_prep_io_writel (void *opaque, target_phys_addr_t addr,
> +static void PPC_prep_io_writel (void *opaque, hwaddr addr,
>                                  uint32_t value)
>  {
>      sysctrl_t *sysctrl = opaque;
> @@ -409,7 +409,7 @@ static void PPC_prep_io_writel (void *opaque, target_phys_addr_t addr,
>      cpu_outl(addr, value);
>  }
>  
> -static uint32_t PPC_prep_io_readl (void *opaque, target_phys_addr_t addr)
> +static uint32_t PPC_prep_io_readl (void *opaque, hwaddr addr)
>  {
>      sysctrl_t *sysctrl = opaque;
>      uint32_t ret;
> @@ -525,7 +525,7 @@ static void ppc_prep_init(QEMUMachineInitArgs *args)
>          bios_size = -1;
>      }
>      if (bios_size > 0 && bios_size <= BIOS_SIZE) {
> -        target_phys_addr_t bios_addr;
> +        hwaddr bios_addr;
>          bios_size = (bios_size + 0xfff) & ~0xfff;
>          bios_addr = (uint32_t)(-bios_size);
>          bios_size = load_image_targphys(filename, bios_addr, bios_size);
> diff --git a/hw/ppce500_pci.c b/hw/ppce500_pci.c
> index 92b1dc0..332748a 100644
> --- a/hw/ppce500_pci.c
> +++ b/hw/ppce500_pci.c
> @@ -91,7 +91,7 @@ struct PPCE500PCIState {
>  
>  typedef struct PPCE500PCIState PPCE500PCIState;
>  
> -static uint64_t pci_reg_read4(void *opaque, target_phys_addr_t addr,
> +static uint64_t pci_reg_read4(void *opaque, hwaddr addr,
>                                unsigned size)
>  {
>      PPCE500PCIState *pci = opaque;
> @@ -160,7 +160,7 @@ static uint64_t pci_reg_read4(void *opaque, target_phys_addr_t addr,
>      return value;
>  }
>  
> -static void pci_reg_write4(void *opaque, target_phys_addr_t addr,
> +static void pci_reg_write4(void *opaque, hwaddr addr,
>                             uint64_t value, unsigned size)
>  {
>      PPCE500PCIState *pci = opaque;
> diff --git a/hw/ppce500_spin.c b/hw/ppce500_spin.c
> index c5b8e05..55aa9dc 100644
> --- a/hw/ppce500_spin.c
> +++ b/hw/ppce500_spin.c
> @@ -68,18 +68,18 @@ static void spin_reset(void *opaque)
>  }
>  
>  /* Create -kernel TLB entries for BookE, linearly spanning 256MB.  */
> -static inline target_phys_addr_t booke206_page_size_to_tlb(uint64_t size)
> +static inline hwaddr booke206_page_size_to_tlb(uint64_t size)
>  {
>      return (ffs(size >> 10) - 1) >> 1;
>  }
>  
>  static void mmubooke_create_initial_mapping(CPUPPCState *env,
>                                       target_ulong va,
> -                                     target_phys_addr_t pa,
> -                                     target_phys_addr_t len)
> +                                     hwaddr pa,
> +                                     hwaddr len)
>  {
>      ppcmas_tlb_t *tlb = booke206_get_tlbm(env, 1, 0, 1);
> -    target_phys_addr_t size;
> +    hwaddr size;
>  
>      size = (booke206_page_size_to_tlb(len) << MAS1_TSIZE_SHIFT);
>      tlb->mas1 = MAS1_VALID | size;
> @@ -94,8 +94,8 @@ static void spin_kick(void *data)
>      SpinKick *kick = data;
>      CPUPPCState *env = kick->env;
>      SpinInfo *curspin = kick->spin;
> -    target_phys_addr_t map_size = 64 * 1024 * 1024;
> -    target_phys_addr_t map_start;
> +    hwaddr map_size = 64 * 1024 * 1024;
> +    hwaddr map_start;
>  
>      cpu_synchronize_state(env);
>      stl_p(&curspin->pir, env->spr[SPR_PIR]);
> @@ -117,7 +117,7 @@ static void spin_kick(void *data)
>      qemu_cpu_kick(env);
>  }
>  
> -static void spin_write(void *opaque, target_phys_addr_t addr, uint64_t value,
> +static void spin_write(void *opaque, hwaddr addr, uint64_t value,
>                         unsigned len)
>  {
>      SpinState *s = opaque;
> @@ -166,7 +166,7 @@ static void spin_write(void *opaque, target_phys_addr_t addr, uint64_t value,
>      }
>  }
>  
> -static uint64_t spin_read(void *opaque, target_phys_addr_t addr, unsigned len)
> +static uint64_t spin_read(void *opaque, hwaddr addr, unsigned len)
>  {
>      SpinState *s = opaque;
>      uint8_t *spin_p = &((uint8_t*)s->spin)[addr];
> diff --git a/hw/prep_pci.c b/hw/prep_pci.c
> index cc44e61..0bc479c 100644
> --- a/hw/prep_pci.c
> +++ b/hw/prep_pci.c
> @@ -44,7 +44,7 @@
>      PCIDevice dev;
>  } RavenPCIState;
>  
> -static inline uint32_t PPC_PCIIO_config(target_phys_addr_t addr)
> +static inline uint32_t PPC_PCIIO_config(hwaddr addr)
>  {
>      int i;
>  
> @@ -56,7 +56,7 @@ static inline uint32_t PPC_PCIIO_config(target_phys_addr_t addr)
>      return (addr & 0x7ff) |  (i << 11);
>  }
>  
> -static void ppc_pci_io_write(void *opaque, target_phys_addr_t addr,
> +static void ppc_pci_io_write(void *opaque, hwaddr addr,
>                               uint64_t val, unsigned int size)
>  {
>      PREPPCIState *s = opaque;
> @@ -64,7 +64,7 @@ static void ppc_pci_io_write(void *opaque, target_phys_addr_t addr,
>      pci_data_write(phb->bus, PPC_PCIIO_config(addr), val, size);
>  }
>  
> -static uint64_t ppc_pci_io_read(void *opaque, target_phys_addr_t addr,
> +static uint64_t ppc_pci_io_read(void *opaque, hwaddr addr,
>                                  unsigned int size)
>  {
>      PREPPCIState *s = opaque;
> @@ -78,7 +78,7 @@ static uint64_t ppc_pci_io_read(void *opaque, target_phys_addr_t addr,
>      .endianness = DEVICE_LITTLE_ENDIAN,
>  };
>  
> -static uint64_t ppc_intack_read(void *opaque, target_phys_addr_t addr,
> +static uint64_t ppc_intack_read(void *opaque, hwaddr addr,
>                                  unsigned int size)
>  {
>      return pic_read_irq(isa_pic);
> diff --git a/hw/puv3_dma.c b/hw/puv3_dma.c
> index 85b97bf..9de63b4 100644
> --- a/hw/puv3_dma.c
> +++ b/hw/puv3_dma.c
> @@ -24,7 +24,7 @@
>      uint32_t reg_CFG[PUV3_DMA_CH_NR];
>  } PUV3DMAState;
>  
> -static uint64_t puv3_dma_read(void *opaque, target_phys_addr_t offset,
> +static uint64_t puv3_dma_read(void *opaque, hwaddr offset,
>          unsigned size)
>  {
>      PUV3DMAState *s = opaque;
> @@ -44,7 +44,7 @@ static uint64_t puv3_dma_read(void *opaque, target_phys_addr_t offset,
>      return ret;
>  }
>  
> -static void puv3_dma_write(void *opaque, target_phys_addr_t offset,
> +static void puv3_dma_write(void *opaque, hwaddr offset,
>          uint64_t value, unsigned size)
>  {
>      PUV3DMAState *s = opaque;
> diff --git a/hw/puv3_gpio.c b/hw/puv3_gpio.c
> index 9436e6c..152248d 100644
> --- a/hw/puv3_gpio.c
> +++ b/hw/puv3_gpio.c
> @@ -24,7 +24,7 @@
>      uint32_t reg_GPIR;
>  } PUV3GPIOState;
>  
> -static uint64_t puv3_gpio_read(void *opaque, target_phys_addr_t offset,
> +static uint64_t puv3_gpio_read(void *opaque, hwaddr offset,
>          unsigned size)
>  {
>      PUV3GPIOState *s = opaque;
> @@ -48,7 +48,7 @@ static uint64_t puv3_gpio_read(void *opaque, target_phys_addr_t offset,
>      return ret;
>  }
>  
> -static void puv3_gpio_write(void *opaque, target_phys_addr_t offset,
> +static void puv3_gpio_write(void *opaque, hwaddr offset,
>          uint64_t value, unsigned size)
>  {
>      PUV3GPIOState *s = opaque;
> diff --git a/hw/puv3_intc.c b/hw/puv3_intc.c
> index 9e0b975..07f5649 100644
> --- a/hw/puv3_intc.c
> +++ b/hw/puv3_intc.c
> @@ -46,7 +46,7 @@ static void puv3_intc_handler(void *opaque, int irq, int level)
>      puv3_intc_update(s);
>  }
>  
> -static uint64_t puv3_intc_read(void *opaque, target_phys_addr_t offset,
> +static uint64_t puv3_intc_read(void *opaque, hwaddr offset,
>          unsigned size)
>  {
>      PUV3INTCState *s = opaque;
> @@ -66,7 +66,7 @@ static uint64_t puv3_intc_read(void *opaque, target_phys_addr_t offset,
>      return ret;
>  }
>  
> -static void puv3_intc_write(void *opaque, target_phys_addr_t offset,
> +static void puv3_intc_write(void *opaque, hwaddr offset,
>          uint64_t value, unsigned size)
>  {
>      PUV3INTCState *s = opaque;
> diff --git a/hw/puv3_ost.c b/hw/puv3_ost.c
> index dd30cad..14c6f21 100644
> --- a/hw/puv3_ost.c
> +++ b/hw/puv3_ost.c
> @@ -28,7 +28,7 @@
>      uint32_t reg_OIER;
>  } PUV3OSTState;
>  
> -static uint64_t puv3_ost_read(void *opaque, target_phys_addr_t offset,
> +static uint64_t puv3_ost_read(void *opaque, hwaddr offset,
>          unsigned size)
>  {
>      PUV3OSTState *s = opaque;
> @@ -51,7 +51,7 @@ static uint64_t puv3_ost_read(void *opaque, target_phys_addr_t offset,
>      return ret;
>  }
>  
> -static void puv3_ost_write(void *opaque, target_phys_addr_t offset,
> +static void puv3_ost_write(void *opaque, hwaddr offset,
>          uint64_t value, unsigned size)
>  {
>      PUV3OSTState *s = opaque;
> diff --git a/hw/puv3_pm.c b/hw/puv3_pm.c
> index 621c968..87a687a 100644
> --- a/hw/puv3_pm.c
> +++ b/hw/puv3_pm.c
> @@ -26,7 +26,7 @@
>      uint32_t reg_DIVCFG;
>  } PUV3PMState;
>  
> -static uint64_t puv3_pm_read(void *opaque, target_phys_addr_t offset,
> +static uint64_t puv3_pm_read(void *opaque, hwaddr offset,
>          unsigned size)
>  {
>      PUV3PMState *s = opaque;
> @@ -74,7 +74,7 @@ static uint64_t puv3_pm_read(void *opaque, target_phys_addr_t offset,
>      return ret;
>  }
>  
> -static void puv3_pm_write(void *opaque, target_phys_addr_t offset,
> +static void puv3_pm_write(void *opaque, hwaddr offset,
>          uint64_t value, unsigned size)
>  {
>      PUV3PMState *s = opaque;
> diff --git a/hw/pxa.h b/hw/pxa.h
> index 6a21205..49ac820 100644
> --- a/hw/pxa.h
> +++ b/hw/pxa.h
> @@ -65,28 +65,28 @@
>  # define PXA2XX_INTERNAL_SIZE	0x40000
>  
>  /* pxa2xx_pic.c */
> -DeviceState *pxa2xx_pic_init(target_phys_addr_t base, ARMCPU *cpu);
> +DeviceState *pxa2xx_pic_init(hwaddr base, ARMCPU *cpu);
>  
>  /* pxa2xx_gpio.c */
> -DeviceState *pxa2xx_gpio_init(target_phys_addr_t base,
> +DeviceState *pxa2xx_gpio_init(hwaddr base,
>                  CPUARMState *env, DeviceState *pic, int lines);
>  void pxa2xx_gpio_read_notifier(DeviceState *dev, qemu_irq handler);
>  
>  /* pxa2xx_dma.c */
> -DeviceState *pxa255_dma_init(target_phys_addr_t base, qemu_irq irq);
> -DeviceState *pxa27x_dma_init(target_phys_addr_t base, qemu_irq irq);
> +DeviceState *pxa255_dma_init(hwaddr base, qemu_irq irq);
> +DeviceState *pxa27x_dma_init(hwaddr base, qemu_irq irq);
>  
>  /* pxa2xx_lcd.c */
>  typedef struct PXA2xxLCDState PXA2xxLCDState;
>  PXA2xxLCDState *pxa2xx_lcdc_init(MemoryRegion *sysmem,
> -                target_phys_addr_t base, qemu_irq irq);
> +                hwaddr base, qemu_irq irq);
>  void pxa2xx_lcd_vsync_notifier(PXA2xxLCDState *s, qemu_irq handler);
>  void pxa2xx_lcdc_oritentation(void *opaque, int angle);
>  
>  /* pxa2xx_mmci.c */
>  typedef struct PXA2xxMMCIState PXA2xxMMCIState;
>  PXA2xxMMCIState *pxa2xx_mmci_init(MemoryRegion *sysmem,
> -                target_phys_addr_t base,
> +                hwaddr base,
>                  BlockDriverState *bd, qemu_irq irq,
>                  qemu_irq rx_dma, qemu_irq tx_dma);
>  void pxa2xx_mmci_handlers(PXA2xxMMCIState *s, qemu_irq readonly,
> @@ -95,7 +95,7 @@ void pxa2xx_mmci_handlers(PXA2xxMMCIState *s, qemu_irq readonly,
>  /* pxa2xx_pcmcia.c */
>  typedef struct PXA2xxPCMCIAState PXA2xxPCMCIAState;
>  PXA2xxPCMCIAState *pxa2xx_pcmcia_init(MemoryRegion *sysmem,
> -                                      target_phys_addr_t base);
> +                                      hwaddr base);
>  int pxa2xx_pcmcia_attach(void *opaque, PCMCIACardState *card);
>  int pxa2xx_pcmcia_dettach(void *opaque);
>  void pxa2xx_pcmcia_set_irq_cb(void *opaque, qemu_irq irq, qemu_irq cd_irq);
> @@ -107,14 +107,14 @@ struct  keymap {
>  };
>  typedef struct PXA2xxKeyPadState PXA2xxKeyPadState;
>  PXA2xxKeyPadState *pxa27x_keypad_init(MemoryRegion *sysmem,
> -                                      target_phys_addr_t base,
> +                                      hwaddr base,
>                                        qemu_irq irq);
>  void pxa27x_register_keypad(PXA2xxKeyPadState *kp, struct keymap *map,
>                  int size);
>  
>  /* pxa2xx.c */
>  typedef struct PXA2xxI2CState PXA2xxI2CState;
> -PXA2xxI2CState *pxa2xx_i2c_init(target_phys_addr_t base,
> +PXA2xxI2CState *pxa2xx_i2c_init(hwaddr base,
>                  qemu_irq irq, uint32_t page_size);
>  i2c_bus *pxa2xx_i2c_bus(PXA2xxI2CState *s);
>  
> @@ -142,16 +142,16 @@ typedef struct {
>      PXA2xxKeyPadState *kp;
>  
>      /* Power management */
> -    target_phys_addr_t pm_base;
> +    hwaddr pm_base;
>      uint32_t pm_regs[0x40];
>  
>      /* Clock management */
> -    target_phys_addr_t cm_base;
> +    hwaddr cm_base;
>      uint32_t cm_regs[4];
>      uint32_t clkcfg;
>  
>      /* Memory management */
> -    target_phys_addr_t mm_base;
> +    hwaddr mm_base;
>      uint32_t mm_regs[0x1a];
>  
>      /* Performance monitoring */
> diff --git a/hw/pxa2xx.c b/hw/pxa2xx.c
> index 4ec904f..0fb2179 100644
> --- a/hw/pxa2xx.c
> +++ b/hw/pxa2xx.c
> @@ -17,7 +17,7 @@
>  #include "blockdev.h"
>  
>  static struct {
> -    target_phys_addr_t io_base;
> +    hwaddr io_base;
>      int irqn;
>  } pxa255_serial[] = {
>      { 0x40100000, PXA2XX_PIC_FFUART },
> @@ -33,7 +33,7 @@
>  };
>  
>  typedef struct PXASSPDef {
> -    target_phys_addr_t io_base;
> +    hwaddr io_base;
>      int irqn;
>  } PXASSPDef;
>  
> @@ -88,7 +88,7 @@
>  #define PCMD0	0x80	/* Power Manager I2C Command register File 0 */
>  #define PCMD31	0xfc	/* Power Manager I2C Command register File 31 */
>  
> -static uint64_t pxa2xx_pm_read(void *opaque, target_phys_addr_t addr,
> +static uint64_t pxa2xx_pm_read(void *opaque, hwaddr addr,
>                                 unsigned size)
>  {
>      PXA2xxState *s = (PXA2xxState *) opaque;
> @@ -107,7 +107,7 @@ static uint64_t pxa2xx_pm_read(void *opaque, target_phys_addr_t addr,
>      return 0;
>  }
>  
> -static void pxa2xx_pm_write(void *opaque, target_phys_addr_t addr,
> +static void pxa2xx_pm_write(void *opaque, hwaddr addr,
>                              uint64_t value, unsigned size)
>  {
>      PXA2xxState *s = (PXA2xxState *) opaque;
> @@ -160,7 +160,7 @@ static void pxa2xx_pm_write(void *opaque, target_phys_addr_t addr,
>  #define OSCC	0x08	/* Oscillator Configuration register */
>  #define CCSR	0x0c	/* Core Clock Status register */
>  
> -static uint64_t pxa2xx_cm_read(void *opaque, target_phys_addr_t addr,
> +static uint64_t pxa2xx_cm_read(void *opaque, hwaddr addr,
>                                 unsigned size)
>  {
>      PXA2xxState *s = (PXA2xxState *) opaque;
> @@ -181,7 +181,7 @@ static uint64_t pxa2xx_cm_read(void *opaque, target_phys_addr_t addr,
>      return 0;
>  }
>  
> -static void pxa2xx_cm_write(void *opaque, target_phys_addr_t addr,
> +static void pxa2xx_cm_write(void *opaque, hwaddr addr,
>                              uint64_t value, unsigned size)
>  {
>      PXA2xxState *s = (PXA2xxState *) opaque;
> @@ -405,7 +405,7 @@ static void pxa2xx_setup_cp14(PXA2xxState *s)
>  #define BSCNTR3		0x60	/* Memory Buffer Strength Control register 3 */
>  #define SA1110		0x64	/* SA-1110 Memory Compatibility register */
>  
> -static uint64_t pxa2xx_mm_read(void *opaque, target_phys_addr_t addr,
> +static uint64_t pxa2xx_mm_read(void *opaque, hwaddr addr,
>                                 unsigned size)
>  {
>      PXA2xxState *s = (PXA2xxState *) opaque;
> @@ -422,7 +422,7 @@ static uint64_t pxa2xx_mm_read(void *opaque, target_phys_addr_t addr,
>      return 0;
>  }
>  
> -static void pxa2xx_mm_write(void *opaque, target_phys_addr_t addr,
> +static void pxa2xx_mm_write(void *opaque, hwaddr addr,
>                              uint64_t value, unsigned size)
>  {
>      PXA2xxState *s = (PXA2xxState *) opaque;
> @@ -567,7 +567,7 @@ static void pxa2xx_ssp_fifo_update(PXA2xxSSPState *s)
>      pxa2xx_ssp_int_update(s);
>  }
>  
> -static uint64_t pxa2xx_ssp_read(void *opaque, target_phys_addr_t addr,
> +static uint64_t pxa2xx_ssp_read(void *opaque, hwaddr addr,
>                                  unsigned size)
>  {
>      PXA2xxSSPState *s = (PXA2xxSSPState *) opaque;
> @@ -613,7 +613,7 @@ static uint64_t pxa2xx_ssp_read(void *opaque, target_phys_addr_t addr,
>      return 0;
>  }
>  
> -static void pxa2xx_ssp_write(void *opaque, target_phys_addr_t addr,
> +static void pxa2xx_ssp_write(void *opaque, hwaddr addr,
>                               uint64_t value64, unsigned size)
>  {
>      PXA2xxSSPState *s = (PXA2xxSSPState *) opaque;
> @@ -943,7 +943,7 @@ static inline void pxa2xx_rtc_pi_tick(void *opaque)
>      pxa2xx_rtc_int_update(s);
>  }
>  
> -static uint64_t pxa2xx_rtc_read(void *opaque, target_phys_addr_t addr,
> +static uint64_t pxa2xx_rtc_read(void *opaque, hwaddr addr,
>                                  unsigned size)
>  {
>      PXA2xxRTCState *s = (PXA2xxRTCState *) opaque;
> @@ -989,7 +989,7 @@ static uint64_t pxa2xx_rtc_read(void *opaque, target_phys_addr_t addr,
>      return 0;
>  }
>  
> -static void pxa2xx_rtc_write(void *opaque, target_phys_addr_t addr,
> +static void pxa2xx_rtc_write(void *opaque, hwaddr addr,
>                               uint64_t value64, unsigned size)
>  {
>      PXA2xxRTCState *s = (PXA2xxRTCState *) opaque;
> @@ -1294,7 +1294,7 @@ static int pxa2xx_i2c_tx(I2CSlave *i2c, uint8_t data)
>      return 1;
>  }
>  
> -static uint64_t pxa2xx_i2c_read(void *opaque, target_phys_addr_t addr,
> +static uint64_t pxa2xx_i2c_read(void *opaque, hwaddr addr,
>                                  unsigned size)
>  {
>      PXA2xxI2CState *s = (PXA2xxI2CState *) opaque;
> @@ -1322,7 +1322,7 @@ static uint64_t pxa2xx_i2c_read(void *opaque, target_phys_addr_t addr,
>      return 0;
>  }
>  
> -static void pxa2xx_i2c_write(void *opaque, target_phys_addr_t addr,
> +static void pxa2xx_i2c_write(void *opaque, hwaddr addr,
>                               uint64_t value64, unsigned size)
>  {
>      PXA2xxI2CState *s = (PXA2xxI2CState *) opaque;
> @@ -1449,7 +1449,7 @@ static void pxa2xx_i2c_slave_class_init(ObjectClass *klass, void *data)
>      .class_init    = pxa2xx_i2c_slave_class_init,
>  };
>  
> -PXA2xxI2CState *pxa2xx_i2c_init(target_phys_addr_t base,
> +PXA2xxI2CState *pxa2xx_i2c_init(hwaddr base,
>                  qemu_irq irq, uint32_t region_size)
>  {
>      DeviceState *dev;
> @@ -1572,7 +1572,7 @@ static inline void pxa2xx_i2s_update(PXA2xxI2SState *i2s)
>  #define SADIV	0x60	/* Serial Audio Clock Divider register */
>  #define SADR	0x80	/* Serial Audio Data register */
>  
> -static uint64_t pxa2xx_i2s_read(void *opaque, target_phys_addr_t addr,
> +static uint64_t pxa2xx_i2s_read(void *opaque, hwaddr addr,
>                                  unsigned size)
>  {
>      PXA2xxI2SState *s = (PXA2xxI2SState *) opaque;
> @@ -1604,7 +1604,7 @@ static uint64_t pxa2xx_i2s_read(void *opaque, target_phys_addr_t addr,
>      return 0;
>  }
>  
> -static void pxa2xx_i2s_write(void *opaque, target_phys_addr_t addr,
> +static void pxa2xx_i2s_write(void *opaque, hwaddr addr,
>                               uint64_t value, unsigned size)
>  {
>      PXA2xxI2SState *s = (PXA2xxI2SState *) opaque;
> @@ -1706,7 +1706,7 @@ static void pxa2xx_i2s_data_req(void *opaque, int tx, int rx)
>  }
>  
>  static PXA2xxI2SState *pxa2xx_i2s_init(MemoryRegion *sysmem,
> -                target_phys_addr_t base,
> +                hwaddr base,
>                  qemu_irq irq, qemu_irq rx_dma, qemu_irq tx_dma)
>  {
>      PXA2xxI2SState *s = (PXA2xxI2SState *)
> @@ -1801,7 +1801,7 @@ static inline void pxa2xx_fir_update(PXA2xxFIrState *s)
>  #define ICSR1	0x18	/* FICP Status register 1 */
>  #define ICFOR	0x1c	/* FICP FIFO Occupancy Status register */
>  
> -static uint64_t pxa2xx_fir_read(void *opaque, target_phys_addr_t addr,
> +static uint64_t pxa2xx_fir_read(void *opaque, hwaddr addr,
>                                  unsigned size)
>  {
>      PXA2xxFIrState *s = (PXA2xxFIrState *) opaque;
> @@ -1839,7 +1839,7 @@ static uint64_t pxa2xx_fir_read(void *opaque, target_phys_addr_t addr,
>      return 0;
>  }
>  
> -static void pxa2xx_fir_write(void *opaque, target_phys_addr_t addr,
> +static void pxa2xx_fir_write(void *opaque, hwaddr addr,
>                               uint64_t value64, unsigned size)
>  {
>      PXA2xxFIrState *s = (PXA2xxFIrState *) opaque;
> @@ -1963,7 +1963,7 @@ static int pxa2xx_fir_load(QEMUFile *f, void *opaque, int version_id)
>  }
>  
>  static PXA2xxFIrState *pxa2xx_fir_init(MemoryRegion *sysmem,
> -                target_phys_addr_t base,
> +                hwaddr base,
>                  qemu_irq irq, qemu_irq rx_dma, qemu_irq tx_dma,
>                  CharDriverState *chr)
>  {
> diff --git a/hw/pxa2xx_dma.c b/hw/pxa2xx_dma.c
> index 0310154..dbea1d2 100644
> --- a/hw/pxa2xx_dma.c
> +++ b/hw/pxa2xx_dma.c
> @@ -147,7 +147,7 @@ static inline void pxa2xx_dma_descriptor_fetch(
>                  PXA2xxDMAState *s, int ch)
>  {
>      uint32_t desc[4];
> -    target_phys_addr_t daddr = s->chan[ch].descr & ~0xf;
> +    hwaddr daddr = s->chan[ch].descr & ~0xf;
>      if ((s->chan[ch].descr & DDADR_BREN) && (s->chan[ch].state & DCSR_CMPST))
>          daddr += 32;
>  
> @@ -251,7 +251,7 @@ static void pxa2xx_dma_run(PXA2xxDMAState *s)
>      }
>  }
>  
> -static uint64_t pxa2xx_dma_read(void *opaque, target_phys_addr_t offset,
> +static uint64_t pxa2xx_dma_read(void *opaque, hwaddr offset,
>                                  unsigned size)
>  {
>      PXA2xxDMAState *s = (PXA2xxDMAState *) opaque;
> @@ -310,7 +310,7 @@ static uint64_t pxa2xx_dma_read(void *opaque, target_phys_addr_t offset,
>      return 7;
>  }
>  
> -static void pxa2xx_dma_write(void *opaque, target_phys_addr_t offset,
> +static void pxa2xx_dma_write(void *opaque, hwaddr offset,
>                               uint64_t value, unsigned size)
>  {
>      PXA2xxDMAState *s = (PXA2xxDMAState *) opaque;
> @@ -473,7 +473,7 @@ static int pxa2xx_dma_init(SysBusDevice *dev)
>      return 0;
>  }
>  
> -DeviceState *pxa27x_dma_init(target_phys_addr_t base, qemu_irq irq)
> +DeviceState *pxa27x_dma_init(hwaddr base, qemu_irq irq)
>  {
>      DeviceState *dev;
>  
> @@ -487,7 +487,7 @@ DeviceState *pxa27x_dma_init(target_phys_addr_t base, qemu_irq irq)
>      return dev;
>  }
>  
> -DeviceState *pxa255_dma_init(target_phys_addr_t base, qemu_irq irq)
> +DeviceState *pxa255_dma_init(hwaddr base, qemu_irq irq)
>  {
>      DeviceState *dev;
>  
> diff --git a/hw/pxa2xx_gpio.c b/hw/pxa2xx_gpio.c
> index 3c90c9c..7aaf409 100644
> --- a/hw/pxa2xx_gpio.c
> +++ b/hw/pxa2xx_gpio.c
> @@ -139,7 +139,7 @@ static void pxa2xx_gpio_handler_update(PXA2xxGPIOInfo *s) {
>      }
>  }
>  
> -static uint64_t pxa2xx_gpio_read(void *opaque, target_phys_addr_t offset,
> +static uint64_t pxa2xx_gpio_read(void *opaque, hwaddr offset,
>                                   unsigned size)
>  {
>      PXA2xxGPIOInfo *s = (PXA2xxGPIOInfo *) opaque;
> @@ -191,7 +191,7 @@ static uint64_t pxa2xx_gpio_read(void *opaque, target_phys_addr_t offset,
>      return 0;
>  }
>  
> -static void pxa2xx_gpio_write(void *opaque, target_phys_addr_t offset,
> +static void pxa2xx_gpio_write(void *opaque, hwaddr offset,
>                                uint64_t value, unsigned size)
>  {
>      PXA2xxGPIOInfo *s = (PXA2xxGPIOInfo *) opaque;
> @@ -249,7 +249,7 @@ static void pxa2xx_gpio_write(void *opaque, target_phys_addr_t offset,
>      .endianness = DEVICE_NATIVE_ENDIAN,
>  };
>  
> -DeviceState *pxa2xx_gpio_init(target_phys_addr_t base,
> +DeviceState *pxa2xx_gpio_init(hwaddr base,
>                  CPUARMState *env, DeviceState *pic, int lines)
>  {
>      DeviceState *dev;
> diff --git a/hw/pxa2xx_keypad.c b/hw/pxa2xx_keypad.c
> index 1a997c9..257984c 100644
> --- a/hw/pxa2xx_keypad.c
> +++ b/hw/pxa2xx_keypad.c
> @@ -174,7 +174,7 @@ static void pxa27x_keyboard_event (PXA2xxKeyPadState *kp, int keycode)
>      }
>  }
>  
> -static uint64_t pxa2xx_keypad_read(void *opaque, target_phys_addr_t offset,
> +static uint64_t pxa2xx_keypad_read(void *opaque, hwaddr offset,
>                                     unsigned size)
>  {
>      PXA2xxKeyPadState *s = (PXA2xxKeyPadState *) opaque;
> @@ -236,7 +236,7 @@ static uint64_t pxa2xx_keypad_read(void *opaque, target_phys_addr_t offset,
>      return 0;
>  }
>  
> -static void pxa2xx_keypad_write(void *opaque, target_phys_addr_t offset,
> +static void pxa2xx_keypad_write(void *opaque, hwaddr offset,
>                                  uint64_t value, unsigned size)
>  {
>      PXA2xxKeyPadState *s = (PXA2xxKeyPadState *) opaque;
> @@ -305,7 +305,7 @@ static void pxa2xx_keypad_write(void *opaque, target_phys_addr_t offset,
>  };
>  
>  PXA2xxKeyPadState *pxa27x_keypad_init(MemoryRegion *sysmem,
> -                                      target_phys_addr_t base,
> +                                      hwaddr base,
>                                        qemu_irq irq)
>  {
>      PXA2xxKeyPadState *s;
> diff --git a/hw/pxa2xx_lcd.c b/hw/pxa2xx_lcd.c
> index ee8bf57..38c3889 100644
> --- a/hw/pxa2xx_lcd.c
> +++ b/hw/pxa2xx_lcd.c
> @@ -23,7 +23,7 @@ struct DMAChannel {
>      uint8_t up;
>      uint8_t palette[1024];
>      uint8_t pbuffer[1024];
> -    void (*redraw)(PXA2xxLCDState *s, target_phys_addr_t addr,
> +    void (*redraw)(PXA2xxLCDState *s, hwaddr addr,
>                     int *miny, int *maxy);
>  
>      uint32_t descriptor;
> @@ -291,7 +291,7 @@ static inline void pxa2xx_dma_rdst_set(PXA2xxLCDState *s)
>  static void pxa2xx_descriptor_load(PXA2xxLCDState *s)
>  {
>      PXAFrameDescriptor desc;
> -    target_phys_addr_t descptr;
> +    hwaddr descptr;
>      int i;
>  
>      for (i = 0; i < PXA_LCDDMA_CHANS; i ++) {
> @@ -323,7 +323,7 @@ static void pxa2xx_descriptor_load(PXA2xxLCDState *s)
>      }
>  }
>  
> -static uint64_t pxa2xx_lcdc_read(void *opaque, target_phys_addr_t offset,
> +static uint64_t pxa2xx_lcdc_read(void *opaque, hwaddr offset,
>                                   unsigned size)
>  {
>      PXA2xxLCDState *s = (PXA2xxLCDState *) opaque;
> @@ -417,7 +417,7 @@ static uint64_t pxa2xx_lcdc_read(void *opaque, target_phys_addr_t offset,
>      return 0;
>  }
>  
> -static void pxa2xx_lcdc_write(void *opaque, target_phys_addr_t offset,
> +static void pxa2xx_lcdc_write(void *opaque, hwaddr offset,
>                                uint64_t value, unsigned size)
>  {
>      PXA2xxLCDState *s = (PXA2xxLCDState *) opaque;
> @@ -674,7 +674,7 @@ static void pxa2xx_palette_parse(PXA2xxLCDState *s, int ch, int bpp)
>  }
>  
>  static void pxa2xx_lcdc_dma0_redraw_rot0(PXA2xxLCDState *s,
> -                target_phys_addr_t addr, int *miny, int *maxy)
> +                hwaddr addr, int *miny, int *maxy)
>  {
>      int src_width, dest_width;
>      drawfn fn = NULL;
> @@ -701,7 +701,7 @@ static void pxa2xx_lcdc_dma0_redraw_rot0(PXA2xxLCDState *s,
>  }
>  
>  static void pxa2xx_lcdc_dma0_redraw_rot90(PXA2xxLCDState *s,
> -               target_phys_addr_t addr, int *miny, int *maxy)
> +               hwaddr addr, int *miny, int *maxy)
>  {
>      int src_width, dest_width;
>      drawfn fn = NULL;
> @@ -729,7 +729,7 @@ static void pxa2xx_lcdc_dma0_redraw_rot90(PXA2xxLCDState *s,
>  }
>  
>  static void pxa2xx_lcdc_dma0_redraw_rot180(PXA2xxLCDState *s,
> -                target_phys_addr_t addr, int *miny, int *maxy)
> +                hwaddr addr, int *miny, int *maxy)
>  {
>      int src_width, dest_width;
>      drawfn fn = NULL;
> @@ -759,7 +759,7 @@ static void pxa2xx_lcdc_dma0_redraw_rot180(PXA2xxLCDState *s,
>  }
>  
>  static void pxa2xx_lcdc_dma0_redraw_rot270(PXA2xxLCDState *s,
> -               target_phys_addr_t addr, int *miny, int *maxy)
> +               hwaddr addr, int *miny, int *maxy)
>  {
>      int src_width, dest_width;
>      drawfn fn = NULL;
> @@ -813,7 +813,7 @@ static void pxa2xx_lcdc_resize(PXA2xxLCDState *s)
>  static void pxa2xx_update_display(void *opaque)
>  {
>      PXA2xxLCDState *s = (PXA2xxLCDState *) opaque;
> -    target_phys_addr_t fbptr;
> +    hwaddr fbptr;
>      int miny, maxy;
>      int ch;
>      if (!(s->control[0] & LCCR0_ENB))
> @@ -987,7 +987,7 @@ static int pxa2xx_lcdc_post_load(void *opaque, int version_id)
>  #include "pxa2xx_template.h"
>  
>  PXA2xxLCDState *pxa2xx_lcdc_init(MemoryRegion *sysmem,
> -                                 target_phys_addr_t base, qemu_irq irq)
> +                                 hwaddr base, qemu_irq irq)
>  {
>      PXA2xxLCDState *s;
>  
> diff --git a/hw/pxa2xx_mmci.c b/hw/pxa2xx_mmci.c
> index b505a4c..3589968 100644
> --- a/hw/pxa2xx_mmci.c
> +++ b/hw/pxa2xx_mmci.c
> @@ -215,7 +215,7 @@ static void pxa2xx_mmci_wakequeues(PXA2xxMMCIState *s)
>      pxa2xx_mmci_fifo_update(s);
>  }
>  
> -static uint32_t pxa2xx_mmci_read(void *opaque, target_phys_addr_t offset)
> +static uint32_t pxa2xx_mmci_read(void *opaque, hwaddr offset)
>  {
>      PXA2xxMMCIState *s = (PXA2xxMMCIState *) opaque;
>      uint32_t ret;
> @@ -277,7 +277,7 @@ static uint32_t pxa2xx_mmci_read(void *opaque, target_phys_addr_t offset)
>  }
>  
>  static void pxa2xx_mmci_write(void *opaque,
> -                target_phys_addr_t offset, uint32_t value)
> +                hwaddr offset, uint32_t value)
>  {
>      PXA2xxMMCIState *s = (PXA2xxMMCIState *) opaque;
>  
> @@ -386,21 +386,21 @@ static void pxa2xx_mmci_write(void *opaque,
>      }
>  }
>  
> -static uint32_t pxa2xx_mmci_readb(void *opaque, target_phys_addr_t offset)
> +static uint32_t pxa2xx_mmci_readb(void *opaque, hwaddr offset)
>  {
>      PXA2xxMMCIState *s = (PXA2xxMMCIState *) opaque;
>      s->ac_width = 1;
>      return pxa2xx_mmci_read(opaque, offset);
>  }
>  
> -static uint32_t pxa2xx_mmci_readh(void *opaque, target_phys_addr_t offset)
> +static uint32_t pxa2xx_mmci_readh(void *opaque, hwaddr offset)
>  {
>      PXA2xxMMCIState *s = (PXA2xxMMCIState *) opaque;
>      s->ac_width = 2;
>      return pxa2xx_mmci_read(opaque, offset);
>  }
>  
> -static uint32_t pxa2xx_mmci_readw(void *opaque, target_phys_addr_t offset)
> +static uint32_t pxa2xx_mmci_readw(void *opaque, hwaddr offset)
>  {
>      PXA2xxMMCIState *s = (PXA2xxMMCIState *) opaque;
>      s->ac_width = 4;
> @@ -408,7 +408,7 @@ static uint32_t pxa2xx_mmci_readw(void *opaque, target_phys_addr_t offset)
>  }
>  
>  static void pxa2xx_mmci_writeb(void *opaque,
> -                target_phys_addr_t offset, uint32_t value)
> +                hwaddr offset, uint32_t value)
>  {
>      PXA2xxMMCIState *s = (PXA2xxMMCIState *) opaque;
>      s->ac_width = 1;
> @@ -416,7 +416,7 @@ static void pxa2xx_mmci_writeb(void *opaque,
>  }
>  
>  static void pxa2xx_mmci_writeh(void *opaque,
> -                target_phys_addr_t offset, uint32_t value)
> +                hwaddr offset, uint32_t value)
>  {
>      PXA2xxMMCIState *s = (PXA2xxMMCIState *) opaque;
>      s->ac_width = 2;
> @@ -424,7 +424,7 @@ static void pxa2xx_mmci_writeh(void *opaque,
>  }
>  
>  static void pxa2xx_mmci_writew(void *opaque,
> -                target_phys_addr_t offset, uint32_t value)
> +                hwaddr offset, uint32_t value)
>  {
>      PXA2xxMMCIState *s = (PXA2xxMMCIState *) opaque;
>      s->ac_width = 4;
> @@ -522,7 +522,7 @@ static int pxa2xx_mmci_load(QEMUFile *f, void *opaque, int version_id)
>  }
>  
>  PXA2xxMMCIState *pxa2xx_mmci_init(MemoryRegion *sysmem,
> -                target_phys_addr_t base,
> +                hwaddr base,
>                  BlockDriverState *bd, qemu_irq irq,
>                  qemu_irq rx_dma, qemu_irq tx_dma)
>  {
> diff --git a/hw/pxa2xx_pcmcia.c b/hw/pxa2xx_pcmcia.c
> index b15872a..3a79c72 100644
> --- a/hw/pxa2xx_pcmcia.c
> +++ b/hw/pxa2xx_pcmcia.c
> @@ -27,7 +27,7 @@ struct PXA2xxPCMCIAState {
>  };
>  
>  static uint64_t pxa2xx_pcmcia_common_read(void *opaque,
> -                target_phys_addr_t offset, unsigned size)
> +                hwaddr offset, unsigned size)
>  {
>      PXA2xxPCMCIAState *s = (PXA2xxPCMCIAState *) opaque;
>  
> @@ -38,7 +38,7 @@ static uint64_t pxa2xx_pcmcia_common_read(void *opaque,
>      return 0;
>  }
>  
> -static void pxa2xx_pcmcia_common_write(void *opaque, target_phys_addr_t offset,
> +static void pxa2xx_pcmcia_common_write(void *opaque, hwaddr offset,
>                                         uint64_t value, unsigned size)
>  {
>      PXA2xxPCMCIAState *s = (PXA2xxPCMCIAState *) opaque;
> @@ -49,7 +49,7 @@ static void pxa2xx_pcmcia_common_write(void *opaque, target_phys_addr_t offset,
>  }
>  
>  static uint64_t pxa2xx_pcmcia_attr_read(void *opaque,
> -                target_phys_addr_t offset, unsigned size)
> +                hwaddr offset, unsigned size)
>  {
>      PXA2xxPCMCIAState *s = (PXA2xxPCMCIAState *) opaque;
>  
> @@ -60,7 +60,7 @@ static uint64_t pxa2xx_pcmcia_attr_read(void *opaque,
>      return 0;
>  }
>  
> -static void pxa2xx_pcmcia_attr_write(void *opaque, target_phys_addr_t offset,
> +static void pxa2xx_pcmcia_attr_write(void *opaque, hwaddr offset,
>                                       uint64_t value, unsigned size)
>  {
>      PXA2xxPCMCIAState *s = (PXA2xxPCMCIAState *) opaque;
> @@ -71,7 +71,7 @@ static void pxa2xx_pcmcia_attr_write(void *opaque, target_phys_addr_t offset,
>  }
>  
>  static uint64_t pxa2xx_pcmcia_io_read(void *opaque,
> -                target_phys_addr_t offset, unsigned size)
> +                hwaddr offset, unsigned size)
>  {
>      PXA2xxPCMCIAState *s = (PXA2xxPCMCIAState *) opaque;
>  
> @@ -82,7 +82,7 @@ static uint64_t pxa2xx_pcmcia_io_read(void *opaque,
>      return 0;
>  }
>  
> -static void pxa2xx_pcmcia_io_write(void *opaque, target_phys_addr_t offset,
> +static void pxa2xx_pcmcia_io_write(void *opaque, hwaddr offset,
>                                     uint64_t value, unsigned size)
>  {
>      PXA2xxPCMCIAState *s = (PXA2xxPCMCIAState *) opaque;
> @@ -120,7 +120,7 @@ static void pxa2xx_pcmcia_set_irq(void *opaque, int line, int level)
>  }
>  
>  PXA2xxPCMCIAState *pxa2xx_pcmcia_init(MemoryRegion *sysmem,
> -                                      target_phys_addr_t base)
> +                                      hwaddr base)
>  {
>      PXA2xxPCMCIAState *s;
>  
> diff --git a/hw/pxa2xx_pic.c b/hw/pxa2xx_pic.c
> index e1e8830..70b2b79 100644
> --- a/hw/pxa2xx_pic.c
> +++ b/hw/pxa2xx_pic.c
> @@ -119,7 +119,7 @@ static inline uint32_t pxa2xx_pic_highest(PXA2xxPICState *s) {
>      return ichp;
>  }
>  
> -static uint64_t pxa2xx_pic_mem_read(void *opaque, target_phys_addr_t offset,
> +static uint64_t pxa2xx_pic_mem_read(void *opaque, hwaddr offset,
>                                      unsigned size)
>  {
>      PXA2xxPICState *s = (PXA2xxPICState *) opaque;
> @@ -159,7 +159,7 @@ static uint64_t pxa2xx_pic_mem_read(void *opaque, target_phys_addr_t offset,
>      }
>  }
>  
> -static void pxa2xx_pic_mem_write(void *opaque, target_phys_addr_t offset,
> +static void pxa2xx_pic_mem_write(void *opaque, hwaddr offset,
>                                   uint64_t value, unsigned size)
>  {
>      PXA2xxPICState *s = (PXA2xxPICState *) opaque;
> @@ -257,7 +257,7 @@ static int pxa2xx_pic_post_load(void *opaque, int version_id)
>      return 0;
>  }
>  
> -DeviceState *pxa2xx_pic_init(target_phys_addr_t base, ARMCPU *cpu)
> +DeviceState *pxa2xx_pic_init(hwaddr base, ARMCPU *cpu)
>  {
>      CPUARMState *env = &cpu->env;
>      DeviceState *dev = qdev_create(NULL, "pxa2xx_pic");
> diff --git a/hw/pxa2xx_timer.c b/hw/pxa2xx_timer.c
> index 77b033b..8242d26 100644
> --- a/hw/pxa2xx_timer.c
> +++ b/hw/pxa2xx_timer.c
> @@ -149,7 +149,7 @@ static void pxa2xx_timer_update4(void *opaque, uint64_t now_qemu, int n)
>      qemu_mod_timer(s->tm4[n].tm.qtimer, new_qemu);
>  }
>  
> -static uint64_t pxa2xx_timer_read(void *opaque, target_phys_addr_t offset,
> +static uint64_t pxa2xx_timer_read(void *opaque, hwaddr offset,
>                                    unsigned size)
>  {
>      PXA2xxTimerInfo *s = (PXA2xxTimerInfo *) opaque;
> @@ -227,7 +227,7 @@ static uint64_t pxa2xx_timer_read(void *opaque, target_phys_addr_t offset,
>      return 0;
>  }
>  
> -static void pxa2xx_timer_write(void *opaque, target_phys_addr_t offset,
> +static void pxa2xx_timer_write(void *opaque, hwaddr offset,
>                                 uint64_t value, unsigned size)
>  {
>      int i, tm = 0;
> diff --git a/hw/qdev-addr.c b/hw/qdev-addr.c
> index b711b6b..de0ba87 100644
> --- a/hw/qdev-addr.c
> +++ b/hw/qdev-addr.c
> @@ -1,12 +1,12 @@
>  #include "qdev.h"
>  #include "qdev-addr.h"
> -#include "targphys.h"
> +#include "hwaddr.h"
>  
>  /* --- target physical address --- */
>  
>  static int parse_taddr(DeviceState *dev, Property *prop, const char *str)
>  {
> -    target_phys_addr_t *ptr = qdev_get_prop_ptr(dev, prop);
> +    hwaddr *ptr = qdev_get_prop_ptr(dev, prop);
>  
>      *ptr = strtoull(str, NULL, 16);
>      return 0;
> @@ -14,7 +14,7 @@ static int parse_taddr(DeviceState *dev, Property *prop, const char *str)
>  
>  static int print_taddr(DeviceState *dev, Property *prop, char *dest, size_t len)
>  {
> -    target_phys_addr_t *ptr = qdev_get_prop_ptr(dev, prop);
> +    hwaddr *ptr = qdev_get_prop_ptr(dev, prop);
>      return snprintf(dest, len, "0x" TARGET_FMT_plx, *ptr);
>  }
>  
> @@ -23,7 +23,7 @@ static void get_taddr(Object *obj, Visitor *v, void *opaque,
>  {
>      DeviceState *dev = DEVICE(obj);
>      Property *prop = opaque;
> -    target_phys_addr_t *ptr = qdev_get_prop_ptr(dev, prop);
> +    hwaddr *ptr = qdev_get_prop_ptr(dev, prop);
>      int64_t value;
>  
>      value = *ptr;
> @@ -35,7 +35,7 @@ static void set_taddr(Object *obj, Visitor *v, void *opaque,
>  {
>      DeviceState *dev = DEVICE(obj);
>      Property *prop = opaque;
> -    target_phys_addr_t *ptr = qdev_get_prop_ptr(dev, prop);
> +    hwaddr *ptr = qdev_get_prop_ptr(dev, prop);
>      Error *local_err = NULL;
>      int64_t value;
>  
> @@ -49,12 +49,12 @@ static void set_taddr(Object *obj, Visitor *v, void *opaque,
>          error_propagate(errp, local_err);
>          return;
>      }
> -    if ((uint64_t)value <= (uint64_t) ~(target_phys_addr_t)0) {
> +    if ((uint64_t)value <= (uint64_t) ~(hwaddr)0) {
>          *ptr = value;
>      } else {
>          error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE,
>                    dev->id?:"", name, value, (uint64_t) 0,
> -                  (uint64_t) ~(target_phys_addr_t)0);
> +                  (uint64_t) ~(hwaddr)0);
>      }
>  }
>  
> @@ -67,7 +67,7 @@ static void set_taddr(Object *obj, Visitor *v, void *opaque,
>      .set   = set_taddr,
>  };
>  
> -void qdev_prop_set_taddr(DeviceState *dev, const char *name, target_phys_addr_t value)
> +void qdev_prop_set_taddr(DeviceState *dev, const char *name, hwaddr value)
>  {
>      Error *errp = NULL;
>      object_property_set_int(OBJECT(dev), value, name, &errp);
> diff --git a/hw/qdev-addr.h b/hw/qdev-addr.h
> index a0ddf38..ea5ecb4 100644
> --- a/hw/qdev-addr.h
> +++ b/hw/qdev-addr.h
> @@ -1,5 +1,5 @@
>  #define DEFINE_PROP_TADDR(_n, _s, _f, _d)                               \
> -    DEFINE_PROP_DEFAULT(_n, _s, _f, _d, qdev_prop_taddr, target_phys_addr_t)
> +    DEFINE_PROP_DEFAULT(_n, _s, _f, _d, qdev_prop_taddr, hwaddr)
>  
>  extern PropertyInfo qdev_prop_taddr;
> -void qdev_prop_set_taddr(DeviceState *dev, const char *name, target_phys_addr_t value);
> +void qdev_prop_set_taddr(DeviceState *dev, const char *name, hwaddr value);
> diff --git a/hw/qxl.c b/hw/qxl.c
> index 1d16863..d54daf6 100644
> --- a/hw/qxl.c
> +++ b/hw/qxl.c
> @@ -1428,7 +1428,7 @@ static void qxl_set_mode(PCIQXLDevice *d, int modenr, int loadvm)
>      qxl_rom_set_dirty(d);
>  }
>  
> -static void ioport_write(void *opaque, target_phys_addr_t addr,
> +static void ioport_write(void *opaque, hwaddr addr,
>                           uint64_t val, unsigned size)
>  {
>      PCIQXLDevice *d = opaque;
> @@ -1653,7 +1653,7 @@ static void ioport_write(void *opaque, target_phys_addr_t addr,
>      }
>  }
>  
> -static uint64_t ioport_read(void *opaque, target_phys_addr_t addr,
> +static uint64_t ioport_read(void *opaque, hwaddr addr,
>                              unsigned size)
>  {
>      PCIQXLDevice *qxl = opaque;
> diff --git a/hw/r2d.c b/hw/r2d.c
> index 3cb6942..66212e9 100644
> --- a/hw/r2d.c
> +++ b/hw/r2d.c
> @@ -127,7 +127,7 @@ static void r2d_fpga_irq_set(void *opaque, int n, int level)
>      update_irl(fpga);
>  }
>  
> -static uint32_t r2d_fpga_read(void *opaque, target_phys_addr_t addr)
> +static uint32_t r2d_fpga_read(void *opaque, hwaddr addr)
>  {
>      r2d_fpga_t *s = opaque;
>  
> @@ -146,7 +146,7 @@ static uint32_t r2d_fpga_read(void *opaque, target_phys_addr_t addr)
>  }
>  
>  static void
> -r2d_fpga_write(void *opaque, target_phys_addr_t addr, uint32_t value)
> +r2d_fpga_write(void *opaque, hwaddr addr, uint32_t value)
>  {
>      r2d_fpga_t *s = opaque;
>  
> @@ -178,7 +178,7 @@ static uint32_t r2d_fpga_read(void *opaque, target_phys_addr_t addr)
>  };
>  
>  static qemu_irq *r2d_fpga_init(MemoryRegion *sysmem,
> -                               target_phys_addr_t base, qemu_irq irl)
> +                               hwaddr base, qemu_irq irl)
>  {
>      r2d_fpga_t *s;
>  
> diff --git a/hw/rc4030.c b/hw/rc4030.c
> index 9f39b30..e0024c8 100644
> --- a/hw/rc4030.c
> +++ b/hw/rc4030.c
> @@ -112,7 +112,7 @@ static void set_next_tick(rc4030State *s)
>  }
>  
>  /* called for accesses to rc4030 */
> -static uint32_t rc4030_readl(void *opaque, target_phys_addr_t addr)
> +static uint32_t rc4030_readl(void *opaque, hwaddr addr)
>  {
>      rc4030State *s = opaque;
>      uint32_t val;
> @@ -250,7 +250,7 @@ static uint32_t rc4030_readl(void *opaque, target_phys_addr_t addr)
>      return val;
>  }
>  
> -static uint32_t rc4030_readw(void *opaque, target_phys_addr_t addr)
> +static uint32_t rc4030_readw(void *opaque, hwaddr addr)
>  {
>      uint32_t v = rc4030_readl(opaque, addr & ~0x3);
>      if (addr & 0x2)
> @@ -259,13 +259,13 @@ static uint32_t rc4030_readw(void *opaque, target_phys_addr_t addr)
>          return v & 0xffff;
>  }
>  
> -static uint32_t rc4030_readb(void *opaque, target_phys_addr_t addr)
> +static uint32_t rc4030_readb(void *opaque, hwaddr addr)
>  {
>      uint32_t v = rc4030_readl(opaque, addr & ~0x3);
>      return (v >> (8 * (addr & 0x3))) & 0xff;
>  }
>  
> -static void rc4030_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
> +static void rc4030_writel(void *opaque, hwaddr addr, uint32_t val)
>  {
>      rc4030State *s = opaque;
>      addr &= 0x3fff;
> @@ -308,7 +308,7 @@ static void rc4030_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
>      case 0x0060:
>          /* HACK */
>          if (s->cache_ltag == 0x80000001 && s->cache_bmask == 0xf0f0f0f) {
> -            target_phys_addr_t dest = s->cache_ptag & ~0x1;
> +            hwaddr dest = s->cache_ptag & ~0x1;
>              dest += (s->cache_maint & 0x3) << 3;
>              cpu_physical_memory_write(dest, &val, 4);
>          }
> @@ -390,7 +390,7 @@ static void rc4030_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
>      }
>  }
>  
> -static void rc4030_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
> +static void rc4030_writew(void *opaque, hwaddr addr, uint32_t val)
>  {
>      uint32_t old_val = rc4030_readl(opaque, addr & ~0x3);
>  
> @@ -401,7 +401,7 @@ static void rc4030_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
>      rc4030_writel(opaque, addr & ~0x3, val);
>  }
>  
> -static void rc4030_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
> +static void rc4030_writeb(void *opaque, hwaddr addr, uint32_t val)
>  {
>      uint32_t old_val = rc4030_readl(opaque, addr & ~0x3);
>  
> @@ -479,7 +479,7 @@ static void rc4030_periodic_timer(void *opaque)
>      qemu_irq_raise(s->timer_irq);
>  }
>  
> -static uint32_t jazzio_readw(void *opaque, target_phys_addr_t addr)
> +static uint32_t jazzio_readw(void *opaque, hwaddr addr)
>  {
>      rc4030State *s = opaque;
>      uint32_t val;
> @@ -517,14 +517,14 @@ static uint32_t jazzio_readw(void *opaque, target_phys_addr_t addr)
>      return val;
>  }
>  
> -static uint32_t jazzio_readb(void *opaque, target_phys_addr_t addr)
> +static uint32_t jazzio_readb(void *opaque, hwaddr addr)
>  {
>      uint32_t v;
>      v = jazzio_readw(opaque, addr & ~0x1);
>      return (v >> (8 * (addr & 0x1))) & 0xff;
>  }
>  
> -static uint32_t jazzio_readl(void *opaque, target_phys_addr_t addr)
> +static uint32_t jazzio_readl(void *opaque, hwaddr addr)
>  {
>      uint32_t v;
>      v = jazzio_readw(opaque, addr);
> @@ -532,7 +532,7 @@ static uint32_t jazzio_readl(void *opaque, target_phys_addr_t addr)
>      return v;
>  }
>  
> -static void jazzio_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
> +static void jazzio_writew(void *opaque, hwaddr addr, uint32_t val)
>  {
>      rc4030State *s = opaque;
>      addr &= 0xfff;
> @@ -551,7 +551,7 @@ static void jazzio_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
>      }
>  }
>  
> -static void jazzio_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
> +static void jazzio_writeb(void *opaque, hwaddr addr, uint32_t val)
>  {
>      uint32_t old_val = jazzio_readw(opaque, addr & ~0x1);
>  
> @@ -566,7 +566,7 @@ static void jazzio_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
>      jazzio_writew(opaque, addr & ~0x1, val);
>  }
>  
> -static void jazzio_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
> +static void jazzio_writel(void *opaque, hwaddr addr, uint32_t val)
>  {
>      jazzio_writew(opaque, addr, val & 0xffff);
>      jazzio_writew(opaque, addr + 2, (val >> 16) & 0xffff);
> @@ -672,11 +672,11 @@ static void rc4030_save(QEMUFile *f, void *opaque)
>      qemu_put_be32(f, s->itr);
>  }
>  
> -void rc4030_dma_memory_rw(void *opaque, target_phys_addr_t addr, uint8_t *buf, int len, int is_write)
> +void rc4030_dma_memory_rw(void *opaque, hwaddr addr, uint8_t *buf, int len, int is_write)
>  {
>      rc4030State *s = opaque;
> -    target_phys_addr_t entry_addr;
> -    target_phys_addr_t phys_addr;
> +    hwaddr entry_addr;
> +    hwaddr phys_addr;
>      dma_pagetable_entry entry;
>      int index;
>      int ncpy, i;
> @@ -713,7 +713,7 @@ void rc4030_dma_memory_rw(void *opaque, target_phys_addr_t addr, uint8_t *buf, i
>  static void rc4030_do_dma(void *opaque, int n, uint8_t *buf, int len, int is_write)
>  {
>      rc4030State *s = opaque;
> -    target_phys_addr_t dma_addr;
> +    hwaddr dma_addr;
>      int dev_to_mem;
>  
>      s->dma_regs[n][DMA_REG_ENABLE] &= ~(DMA_FLAG_TC_INTR | DMA_FLAG_MEM_INTR | DMA_FLAG_ADDR_INTR);
> diff --git a/hw/realview.c b/hw/realview.c
> index 8dc4be6..baa92d4 100644
> --- a/hw/realview.c
> +++ b/hw/realview.c
> @@ -145,7 +145,7 @@ static void realview_init(ram_addr_t ram_size,
>      sysbus_mmio_map(sysbus_from_qdev(sysctl), 0, 0x10000000);
>  
>      if (is_mpcore) {
> -        target_phys_addr_t periphbase;
> +        hwaddr periphbase;
>          dev = qdev_create(NULL, is_pb ? "a9mpcore_priv": "realview_mpcore");
>          qdev_prop_set_uint32(dev, "num-cpu", smp_cpus);
>          qdev_init_nofail(dev);
> diff --git a/hw/rtl8139.c b/hw/rtl8139.c
> index 6b28fea..10ced8b 100644
> --- a/hw/rtl8139.c
> +++ b/hw/rtl8139.c
> @@ -2455,7 +2455,7 @@ static void rtl8139_TxStatus_write(RTL8139State *s, uint32_t txRegOffset, uint32
>  
>          if (descriptor == 0 && (val & 0x8))
>          {
> -            target_phys_addr_t tc_addr = rtl8139_addr64(s->TxStatus[0] & ~0x3f, s->TxStatus[1]);
> +            hwaddr tc_addr = rtl8139_addr64(s->TxStatus[0] & ~0x3f, s->TxStatus[1]);
>  
>              /* dump tally counters to specified memory location */
>              RTL8139TallyCounters_dma_write(s, tc_addr);
> @@ -3219,33 +3219,33 @@ static uint32_t rtl8139_ioport_readl(void *opaque, uint32_t addr)
>  
>  /* */
>  
> -static void rtl8139_mmio_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
> +static void rtl8139_mmio_writeb(void *opaque, hwaddr addr, uint32_t val)
>  {
>      rtl8139_io_writeb(opaque, addr & 0xFF, val);
>  }
>  
> -static void rtl8139_mmio_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
> +static void rtl8139_mmio_writew(void *opaque, hwaddr addr, uint32_t val)
>  {
>      rtl8139_io_writew(opaque, addr & 0xFF, val);
>  }
>  
> -static void rtl8139_mmio_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
> +static void rtl8139_mmio_writel(void *opaque, hwaddr addr, uint32_t val)
>  {
>      rtl8139_io_writel(opaque, addr & 0xFF, val);
>  }
>  
> -static uint32_t rtl8139_mmio_readb(void *opaque, target_phys_addr_t addr)
> +static uint32_t rtl8139_mmio_readb(void *opaque, hwaddr addr)
>  {
>      return rtl8139_io_readb(opaque, addr & 0xFF);
>  }
>  
> -static uint32_t rtl8139_mmio_readw(void *opaque, target_phys_addr_t addr)
> +static uint32_t rtl8139_mmio_readw(void *opaque, hwaddr addr)
>  {
>      uint32_t val = rtl8139_io_readw(opaque, addr & 0xFF);
>      return val;
>  }
>  
> -static uint32_t rtl8139_mmio_readl(void *opaque, target_phys_addr_t addr)
> +static uint32_t rtl8139_mmio_readl(void *opaque, hwaddr addr)
>  {
>      uint32_t val = rtl8139_io_readl(opaque, addr & 0xFF);
>      return val;
> diff --git a/hw/s390-virtio-bus.c b/hw/s390-virtio-bus.c
> index a245684..5849a96 100644
> --- a/hw/s390-virtio-bus.c
> +++ b/hw/s390-virtio-bus.c
> @@ -56,7 +56,7 @@
>  static ram_addr_t s390_virtio_device_num_vq(VirtIOS390Device *dev);
>  
>  /* length of VirtIO device pages */
> -const target_phys_addr_t virtio_size = S390_DEVICE_PAGES * TARGET_PAGE_SIZE;
> +const hwaddr virtio_size = S390_DEVICE_PAGES * TARGET_PAGE_SIZE;
>  
>  static void s390_virtio_bus_reset(void *opaque)
>  {
> @@ -67,7 +67,7 @@ static void s390_virtio_bus_reset(void *opaque)
>  void s390_virtio_reset_idx(VirtIOS390Device *dev)
>  {
>      int i;
> -    target_phys_addr_t idx_addr;
> +    hwaddr idx_addr;
>      uint8_t num_vq;
>  
>      num_vq = s390_virtio_device_num_vq(dev);
> diff --git a/hw/s390-virtio.c b/hw/s390-virtio.c
> index 39ff178..85bd13e 100644
> --- a/hw/s390-virtio.c
> +++ b/hw/s390-virtio.c
> @@ -168,8 +168,8 @@ static void s390_init(QEMUMachineInitArgs *args)
>      int shift = 0;
>      uint8_t *storage_keys;
>      void *virtio_region;
> -    target_phys_addr_t virtio_region_len;
> -    target_phys_addr_t virtio_region_start;
> +    hwaddr virtio_region_len;
> +    hwaddr virtio_region_start;
>      int i;
>  
>      /* s390x ram size detection needs a 16bit multiplier + an increment. So
> diff --git a/hw/sbi.c b/hw/sbi.c
> index 52982a9..ca78a38 100644
> --- a/hw/sbi.c
> +++ b/hw/sbi.c
> @@ -52,7 +52,7 @@ static void sbi_set_irq(void *opaque, int irq, int level)
>  {
>  }
>  
> -static uint64_t sbi_mem_read(void *opaque, target_phys_addr_t addr,
> +static uint64_t sbi_mem_read(void *opaque, hwaddr addr,
>                               unsigned size)
>  {
>      SBIState *s = opaque;
> @@ -69,7 +69,7 @@ static uint64_t sbi_mem_read(void *opaque, target_phys_addr_t addr,
>      return ret;
>  }
>  
> -static void sbi_mem_write(void *opaque, target_phys_addr_t addr,
> +static void sbi_mem_write(void *opaque, hwaddr addr,
>                            uint64_t val, unsigned dize)
>  {
>      SBIState *s = opaque;
> diff --git a/hw/serial.c b/hw/serial.c
> index 5adbfaf..ae84b22 100644
> --- a/hw/serial.c
> +++ b/hw/serial.c
> @@ -734,14 +734,14 @@ SerialState *serial_init(int base, qemu_irq irq, int baudbase,
>  }
>  
>  /* Memory mapped interface */
> -static uint64_t serial_mm_read(void *opaque, target_phys_addr_t addr,
> +static uint64_t serial_mm_read(void *opaque, hwaddr addr,
>                                 unsigned size)
>  {
>      SerialState *s = opaque;
>      return serial_ioport_read(s, addr >> s->it_shift);
>  }
>  
> -static void serial_mm_write(void *opaque, target_phys_addr_t addr,
> +static void serial_mm_write(void *opaque, hwaddr addr,
>                              uint64_t value, unsigned size)
>  {
>      SerialState *s = opaque;
> @@ -768,7 +768,7 @@ static void serial_mm_write(void *opaque, target_phys_addr_t addr,
>  };
>  
>  SerialState *serial_mm_init(MemoryRegion *address_space,
> -                            target_phys_addr_t base, int it_shift,
> +                            hwaddr base, int it_shift,
>                              qemu_irq irq, int baudbase,
>                              CharDriverState *chr, enum device_endian end)
>  {
> diff --git a/hw/serial.h b/hw/serial.h
> index 55a1ac5..f1e3c4a 100644
> --- a/hw/serial.h
> +++ b/hw/serial.h
> @@ -91,7 +91,7 @@ void serial_set_frequency(SerialState *s, uint32_t frequency);
>  SerialState *serial_init(int base, qemu_irq irq, int baudbase,
>                           CharDriverState *chr);
>  SerialState *serial_mm_init(MemoryRegion *address_space,
> -                            target_phys_addr_t base, int it_shift,
> +                            hwaddr base, int it_shift,
>                              qemu_irq irq, int baudbase,
>                              CharDriverState *chr, enum device_endian end);
>  
> diff --git a/hw/sh.h b/hw/sh.h
> index 40df18c..77bf8aa 100644
> --- a/hw/sh.h
> +++ b/hw/sh.h
> @@ -31,7 +31,7 @@ int sh7750_register_io_device(struct SH7750State *s,
>  #define TMU012_FEAT_TOCR   (1 << 0)
>  #define TMU012_FEAT_3CHAN  (1 << 1)
>  #define TMU012_FEAT_EXTCLK (1 << 2)
> -void tmu012_init(struct MemoryRegion *sysmem, target_phys_addr_t base,
> +void tmu012_init(struct MemoryRegion *sysmem, hwaddr base,
>                   int feat, uint32_t freq,
>  		 qemu_irq ch0_irq, qemu_irq ch1_irq,
>  		 qemu_irq ch2_irq0, qemu_irq ch2_irq1);
> @@ -40,7 +40,7 @@ void tmu012_init(struct MemoryRegion *sysmem, target_phys_addr_t base,
>  /* sh_serial.c */
>  #define SH_SERIAL_FEAT_SCIF (1 << 0)
>  void sh_serial_init(MemoryRegion *sysmem,
> -                    target_phys_addr_t base, int feat,
> +                    hwaddr base, int feat,
>  		     uint32_t freq, CharDriverState *chr,
>  		     qemu_irq eri_source,
>  		     qemu_irq rxi_source,
> diff --git a/hw/sh7750.c b/hw/sh7750.c
> index e712928..8bcf0df 100644
> --- a/hw/sh7750.c
> +++ b/hw/sh7750.c
> @@ -197,19 +197,19 @@ static void portb_changed(SH7750State * s, uint16_t prev)
>   Memory
>  **********************************************************************/
>  
> -static void error_access(const char *kind, target_phys_addr_t addr)
> +static void error_access(const char *kind, hwaddr addr)
>  {
>      fprintf(stderr, "%s to %s (0x" TARGET_FMT_plx ") not supported\n",
>  	    kind, regname(addr), addr);
>  }
>  
> -static void ignore_access(const char *kind, target_phys_addr_t addr)
> +static void ignore_access(const char *kind, hwaddr addr)
>  {
>      fprintf(stderr, "%s to %s (0x" TARGET_FMT_plx ") ignored\n",
>  	    kind, regname(addr), addr);
>  }
>  
> -static uint32_t sh7750_mem_readb(void *opaque, target_phys_addr_t addr)
> +static uint32_t sh7750_mem_readb(void *opaque, hwaddr addr)
>  {
>      switch (addr) {
>      default:
> @@ -218,7 +218,7 @@ static uint32_t sh7750_mem_readb(void *opaque, target_phys_addr_t addr)
>      }
>  }
>  
> -static uint32_t sh7750_mem_readw(void *opaque, target_phys_addr_t addr)
> +static uint32_t sh7750_mem_readw(void *opaque, hwaddr addr)
>  {
>      SH7750State *s = opaque;
>  
> @@ -252,7 +252,7 @@ static uint32_t sh7750_mem_readw(void *opaque, target_phys_addr_t addr)
>      }
>  }
>  
> -static uint32_t sh7750_mem_readl(void *opaque, target_phys_addr_t addr)
> +static uint32_t sh7750_mem_readl(void *opaque, hwaddr addr)
>  {
>      SH7750State *s = opaque;
>  
> @@ -301,7 +301,7 @@ static uint32_t sh7750_mem_readl(void *opaque, target_phys_addr_t addr)
>  
>  #define is_in_sdrmx(a, x) (a >= SH7750_SDMR ## x ## _A7 \
>  			&& a <= (SH7750_SDMR ## x ## _A7 + SH7750_SDMR ## x ## _REGNB))
> -static void sh7750_mem_writeb(void *opaque, target_phys_addr_t addr,
> +static void sh7750_mem_writeb(void *opaque, hwaddr addr,
>  			      uint32_t mem_value)
>  {
>  
> @@ -314,7 +314,7 @@ static void sh7750_mem_writeb(void *opaque, target_phys_addr_t addr,
>      abort();
>  }
>  
> -static void sh7750_mem_writew(void *opaque, target_phys_addr_t addr,
> +static void sh7750_mem_writew(void *opaque, hwaddr addr,
>  			      uint32_t mem_value)
>  {
>      SH7750State *s = opaque;
> @@ -366,7 +366,7 @@ static void sh7750_mem_writew(void *opaque, target_phys_addr_t addr,
>      }
>  }
>  
> -static void sh7750_mem_writel(void *opaque, target_phys_addr_t addr,
> +static void sh7750_mem_writel(void *opaque, hwaddr addr,
>  			      uint32_t mem_value)
>  {
>      SH7750State *s = opaque;
> @@ -624,14 +624,14 @@ enum {
>  #define MM_UTLB_DATA     (7)
>  #define MM_REGION_TYPE(addr)  ((addr & MM_REGION_MASK) >> 24)
>  
> -static uint64_t invalid_read(void *opaque, target_phys_addr_t addr)
> +static uint64_t invalid_read(void *opaque, hwaddr addr)
>  {
>      abort();
>  
>      return 0;
>  }
>  
> -static uint64_t sh7750_mmct_read(void *opaque, target_phys_addr_t addr,
> +static uint64_t sh7750_mmct_read(void *opaque, hwaddr addr,
>                                   unsigned size)
>  {
>      SH7750State *s = opaque;
> @@ -669,13 +669,13 @@ static uint64_t sh7750_mmct_read(void *opaque, target_phys_addr_t addr,
>      return ret;
>  }
>  
> -static void invalid_write(void *opaque, target_phys_addr_t addr,
> +static void invalid_write(void *opaque, hwaddr addr,
>                            uint64_t mem_value)
>  {
>      abort();
>  }
>  
> -static void sh7750_mmct_write(void *opaque, target_phys_addr_t addr,
> +static void sh7750_mmct_write(void *opaque, hwaddr addr,
>                                uint64_t mem_value, unsigned size)
>  {
>      SH7750State *s = opaque;
> diff --git a/hw/sh_intc.c b/hw/sh_intc.c
> index 7d31ced..c3f77d5 100644
> --- a/hw/sh_intc.c
> +++ b/hw/sh_intc.c
> @@ -219,7 +219,7 @@ static void sh_intc_toggle_mask(struct intc_desc *desc, intc_enum id,
>  #endif
>  }
>  
> -static uint64_t sh_intc_read(void *opaque, target_phys_addr_t offset,
> +static uint64_t sh_intc_read(void *opaque, hwaddr offset,
>                               unsigned size)
>  {
>      struct intc_desc *desc = opaque;
> @@ -238,7 +238,7 @@ static uint64_t sh_intc_read(void *opaque, target_phys_addr_t offset,
>      return *valuep;
>  }
>  
> -static void sh_intc_write(void *opaque, target_phys_addr_t offset,
> +static void sh_intc_write(void *opaque, hwaddr offset,
>                            uint64_t value, unsigned size)
>  {
>      struct intc_desc *desc = opaque;
> diff --git a/hw/sh_pci.c b/hw/sh_pci.c
> index 0cfac46..fdec71b 100644
> --- a/hw/sh_pci.c
> +++ b/hw/sh_pci.c
> @@ -41,7 +41,7 @@
>      uint32_t iobr;
>  } SHPCIState;
>  
> -static void sh_pci_reg_write (void *p, target_phys_addr_t addr, uint64_t val,
> +static void sh_pci_reg_write (void *p, hwaddr addr, uint64_t val,
>                                unsigned size)
>  {
>      SHPCIState *pcic = p;
> @@ -69,7 +69,7 @@ static void sh_pci_reg_write (void *p, target_phys_addr_t addr, uint64_t val,
>      }
>  }
>  
> -static uint64_t sh_pci_reg_read (void *p, target_phys_addr_t addr,
> +static uint64_t sh_pci_reg_read (void *p, hwaddr addr,
>                                   unsigned size)
>  {
>      SHPCIState *pcic = p;
> diff --git a/hw/sh_serial.c b/hw/sh_serial.c
> index 1d1883d..9da5d08 100644
> --- a/hw/sh_serial.c
> +++ b/hw/sh_serial.c
> @@ -78,7 +78,7 @@ static void sh_serial_clear_fifo(sh_serial_state * s)
>      s->rx_tail = 0;
>  }
>  
> -static void sh_serial_write(void *opaque, target_phys_addr_t offs,
> +static void sh_serial_write(void *opaque, hwaddr offs,
>                              uint64_t val, unsigned size)
>  {
>      sh_serial_state *s = opaque;
> @@ -187,11 +187,11 @@ static void sh_serial_write(void *opaque, target_phys_addr_t offs,
>      }
>  
>      fprintf(stderr, "sh_serial: unsupported write to 0x%02"
> -            TARGET_PRIxPHYS "\n", offs);
> +            HWADDR_PRIx "\n", offs);
>      abort();
>  }
>  
> -static uint64_t sh_serial_read(void *opaque, target_phys_addr_t offs,
> +static uint64_t sh_serial_read(void *opaque, hwaddr offs,
>                                 unsigned size)
>  {
>      sh_serial_state *s = opaque;
> @@ -289,7 +289,7 @@ static uint64_t sh_serial_read(void *opaque, target_phys_addr_t offs,
>  
>      if (ret & ~((1 << 16) - 1)) {
>          fprintf(stderr, "sh_serial: unsupported read from 0x%02"
> -                TARGET_PRIxPHYS "\n", offs);
> +                HWADDR_PRIx "\n", offs);
>          abort();
>      }
>  
> @@ -353,7 +353,7 @@ static void sh_serial_event(void *opaque, int event)
>  };
>  
>  void sh_serial_init(MemoryRegion *sysmem,
> -                    target_phys_addr_t base, int feat,
> +                    hwaddr base, int feat,
>                      uint32_t freq, CharDriverState *chr,
>                      qemu_irq eri_source,
>                      qemu_irq rxi_source,
> diff --git a/hw/sh_timer.c b/hw/sh_timer.c
> index 64bf604..c0365b1 100644
> --- a/hw/sh_timer.c
> +++ b/hw/sh_timer.c
> @@ -59,7 +59,7 @@ static void sh_timer_update(sh_timer_state *s)
>      s->int_level = new_level;
>  }
>  
> -static uint32_t sh_timer_read(void *opaque, target_phys_addr_t offset)
> +static uint32_t sh_timer_read(void *opaque, hwaddr offset)
>  {
>      sh_timer_state *s = (sh_timer_state *)opaque;
>  
> @@ -79,7 +79,7 @@ static uint32_t sh_timer_read(void *opaque, target_phys_addr_t offset)
>      }
>  }
>  
> -static void sh_timer_write(void *opaque, target_phys_addr_t offset,
> +static void sh_timer_write(void *opaque, hwaddr offset,
>                              uint32_t value)
>  {
>      sh_timer_state *s = (sh_timer_state *)opaque;
> @@ -222,7 +222,7 @@ static void *sh_timer_init(uint32_t freq, int feat, qemu_irq irq)
>      int feat;
>  } tmu012_state;
>  
> -static uint64_t tmu012_read(void *opaque, target_phys_addr_t offset,
> +static uint64_t tmu012_read(void *opaque, hwaddr offset,
>                              unsigned size)
>  {
>      tmu012_state *s = (tmu012_state *)opaque;
> @@ -253,7 +253,7 @@ static uint64_t tmu012_read(void *opaque, target_phys_addr_t offset,
>      return 0;
>  }
>  
> -static void tmu012_write(void *opaque, target_phys_addr_t offset,
> +static void tmu012_write(void *opaque, hwaddr offset,
>                          uint64_t value, unsigned size)
>  {
>      tmu012_state *s = (tmu012_state *)opaque;
> @@ -303,7 +303,7 @@ static void tmu012_write(void *opaque, target_phys_addr_t offset,
>      .endianness = DEVICE_NATIVE_ENDIAN,
>  };
>  
> -void tmu012_init(MemoryRegion *sysmem, target_phys_addr_t base,
> +void tmu012_init(MemoryRegion *sysmem, hwaddr base,
>                   int feat, uint32_t freq,
>  		 qemu_irq ch0_irq, qemu_irq ch1_irq,
>  		 qemu_irq ch2_irq0, qemu_irq ch2_irq1)
> diff --git a/hw/sharpsl.h b/hw/sharpsl.h
> index 0b3a774..13981a6 100644
> --- a/hw/sharpsl.h
> +++ b/hw/sharpsl.h
> @@ -12,6 +12,6 @@
>  /* zaurus.c */
>  
>  #define SL_PXA_PARAM_BASE	0xa0000a00
> -void sl_bootparam_write(target_phys_addr_t ptr);
> +void sl_bootparam_write(hwaddr ptr);
>  
>  #endif
> diff --git a/hw/shpc.c b/hw/shpc.c
> index a5baf24..4597bbd 100644
> --- a/hw/shpc.c
> +++ b/hw/shpc.c
> @@ -466,13 +466,13 @@ static int shpc_cap_add_config(PCIDevice *d)
>      return 0;
>  }
>  
> -static uint64_t shpc_mmio_read(void *opaque, target_phys_addr_t addr,
> +static uint64_t shpc_mmio_read(void *opaque, hwaddr addr,
>                                 unsigned size)
>  {
>      return shpc_read(opaque, addr, size);
>  }
>  
> -static void shpc_mmio_write(void *opaque, target_phys_addr_t addr,
> +static void shpc_mmio_write(void *opaque, hwaddr addr,
>                              uint64_t val, unsigned size)
>  {
>      shpc_write(opaque, addr, val, size);
> diff --git a/hw/slavio_intctl.c b/hw/slavio_intctl.c
> index 7fdc3be..6aafa8b 100644
> --- a/hw/slavio_intctl.c
> +++ b/hw/slavio_intctl.c
> @@ -78,7 +78,7 @@
>  static void slavio_check_interrupts(SLAVIO_INTCTLState *s, int set_irqs);
>  
>  // per-cpu interrupt controller
> -static uint64_t slavio_intctl_mem_readl(void *opaque, target_phys_addr_t addr,
> +static uint64_t slavio_intctl_mem_readl(void *opaque, hwaddr addr,
>                                          unsigned size)
>  {
>      SLAVIO_CPUINTCTLState *s = opaque;
> @@ -98,7 +98,7 @@ static uint64_t slavio_intctl_mem_readl(void *opaque, target_phys_addr_t addr,
>      return ret;
>  }
>  
> -static void slavio_intctl_mem_writel(void *opaque, target_phys_addr_t addr,
> +static void slavio_intctl_mem_writel(void *opaque, hwaddr addr,
>                                       uint64_t val, unsigned size)
>  {
>      SLAVIO_CPUINTCTLState *s = opaque;
> @@ -135,7 +135,7 @@ static void slavio_intctl_mem_writel(void *opaque, target_phys_addr_t addr,
>  };
>  
>  // master system interrupt controller
> -static uint64_t slavio_intctlm_mem_readl(void *opaque, target_phys_addr_t addr,
> +static uint64_t slavio_intctlm_mem_readl(void *opaque, hwaddr addr,
>                                           unsigned size)
>  {
>      SLAVIO_INTCTLState *s = opaque;
> @@ -161,7 +161,7 @@ static uint64_t slavio_intctlm_mem_readl(void *opaque, target_phys_addr_t addr,
>      return ret;
>  }
>  
> -static void slavio_intctlm_mem_writel(void *opaque, target_phys_addr_t addr,
> +static void slavio_intctlm_mem_writel(void *opaque, hwaddr addr,
>                                        uint64_t val, unsigned size)
>  {
>      SLAVIO_INTCTLState *s = opaque;
> diff --git a/hw/slavio_misc.c b/hw/slavio_misc.c
> index 944835e..682fb45 100644
> --- a/hw/slavio_misc.c
> +++ b/hw/slavio_misc.c
> @@ -107,7 +107,7 @@ static void slavio_set_power_fail(void *opaque, int irq, int power_failing)
>      slavio_misc_update_irq(s);
>  }
>  
> -static void slavio_cfg_mem_writeb(void *opaque, target_phys_addr_t addr,
> +static void slavio_cfg_mem_writeb(void *opaque, hwaddr addr,
>                                    uint64_t val, unsigned size)
>  {
>      MiscState *s = opaque;
> @@ -117,7 +117,7 @@ static void slavio_cfg_mem_writeb(void *opaque, target_phys_addr_t addr,
>      slavio_misc_update_irq(s);
>  }
>  
> -static uint64_t slavio_cfg_mem_readb(void *opaque, target_phys_addr_t addr,
> +static uint64_t slavio_cfg_mem_readb(void *opaque, hwaddr addr,
>                                       unsigned size)
>  {
>      MiscState *s = opaque;
> @@ -138,7 +138,7 @@ static uint64_t slavio_cfg_mem_readb(void *opaque, target_phys_addr_t addr,
>      },
>  };
>  
> -static void slavio_diag_mem_writeb(void *opaque, target_phys_addr_t addr,
> +static void slavio_diag_mem_writeb(void *opaque, hwaddr addr,
>                                     uint64_t val, unsigned size)
>  {
>      MiscState *s = opaque;
> @@ -147,7 +147,7 @@ static void slavio_diag_mem_writeb(void *opaque, target_phys_addr_t addr,
>      s->diag = val & 0xff;
>  }
>  
> -static uint64_t slavio_diag_mem_readb(void *opaque, target_phys_addr_t addr,
> +static uint64_t slavio_diag_mem_readb(void *opaque, hwaddr addr,
>                                        unsigned size)
>  {
>      MiscState *s = opaque;
> @@ -168,7 +168,7 @@ static uint64_t slavio_diag_mem_readb(void *opaque, target_phys_addr_t addr,
>      },
>  };
>  
> -static void slavio_mdm_mem_writeb(void *opaque, target_phys_addr_t addr,
> +static void slavio_mdm_mem_writeb(void *opaque, hwaddr addr,
>                                    uint64_t val, unsigned size)
>  {
>      MiscState *s = opaque;
> @@ -177,7 +177,7 @@ static void slavio_mdm_mem_writeb(void *opaque, target_phys_addr_t addr,
>      s->mctrl = val & 0xff;
>  }
>  
> -static uint64_t slavio_mdm_mem_readb(void *opaque, target_phys_addr_t addr,
> +static uint64_t slavio_mdm_mem_readb(void *opaque, hwaddr addr,
>                                       unsigned size)
>  {
>      MiscState *s = opaque;
> @@ -198,7 +198,7 @@ static uint64_t slavio_mdm_mem_readb(void *opaque, target_phys_addr_t addr,
>      },
>  };
>  
> -static void slavio_aux1_mem_writeb(void *opaque, target_phys_addr_t addr,
> +static void slavio_aux1_mem_writeb(void *opaque, hwaddr addr,
>                                     uint64_t val, unsigned size)
>  {
>      MiscState *s = opaque;
> @@ -215,7 +215,7 @@ static void slavio_aux1_mem_writeb(void *opaque, target_phys_addr_t addr,
>      s->aux1 = val & 0xff;
>  }
>  
> -static uint64_t slavio_aux1_mem_readb(void *opaque, target_phys_addr_t addr,
> +static uint64_t slavio_aux1_mem_readb(void *opaque, hwaddr addr,
>                                        unsigned size)
>  {
>      MiscState *s = opaque;
> @@ -236,7 +236,7 @@ static uint64_t slavio_aux1_mem_readb(void *opaque, target_phys_addr_t addr,
>      },
>  };
>  
> -static void slavio_aux2_mem_writeb(void *opaque, target_phys_addr_t addr,
> +static void slavio_aux2_mem_writeb(void *opaque, hwaddr addr,
>                                     uint64_t val, unsigned size)
>  {
>      MiscState *s = opaque;
> @@ -252,7 +252,7 @@ static void slavio_aux2_mem_writeb(void *opaque, target_phys_addr_t addr,
>      slavio_misc_update_irq(s);
>  }
>  
> -static uint64_t slavio_aux2_mem_readb(void *opaque, target_phys_addr_t addr,
> +static uint64_t slavio_aux2_mem_readb(void *opaque, hwaddr addr,
>                                        unsigned size)
>  {
>      MiscState *s = opaque;
> @@ -273,7 +273,7 @@ static uint64_t slavio_aux2_mem_readb(void *opaque, target_phys_addr_t addr,
>      },
>  };
>  
> -static void apc_mem_writeb(void *opaque, target_phys_addr_t addr,
> +static void apc_mem_writeb(void *opaque, hwaddr addr,
>                             uint64_t val, unsigned size)
>  {
>      APCState *s = opaque;
> @@ -282,7 +282,7 @@ static void apc_mem_writeb(void *opaque, target_phys_addr_t addr,
>      qemu_irq_raise(s->cpu_halt);
>  }
>  
> -static uint64_t apc_mem_readb(void *opaque, target_phys_addr_t addr,
> +static uint64_t apc_mem_readb(void *opaque, hwaddr addr,
>                                unsigned size)
>  {
>      uint32_t ret = 0;
> @@ -301,7 +301,7 @@ static uint64_t apc_mem_readb(void *opaque, target_phys_addr_t addr,
>      }
>  };
>  
> -static uint64_t slavio_sysctrl_mem_readl(void *opaque, target_phys_addr_t addr,
> +static uint64_t slavio_sysctrl_mem_readl(void *opaque, hwaddr addr,
>                                           unsigned size)
>  {
>      MiscState *s = opaque;
> @@ -318,7 +318,7 @@ static uint64_t slavio_sysctrl_mem_readl(void *opaque, target_phys_addr_t addr,
>      return ret;
>  }
>  
> -static void slavio_sysctrl_mem_writel(void *opaque, target_phys_addr_t addr,
> +static void slavio_sysctrl_mem_writel(void *opaque, hwaddr addr,
>                                        uint64_t val, unsigned size)
>  {
>      MiscState *s = opaque;
> @@ -346,7 +346,7 @@ static void slavio_sysctrl_mem_writel(void *opaque, target_phys_addr_t addr,
>      },
>  };
>  
> -static uint64_t slavio_led_mem_readw(void *opaque, target_phys_addr_t addr,
> +static uint64_t slavio_led_mem_readw(void *opaque, hwaddr addr,
>                                       unsigned size)
>  {
>      MiscState *s = opaque;
> @@ -363,7 +363,7 @@ static uint64_t slavio_led_mem_readw(void *opaque, target_phys_addr_t addr,
>      return ret;
>  }
>  
> -static void slavio_led_mem_writew(void *opaque, target_phys_addr_t addr,
> +static void slavio_led_mem_writew(void *opaque, hwaddr addr,
>                                    uint64_t val, unsigned size)
>  {
>      MiscState *s = opaque;
> diff --git a/hw/slavio_timer.c b/hw/slavio_timer.c
> index 97edebb..c07ceb1 100644
> --- a/hw/slavio_timer.c
> +++ b/hw/slavio_timer.c
> @@ -130,7 +130,7 @@ static void slavio_timer_irq(void *opaque)
>      }
>  }
>  
> -static uint64_t slavio_timer_mem_readl(void *opaque, target_phys_addr_t addr,
> +static uint64_t slavio_timer_mem_readl(void *opaque, hwaddr addr,
>                                         unsigned size)
>  {
>      TimerContext *tc = opaque;
> @@ -190,7 +190,7 @@ static uint64_t slavio_timer_mem_readl(void *opaque, target_phys_addr_t addr,
>      return ret;
>  }
>  
> -static void slavio_timer_mem_writel(void *opaque, target_phys_addr_t addr,
> +static void slavio_timer_mem_writel(void *opaque, hwaddr addr,
>                                      uint64_t val, unsigned size)
>  {
>      TimerContext *tc = opaque;
> diff --git a/hw/sm501.c b/hw/sm501.c
> index 050d096..4aafe49 100644
> --- a/hw/sm501.c
> +++ b/hw/sm501.c
> @@ -456,7 +456,7 @@
>      DisplayState *ds;
>  
>      /* status & internal resources */
> -    target_phys_addr_t base;
> +    hwaddr base;
>      uint32_t local_mem_size_index;
>      uint8_t * local_mem;
>      MemoryRegion local_mem_region;
> @@ -726,7 +726,7 @@ static void sm501_2d_operation(SM501State * s)
>      }
>  }
>  
> -static uint64_t sm501_system_config_read(void *opaque, target_phys_addr_t addr,
> +static uint64_t sm501_system_config_read(void *opaque, hwaddr addr,
>                                           unsigned size)
>  {
>      SM501State * s = (SM501State *)opaque;
> @@ -779,7 +779,7 @@ static uint64_t sm501_system_config_read(void *opaque, target_phys_addr_t addr,
>      return ret;
>  }
>  
> -static void sm501_system_config_write(void *opaque, target_phys_addr_t addr,
> +static void sm501_system_config_write(void *opaque, hwaddr addr,
>                                        uint64_t value, unsigned size)
>  {
>      SM501State * s = (SM501State *)opaque;
> @@ -837,7 +837,7 @@ static void sm501_system_config_write(void *opaque, target_phys_addr_t addr,
>      .endianness = DEVICE_NATIVE_ENDIAN,
>  };
>  
> -static uint32_t sm501_palette_read(void *opaque, target_phys_addr_t addr)
> +static uint32_t sm501_palette_read(void *opaque, hwaddr addr)
>  {
>      SM501State * s = (SM501State *)opaque;
>      SM501_DPRINTF("sm501 palette read addr=%x\n", (int)addr);
> @@ -850,7 +850,7 @@ static uint32_t sm501_palette_read(void *opaque, target_phys_addr_t addr)
>  }
>  
>  static void sm501_palette_write(void *opaque,
> -				target_phys_addr_t addr, uint32_t value)
> +				hwaddr addr, uint32_t value)
>  {
>      SM501State * s = (SM501State *)opaque;
>      SM501_DPRINTF("sm501 palette write addr=%x, val=%x\n",
> @@ -863,7 +863,7 @@ static void sm501_palette_write(void *opaque,
>      *(uint32_t*)&s->dc_palette[addr] = value;
>  }
>  
> -static uint64_t sm501_disp_ctrl_read(void *opaque, target_phys_addr_t addr,
> +static uint64_t sm501_disp_ctrl_read(void *opaque, hwaddr addr,
>                                       unsigned size)
>  {
>      SM501State * s = (SM501State *)opaque;
> @@ -958,7 +958,7 @@ static uint64_t sm501_disp_ctrl_read(void *opaque, target_phys_addr_t addr,
>      return ret;
>  }
>  
> -static void sm501_disp_ctrl_write(void *opaque, target_phys_addr_t addr,
> +static void sm501_disp_ctrl_write(void *opaque, hwaddr addr,
>                                    uint64_t value, unsigned size)
>  {
>      SM501State * s = (SM501State *)opaque;
> @@ -1073,7 +1073,7 @@ static void sm501_disp_ctrl_write(void *opaque, target_phys_addr_t addr,
>      .endianness = DEVICE_NATIVE_ENDIAN,
>  };
>  
> -static uint64_t sm501_2d_engine_read(void *opaque, target_phys_addr_t addr,
> +static uint64_t sm501_2d_engine_read(void *opaque, hwaddr addr,
>                                       unsigned size)
>  {
>      SM501State * s = (SM501State *)opaque;
> @@ -1093,7 +1093,7 @@ static uint64_t sm501_2d_engine_read(void *opaque, target_phys_addr_t addr,
>      return ret;
>  }
>  
> -static void sm501_2d_engine_write(void *opaque, target_phys_addr_t addr,
> +static void sm501_2d_engine_write(void *opaque, hwaddr addr,
>                                    uint64_t value, unsigned size)
>  {
>      SM501State * s = (SM501State *)opaque;
> diff --git a/hw/smc91c111.c b/hw/smc91c111.c
> index d6ef302..4ceed01 100644
> --- a/hw/smc91c111.c
> +++ b/hw/smc91c111.c
> @@ -276,7 +276,7 @@ static void smc91c111_reset(DeviceState *dev)
>  #define SET_LOW(name, val) s->name = (s->name & 0xff00) | val
>  #define SET_HIGH(name, val) s->name = (s->name & 0xff) | (val << 8)
>  
> -static void smc91c111_writeb(void *opaque, target_phys_addr_t offset,
> +static void smc91c111_writeb(void *opaque, hwaddr offset,
>                               uint32_t value)
>  {
>      smc91c111_state *s = (smc91c111_state *)opaque;
> @@ -451,7 +451,7 @@ static void smc91c111_writeb(void *opaque, target_phys_addr_t offset,
>      hw_error("smc91c111_write: Bad reg %d:%x\n", s->bank, (int)offset);
>  }
>  
> -static uint32_t smc91c111_readb(void *opaque, target_phys_addr_t offset)
> +static uint32_t smc91c111_readb(void *opaque, hwaddr offset)
>  {
>      smc91c111_state *s = (smc91c111_state *)opaque;
>  
> @@ -595,14 +595,14 @@ static uint32_t smc91c111_readb(void *opaque, target_phys_addr_t offset)
>      return 0;
>  }
>  
> -static void smc91c111_writew(void *opaque, target_phys_addr_t offset,
> +static void smc91c111_writew(void *opaque, hwaddr offset,
>                               uint32_t value)
>  {
>      smc91c111_writeb(opaque, offset, value & 0xff);
>      smc91c111_writeb(opaque, offset + 1, value >> 8);
>  }
>  
> -static void smc91c111_writel(void *opaque, target_phys_addr_t offset,
> +static void smc91c111_writel(void *opaque, hwaddr offset,
>                               uint32_t value)
>  {
>      /* 32-bit writes to offset 0xc only actually write to the bank select
> @@ -612,7 +612,7 @@ static void smc91c111_writel(void *opaque, target_phys_addr_t offset,
>      smc91c111_writew(opaque, offset + 2, value >> 16);
>  }
>  
> -static uint32_t smc91c111_readw(void *opaque, target_phys_addr_t offset)
> +static uint32_t smc91c111_readw(void *opaque, hwaddr offset)
>  {
>      uint32_t val;
>      val = smc91c111_readb(opaque, offset);
> @@ -620,7 +620,7 @@ static uint32_t smc91c111_readw(void *opaque, target_phys_addr_t offset)
>      return val;
>  }
>  
> -static uint32_t smc91c111_readl(void *opaque, target_phys_addr_t offset)
> +static uint32_t smc91c111_readl(void *opaque, hwaddr offset)
>  {
>      uint32_t val;
>      val = smc91c111_readw(opaque, offset);
> diff --git a/hw/soc_dma.c b/hw/soc_dma.c
> index 03bc846..50d5f84 100644
> --- a/hw/soc_dma.c
> +++ b/hw/soc_dma.c
> @@ -64,7 +64,7 @@ struct dma_s {
>  
>      struct memmap_entry_s {
>          enum soc_dma_port_type type;
> -        target_phys_addr_t addr;
> +        hwaddr addr;
>          union {
>             struct {
>                 void *opaque;
> @@ -105,7 +105,7 @@ static void soc_dma_ch_run(void *opaque)
>  }
>  
>  static inline struct memmap_entry_s *soc_dma_lookup(struct dma_s *dma,
> -                target_phys_addr_t addr)
> +                hwaddr addr)
>  {
>      struct memmap_entry_s *lo;
>      int hi;
> @@ -255,7 +255,7 @@ struct soc_dma_s *soc_dma_init(int n)
>      return &s->soc;
>  }
>  
> -void soc_dma_port_add_fifo(struct soc_dma_s *soc, target_phys_addr_t virt_base,
> +void soc_dma_port_add_fifo(struct soc_dma_s *soc, hwaddr virt_base,
>                  soc_dma_io_t fn, void *opaque, int out)
>  {
>      struct memmap_entry_s *entry;
> @@ -308,7 +308,7 @@ void soc_dma_port_add_fifo(struct soc_dma_s *soc, target_phys_addr_t virt_base,
>  }
>  
>  void soc_dma_port_add_mem(struct soc_dma_s *soc, uint8_t *phys_base,
> -                target_phys_addr_t virt_base, size_t size)
> +                hwaddr virt_base, size_t size)
>  {
>      struct memmap_entry_s *entry;
>      struct dma_s *dma = (struct dma_s *) soc;
> diff --git a/hw/soc_dma.h b/hw/soc_dma.h
> index 904b26c..9340b8f 100644
> --- a/hw/soc_dma.h
> +++ b/hw/soc_dma.h
> @@ -51,7 +51,7 @@ struct soc_dma_ch_s {
>      int bytes;
>      /* Initialised by the DMA module, call soc_dma_ch_update after writing.  */
>      enum soc_dma_access_type type[2];
> -    target_phys_addr_t vaddr[2];	/* Updated by .transfer_fn().  */
> +    hwaddr vaddr[2];	/* Updated by .transfer_fn().  */
>      /* Private */
>      void *paddr[2];
>      soc_dma_io_t io_fn[2];
> @@ -91,19 +91,19 @@ void soc_dma_ch_update(struct soc_dma_ch_s *ch);
>  void soc_dma_reset(struct soc_dma_s *s);
>  struct soc_dma_s *soc_dma_init(int n);
>  
> -void soc_dma_port_add_fifo(struct soc_dma_s *dma, target_phys_addr_t virt_base,
> +void soc_dma_port_add_fifo(struct soc_dma_s *dma, hwaddr virt_base,
>                  soc_dma_io_t fn, void *opaque, int out);
>  void soc_dma_port_add_mem(struct soc_dma_s *dma, uint8_t *phys_base,
> -                target_phys_addr_t virt_base, size_t size);
> +                hwaddr virt_base, size_t size);
>  
>  static inline void soc_dma_port_add_fifo_in(struct soc_dma_s *dma,
> -                target_phys_addr_t virt_base, soc_dma_io_t fn, void *opaque)
> +                hwaddr virt_base, soc_dma_io_t fn, void *opaque)
>  {
>      return soc_dma_port_add_fifo(dma, virt_base, fn, opaque, 0);
>  }
>  
>  static inline void soc_dma_port_add_fifo_out(struct soc_dma_s *dma,
> -                target_phys_addr_t virt_base, soc_dma_io_t fn, void *opaque)
> +                hwaddr virt_base, soc_dma_io_t fn, void *opaque)
>  {
>      return soc_dma_port_add_fifo(dma, virt_base, fn, opaque, 1);
>  }
> diff --git a/hw/spapr.c b/hw/spapr.c
> index 637b3fb..73d75e8 100644
> --- a/hw/spapr.c
> +++ b/hw/spapr.c
> @@ -228,9 +228,9 @@ static size_t create_page_sizes_prop(CPUPPCState *env, uint32_t *prop,
>  
>  
>  static void *spapr_create_fdt_skel(const char *cpu_model,
> -                                   target_phys_addr_t initrd_base,
> -                                   target_phys_addr_t initrd_size,
> -                                   target_phys_addr_t kernel_size,
> +                                   hwaddr initrd_base,
> +                                   hwaddr initrd_size,
> +                                   hwaddr kernel_size,
>                                     const char *boot_device,
>                                     const char *kernel_cmdline)
>  {
> @@ -445,7 +445,7 @@ static int spapr_populate_memory(sPAPREnvironment *spapr, void *fdt)
>                                  cpu_to_be32(0x0), cpu_to_be32(0x0),
>                                  cpu_to_be32(0x0)};
>      char mem_name[32];
> -    target_phys_addr_t node0_size, mem_start;
> +    hwaddr node0_size, mem_start;
>      uint64_t mem_reg_property[2];
>      int i, off;
>  
> @@ -502,9 +502,9 @@ static int spapr_populate_memory(sPAPREnvironment *spapr, void *fdt)
>  }
>  
>  static void spapr_finalize_fdt(sPAPREnvironment *spapr,
> -                               target_phys_addr_t fdt_addr,
> -                               target_phys_addr_t rtas_addr,
> -                               target_phys_addr_t rtas_size)
> +                               hwaddr fdt_addr,
> +                               hwaddr rtas_addr,
> +                               hwaddr rtas_size)
>  {
>      int ret;
>      void *fdt;
> @@ -679,7 +679,7 @@ static void ppc_spapr_init(QEMUMachineInitArgs *args)
>      int i;
>      MemoryRegion *sysmem = get_system_memory();
>      MemoryRegion *ram = g_new(MemoryRegion, 1);
> -    target_phys_addr_t rma_alloc_size;
> +    hwaddr rma_alloc_size;
>      uint32_t initrd_base = 0;
>      long kernel_size = 0, initrd_size = 0;
>      long load_limit, rtas_limit, fw_size;
> diff --git a/hw/spapr.h b/hw/spapr.h
> index e984e3f..8ee69bd 100644
> --- a/hw/spapr.h
> +++ b/hw/spapr.h
> @@ -13,12 +13,12 @@ typedef struct sPAPREnvironment {
>      QLIST_HEAD(, sPAPRPHBState) phbs;
>      struct icp_state *icp;
>  
> -    target_phys_addr_t ram_limit;
> +    hwaddr ram_limit;
>      void *htab;
>      long htab_shift;
> -    target_phys_addr_t rma_size;
> +    hwaddr rma_size;
>      int vrma_adjust;
> -    target_phys_addr_t fdt_addr, rtas_addr;
> +    hwaddr fdt_addr, rtas_addr;
>      long rtas_size;
>      void *fdt_skel;
>      target_ulong entry_point;
> @@ -321,8 +321,8 @@ void spapr_rtas_register(const char *name, spapr_rtas_fn fn);
>  target_ulong spapr_rtas_call(sPAPREnvironment *spapr,
>                               uint32_t token, uint32_t nargs, target_ulong args,
>                               uint32_t nret, target_ulong rets);
> -int spapr_rtas_device_tree_setup(void *fdt, target_phys_addr_t rtas_addr,
> -                                 target_phys_addr_t rtas_size);
> +int spapr_rtas_device_tree_setup(void *fdt, hwaddr rtas_addr,
> +                                 hwaddr rtas_size);
>  
>  #define SPAPR_TCE_PAGE_SHIFT   12
>  #define SPAPR_TCE_PAGE_SIZE    (1ULL << SPAPR_TCE_PAGE_SHIFT)
> diff --git a/hw/spapr_iommu.c b/hw/spapr_iommu.c
> index 33f84e2..86dc8f9 100644
> --- a/hw/spapr_iommu.c
> +++ b/hw/spapr_iommu.c
> @@ -66,8 +66,8 @@ static sPAPRTCETable *spapr_tce_find_by_liobn(uint32_t liobn)
>  
>  static int spapr_tce_translate(DMAContext *dma,
>                                 dma_addr_t addr,
> -                               target_phys_addr_t *paddr,
> -                               target_phys_addr_t *len,
> +                               hwaddr *paddr,
> +                               hwaddr *len,
>                                 DMADirection dir)
>  {
>      sPAPRTCETable *tcet = DO_UPCAST(sPAPRTCETable, dma, dma);
> @@ -82,7 +82,7 @@ static int spapr_tce_translate(DMAContext *dma,
>  
>      if (tcet->bypass) {
>          *paddr = addr;
> -        *len = (target_phys_addr_t)-1;
> +        *len = (hwaddr)-1;
>          return 0;
>      }
>  
> diff --git a/hw/spapr_pci.c b/hw/spapr_pci.c
> index b628f89..a08ed11 100644
> --- a/hw/spapr_pci.c
> +++ b/hw/spapr_pci.c
> @@ -258,7 +258,7 @@ static int spapr_msicfg_find(sPAPRPHBState *phb, uint32_t config_addr,
>   * This is required for msi_notify()/msix_notify() which
>   * will write at the addresses via spapr_msi_write().
>   */
> -static void spapr_msi_setmsg(PCIDevice *pdev, target_phys_addr_t addr,
> +static void spapr_msi_setmsg(PCIDevice *pdev, hwaddr addr,
>                               bool msix, unsigned req_num)
>  {
>      unsigned i;
> @@ -439,7 +439,7 @@ static void pci_spapr_set_irq(void *opaque, int irq_num, int level)
>      qemu_set_irq(spapr_phb_lsi_qirq(phb, irq_num), level);
>  }
>  
> -static uint64_t spapr_io_read(void *opaque, target_phys_addr_t addr,
> +static uint64_t spapr_io_read(void *opaque, hwaddr addr,
>                                unsigned size)
>  {
>      switch (size) {
> @@ -453,7 +453,7 @@ static uint64_t spapr_io_read(void *opaque, target_phys_addr_t addr,
>      assert(0);
>  }
>  
> -static void spapr_io_write(void *opaque, target_phys_addr_t addr,
> +static void spapr_io_write(void *opaque, hwaddr addr,
>                             uint64_t data, unsigned size)
>  {
>      switch (size) {
> @@ -483,7 +483,7 @@ static void spapr_io_write(void *opaque, target_phys_addr_t addr,
>   * data is set to 0.
>   * For MSI, the vector number is encoded in least bits in data.
>   */
> -static void spapr_msi_write(void *opaque, target_phys_addr_t addr,
> +static void spapr_msi_write(void *opaque, hwaddr addr,
>                              uint64_t data, unsigned size)
>  {
>      sPAPRPHBState *phb = opaque;
> diff --git a/hw/spapr_pci.h b/hw/spapr_pci.h
> index 670dc62..e307ac8 100644
> --- a/hw/spapr_pci.h
> +++ b/hw/spapr_pci.h
> @@ -42,8 +42,8 @@ typedef struct sPAPRPHBState {
>      char *dtbusname;
>  
>      MemoryRegion memspace, iospace;
> -    target_phys_addr_t mem_win_addr, mem_win_size, io_win_addr, io_win_size;
> -    target_phys_addr_t msi_win_addr;
> +    hwaddr mem_win_addr, mem_win_size, io_win_addr, io_win_size;
> +    hwaddr msi_win_addr;
>      MemoryRegion memwindow, iowindow, msiwindow;
>  
>      uint32_t dma_liobn;
> diff --git a/hw/spapr_rtas.c b/hw/spapr_rtas.c
> index b808f80..67da27b 100644
> --- a/hw/spapr_rtas.c
> +++ b/hw/spapr_rtas.c
> @@ -249,8 +249,8 @@ void spapr_rtas_register(const char *name, spapr_rtas_fn fn)
>      rtas_next++;
>  }
>  
> -int spapr_rtas_device_tree_setup(void *fdt, target_phys_addr_t rtas_addr,
> -                                 target_phys_addr_t rtas_size)
> +int spapr_rtas_device_tree_setup(void *fdt, hwaddr rtas_addr,
> +                                 hwaddr rtas_size)
>  {
>      int ret;
>      int i;
> diff --git a/hw/sparc32_dma.c b/hw/sparc32_dma.c
> index 1dbf69e..d11a302 100644
> --- a/hw/sparc32_dma.c
> +++ b/hw/sparc32_dma.c
> @@ -78,7 +78,7 @@ enum {
>  };
>  
>  /* Note: on sparc, the lance 16 bit bus is swapped */
> -void ledma_memory_read(void *opaque, target_phys_addr_t addr,
> +void ledma_memory_read(void *opaque, hwaddr addr,
>                         uint8_t *buf, int len, int do_bswap)
>  {
>      DMAState *s = opaque;
> @@ -98,7 +98,7 @@ void ledma_memory_read(void *opaque, target_phys_addr_t addr,
>      }
>  }
>  
> -void ledma_memory_write(void *opaque, target_phys_addr_t addr,
> +void ledma_memory_write(void *opaque, hwaddr addr,
>                          uint8_t *buf, int len, int do_bswap)
>  {
>      DMAState *s = opaque;
> @@ -165,7 +165,7 @@ void espdma_memory_write(void *opaque, uint8_t *buf, int len)
>      s->dmaregs[1] += len;
>  }
>  
> -static uint64_t dma_mem_read(void *opaque, target_phys_addr_t addr,
> +static uint64_t dma_mem_read(void *opaque, hwaddr addr,
>                               unsigned size)
>  {
>      DMAState *s = opaque;
> @@ -182,7 +182,7 @@ static uint64_t dma_mem_read(void *opaque, target_phys_addr_t addr,
>      return s->dmaregs[saddr];
>  }
>  
> -static void dma_mem_write(void *opaque, target_phys_addr_t addr,
> +static void dma_mem_write(void *opaque, hwaddr addr,
>                            uint64_t val, unsigned size)
>  {
>      DMAState *s = opaque;
> diff --git a/hw/sparc32_dma.h b/hw/sparc32_dma.h
> index 8b72c37..9497b13 100644
> --- a/hw/sparc32_dma.h
> +++ b/hw/sparc32_dma.h
> @@ -2,9 +2,9 @@
>  #define SPARC32_DMA_H
>  
>  /* sparc32_dma.c */
> -void ledma_memory_read(void *opaque, target_phys_addr_t addr,
> +void ledma_memory_read(void *opaque, hwaddr addr,
>                         uint8_t *buf, int len, int do_bswap);
> -void ledma_memory_write(void *opaque, target_phys_addr_t addr,
> +void ledma_memory_write(void *opaque, hwaddr addr,
>                          uint8_t *buf, int len, int do_bswap);
>  void espdma_memory_read(void *opaque, uint8_t *buf, int len);
>  void espdma_memory_write(void *opaque, uint8_t *buf, int len);
> diff --git a/hw/spitz.c b/hw/spitz.c
> index 2942626..944c274 100644
> --- a/hw/spitz.c
> +++ b/hw/spitz.c
> @@ -60,7 +60,7 @@
>      ECCState ecc;
>  } SLNANDState;
>  
> -static uint64_t sl_read(void *opaque, target_phys_addr_t addr, unsigned size)
> +static uint64_t sl_read(void *opaque, hwaddr addr, unsigned size)
>  {
>      SLNANDState *s = (SLNANDState *) opaque;
>      int ryby;
> @@ -102,7 +102,7 @@ static uint64_t sl_read(void *opaque, target_phys_addr_t addr, unsigned size)
>      return 0;
>  }
>  
> -static void sl_write(void *opaque, target_phys_addr_t addr,
> +static void sl_write(void *opaque, hwaddr addr,
>                       uint64_t value, unsigned size)
>  {
>      SLNANDState *s = (SLNANDState *) opaque;
> diff --git a/hw/stellaris.c b/hw/stellaris.c
> index bfb18b0..b038f10 100644
> --- a/hw/stellaris.c
> +++ b/hw/stellaris.c
> @@ -141,7 +141,7 @@ static void gptm_tick(void *opaque)
>      gptm_update_irq(s);
>  }
>  
> -static uint64_t gptm_read(void *opaque, target_phys_addr_t offset,
> +static uint64_t gptm_read(void *opaque, hwaddr offset,
>                            unsigned size)
>  {
>      gptm_state *s = (gptm_state *)opaque;
> @@ -190,7 +190,7 @@ static uint64_t gptm_read(void *opaque, target_phys_addr_t offset,
>      }
>  }
>  
> -static void gptm_write(void *opaque, target_phys_addr_t offset,
> +static void gptm_write(void *opaque, hwaddr offset,
>                         uint64_t value, unsigned size)
>  {
>      gptm_state *s = (gptm_state *)opaque;
> @@ -410,7 +410,7 @@ static int ssys_board_class(const ssys_state *s)
>      }
>  }
>  
> -static uint64_t ssys_read(void *opaque, target_phys_addr_t offset,
> +static uint64_t ssys_read(void *opaque, hwaddr offset,
>                            unsigned size)
>  {
>      ssys_state *s = (ssys_state *)opaque;
> @@ -515,7 +515,7 @@ static void ssys_calculate_system_clock(ssys_state *s)
>      }
>  }
>  
> -static void ssys_write(void *opaque, target_phys_addr_t offset,
> +static void ssys_write(void *opaque, hwaddr offset,
>                         uint64_t value, unsigned size)
>  {
>      ssys_state *s = (ssys_state *)opaque;
> @@ -701,7 +701,7 @@ static int stellaris_sys_init(uint32_t base, qemu_irq irq,
>  #define STELLARIS_I2C_MCS_IDLE    0x20
>  #define STELLARIS_I2C_MCS_BUSBSY  0x40
>  
> -static uint64_t stellaris_i2c_read(void *opaque, target_phys_addr_t offset,
> +static uint64_t stellaris_i2c_read(void *opaque, hwaddr offset,
>                                     unsigned size)
>  {
>      stellaris_i2c_state *s = (stellaris_i2c_state *)opaque;
> @@ -738,7 +738,7 @@ static void stellaris_i2c_update(stellaris_i2c_state *s)
>      qemu_set_irq(s->irq, level);
>  }
>  
> -static void stellaris_i2c_write(void *opaque, target_phys_addr_t offset,
> +static void stellaris_i2c_write(void *opaque, hwaddr offset,
>                                  uint64_t value, unsigned size)
>  {
>      stellaris_i2c_state *s = (stellaris_i2c_state *)opaque;
> @@ -989,7 +989,7 @@ static void stellaris_adc_reset(stellaris_adc_state *s)
>      }
>  }
>  
> -static uint64_t stellaris_adc_read(void *opaque, target_phys_addr_t offset,
> +static uint64_t stellaris_adc_read(void *opaque, hwaddr offset,
>                                     unsigned size)
>  {
>      stellaris_adc_state *s = (stellaris_adc_state *)opaque;
> @@ -1037,7 +1037,7 @@ static uint64_t stellaris_adc_read(void *opaque, target_phys_addr_t offset,
>      }
>  }
>  
> -static void stellaris_adc_write(void *opaque, target_phys_addr_t offset,
> +static void stellaris_adc_write(void *opaque, hwaddr offset,
>                                  uint64_t value, unsigned size)
>  {
>      stellaris_adc_state *s = (stellaris_adc_state *)opaque;
> diff --git a/hw/stellaris_enet.c b/hw/stellaris_enet.c
> index bc97280..a530b10 100644
> --- a/hw/stellaris_enet.c
> +++ b/hw/stellaris_enet.c
> @@ -130,7 +130,7 @@ static int stellaris_enet_can_receive(NetClientState *nc)
>      return (s->np < 31);
>  }
>  
> -static uint64_t stellaris_enet_read(void *opaque, target_phys_addr_t offset,
> +static uint64_t stellaris_enet_read(void *opaque, hwaddr offset,
>                                      unsigned size)
>  {
>      stellaris_enet_state *s = (stellaris_enet_state *)opaque;
> @@ -198,7 +198,7 @@ static uint64_t stellaris_enet_read(void *opaque, target_phys_addr_t offset,
>      }
>  }
>  
> -static void stellaris_enet_write(void *opaque, target_phys_addr_t offset,
> +static void stellaris_enet_write(void *opaque, hwaddr offset,
>                                   uint64_t value, unsigned size)
>  {
>      stellaris_enet_state *s = (stellaris_enet_state *)opaque;
> diff --git a/hw/strongarm.c b/hw/strongarm.c
> index 7150eeb..4385515 100644
> --- a/hw/strongarm.c
> +++ b/hw/strongarm.c
> @@ -59,7 +59,7 @@
>  #endif
>  
>  static struct {
> -    target_phys_addr_t io_base;
> +    hwaddr io_base;
>      int irq;
>  } sa_serial[] = {
>      { 0x80010000, SA_PIC_UART1 },
> @@ -113,7 +113,7 @@ static void strongarm_pic_set_irq(void *opaque, int irq, int level)
>      strongarm_pic_update(s);
>  }
>  
> -static uint64_t strongarm_pic_mem_read(void *opaque, target_phys_addr_t offset,
> +static uint64_t strongarm_pic_mem_read(void *opaque, hwaddr offset,
>                                         unsigned size)
>  {
>      StrongARMPICState *s = opaque;
> @@ -138,7 +138,7 @@ static uint64_t strongarm_pic_mem_read(void *opaque, target_phys_addr_t offset,
>      }
>  }
>  
> -static void strongarm_pic_mem_write(void *opaque, target_phys_addr_t offset,
> +static void strongarm_pic_mem_write(void *opaque, hwaddr offset,
>                                      uint64_t value, unsigned size)
>  {
>      StrongARMPICState *s = opaque;
> @@ -294,7 +294,7 @@ static inline void strongarm_rtc_hz_tick(void *opaque)
>      strongarm_rtc_int_update(s);
>  }
>  
> -static uint64_t strongarm_rtc_read(void *opaque, target_phys_addr_t addr,
> +static uint64_t strongarm_rtc_read(void *opaque, hwaddr addr,
>                                     unsigned size)
>  {
>      StrongARMRTCState *s = opaque;
> @@ -316,7 +316,7 @@ static uint64_t strongarm_rtc_read(void *opaque, target_phys_addr_t addr,
>      }
>  }
>  
> -static void strongarm_rtc_write(void *opaque, target_phys_addr_t addr,
> +static void strongarm_rtc_write(void *opaque, hwaddr addr,
>                                  uint64_t value, unsigned size)
>  {
>      StrongARMRTCState *s = opaque;
> @@ -517,7 +517,7 @@ static void strongarm_gpio_handler_update(StrongARMGPIOInfo *s)
>      s->prev_level = level;
>  }
>  
> -static uint64_t strongarm_gpio_read(void *opaque, target_phys_addr_t offset,
> +static uint64_t strongarm_gpio_read(void *opaque, hwaddr offset,
>                                      unsigned size)
>  {
>      StrongARMGPIOInfo *s = opaque;
> @@ -559,7 +559,7 @@ static uint64_t strongarm_gpio_read(void *opaque, target_phys_addr_t offset,
>      return 0;
>  }
>  
> -static void strongarm_gpio_write(void *opaque, target_phys_addr_t offset,
> +static void strongarm_gpio_write(void *opaque, hwaddr offset,
>                                   uint64_t value, unsigned size)
>  {
>      StrongARMGPIOInfo *s = opaque;
> @@ -609,7 +609,7 @@ static void strongarm_gpio_write(void *opaque, target_phys_addr_t offset,
>      .endianness = DEVICE_NATIVE_ENDIAN,
>  };
>  
> -static DeviceState *strongarm_gpio_init(target_phys_addr_t base,
> +static DeviceState *strongarm_gpio_init(hwaddr base,
>                  DeviceState *pic)
>  {
>      DeviceState *dev;
> @@ -729,7 +729,7 @@ static void strongarm_ppc_handler_update(StrongARMPPCInfo *s)
>      s->prev_level = level;
>  }
>  
> -static uint64_t strongarm_ppc_read(void *opaque, target_phys_addr_t offset,
> +static uint64_t strongarm_ppc_read(void *opaque, hwaddr offset,
>                                     unsigned size)
>  {
>      StrongARMPPCInfo *s = opaque;
> @@ -759,7 +759,7 @@ static uint64_t strongarm_ppc_read(void *opaque, target_phys_addr_t offset,
>      return 0;
>  }
>  
> -static void strongarm_ppc_write(void *opaque, target_phys_addr_t offset,
> +static void strongarm_ppc_write(void *opaque, hwaddr offset,
>                                  uint64_t value, unsigned size)
>  {
>      StrongARMPPCInfo *s = opaque;
> @@ -1095,7 +1095,7 @@ static void strongarm_uart_tx(void *opaque)
>      strongarm_uart_update_int_status(s);
>  }
>  
> -static uint64_t strongarm_uart_read(void *opaque, target_phys_addr_t addr,
> +static uint64_t strongarm_uart_read(void *opaque, hwaddr addr,
>                                      unsigned size)
>  {
>      StrongARMUARTState *s = opaque;
> @@ -1137,7 +1137,7 @@ static uint64_t strongarm_uart_read(void *opaque, target_phys_addr_t addr,
>      }
>  }
>  
> -static void strongarm_uart_write(void *opaque, target_phys_addr_t addr,
> +static void strongarm_uart_write(void *opaque, hwaddr addr,
>                                   uint64_t value, unsigned size)
>  {
>      StrongARMUARTState *s = opaque;
> @@ -1376,7 +1376,7 @@ static void strongarm_ssp_fifo_update(StrongARMSSPState *s)
>      strongarm_ssp_int_update(s);
>  }
>  
> -static uint64_t strongarm_ssp_read(void *opaque, target_phys_addr_t addr,
> +static uint64_t strongarm_ssp_read(void *opaque, hwaddr addr,
>                                     unsigned size)
>  {
>      StrongARMSSPState *s = opaque;
> @@ -1409,7 +1409,7 @@ static uint64_t strongarm_ssp_read(void *opaque, target_phys_addr_t addr,
>      return 0;
>  }
>  
> -static void strongarm_ssp_write(void *opaque, target_phys_addr_t addr,
> +static void strongarm_ssp_write(void *opaque, hwaddr addr,
>                                  uint64_t value, unsigned size)
>  {
>      StrongARMSSPState *s = opaque;
> diff --git a/hw/sun4c_intctl.c b/hw/sun4c_intctl.c
> index 8dfa5ec..8cd70ab 100644
> --- a/hw/sun4c_intctl.c
> +++ b/hw/sun4c_intctl.c
> @@ -61,7 +61,7 @@
>  
>  static void sun4c_check_interrupts(void *opaque);
>  
> -static uint64_t sun4c_intctl_mem_read(void *opaque, target_phys_addr_t addr,
> +static uint64_t sun4c_intctl_mem_read(void *opaque, hwaddr addr,
>                                        unsigned size)
>  {
>      Sun4c_INTCTLState *s = opaque;
> @@ -73,7 +73,7 @@ static uint64_t sun4c_intctl_mem_read(void *opaque, target_phys_addr_t addr,
>      return ret;
>  }
>  
> -static void sun4c_intctl_mem_write(void *opaque, target_phys_addr_t addr,
> +static void sun4c_intctl_mem_write(void *opaque, hwaddr addr,
>                                     uint64_t val, unsigned size)
>  {
>      Sun4c_INTCTLState *s = opaque;
> diff --git a/hw/sun4m.c b/hw/sun4m.c
> index dbe93f9..02673b2 100644
> --- a/hw/sun4m.c
> +++ b/hw/sun4m.c
> @@ -87,16 +87,16 @@
>  #define ESCC_CLOCK 4915200
>  
>  struct sun4m_hwdef {
> -    target_phys_addr_t iommu_base, iommu_pad_base, iommu_pad_len, slavio_base;
> -    target_phys_addr_t intctl_base, counter_base, nvram_base, ms_kb_base;
> -    target_phys_addr_t serial_base, fd_base;
> -    target_phys_addr_t afx_base, idreg_base, dma_base, esp_base, le_base;
> -    target_phys_addr_t tcx_base, cs_base, apc_base, aux1_base, aux2_base;
> -    target_phys_addr_t bpp_base, dbri_base, sx_base;
> +    hwaddr iommu_base, iommu_pad_base, iommu_pad_len, slavio_base;
> +    hwaddr intctl_base, counter_base, nvram_base, ms_kb_base;
> +    hwaddr serial_base, fd_base;
> +    hwaddr afx_base, idreg_base, dma_base, esp_base, le_base;
> +    hwaddr tcx_base, cs_base, apc_base, aux1_base, aux2_base;
> +    hwaddr bpp_base, dbri_base, sx_base;
>      struct {
> -        target_phys_addr_t reg_base, vram_base;
> +        hwaddr reg_base, vram_base;
>      } vsimm[MAX_VSIMMS];
> -    target_phys_addr_t ecc_base;
> +    hwaddr ecc_base;
>      uint64_t max_mem;
>      const char * const default_cpu_model;
>      uint32_t ecc_version;
> @@ -108,13 +108,13 @@ struct sun4m_hwdef {
>  #define MAX_IOUNITS 5
>  
>  struct sun4d_hwdef {
> -    target_phys_addr_t iounit_bases[MAX_IOUNITS], slavio_base;
> -    target_phys_addr_t counter_base, nvram_base, ms_kb_base;
> -    target_phys_addr_t serial_base;
> -    target_phys_addr_t espdma_base, esp_base;
> -    target_phys_addr_t ledma_base, le_base;
> -    target_phys_addr_t tcx_base;
> -    target_phys_addr_t sbi_base;
> +    hwaddr iounit_bases[MAX_IOUNITS], slavio_base;
> +    hwaddr counter_base, nvram_base, ms_kb_base;
> +    hwaddr serial_base;
> +    hwaddr espdma_base, esp_base;
> +    hwaddr ledma_base, le_base;
> +    hwaddr tcx_base;
> +    hwaddr sbi_base;
>      uint64_t max_mem;
>      const char * const default_cpu_model;
>      uint32_t iounit_version;
> @@ -123,11 +123,11 @@ struct sun4d_hwdef {
>  };
>  
>  struct sun4c_hwdef {
> -    target_phys_addr_t iommu_base, slavio_base;
> -    target_phys_addr_t intctl_base, counter_base, nvram_base, ms_kb_base;
> -    target_phys_addr_t serial_base, fd_base;
> -    target_phys_addr_t idreg_base, dma_base, esp_base, le_base;
> -    target_phys_addr_t tcx_base, aux1_base;
> +    hwaddr iommu_base, slavio_base;
> +    hwaddr intctl_base, counter_base, nvram_base, ms_kb_base;
> +    hwaddr serial_base, fd_base;
> +    hwaddr idreg_base, dma_base, esp_base, le_base;
> +    hwaddr tcx_base, aux1_base;
>      uint64_t max_mem;
>      const char * const default_cpu_model;
>      uint32_t iommu_version;
> @@ -373,7 +373,7 @@ static unsigned long sun4m_load_kernel(const char *kernel_filename,
>      return kernel_size;
>  }
>  
> -static void *iommu_init(target_phys_addr_t addr, uint32_t version, qemu_irq irq)
> +static void *iommu_init(hwaddr addr, uint32_t version, qemu_irq irq)
>  {
>      DeviceState *dev;
>      SysBusDevice *s;
> @@ -388,7 +388,7 @@ static void *iommu_init(target_phys_addr_t addr, uint32_t version, qemu_irq irq)
>      return s;
>  }
>  
> -static void *sparc32_dma_init(target_phys_addr_t daddr, qemu_irq parent_irq,
> +static void *sparc32_dma_init(hwaddr daddr, qemu_irq parent_irq,
>                                void *iommu, qemu_irq *dev_irq, int is_ledma)
>  {
>      DeviceState *dev;
> @@ -406,7 +406,7 @@ static void *sparc32_dma_init(target_phys_addr_t daddr, qemu_irq parent_irq,
>      return s;
>  }
>  
> -static void lance_init(NICInfo *nd, target_phys_addr_t leaddr,
> +static void lance_init(NICInfo *nd, hwaddr leaddr,
>                         void *dma_opaque, qemu_irq irq)
>  {
>      DeviceState *dev;
> @@ -426,8 +426,8 @@ static void lance_init(NICInfo *nd, target_phys_addr_t leaddr,
>      qdev_connect_gpio_out(dma_opaque, 0, reset);
>  }
>  
> -static DeviceState *slavio_intctl_init(target_phys_addr_t addr,
> -                                       target_phys_addr_t addrg,
> +static DeviceState *slavio_intctl_init(hwaddr addr,
> +                                       hwaddr addrg,
>                                         qemu_irq **parent_irq)
>  {
>      DeviceState *dev;
> @@ -455,7 +455,7 @@ static DeviceState *slavio_intctl_init(target_phys_addr_t addr,
>  #define SYS_TIMER_OFFSET      0x10000ULL
>  #define CPU_TIMER_OFFSET(cpu) (0x1000ULL * cpu)
>  
> -static void slavio_timer_init_all(target_phys_addr_t addr, qemu_irq master_irq,
> +static void slavio_timer_init_all(hwaddr addr, qemu_irq master_irq,
>                                    qemu_irq *cpu_irqs, unsigned int num_cpus)
>  {
>      DeviceState *dev;
> @@ -470,7 +470,7 @@ static void slavio_timer_init_all(target_phys_addr_t addr, qemu_irq master_irq,
>      sysbus_mmio_map(s, 0, addr + SYS_TIMER_OFFSET);
>  
>      for (i = 0; i < MAX_CPUS; i++) {
> -        sysbus_mmio_map(s, i + 1, addr + (target_phys_addr_t)CPU_TIMER_OFFSET(i));
> +        sysbus_mmio_map(s, i + 1, addr + (hwaddr)CPU_TIMER_OFFSET(i));
>          sysbus_connect_irq(s, i + 1, cpu_irqs[i]);
>      }
>  }
> @@ -492,9 +492,9 @@ static void slavio_powerdown_req(Notifier *n, void *opaque)
>  #define MISC_MDM  0x01b00000
>  #define MISC_SYS  0x01f00000
>  
> -static void slavio_misc_init(target_phys_addr_t base,
> -                             target_phys_addr_t aux1_base,
> -                             target_phys_addr_t aux2_base, qemu_irq irq,
> +static void slavio_misc_init(hwaddr base,
> +                             hwaddr aux1_base,
> +                             hwaddr aux2_base, qemu_irq irq,
>                               qemu_irq fdc_tc)
>  {
>      DeviceState *dev;
> @@ -532,7 +532,7 @@ static void slavio_misc_init(target_phys_addr_t base,
>      qemu_register_powerdown_notifier(&slavio_system_powerdown_notifier);
>  }
>  
> -static void ecc_init(target_phys_addr_t base, qemu_irq irq, uint32_t version)
> +static void ecc_init(hwaddr base, qemu_irq irq, uint32_t version)
>  {
>      DeviceState *dev;
>      SysBusDevice *s;
> @@ -548,7 +548,7 @@ static void ecc_init(target_phys_addr_t base, qemu_irq irq, uint32_t version)
>      }
>  }
>  
> -static void apc_init(target_phys_addr_t power_base, qemu_irq cpu_halt)
> +static void apc_init(hwaddr power_base, qemu_irq cpu_halt)
>  {
>      DeviceState *dev;
>      SysBusDevice *s;
> @@ -561,7 +561,7 @@ static void apc_init(target_phys_addr_t power_base, qemu_irq cpu_halt)
>      sysbus_connect_irq(s, 0, cpu_halt);
>  }
>  
> -static void tcx_init(target_phys_addr_t addr, int vram_size, int width,
> +static void tcx_init(hwaddr addr, int vram_size, int width,
>                       int height, int depth)
>  {
>      DeviceState *dev;
> @@ -597,7 +597,7 @@ static void tcx_init(target_phys_addr_t addr, int vram_size, int width,
>  /* NCR89C100/MACIO Internal ID register */
>  static const uint8_t idreg_data[] = { 0xfe, 0x81, 0x01, 0x03 };
>  
> -static void idreg_init(target_phys_addr_t addr)
> +static void idreg_init(hwaddr addr)
>  {
>      DeviceState *dev;
>      SysBusDevice *s;
> @@ -646,7 +646,7 @@ static void idreg_class_init(ObjectClass *klass, void *data)
>  } AFXState;
>  
>  /* SS-5 TCX AFX register */
> -static void afx_init(target_phys_addr_t addr)
> +static void afx_init(hwaddr addr)
>  {
>      DeviceState *dev;
>      SysBusDevice *s;
> @@ -690,11 +690,11 @@ static void afx_class_init(ObjectClass *klass, void *data)
>  /* Boot PROM (OpenBIOS) */
>  static uint64_t translate_prom_address(void *opaque, uint64_t addr)
>  {
> -    target_phys_addr_t *base_addr = (target_phys_addr_t *)opaque;
> +    hwaddr *base_addr = (hwaddr *)opaque;
>      return addr + *base_addr - PROM_VADDR;
>  }
>  
> -static void prom_init(target_phys_addr_t addr, const char *bios_name)
> +static void prom_init(hwaddr addr, const char *bios_name)
>  {
>      DeviceState *dev;
>      SysBusDevice *s;
> @@ -777,7 +777,7 @@ static int ram_init1(SysBusDevice *dev)
>      return 0;
>  }
>  
> -static void ram_init(target_phys_addr_t addr, ram_addr_t RAM_size,
> +static void ram_init(hwaddr addr, ram_addr_t RAM_size,
>                       uint64_t max_mem)
>  {
>      DeviceState *dev;
> @@ -1544,7 +1544,7 @@ static void sbook_init(QEMUMachineInitArgs *args)
>      },
>  };
>  
> -static DeviceState *sbi_init(target_phys_addr_t addr, qemu_irq **parent_irq)
> +static DeviceState *sbi_init(hwaddr addr, qemu_irq **parent_irq)
>  {
>      DeviceState *dev;
>      SysBusDevice *s;
> @@ -1605,7 +1605,7 @@ static void sun4d_hw_init(const struct sun4d_hwdef *hwdef, ram_addr_t RAM_size,
>      }
>  
>      for (i = 0; i < MAX_IOUNITS; i++)
> -        if (hwdef->iounit_bases[i] != (target_phys_addr_t)-1)
> +        if (hwdef->iounit_bases[i] != (hwaddr)-1)
>              iounits[i] = iommu_init(hwdef->iounit_bases[i],
>                                      hwdef->iounit_version,
>                                      sbi_irq[0]);
> @@ -1744,7 +1744,7 @@ static void ss2000_init(QEMUMachineInitArgs *args)
>      },
>  };
>  
> -static DeviceState *sun4c_intctl_init(target_phys_addr_t addr,
> +static DeviceState *sun4c_intctl_init(hwaddr addr,
>                                        qemu_irq *parent_irq)
>  {
>      DeviceState *dev;
> @@ -1825,7 +1825,7 @@ static void sun4c_hw_init(const struct sun4c_hwdef *hwdef, ram_addr_t RAM_size,
>                slavio_irq[1], serial_hds[0], serial_hds[1],
>                ESCC_CLOCK, 1);
>  
> -    if (hwdef->fd_base != (target_phys_addr_t)-1) {
> +    if (hwdef->fd_base != (hwaddr)-1) {
>          /* there is zero or one floppy drive */
>          memset(fd, 0, sizeof(fd));
>          fd[0] = drive_get(IF_FLOPPY, 0, 0);
> diff --git a/hw/sun4m.h b/hw/sun4m.h
> index 504c3af..a8c3133 100644
> --- a/hw/sun4m.h
> +++ b/hw/sun4m.h
> @@ -6,17 +6,17 @@
>  /* Devices used by sparc32 system.  */
>  
>  /* iommu.c */
> -void sparc_iommu_memory_rw(void *opaque, target_phys_addr_t addr,
> +void sparc_iommu_memory_rw(void *opaque, hwaddr addr,
>                                   uint8_t *buf, int len, int is_write);
>  static inline void sparc_iommu_memory_read(void *opaque,
> -                                           target_phys_addr_t addr,
> +                                           hwaddr addr,
>                                             uint8_t *buf, int len)
>  {
>      sparc_iommu_memory_rw(opaque, addr, buf, len, 0);
>  }
>  
>  static inline void sparc_iommu_memory_write(void *opaque,
> -                                            target_phys_addr_t addr,
> +                                            hwaddr addr,
>                                              uint8_t *buf, int len)
>  {
>      sparc_iommu_memory_rw(opaque, addr, buf, len, 1);
> diff --git a/hw/sun4m_iommu.c b/hw/sun4m_iommu.c
> index ebefa91..ce6819e 100644
> --- a/hw/sun4m_iommu.c
> +++ b/hw/sun4m_iommu.c
> @@ -130,16 +130,16 @@
>      SysBusDevice busdev;
>      MemoryRegion iomem;
>      uint32_t regs[IOMMU_NREGS];
> -    target_phys_addr_t iostart;
> +    hwaddr iostart;
>      qemu_irq irq;
>      uint32_t version;
>  } IOMMUState;
>  
> -static uint64_t iommu_mem_read(void *opaque, target_phys_addr_t addr,
> +static uint64_t iommu_mem_read(void *opaque, hwaddr addr,
>                                 unsigned size)
>  {
>      IOMMUState *s = opaque;
> -    target_phys_addr_t saddr;
> +    hwaddr saddr;
>      uint32_t ret;
>  
>      saddr = addr >> 2;
> @@ -157,11 +157,11 @@ static uint64_t iommu_mem_read(void *opaque, target_phys_addr_t addr,
>      return ret;
>  }
>  
> -static void iommu_mem_write(void *opaque, target_phys_addr_t addr,
> +static void iommu_mem_write(void *opaque, hwaddr addr,
>                              uint64_t val, unsigned size)
>  {
>      IOMMUState *s = opaque;
> -    target_phys_addr_t saddr;
> +    hwaddr saddr;
>  
>      saddr = addr >> 2;
>      trace_sun4m_iommu_mem_writel(saddr, val);
> @@ -249,11 +249,11 @@ static void iommu_mem_write(void *opaque, target_phys_addr_t addr,
>      },
>  };
>  
> -static uint32_t iommu_page_get_flags(IOMMUState *s, target_phys_addr_t addr)
> +static uint32_t iommu_page_get_flags(IOMMUState *s, hwaddr addr)
>  {
>      uint32_t ret;
> -    target_phys_addr_t iopte;
> -    target_phys_addr_t pa = addr;
> +    hwaddr iopte;
> +    hwaddr pa = addr;
>  
>      iopte = s->regs[IOMMU_BASE] << 4;
>      addr &= ~s->iostart;
> @@ -264,17 +264,17 @@ static uint32_t iommu_page_get_flags(IOMMUState *s, target_phys_addr_t addr)
>      return ret;
>  }
>  
> -static target_phys_addr_t iommu_translate_pa(target_phys_addr_t addr,
> +static hwaddr iommu_translate_pa(hwaddr addr,
>                                               uint32_t pte)
>  {
> -    target_phys_addr_t pa;
> +    hwaddr pa;
>  
>      pa = ((pte & IOPTE_PAGE) << 4) + (addr & ~IOMMU_PAGE_MASK);
>      trace_sun4m_iommu_translate_pa(addr, pa, pte);
>      return pa;
>  }
>  
> -static void iommu_bad_addr(IOMMUState *s, target_phys_addr_t addr,
> +static void iommu_bad_addr(IOMMUState *s, hwaddr addr,
>                             int is_write)
>  {
>      trace_sun4m_iommu_bad_addr(addr);
> @@ -286,12 +286,12 @@ static void iommu_bad_addr(IOMMUState *s, target_phys_addr_t addr,
>      qemu_irq_raise(s->irq);
>  }
>  
> -void sparc_iommu_memory_rw(void *opaque, target_phys_addr_t addr,
> +void sparc_iommu_memory_rw(void *opaque, hwaddr addr,
>                             uint8_t *buf, int len, int is_write)
>  {
>      int l;
>      uint32_t flags;
> -    target_phys_addr_t page, phys_addr;
> +    hwaddr page, phys_addr;
>  
>      while (len > 0) {
>          page = addr & IOMMU_PAGE_MASK;
> diff --git a/hw/sun4u.c b/hw/sun4u.c
> index eeb6496..1621171 100644
> --- a/hw/sun4u.c
> +++ b/hw/sun4u.c
> @@ -632,12 +632,12 @@ static void ebus_class_init(ObjectClass *klass, void *data)
>  
>  static uint64_t translate_prom_address(void *opaque, uint64_t addr)
>  {
> -    target_phys_addr_t *base_addr = (target_phys_addr_t *)opaque;
> +    hwaddr *base_addr = (hwaddr *)opaque;
>      return addr + *base_addr - PROM_VADDR;
>  }
>  
>  /* Boot PROM (OpenBIOS) */
> -static void prom_init(target_phys_addr_t addr, const char *bios_name)
> +static void prom_init(hwaddr addr, const char *bios_name)
>  {
>      DeviceState *dev;
>      SysBusDevice *s;
> @@ -721,7 +721,7 @@ static int ram_init1(SysBusDevice *dev)
>      return 0;
>  }
>  
> -static void ram_init(target_phys_addr_t addr, ram_addr_t RAM_size)
> +static void ram_init(hwaddr addr, ram_addr_t RAM_size)
>  {
>      DeviceState *dev;
>      SysBusDevice *s;
> diff --git a/hw/sysbus.c b/hw/sysbus.c
> index c173840..4969f06 100644
> --- a/hw/sysbus.c
> +++ b/hw/sysbus.c
> @@ -48,7 +48,7 @@ void sysbus_connect_irq(SysBusDevice *dev, int n, qemu_irq irq)
>      }
>  }
>  
> -void sysbus_mmio_map(SysBusDevice *dev, int n, target_phys_addr_t addr)
> +void sysbus_mmio_map(SysBusDevice *dev, int n, hwaddr addr)
>  {
>      assert(n >= 0 && n < dev->num_mmio);
>  
> @@ -56,7 +56,7 @@ void sysbus_mmio_map(SysBusDevice *dev, int n, target_phys_addr_t addr)
>          /* ??? region already mapped here.  */
>          return;
>      }
> -    if (dev->mmio[n].addr != (target_phys_addr_t)-1) {
> +    if (dev->mmio[n].addr != (hwaddr)-1) {
>          /* Unregister previous mapping.  */
>          memory_region_del_subregion(get_system_memory(), dev->mmio[n].memory);
>      }
> @@ -122,7 +122,7 @@ static int sysbus_device_init(DeviceState *dev)
>  }
>  
>  DeviceState *sysbus_create_varargs(const char *name,
> -                                   target_phys_addr_t addr, ...)
> +                                   hwaddr addr, ...)
>  {
>      DeviceState *dev;
>      SysBusDevice *s;
> @@ -133,7 +133,7 @@ DeviceState *sysbus_create_varargs(const char *name,
>      dev = qdev_create(NULL, name);
>      s = sysbus_from_qdev(dev);
>      qdev_init_nofail(dev);
> -    if (addr != (target_phys_addr_t)-1) {
> +    if (addr != (hwaddr)-1) {
>          sysbus_mmio_map(s, 0, addr);
>      }
>      va_start(va, addr);
> @@ -151,7 +151,7 @@ DeviceState *sysbus_create_varargs(const char *name,
>  }
>  
>  DeviceState *sysbus_try_create_varargs(const char *name,
> -                                       target_phys_addr_t addr, ...)
> +                                       hwaddr addr, ...)
>  {
>      DeviceState *dev;
>      SysBusDevice *s;
> @@ -165,7 +165,7 @@ DeviceState *sysbus_try_create_varargs(const char *name,
>      }
>      s = sysbus_from_qdev(dev);
>      qdev_init_nofail(dev);
> -    if (addr != (target_phys_addr_t)-1) {
> +    if (addr != (hwaddr)-1) {
>          sysbus_mmio_map(s, 0, addr);
>      }
>      va_start(va, addr);
> @@ -185,7 +185,7 @@ DeviceState *sysbus_try_create_varargs(const char *name,
>  static void sysbus_dev_print(Monitor *mon, DeviceState *dev, int indent)
>  {
>      SysBusDevice *s = sysbus_from_qdev(dev);
> -    target_phys_addr_t size;
> +    hwaddr size;
>      int i;
>  
>      monitor_printf(mon, "%*sirq %d\n", indent, "", s->num_irq);
> @@ -214,13 +214,13 @@ static char *sysbus_get_fw_dev_path(DeviceState *dev)
>      return g_strdup(path);
>  }
>  
> -void sysbus_add_memory(SysBusDevice *dev, target_phys_addr_t addr,
> +void sysbus_add_memory(SysBusDevice *dev, hwaddr addr,
>                         MemoryRegion *mem)
>  {
>      memory_region_add_subregion(get_system_memory(), addr, mem);
>  }
>  
> -void sysbus_add_memory_overlap(SysBusDevice *dev, target_phys_addr_t addr,
> +void sysbus_add_memory_overlap(SysBusDevice *dev, hwaddr addr,
>                                 MemoryRegion *mem, unsigned priority)
>  {
>      memory_region_add_subregion_overlap(get_system_memory(), addr, mem,
> @@ -232,7 +232,7 @@ void sysbus_del_memory(SysBusDevice *dev, MemoryRegion *mem)
>      memory_region_del_subregion(get_system_memory(), mem);
>  }
>  
> -void sysbus_add_io(SysBusDevice *dev, target_phys_addr_t addr,
> +void sysbus_add_io(SysBusDevice *dev, hwaddr addr,
>                         MemoryRegion *mem)
>  {
>      memory_region_add_subregion(get_system_io(), addr, mem);
> diff --git a/hw/sysbus.h b/hw/sysbus.h
> index acfbcfb..e58baaa 100644
> --- a/hw/sysbus.h
> +++ b/hw/sysbus.h
> @@ -36,7 +36,7 @@ struct SysBusDevice {
>      qemu_irq *irqp[QDEV_MAX_IRQ];
>      int num_mmio;
>      struct {
> -        target_phys_addr_t addr;
> +        hwaddr addr;
>          MemoryRegion *memory;
>      } mmio[QDEV_MAX_MMIO];
>      int num_pio;
> @@ -56,31 +56,31 @@ void sysbus_init_ioports(SysBusDevice *dev, pio_addr_t ioport, pio_addr_t size);
>  
>  
>  void sysbus_connect_irq(SysBusDevice *dev, int n, qemu_irq irq);
> -void sysbus_mmio_map(SysBusDevice *dev, int n, target_phys_addr_t addr);
> -void sysbus_add_memory(SysBusDevice *dev, target_phys_addr_t addr,
> +void sysbus_mmio_map(SysBusDevice *dev, int n, hwaddr addr);
> +void sysbus_add_memory(SysBusDevice *dev, hwaddr addr,
>                         MemoryRegion *mem);
> -void sysbus_add_memory_overlap(SysBusDevice *dev, target_phys_addr_t addr,
> +void sysbus_add_memory_overlap(SysBusDevice *dev, hwaddr addr,
>                                 MemoryRegion *mem, unsigned priority);
>  void sysbus_del_memory(SysBusDevice *dev, MemoryRegion *mem);
> -void sysbus_add_io(SysBusDevice *dev, target_phys_addr_t addr,
> +void sysbus_add_io(SysBusDevice *dev, hwaddr addr,
>                     MemoryRegion *mem);
>  void sysbus_del_io(SysBusDevice *dev, MemoryRegion *mem);
>  MemoryRegion *sysbus_address_space(SysBusDevice *dev);
>  
>  /* Legacy helper function for creating devices.  */
>  DeviceState *sysbus_create_varargs(const char *name,
> -                                 target_phys_addr_t addr, ...);
> +                                 hwaddr addr, ...);
>  DeviceState *sysbus_try_create_varargs(const char *name,
> -                                       target_phys_addr_t addr, ...);
> +                                       hwaddr addr, ...);
>  static inline DeviceState *sysbus_create_simple(const char *name,
> -                                              target_phys_addr_t addr,
> +                                              hwaddr addr,
>                                                qemu_irq irq)
>  {
>      return sysbus_create_varargs(name, addr, irq, NULL);
>  }
>  
>  static inline DeviceState *sysbus_try_create_simple(const char *name,
> -                                                    target_phys_addr_t addr,
> +                                                    hwaddr addr,
>                                                      qemu_irq irq)
>  {
>      return sysbus_try_create_varargs(name, addr, irq, NULL);
> diff --git a/hw/tc6393xb.c b/hw/tc6393xb.c
> index 420925c..31d4f26 100644
> --- a/hw/tc6393xb.c
> +++ b/hw/tc6393xb.c
> @@ -215,7 +215,7 @@ static void tc6393xb_sub_irq(void *opaque, int line, int level) {
>      case SCR_ ##N(1): return s->scr.N[1];       \
>      case SCR_ ##N(2): return s->scr.N[2]
>  
> -static uint32_t tc6393xb_scr_readb(TC6393xbState *s, target_phys_addr_t addr)
> +static uint32_t tc6393xb_scr_readb(TC6393xbState *s, hwaddr addr)
>  {
>      switch (addr) {
>          case SCR_REVID:
> @@ -276,7 +276,7 @@ static uint32_t tc6393xb_scr_readb(TC6393xbState *s, target_phys_addr_t addr)
>      case SCR_ ##N(1): s->scr.N[1] = value; return;   \
>      case SCR_ ##N(2): s->scr.N[2] = value; return
>  
> -static void tc6393xb_scr_writeb(TC6393xbState *s, target_phys_addr_t addr, uint32_t value)
> +static void tc6393xb_scr_writeb(TC6393xbState *s, hwaddr addr, uint32_t value)
>  {
>      switch (addr) {
>          SCR_REG_B(ISR);
> @@ -327,7 +327,7 @@ static void tc6393xb_nand_irq(TC6393xbState *s) {
>              (s->nand.imr & 0x80) && (s->nand.imr & s->nand.isr));
>  }
>  
> -static uint32_t tc6393xb_nand_cfg_readb(TC6393xbState *s, target_phys_addr_t addr) {
> +static uint32_t tc6393xb_nand_cfg_readb(TC6393xbState *s, hwaddr addr) {
>      switch (addr) {
>          case NAND_CFG_COMMAND:
>              return s->nand_enable ? 2 : 0;
> @@ -340,7 +340,7 @@ static uint32_t tc6393xb_nand_cfg_readb(TC6393xbState *s, target_phys_addr_t add
>      fprintf(stderr, "tc6393xb_nand_cfg: unhandled read at %08x\n", (uint32_t) addr);
>      return 0;
>  }
> -static void tc6393xb_nand_cfg_writeb(TC6393xbState *s, target_phys_addr_t addr, uint32_t value) {
> +static void tc6393xb_nand_cfg_writeb(TC6393xbState *s, hwaddr addr, uint32_t value) {
>      switch (addr) {
>          case NAND_CFG_COMMAND:
>              s->nand_enable = (value & 0x2);
> @@ -357,7 +357,7 @@ static void tc6393xb_nand_cfg_writeb(TC6393xbState *s, target_phys_addr_t addr,
>  					(uint32_t) addr, value & 0xff);
>  }
>  
> -static uint32_t tc6393xb_nand_readb(TC6393xbState *s, target_phys_addr_t addr) {
> +static uint32_t tc6393xb_nand_readb(TC6393xbState *s, hwaddr addr) {
>      switch (addr) {
>          case NAND_DATA + 0:
>          case NAND_DATA + 1:
> @@ -376,7 +376,7 @@ static uint32_t tc6393xb_nand_readb(TC6393xbState *s, target_phys_addr_t addr) {
>      fprintf(stderr, "tc6393xb_nand: unhandled read at %08x\n", (uint32_t) addr);
>      return 0;
>  }
> -static void tc6393xb_nand_writeb(TC6393xbState *s, target_phys_addr_t addr, uint32_t value) {
> +static void tc6393xb_nand_writeb(TC6393xbState *s, hwaddr addr, uint32_t value) {
>  //    fprintf(stderr, "tc6393xb_nand: write at %08x: %02x\n",
>  //					(uint32_t) addr, value & 0xff);
>      switch (addr) {
> @@ -499,7 +499,7 @@ static void tc6393xb_update_display(void *opaque)
>  }
>  
>  
> -static uint64_t tc6393xb_readb(void *opaque, target_phys_addr_t addr,
> +static uint64_t tc6393xb_readb(void *opaque, hwaddr addr,
>                                 unsigned size)
>  {
>      TC6393xbState *s = opaque;
> @@ -522,7 +522,7 @@ static uint64_t tc6393xb_readb(void *opaque, target_phys_addr_t addr,
>      return 0;
>  }
>  
> -static void tc6393xb_writeb(void *opaque, target_phys_addr_t addr,
> +static void tc6393xb_writeb(void *opaque, hwaddr addr,
>                              uint64_t value, unsigned size) {
>      TC6393xbState *s = opaque;
>  
> diff --git a/hw/tcx.c b/hw/tcx.c
> index 2db2db1..7abe865 100644
> --- a/hw/tcx.c
> +++ b/hw/tcx.c
> @@ -36,7 +36,7 @@
>  
>  typedef struct TCXState {
>      SysBusDevice busdev;
> -    target_phys_addr_t addr;
> +    hwaddr addr;
>      DisplayState *ds;
>      uint8_t *vram;
>      uint32_t *vram24, *cplane;
> @@ -432,13 +432,13 @@ static void tcx_reset(DeviceState *d)
>      s->dac_state = 0;
>  }
>  
> -static uint64_t tcx_dac_readl(void *opaque, target_phys_addr_t addr,
> +static uint64_t tcx_dac_readl(void *opaque, hwaddr addr,
>                                unsigned size)
>  {
>      return 0;
>  }
>  
> -static void tcx_dac_writel(void *opaque, target_phys_addr_t addr, uint64_t val,
> +static void tcx_dac_writel(void *opaque, hwaddr addr, uint64_t val,
>                             unsigned size)
>  {
>      TCXState *s = opaque;
> @@ -484,13 +484,13 @@ static void tcx_dac_writel(void *opaque, target_phys_addr_t addr, uint64_t val,
>      },
>  };
>  
> -static uint64_t dummy_readl(void *opaque, target_phys_addr_t addr,
> +static uint64_t dummy_readl(void *opaque, hwaddr addr,
>                              unsigned size)
>  {
>      return 0;
>  }
>  
> -static void dummy_writel(void *opaque, target_phys_addr_t addr,
> +static void dummy_writel(void *opaque, hwaddr addr,
>                           uint64_t val, unsigned size)
>  {
>  }
> diff --git a/hw/tusb6010.c b/hw/tusb6010.c
> index 5ba8da6..325200b 100644
> --- a/hw/tusb6010.c
> +++ b/hw/tusb6010.c
> @@ -281,7 +281,7 @@ static void tusb_gpio_intr_update(TUSBState *s)
>  extern CPUReadMemoryFunc * const musb_read[];
>  extern CPUWriteMemoryFunc * const musb_write[];
>  
> -static uint32_t tusb_async_readb(void *opaque, target_phys_addr_t addr)
> +static uint32_t tusb_async_readb(void *opaque, hwaddr addr)
>  {
>      TUSBState *s = (TUSBState *) opaque;
>  
> @@ -298,7 +298,7 @@ static uint32_t tusb_async_readb(void *opaque, target_phys_addr_t addr)
>      return 0;
>  }
>  
> -static uint32_t tusb_async_readh(void *opaque, target_phys_addr_t addr)
> +static uint32_t tusb_async_readh(void *opaque, hwaddr addr)
>  {
>      TUSBState *s = (TUSBState *) opaque;
>  
> @@ -315,7 +315,7 @@ static uint32_t tusb_async_readh(void *opaque, target_phys_addr_t addr)
>      return 0;
>  }
>  
> -static uint32_t tusb_async_readw(void *opaque, target_phys_addr_t addr)
> +static uint32_t tusb_async_readw(void *opaque, hwaddr addr)
>  {
>      TUSBState *s = (TUSBState *) opaque;
>      int offset = addr & 0xfff;
> @@ -438,7 +438,7 @@ static uint32_t tusb_async_readw(void *opaque, target_phys_addr_t addr)
>      return 0;
>  }
>  
> -static void tusb_async_writeb(void *opaque, target_phys_addr_t addr,
> +static void tusb_async_writeb(void *opaque, hwaddr addr,
>                  uint32_t value)
>  {
>      TUSBState *s = (TUSBState *) opaque;
> @@ -459,7 +459,7 @@ static void tusb_async_writeb(void *opaque, target_phys_addr_t addr,
>      }
>  }
>  
> -static void tusb_async_writeh(void *opaque, target_phys_addr_t addr,
> +static void tusb_async_writeh(void *opaque, hwaddr addr,
>                  uint32_t value)
>  {
>      TUSBState *s = (TUSBState *) opaque;
> @@ -480,7 +480,7 @@ static void tusb_async_writeh(void *opaque, target_phys_addr_t addr,
>      }
>  }
>  
> -static void tusb_async_writew(void *opaque, target_phys_addr_t addr,
> +static void tusb_async_writew(void *opaque, hwaddr addr,
>                  uint32_t value)
>  {
>      TUSBState *s = (TUSBState *) opaque;
> diff --git a/hw/unin_pci.c b/hw/unin_pci.c
> index d1cc680..9981d94 100644
> --- a/hw/unin_pci.c
> +++ b/hw/unin_pci.c
> @@ -111,7 +111,7 @@ static uint32_t unin_get_config_reg(uint32_t reg, uint32_t addr)
>      return retval;
>  }
>  
> -static void unin_data_write(void *opaque, target_phys_addr_t addr,
> +static void unin_data_write(void *opaque, hwaddr addr,
>                              uint64_t val, unsigned len)
>  {
>      UNINState *s = opaque;
> @@ -123,7 +123,7 @@ static void unin_data_write(void *opaque, target_phys_addr_t addr,
>                     val, len);
>  }
>  
> -static uint64_t unin_data_read(void *opaque, target_phys_addr_t addr,
> +static uint64_t unin_data_read(void *opaque, hwaddr addr,
>                                 unsigned len)
>  {
>      UNINState *s = opaque;
> diff --git a/hw/usb/hcd-ehci.c b/hw/usb/hcd-ehci.c
> index 8bdb806..6c65a73 100644
> --- a/hw/usb/hcd-ehci.c
> +++ b/hw/usb/hcd-ehci.c
> @@ -503,7 +503,7 @@ static const char *state2str(uint32_t state)
>      return nr2str(ehci_state_names, ARRAY_SIZE(ehci_state_names), state);
>  }
>  
> -static const char *addr2str(target_phys_addr_t addr)
> +static const char *addr2str(hwaddr addr)
>  {
>      return nr2str(ehci_mmio_names, ARRAY_SIZE(ehci_mmio_names),
>                    addr + OPREGBASE);
> @@ -663,7 +663,7 @@ static int ehci_get_fetch_addr(EHCIState *s, int async)
>      return async ? s->a_fetch_addr : s->p_fetch_addr;
>  }
>  
> -static void ehci_trace_qh(EHCIQueue *q, target_phys_addr_t addr, EHCIqh *qh)
> +static void ehci_trace_qh(EHCIQueue *q, hwaddr addr, EHCIqh *qh)
>  {
>      /* need three here due to argument count limits */
>      trace_usb_ehci_qh_ptrs(q, addr, qh->next,
> @@ -681,7 +681,7 @@ static void ehci_trace_qh(EHCIQueue *q, target_phys_addr_t addr, EHCIqh *qh)
>                             (bool)(qh->epchar & QH_EPCHAR_I));
>  }
>  
> -static void ehci_trace_qtd(EHCIQueue *q, target_phys_addr_t addr, EHCIqtd *qtd)
> +static void ehci_trace_qtd(EHCIQueue *q, hwaddr addr, EHCIqtd *qtd)
>  {
>      /* need three here due to argument count limits */
>      trace_usb_ehci_qtd_ptrs(q, addr, qtd->next, qtd->altnext);
> @@ -698,7 +698,7 @@ static void ehci_trace_qtd(EHCIQueue *q, target_phys_addr_t addr, EHCIqtd *qtd)
>                              (bool)(qtd->token & QTD_TOKEN_XACTERR));
>  }
>  
> -static void ehci_trace_itd(EHCIState *s, target_phys_addr_t addr, EHCIitd *itd)
> +static void ehci_trace_itd(EHCIState *s, hwaddr addr, EHCIitd *itd)
>  {
>      trace_usb_ehci_itd(addr, itd->next,
>                         get_field(itd->bufptr[1], ITD_BUFPTR_MAXPKT),
> @@ -707,7 +707,7 @@ static void ehci_trace_itd(EHCIState *s, target_phys_addr_t addr, EHCIitd *itd)
>                         get_field(itd->bufptr[0], ITD_BUFPTR_DEVADDR));
>  }
>  
> -static void ehci_trace_sitd(EHCIState *s, target_phys_addr_t addr,
> +static void ehci_trace_sitd(EHCIState *s, hwaddr addr,
>                              EHCIsitd *sitd)
>  {
>      trace_usb_ehci_sitd(addr, sitd->next,
> @@ -1100,14 +1100,14 @@ static void ehci_reset(void *opaque)
>      qemu_bh_cancel(s->async_bh);
>  }
>  
> -static uint64_t ehci_caps_read(void *ptr, target_phys_addr_t addr,
> +static uint64_t ehci_caps_read(void *ptr, hwaddr addr,
>                                 unsigned size)
>  {
>      EHCIState *s = ptr;
>      return s->caps[addr];
>  }
>  
> -static uint64_t ehci_opreg_read(void *ptr, target_phys_addr_t addr,
> +static uint64_t ehci_opreg_read(void *ptr, hwaddr addr,
>                                  unsigned size)
>  {
>      EHCIState *s = ptr;
> @@ -1118,7 +1118,7 @@ static uint64_t ehci_opreg_read(void *ptr, target_phys_addr_t addr,
>      return val;
>  }
>  
> -static uint64_t ehci_port_read(void *ptr, target_phys_addr_t addr,
> +static uint64_t ehci_port_read(void *ptr, hwaddr addr,
>                                 unsigned size)
>  {
>      EHCIState *s = ptr;
> @@ -1157,7 +1157,7 @@ static void handle_port_owner_write(EHCIState *s, int port, uint32_t owner)
>      }
>  }
>  
> -static void ehci_port_write(void *ptr, target_phys_addr_t addr,
> +static void ehci_port_write(void *ptr, hwaddr addr,
>                              uint64_t val, unsigned size)
>  {
>      EHCIState *s = ptr;
> @@ -1202,7 +1202,7 @@ static void ehci_port_write(void *ptr, target_phys_addr_t addr,
>      trace_usb_ehci_portsc_change(addr + PORTSC_BEGIN, addr >> 2, *portsc, old);
>  }
>  
> -static void ehci_opreg_write(void *ptr, target_phys_addr_t addr,
> +static void ehci_opreg_write(void *ptr, hwaddr addr,
>                               uint64_t val, unsigned size)
>  {
>      EHCIState *s = ptr;
> diff --git a/hw/usb/hcd-musb.c b/hw/usb/hcd-musb.c
> index 0bb5c7b..dc114fe 100644
> --- a/hw/usb/hcd-musb.c
> +++ b/hw/usb/hcd-musb.c
> @@ -1236,7 +1236,7 @@ static void musb_ep_writeh(void *opaque, int ep, int addr, uint16_t value)
>  }
>  
>  /* Generic control */
> -static uint32_t musb_readb(void *opaque, target_phys_addr_t addr)
> +static uint32_t musb_readb(void *opaque, hwaddr addr)
>  {
>      MUSBState *s = (MUSBState *) opaque;
>      int ep, i;
> @@ -1298,7 +1298,7 @@ static uint32_t musb_readb(void *opaque, target_phys_addr_t addr)
>      };
>  }
>  
> -static void musb_writeb(void *opaque, target_phys_addr_t addr, uint32_t value)
> +static void musb_writeb(void *opaque, hwaddr addr, uint32_t value)
>  {
>      MUSBState *s = (MUSBState *) opaque;
>      int ep;
> @@ -1385,7 +1385,7 @@ static void musb_writeb(void *opaque, target_phys_addr_t addr, uint32_t value)
>      };
>  }
>  
> -static uint32_t musb_readh(void *opaque, target_phys_addr_t addr)
> +static uint32_t musb_readh(void *opaque, hwaddr addr)
>  {
>      MUSBState *s = (MUSBState *) opaque;
>      int ep, i;
> @@ -1439,7 +1439,7 @@ static uint32_t musb_readh(void *opaque, target_phys_addr_t addr)
>      };
>  }
>  
> -static void musb_writeh(void *opaque, target_phys_addr_t addr, uint32_t value)
> +static void musb_writeh(void *opaque, hwaddr addr, uint32_t value)
>  {
>      MUSBState *s = (MUSBState *) opaque;
>      int ep;
> @@ -1495,7 +1495,7 @@ static void musb_writeh(void *opaque, target_phys_addr_t addr, uint32_t value)
>      };
>  }
>  
> -static uint32_t musb_readw(void *opaque, target_phys_addr_t addr)
> +static uint32_t musb_readw(void *opaque, hwaddr addr)
>  {
>      MUSBState *s = (MUSBState *) opaque;
>      int ep;
> @@ -1513,7 +1513,7 @@ static uint32_t musb_readw(void *opaque, target_phys_addr_t addr)
>      };
>  }
>  
> -static void musb_writew(void *opaque, target_phys_addr_t addr, uint32_t value)
> +static void musb_writew(void *opaque, hwaddr addr, uint32_t value)
>  {
>      MUSBState *s = (MUSBState *) opaque;
>      int ep;
> diff --git a/hw/usb/hcd-ohci.c b/hw/usb/hcd-ohci.c
> index 59c7055..0cc1e5d 100644
> --- a/hw/usb/hcd-ohci.c
> +++ b/hw/usb/hcd-ohci.c
> @@ -1473,7 +1473,7 @@ static void ohci_port_set_status(OHCIState *ohci, int portnum, uint32_t val)
>  }
>  
>  static uint64_t ohci_mem_read(void *opaque,
> -                              target_phys_addr_t addr,
> +                              hwaddr addr,
>                                unsigned size)
>  {
>      OHCIState *ohci = opaque;
> @@ -1596,7 +1596,7 @@ static uint64_t ohci_mem_read(void *opaque,
>  }
>  
>  static void ohci_mem_write(void *opaque,
> -                           target_phys_addr_t addr,
> +                           hwaddr addr,
>                             uint64_t val,
>                             unsigned size)
>  {
> diff --git a/hw/usb/hcd-xhci.c b/hw/usb/hcd-xhci.c
> index 3a41b06..37b3dbb 100644
> --- a/hw/usb/hcd-xhci.c
> +++ b/hw/usb/hcd-xhci.c
> @@ -2364,7 +2364,7 @@ static void xhci_reset(DeviceState *dev)
>      xhci_mfwrap_update(xhci);
>  }
>  
> -static uint64_t xhci_cap_read(void *ptr, target_phys_addr_t reg, unsigned size)
> +static uint64_t xhci_cap_read(void *ptr, hwaddr reg, unsigned size)
>  {
>      XHCIState *xhci = ptr;
>      uint32_t ret;
> @@ -2431,7 +2431,7 @@ static uint64_t xhci_cap_read(void *ptr, target_phys_addr_t reg, unsigned size)
>      return ret;
>  }
>  
> -static uint64_t xhci_port_read(void *ptr, target_phys_addr_t reg, unsigned size)
> +static uint64_t xhci_port_read(void *ptr, hwaddr reg, unsigned size)
>  {
>      XHCIPort *port = ptr;
>      uint32_t ret;
> @@ -2455,7 +2455,7 @@ static uint64_t xhci_port_read(void *ptr, target_phys_addr_t reg, unsigned size)
>      return ret;
>  }
>  
> -static void xhci_port_write(void *ptr, target_phys_addr_t reg,
> +static void xhci_port_write(void *ptr, hwaddr reg,
>                              uint64_t val, unsigned size)
>  {
>      XHCIPort *port = ptr;
> @@ -2493,7 +2493,7 @@ static void xhci_port_write(void *ptr, target_phys_addr_t reg,
>      }
>  }
>  
> -static uint64_t xhci_oper_read(void *ptr, target_phys_addr_t reg, unsigned size)
> +static uint64_t xhci_oper_read(void *ptr, hwaddr reg, unsigned size)
>  {
>      XHCIState *xhci = ptr;
>      uint32_t ret;
&g