From patchwork Tue Oct 23 09:42:14 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marcus Shawcroft X-Patchwork-Id: 193406 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) by ozlabs.org (Postfix) with SMTP id 995622C007C for ; Tue, 23 Oct 2012 20:43:05 +1100 (EST) Comment: DKIM? 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Proposed ChangeLog: * doc/invoke.texi (AArch64 Options): New. * doc/md.texi (Machine Constraints): Add AArch64. diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index a9a79343985bdc6bcd070453446a40e996199612..cb5de9e1993eabef512cbbcbe79de6588c6b666a 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -467,6 +467,15 @@ Objective-C and Objective-C++ Dialects}. @c Try and put the significant identifier (CPU or system) first, @c so users have a clue at guessing where the ones they want will be. +@emph{AArch64 Options} +@gccoptlist{-mbig-endian -mlittle-endian @gol +-mgeneral-regs-only @gol +-mcmodel=tiny -mcmodel=small -mcmodel=large @gol +-mstrict-align @gol +-momit-leaf-frame-pointer -mno-omit-leaf-frame-pointer @gol +-mtls-dialect=desc -mtls-dialect=traditional @gol +-march=@var{name} -mcpu=@var{name} -mtune=@var{name}} + @emph{Adapteva Epiphany Options} @gccoptlist{-mhalf-reg-file -mprefer-short-insn-regs @gol -mbranch-cost=@var{num} -mcmove -mnops=@var{num} -msoft-cmpsf @gol @@ -10611,6 +10620,7 @@ platform. @c in Machine Dependent Options @menu +* AArch64 Options:: * Adapteva Epiphany Options:: * ARM Options:: * AVR Options:: @@ -10820,6 +10830,125 @@ purpose. The default is @option{-m1reg- @end table +@node AArch64 Options +@subsection AArch64 Options +@cindex AArch64 Options + +These options are defined for AArch64 implementations: + +@table @gcctabopt + +@item -mbig-endian +@opindex mbig-endian +Generate big-endian code. This is the default when GCC is configured for an +@samp{aarch64_be-*-*} target. + +@item -mgeneral-regs-only +@opindex mgeneral-regs-only +Generate code which uses only the general registers. + +@item -mlittle-endian +@opindex mlittle-endian +Generate little-endian code. This is the default when GCC is configured for an +@samp{aarch64-*-*} but not an @samp{aarch64_be-*-*} target. + +@item -mcmodel=tiny +@opindex mcmodel=tiny +Generate code for the tiny code model. The program and its statically defined +symbols must be within 1GB of each other. Pointers are 64 bits. Programs can +be statically or dynamically linked. This model is not fully implemented and +mostly treated as "small". + +@item -mcmodel=small +@opindex mcmodel=small +Generate code for the small code model. The program and its statically defined +symbols must be within 4GB of each other. Pointers are 64 bits. Programs can +be statically or dynamically linked. This is the default code model. + +@item -mcmodel=large +@opindex mcmodel=large +Generate code for the large code model. This makes no assumptions about +addresses and sizes of sections. Pointers are 64 bits. Programs can be +statically linked only. + +@item -mstrict-align +@opindex mstrict-align +Do not assume that unaligned memory references will be handled by the system. + +@item -momit-leaf-frame-pointer +@item -mno-omit-leaf-frame-pointer +@opindex momit-leaf-frame-pointer +@opindex mno-omit-leaf-frame-pointer +Omit or keep the frame pointer in leaf functions. The former behaviour is the +default. + +@item -mtls-dialect=desc +@opindex mtls-dialect=desc +Use TLS descriptors as the thread-local storage mechanism for dynamic accesses +of TLS variables. This is the default. + +@item -mtls-dialect=traditional +@opindex mtls-dialect=traditional +Use traditional TLS as the thread-local storage mechanism for dynamic accesses +of TLS variables. + +@item -march=@var{name} +@opindex march +Specify the name of the target architecture, optionally suffixed by one or +more feature modifiers. This option has the form +@option{-march=@var{arch}@r{@{}+@r{[}no@r{]}@var{feature}@r{@}*}}, where the +only value for @var{arch} is @samp{armv8-a}. The possible values for +@var{feature} are documented in the sub-section below. + +Where conflicting feature modifiers are specified, the right-most feature is +used. + +GCC uses this name to determine what kind of instructions it can emit when +generating assembly code. This option can be used in conjunction with or +instead of the @option{-mcpu=} option. + +@item -mcpu=@var{name} +@opindex mcpu +Specify the name of the target processor, optionally suffixed by one or more +feature modifiers. This option has the form +@option{-mcpu=@var{cpu}@r{@{}+@r{[}no@r{]}@var{feature}@r{@}*}}, where the +possible values for @var{cpu} are @samp{generic}, @samp{large}. The +possible values for @var{feature} are documented in the sub-section +below. + +Where conflicting feature modifiers are specified, the right-most feature is +used. + +GCC uses this name to determine what kind of instructions it can emit when +generating assembly code. + +@item -mtune=@var{name} +@opindex mtune +Specify the name of the processor to tune the performance for. The code will +be tuned as if the target processor were of the type specified in this option, +but still using instructions compatible with the target processor specified +by a @option{-mcpu=} option. This option cannot be suffixed by feature +modifiers. + +@end table + +@subsubsection @option{-march} and @option{-mcpu} feature modifiers +@cindex @option{-march} feature modifiers +@cindex @option{-mcpu} feature modifiers +Feature modifiers used with @option{-march} and @option{-mcpu} can be one +the following: + +@table @samp +@item crypto +Enable Crypto extension. This implies Advanced SIMD is enabled. +@item fp +Enable floating-point instructions. +@item simd +Enable Advanced SIMD instructions. This implies floating-point instructions +are enabled. This is the default for all current possible values for options +@option{-march} and @option{-mcpu=}. +@end table + @node ARM Options @subsection ARM Options @cindex ARM options diff --git a/gcc/doc/md.texi b/gcc/doc/md.texi index f17d55e292c81836a364e303a115aa376e24b756..02ee623a1b7cfa7dedc83eb9da677373d47cdb3e 100644 --- a/gcc/doc/md.texi +++ b/gcc/doc/md.texi @@ -1653,6 +1653,66 @@ table heading for each architecture is t the meanings of that architecture's constraints. @table @emph +@item AArch64 family---@file{config/aarch64/constraints.md} +@table @code +@item k +The stack pointer register (@code{SP}) + +@item w +Floating point or SIMD vector register + +@item I +Integer constant that is valid as an immediate operand in an @code{ADD} +instruction + +@item J +Integer constant that is valid as an immediate operand in a @code{SUB} +instruction (once negated) + +@item K +Integer constant that can be used with a 32-bit logical instruction + +@item L +Integer constant that can be used with a 64-bit logical instruction + +@item M +Integer constant that is valid as an immediate operand in a 32-bit @code{MOV} +pseudo instruction. The @code{MOV} may be assembled to one of several different +machine instructions depending on the value + +@item N +Integer constant that is valid as an immediate operand in a 64-bit @code{MOV} +pseudo instruction + +@item S +An absolute symbolic address or a label reference + +@item Y +Floating point constant zero + +@item Z +Integer constant zero + +@item Usa +An absolute symbolic address + +@item Ush +The high part (bits 12 and upwards) of the pc-relative address of a symbol +within 4GB of the instruction + +@item Q +A memory address which uses a single base register with no offset + +@item Ump +A memory address suitable for a load/store pair instruction in SI, DI, SF and +DF modes + +@item Utf +A memory address suitable for a load/store pair instruction in TF mode + +@end table + + @item ARM family---@file{config/arm/constraints.md} @table @code @item w