From patchwork Fri Oct 19 23:57:36 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Albert ARIBAUD X-Patchwork-Id: 192880 X-Patchwork-Delegate: prafulla@marvell.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 7FE2C2C008F for ; Sat, 20 Oct 2012 10:58:04 +1100 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 752BD4A4EA; Sat, 20 Oct 2012 01:58:02 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id wvNYzO4JSkcL; Sat, 20 Oct 2012 01:58:02 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id E50C84A4DC; Sat, 20 Oct 2012 01:58:00 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id BF6C74A4DC for ; Sat, 20 Oct 2012 01:57:58 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 0O6ZRgkgYnrW for ; Sat, 20 Oct 2012 01:57:58 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from smtp1-g21.free.fr (smtp1-g21.free.fr [212.27.42.1]) by theia.denx.de (Postfix) with ESMTP id 7368B4A4D9 for ; Sat, 20 Oct 2012 01:57:55 +0200 (CEST) Received: from localhost.localdomain (unknown [IPv6:2a01:e35:2eb9:20:858d:9ff9:1cfd:f1aa]) (Authenticated sender: albert.aribaud) by smtp1-g21.free.fr (Postfix) with ESMTPSA id 8C8EF940063; Sat, 20 Oct 2012 01:57:43 +0200 (CEST) From: Albert ARIBAUD To: U-Boot Date: Sat, 20 Oct 2012 01:57:36 +0200 Message-Id: <1350691057-26414-1-git-send-email-albert.u.boot@aribaud.net> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1350682689-2986-1-git-send-email-albert.u.boot@aribaud.net> References: <1350682689-2986-1-git-send-email-albert.u.boot@aribaud.net> Subject: [U-Boot] [PATCH v3 1/2] mvgbe: allow non-sequential PHY addresses X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de Signed-off-by: Albert ARIBAUD --- Changes in v3: - fixed building when SoC provides only one GbE port. arch/arm/include/asm/arch-kirkwood/kirkwood.h | 1 - arch/arm/include/asm/arch-orion5x/orion5x.h | 1 - drivers/net/mvgbe.c | 12 +++++++++++- drivers/net/mvgbe.h | 7 ------- 4 files changed, 11 insertions(+), 10 deletions(-) diff --git a/arch/arm/include/asm/arch-kirkwood/kirkwood.h b/arch/arm/include/asm/arch-kirkwood/kirkwood.h index 47771d5..503fb1e 100644 --- a/arch/arm/include/asm/arch-kirkwood/kirkwood.h +++ b/arch/arm/include/asm/arch-kirkwood/kirkwood.h @@ -61,7 +61,6 @@ #define KW_SATA_PORT1_OFFSET 0x4000 /* Kirkwood GbE controller has two ports */ -#define MAX_MVGBE_DEVS 2 #define MVGBE0_BASE KW_EGIGA0_BASE #define MVGBE1_BASE KW_EGIGA1_BASE diff --git a/arch/arm/include/asm/arch-orion5x/orion5x.h b/arch/arm/include/asm/arch-orion5x/orion5x.h index b0d3368..b32d1d3 100644 --- a/arch/arm/include/asm/arch-orion5x/orion5x.h +++ b/arch/arm/include/asm/arch-orion5x/orion5x.h @@ -55,7 +55,6 @@ #define ORION5X_SATA_PORT1_OFFSET 0x4000 /* Orion5x GbE controller has a single port */ -#define MAX_MVGBE_DEVS 1 #define MVGBE0_BASE ORION5X_EGIGA_BASE /* Orion5x USB Host controller is port 1 */ diff --git a/drivers/net/mvgbe.c b/drivers/net/mvgbe.c index 47bf27c..2533614 100644 --- a/drivers/net/mvgbe.c +++ b/drivers/net/mvgbe.c @@ -49,6 +49,8 @@ DECLARE_GLOBAL_DATA_PTR; +#define MAX_MVGBE_DEVS 2 + #define MV_PHY_ADR_REQUEST 0xee #define MVGBE_SMI_REG (((struct mvgbe_registers *)MVGBE0_BASE)->smi) @@ -653,6 +655,14 @@ int mvgbe_initialize(bd_t *bis) struct eth_device *dev; int devnum; u8 used_ports[MAX_MVGBE_DEVS] = CONFIG_MVGBE_PORTS; +#if defined(CONFIG_MVGBE_PHY_ADRS) +#define MVGBE_PHY_ADRS CONFIG_MVGBE_PHY_ADRS +#elif defined(CONFIG_PHY_BASE_ADR) +#define MVGBE_PHY_ADRS {CONFIG_PHY_BASE_ADR, CONFIG_PHY_BASE_ADR+1} +#else +#define MVGBE_PHY_ADRS {8, 9} +#endif + u8 used_phy_adrs[MAX_MVGBE_DEVS] = MVGBE_PHY_ADRS; for (devnum = 0; devnum < MAX_MVGBE_DEVS; devnum++) { /*skip if port is configured not to use */ @@ -733,7 +743,7 @@ error1: miiphy_register(dev->name, smi_reg_read, smi_reg_write); /* Set phy address of the port */ miiphy_write(dev->name, MV_PHY_ADR_REQUEST, - MV_PHY_ADR_REQUEST, PHY_BASE_ADR + devnum); + MV_PHY_ADR_REQUEST, used_phy_adrs[devnum]); #endif } return 0; diff --git a/drivers/net/mvgbe.h b/drivers/net/mvgbe.h index d8a5429..5434839 100644 --- a/drivers/net/mvgbe.h +++ b/drivers/net/mvgbe.h @@ -28,13 +28,6 @@ #ifndef __MVGBE_H__ #define __MVGBE_H__ -/* PHY_BASE_ADR is board specific and can be configured */ -#if defined (CONFIG_PHY_BASE_ADR) -#define PHY_BASE_ADR CONFIG_PHY_BASE_ADR -#else -#define PHY_BASE_ADR 0x08 /* default phy base addr */ -#endif - /* Constants */ #define INT_CAUSE_UNMASK_ALL 0x0007ffff #define INT_CAUSE_UNMASK_ALL_EXT 0x0011ffff