From patchwork Thu Oct 18 16:22:02 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tom Rini X-Patchwork-Id: 192382 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 606462C007E for ; Fri, 19 Oct 2012 03:22:18 +1100 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id BC2944A375; Thu, 18 Oct 2012 18:22:15 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id cOCJr+u9k-tF; Thu, 18 Oct 2012 18:22:15 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 57E3C4A369; Thu, 18 Oct 2012 18:22:14 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id BAE5B4A369 for ; Thu, 18 Oct 2012 18:22:12 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 9w2sTKiC-Ppj for ; Thu, 18 Oct 2012 18:22:11 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail-da0-f44.google.com (mail-da0-f44.google.com [209.85.210.44]) by theia.denx.de (Postfix) with ESMTPS id 54DEF4A365 for ; Thu, 18 Oct 2012 18:22:09 +0200 (CEST) Received: by mail-da0-f44.google.com with SMTP id h15so3530625dan.3 for ; Thu, 18 Oct 2012 09:22:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=sender:from:to:cc:subject:date:message-id:x-mailer; bh=Np1rO42flOUnWKcFcnaW4BeSrPLLxgPSX3CDjzSxtL8=; b=0I1DhuWXfTn5txfFDXd6WuwWv9iG74tE1eJRTsOkKEcXQfLDDdmtjc2Vr5KEm8XgoM pWZpv5Dr13CX+sAXONqyKlL9bABADNtyYlN/FqsW/gM32ve9NRFJfMpJXFA0R+w/VyxK 2qdRQLmazQu1zntyDc4thOT8DdAQCByf3/YuqWRaLVpY8ccpRqSrb0Ud70tSHWWjIpe2 tTIy8+eSf72MrEITNkzhJWrQab475eKPcKQS88Zrchr7IVyMzjUckq0ghnN/qaGpeZbv z7yO3Vh5Vcp2B7nLUIZA0yKsKrf5lmp3fXoc7/7iCtFtxv0emir0ydXALO93629cqNUf FPog== Received: by 10.66.77.40 with SMTP id p8mr60632921paw.78.1350577327541; Thu, 18 Oct 2012 09:22:07 -0700 (PDT) Received: from localhost.localdomain (ip68-230-54-74.ph.ph.cox.net. [68.230.54.74]) by mx.google.com with ESMTPS id rw5sm14449228pbc.54.2012.10.18.09.22.05 (version=TLSv1/SSLv3 cipher=OTHER); Thu, 18 Oct 2012 09:22:06 -0700 (PDT) From: Tom Rini To: u-boot@lists.denx.de Date: Thu, 18 Oct 2012 09:22:02 -0700 Message-Id: <1350577322-30278-1-git-send-email-trini@ti.com> X-Mailer: git-send-email 1.7.9.5 Cc: Vaibhav Hiremath Subject: [U-Boot] [PATCH] am335x: Enable RTC 32K OSC clock X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de From: Vaibhav Hiremath In order to support low power state, you must source kernel system timers to persistent clock, available across suspend/resume. In case of AM335x device, the only source we have is, RTC32K, available in wakeup/always-on domain. Having said that, during validation it has been observed that, RTC clock need couple of seconds delay to stabilize the RTC OSC clock; and such a huge delay is not acceptable in kernel especially during early init and also it will impact quick/fast boot use-cases. So, RTC32k OSC enable dependency has been shifted to SPL/first-bootloader. Signed-off-by: Vaibhav Hiremath Signed-off-by: Tom Rini --- arch/arm/cpu/armv7/am33xx/board.c | 21 ++++++++++++++++++++- arch/arm/cpu/armv7/am33xx/clock.c | 6 ++++++ arch/arm/include/asm/arch-am33xx/cpu.h | 15 +++++++++++++++ arch/arm/include/asm/arch-am33xx/hardware.h | 4 ++++ 4 files changed, 45 insertions(+), 1 deletion(-) diff --git a/arch/arm/cpu/armv7/am33xx/board.c b/arch/arm/cpu/armv7/am33xx/board.c index 6de03fd..f6589c2 100644 --- a/arch/arm/cpu/armv7/am33xx/board.c +++ b/arch/arm/cpu/armv7/am33xx/board.c @@ -116,11 +116,27 @@ static int read_eeprom(void) return 0; } -/* UART Defines */ #ifdef CONFIG_SPL_BUILD +/* UART Defines */ #define UART_RESET (0x1 << 1) #define UART_CLK_RUNNING_MASK 0x1 #define UART_SMART_IDLE_EN (0x1 << 0x3) + +static void rtc32k_enable(void) +{ + struct rtc_regs *rtc = (struct rtc_regs *)AM335X_RTC_BASE; + + /* + * Unlock the RTC's registers. For more details please see the + * RTC_SS section of the TRM. In order to unlock we need to + * write these specific values (keys) in this order. + */ + writel(0x83e70b13, rtc->kick0r); + writel(0x95a4f1e0, rtc->kick1r); + + /* Enable the RTC 32K OSC by setting bits 3 and 6. */ + writel((1 << 3) | (1 << 6), rtc->osc); +} #endif /* @@ -154,6 +170,9 @@ void s_init(void) /* Setup the PLLs and the clocks for the peripherals */ pll_init(); + /* Enable RTC32K clock */ + rtc32k_enable(); + /* UART softreset */ u32 regVal; diff --git a/arch/arm/cpu/armv7/am33xx/clock.c b/arch/arm/cpu/armv7/am33xx/clock.c index 2b19506..f870859 100644 --- a/arch/arm/cpu/armv7/am33xx/clock.c +++ b/arch/arm/cpu/armv7/am33xx/clock.c @@ -44,6 +44,7 @@ const struct cm_perpll *cmper = (struct cm_perpll *)CM_PER; const struct cm_wkuppll *cmwkup = (struct cm_wkuppll *)CM_WKUP; const struct cm_dpll *cmdpll = (struct cm_dpll *)CM_DPLL; +const struct cm_rtc *cmrtc = (struct cm_rtc *)CM_RTC; static void enable_interface_clocks(void) { @@ -153,6 +154,11 @@ static void enable_per_clocks(void) writel(PRCM_MOD_EN, &cmper->spi0clkctrl); while (readl(&cmper->spi0clkctrl) != PRCM_MOD_EN) ; + + /* RTC */ + writel(PRCM_MOD_EN, &cmrtc->rtcclkctrl); + while (readl(&cmrtc->rtcclkctrl) != PRCM_MOD_EN) + ; } static void mpu_pll_config(void) diff --git a/arch/arm/include/asm/arch-am33xx/cpu.h b/arch/arm/include/asm/arch-am33xx/cpu.h index 6cfbef7..88057a3 100644 --- a/arch/arm/include/asm/arch-am33xx/cpu.h +++ b/arch/arm/include/asm/arch-am33xx/cpu.h @@ -169,6 +169,12 @@ struct cm_dpll { unsigned int clktimer2clk; /* offset 0x08 */ }; +/* Control Module RTC registers */ +struct cm_rtc { + unsigned int rtcclkctrl; /* offset 0x0 */ + unsigned int clkstctrl; /* offset 0x4 */ +}; + /* Watchdog timer registers */ struct wd_timer { unsigned int resv1[4]; @@ -218,6 +224,15 @@ struct gptimer { unsigned int tcar2; /* offset 0x58 */ }; +/* RTC Registers */ +struct rtc_regs { + unsigned int res[21]; + unsigned int osc; /* offset 0x54 */ + unsigned int res2[6]; + unsigned int kick0r; /* offset 0x6c */ + unsigned int kick1r; /* offset 0x70 */ +}; + /* UART Registers */ struct uart_sys { unsigned int resv1[21]; diff --git a/arch/arm/include/asm/arch-am33xx/hardware.h b/arch/arm/include/asm/arch-am33xx/hardware.h index 62332f2..5bd4bc8 100644 --- a/arch/arm/include/asm/arch-am33xx/hardware.h +++ b/arch/arm/include/asm/arch-am33xx/hardware.h @@ -61,6 +61,7 @@ #define CM_WKUP 0x44E00400 #define CM_DPLL 0x44E00500 #define CM_DEVICE 0x44E00700 +#define CM_RTC 0x44E00800 #define CM_CEFUSE 0x44E00A00 #define PRM_DEVICE 0x44E00F00 @@ -83,4 +84,7 @@ #define AM335X_CPSW_BASE 0x4A100000 #define AM335X_CPSW_MDIO_BASE 0x4A101000 +/* RTC base address */ +#define AM335X_RTC_BASE 0x44E3E000 + #endif /* __AM33XX_HARDWARE_H */