From patchwork Thu Oct 18 05:50:30 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Gibson X-Patchwork-Id: 192195 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 1C50F2C0096 for ; Thu, 18 Oct 2012 17:48:43 +1100 (EST) Received: from localhost ([::1]:38655 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TOj05-0006rW-2i for incoming@patchwork.ozlabs.org; Thu, 18 Oct 2012 01:50:33 -0400 Received: from eggs.gnu.org ([208.118.235.92]:40502) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TOizL-0005YQ-Fr for qemu-devel@nongnu.org; Thu, 18 Oct 2012 01:49:49 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1TOizF-0007db-BD for qemu-devel@nongnu.org; Thu, 18 Oct 2012 01:49:47 -0400 Received: from ozlabs.org ([203.10.76.45]:36833) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TOizE-0007cW-NZ; Thu, 18 Oct 2012 01:49:41 -0400 Received: by ozlabs.org (Postfix, from userid 1007) id 250492C00A7; Thu, 18 Oct 2012 16:49:34 +1100 (EST) From: David Gibson To: agraf@suse.de Date: Thu, 18 Oct 2012 16:50:30 +1100 Message-Id: <1350539437-535-9-git-send-email-david@gibson.dropbear.id.au> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1350539437-535-1-git-send-email-david@gibson.dropbear.id.au> References: <1350539437-535-1-git-send-email-david@gibson.dropbear.id.au> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 203.10.76.45 Cc: Michael Ellerman , qemu-ppc@nongnu.org, qemu-devel@nongnu.org, David Gibson Subject: [Qemu-devel] [PATCH 08/15] pseries: Move XICS initialization before cpu initialization X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Ben Herrenschmidt Currently, the pseries machine initializes the cpus, then the XICS interrupt controller. However, to support the upcoming in-kernel XICS implementation we will need to initialize the irq controller before the vcpus. This patch makes the necesssary rearrangement. This means the xics init code can no longer auto-detect the number of cpus ("interrupt servers" in XICS terminology) and so we must pass that in explicitly from the platform code. Signed-off-by: Michael Ellerman Signed-off-by: Ben Herrenschmidt Signed-off-by: David Gibson --- hw/spapr.c | 11 +++++++---- hw/xics.c | 52 +++++++++++++++++++++++----------------------------- hw/xics.h | 3 ++- 3 files changed, 32 insertions(+), 34 deletions(-) diff --git a/hw/spapr.c b/hw/spapr.c index 789c941..e8dbd97 100644 --- a/hw/spapr.c +++ b/hw/spapr.c @@ -744,6 +744,11 @@ static void ppc_spapr_init(ram_addr_t ram_size, spapr->htab_shift++; } + /* Set up Interrupt Controller before we create the VCPUs */ + spapr->icp = xics_system_init(smp_cpus * kvmppc_smt_threads() / smp_threads, + XICS_IRQS); + spapr->next_irq = XICS_IRQ_BASE; + /* init CPUs */ if (cpu_model == NULL) { cpu_model = kvm_enabled() ? "host" : "POWER7"; @@ -756,6 +761,8 @@ static void ppc_spapr_init(ram_addr_t ram_size, } env = &cpu->env; + xics_cpu_setup(spapr->icp, env); + /* Set time-base frequency to 512 MHz */ cpu_ppc_tb_init(env, TIMEBASE_FREQ); @@ -796,10 +803,6 @@ static void ppc_spapr_init(ram_addr_t ram_size, g_free(filename); - /* Set up Interrupt Controller */ - spapr->icp = xics_system_init(XICS_IRQS); - spapr->next_irq = XICS_IRQ_BASE; - /* Set up EPOW events infrastructure */ spapr_events_init(spapr); diff --git a/hw/xics.c b/hw/xics.c index 6b08430..8860355 100644 --- a/hw/xics.c +++ b/hw/xics.c @@ -507,42 +507,36 @@ static void xics_reset(void *opaque) } } -struct icp_state *xics_system_init(int nr_irqs) +void xics_cpu_setup(struct icp_state *icp, CPUPPCState *env) { - CPUPPCState *env; - int max_server_num; - struct icp_state *icp; - struct ics_state *ics; + struct icp_server_state *ss = &icp->ss[env->cpu_index]; - max_server_num = -1; - for (env = first_cpu; env != NULL; env = env->next_cpu) { - if (env->cpu_index > max_server_num) { - max_server_num = env->cpu_index; - } - } + assert(env->cpu_index < icp->nr_servers); - icp = g_malloc0(sizeof(*icp)); - icp->nr_servers = max_server_num + 1; - icp->ss = g_malloc0(icp->nr_servers*sizeof(struct icp_server_state)); + switch (PPC_INPUT(env)) { + case PPC_FLAGS_INPUT_POWER7: + ss->output = env->irq_inputs[POWER7_INPUT_INT]; + break; - for (env = first_cpu; env != NULL; env = env->next_cpu) { - struct icp_server_state *ss = &icp->ss[env->cpu_index]; + case PPC_FLAGS_INPUT_970: + ss->output = env->irq_inputs[PPC970_INPUT_INT]; + break; - switch (PPC_INPUT(env)) { - case PPC_FLAGS_INPUT_POWER7: - ss->output = env->irq_inputs[POWER7_INPUT_INT]; - break; + default: + fprintf(stderr, "XICS interrupt controller does not support this CPU " + "bus model\n"); + abort(); + } +} - case PPC_FLAGS_INPUT_970: - ss->output = env->irq_inputs[PPC970_INPUT_INT]; - break; +struct icp_state *xics_system_init(int nr_servers, int nr_irqs) +{ + struct icp_state *icp; + struct ics_state *ics; - default: - hw_error("XICS interrupt model does not support this CPU bus " - "model\n"); - exit(1); - } - } + icp = g_malloc0(sizeof(*icp)); + icp->nr_servers = nr_servers; + icp->ss = g_malloc0(icp->nr_servers*sizeof(struct icp_server_state)); ics = g_malloc0(sizeof(*ics)); ics->nr_irqs = nr_irqs; diff --git a/hw/xics.h b/hw/xics.h index c3bf008..b43678a 100644 --- a/hw/xics.h +++ b/hw/xics.h @@ -35,6 +35,7 @@ struct icp_state; qemu_irq xics_get_qirq(struct icp_state *icp, int irq); void xics_set_irq_type(struct icp_state *icp, int irq, bool lsi); -struct icp_state *xics_system_init(int nr_irqs); +struct icp_state *xics_system_init(int nr_servers, int nr_irqs); +void xics_cpu_setup(struct icp_state *icp, CPUPPCState *env); #endif /* __XICS_H__ */