Patchwork i386/cpu: name new CPUID bits

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Submitter Andre Przywara
Date Oct. 17, 2012, 9:17 p.m.
Message ID <1350508646-32386-1-git-send-email-andre.przywara@amd.com>
Download mbox | patch
Permalink /patch/192144/
State New
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Comments

Andre Przywara - Oct. 17, 2012, 9:17 p.m.
Update QEMU's knowledge of CPUID bit names. This allows to
enable/disable those new features on QEMU's command line when
using KVM and prepares future feature enablement in QEMU.

This adds F16C, RDRAND, LWP, TBM, TopoExt, PerfCtr_Core, PerfCtr_NB,
FSGSBASE, BMI1, AVX2, BMI2, ERMS, InvPCID, RTM, RDSeed and ADX.

Sources where the AMD BKDG for Family 15h/Model 10h and the Linux kernel
for the leaf 7 bits.

Signed-off-by: Andre Przywara <andre.przywara@amd.com>
---
 target-i386/cpu.c | 16 ++++++++--------
 target-i386/cpu.h | 21 +++++++++++++++++++++
 2 files changed, 29 insertions(+), 8 deletions(-)
Eduardo Habkost - Oct. 18, 2012, 4:33 p.m.
On Wed, Oct 17, 2012 at 11:17:26PM +0200, Andre Przywara wrote:
> Update QEMU's knowledge of CPUID bit names. This allows to
> enable/disable those new features on QEMU's command line when
> using KVM and prepares future feature enablement in QEMU.
> 
> This adds F16C, RDRAND, LWP, TBM, TopoExt, PerfCtr_Core, PerfCtr_NB,
> FSGSBASE, BMI1, AVX2, BMI2, ERMS, InvPCID, RTM, RDSeed and ADX.
> 
> Sources where the AMD BKDG for Family 15h/Model 10h and the Linux kernel
> for the leaf 7 bits.
> 
> Signed-off-by: Andre Przywara <andre.przywara@amd.com>
> ---
>  target-i386/cpu.c | 16 ++++++++--------
>  target-i386/cpu.h | 21 +++++++++++++++++++++
>  2 files changed, 29 insertions(+), 8 deletions(-)
> 
> diff --git a/target-i386/cpu.c b/target-i386/cpu.c
> index f3708e6..49f9561 100644
> --- a/target-i386/cpu.c
> +++ b/target-i386/cpu.c
> @@ -59,7 +59,7 @@ static const char *ext_feature_name[] = {
>      NULL, "pcid", "dca", "sse4.1|sse4_1",
>      "sse4.2|sse4_2", "x2apic", "movbe", "popcnt",
>      "tsc-deadline", "aes", "xsave", "osxsave",
> -    "avx", NULL, NULL, "hypervisor",
> +    "avx", "f16c", "rdrand", "hypervisor",
>  };
>  /* Feature names that are already defined on feature_name[] but are set on
>   * CPUID[8000_0001].EDX on AMD CPUs don't have their names on
> @@ -79,10 +79,10 @@ static const char *ext3_feature_name[] = {
>      "lahf_lm" /* AMD LahfSahf */, "cmp_legacy", "svm", "extapic" /* AMD ExtApicSpace */,
>      "cr8legacy" /* AMD AltMovCr8 */, "abm", "sse4a", "misalignsse",
>      "3dnowprefetch", "osvw", "ibs", "xop",
> -    "skinit", "wdt", NULL, NULL,
> -    "fma4", NULL, "cvt16", "nodeid_msr",
> -    NULL, NULL, NULL, NULL,
> -    NULL, NULL, NULL, NULL,
> +    "skinit", "wdt", NULL, "lwp",
> +    "fma4", "tce", NULL, "nodeid_msr",

You removed cvt16, here.

All the rest of the flags look OK to me.


> +    NULL, "tbm", "topoext", "perfctr_core",
> +    "perfctr_nb", NULL, NULL, NULL,
>      NULL, NULL, NULL, NULL,
>  };
>  
> @@ -105,9 +105,9 @@ static const char *svm_feature_name[] = {
>  };
>  
>  static const char *cpuid_7_0_ebx_feature_name[] = {
> -    NULL, NULL, NULL, NULL, NULL, NULL, NULL, "smep",
> -    NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
> -    NULL, NULL, NULL, NULL, "smap", NULL, NULL, NULL,
> +    "fsgsbase", NULL, NULL, "bmi1", "hle", "avx2", NULL, "smep",
> +    "bmi2", "erms", "invpcid", "rtm", NULL, NULL, NULL, NULL,
> +    NULL, NULL, "rdseed", "adx", "smap", NULL, NULL, NULL,
>      NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
>  };
>  
> diff --git a/target-i386/cpu.h b/target-i386/cpu.h
> index 871c270..e496b5b 100644
> --- a/target-i386/cpu.h
> +++ b/target-i386/cpu.h
> @@ -403,6 +403,7 @@
>  #define CPUID_EXT_TM2      (1 << 8)
>  #define CPUID_EXT_SSSE3    (1 << 9)
>  #define CPUID_EXT_CID      (1 << 10)
> +#define CPUID_EXT_FMA      (1 << 12)
>  #define CPUID_EXT_CX16     (1 << 13)
>  #define CPUID_EXT_XTPR     (1 << 14)
>  #define CPUID_EXT_PDCM     (1 << 15)
> @@ -417,6 +418,8 @@
>  #define CPUID_EXT_XSAVE    (1 << 26)
>  #define CPUID_EXT_OSXSAVE  (1 << 27)
>  #define CPUID_EXT_AVX      (1 << 28)
> +#define CPUID_EXT_F16C     (1 << 29)
> +#define CPUID_EXT_RDRAND   (1 << 30)
>  #define CPUID_EXT_HYPERVISOR  (1 << 31)
>  
>  #define CPUID_EXT2_FPU     (1 << 0)
> @@ -472,7 +475,15 @@
>  #define CPUID_EXT3_IBS     (1 << 10)
>  #define CPUID_EXT3_XOP     (1 << 11)
>  #define CPUID_EXT3_SKINIT  (1 << 12)
> +#define CPUID_EXT3_WDT     (1 << 13)
> +#define CPUID_EXT3_LWP     (1 << 15)
>  #define CPUID_EXT3_FMA4    (1 << 16)
> +#define CPUID_EXT3_TCE     (1 << 17)
> +#define CPUID_EXT3_NODEID  (1 << 19)
> +#define CPUID_EXT3_TBM     (1 << 21)
> +#define CPUID_EXT3_TOPOEXT (1 << 22)
> +#define CPUID_EXT3_PERFCORE (1 << 23)
> +#define CPUID_EXT3_PERFNB  (1 << 24)
>  
>  #define CPUID_SVM_NPT          (1 << 0)
>  #define CPUID_SVM_LBRV         (1 << 1)
> @@ -485,7 +496,17 @@
>  #define CPUID_SVM_PAUSEFILTER  (1 << 10)
>  #define CPUID_SVM_PFTHRESHOLD  (1 << 12)
>  
> +#define CPUID_7_0_EBX_FSGSBASE (1 << 0)
> +#define CPUID_7_0_EBX_BMI1     (1 << 3)
> +#define CPUID_7_0_EBX_HLE      (1 << 4)
> +#define CPUID_7_0_EBX_AVX2     (1 << 5)
>  #define CPUID_7_0_EBX_SMEP     (1 << 7)
> +#define CPUID_7_0_EBX_BMI2     (1 << 8)
> +#define CPUID_7_0_EBX_ERMS     (1 << 9)
> +#define CPUID_7_0_EBX_INVPCID  (1 << 10)
> +#define CPUID_7_0_EBX_RTM      (1 << 11)
> +#define CPUID_7_0_EBX_RDSEED   (1 << 18)
> +#define CPUID_7_0_EBX_ADX      (1 << 19)
>  #define CPUID_7_0_EBX_SMAP     (1 << 20)
>  
>  #define CPUID_VENDOR_INTEL_1 0x756e6547 /* "Genu" */
> -- 
> 1.7.12.1
> 
>
Andre Przywara - Oct. 18, 2012, 11:34 p.m.
On 10/18/12 18:33, Eduardo Habkost wrote:
> On Wed, Oct 17, 2012 at 11:17:26PM +0200, Andre Przywara wrote:
>> Update QEMU's knowledge of CPUID bit names. This allows to
>> enable/disable those new features on QEMU's command line when
>> using KVM and prepares future feature enablement in QEMU.
...
>> @@ -79,10 +79,10 @@ static const char *ext3_feature_name[] = {
>>       "lahf_lm" /* AMD LahfSahf */, "cmp_legacy", "svm", "extapic" /* AMD ExtApicSpace */,
>>       "cr8legacy" /* AMD AltMovCr8 */, "abm", "sse4a", "misalignsse",
>>       "3dnowprefetch", "osvw", "ibs", "xop",
>> -    "skinit", "wdt", NULL, NULL,
>> -    "fma4", NULL, "cvt16", "nodeid_msr",
>> -    NULL, NULL, NULL, NULL,
>> -    NULL, NULL, NULL, NULL,
>> +    "skinit", "wdt", NULL, "lwp",
>> +    "fma4", "tce", NULL, "nodeid_msr",
>
> You removed cvt16, here.

On purpose, cvt16 is dead. It seems to have been advertised in the 
documentation for some time, but later disappeared. The respective 
instructions are now reported via the F16C flag in the Intel leaf.

If you want to know more, I can dig deeper and ask some people. But the 
bit is now "reserved" and was never '1' in any silicon. (And was 
introduced by me into QEMU :-(

>
> All the rest of the flags look OK to me.

Thanks.

Regards,
Andre.
Eduardo Habkost - Oct. 19, 2012, 1:14 a.m.
On Fri, Oct 19, 2012 at 01:34:19AM +0200, Andre Przywara wrote:
> On 10/18/12 18:33, Eduardo Habkost wrote:
> >On Wed, Oct 17, 2012 at 11:17:26PM +0200, Andre Przywara wrote:
> >>Update QEMU's knowledge of CPUID bit names. This allows to
> >>enable/disable those new features on QEMU's command line when
> >>using KVM and prepares future feature enablement in QEMU.
> ...
> >>@@ -79,10 +79,10 @@ static const char *ext3_feature_name[] = {
> >>      "lahf_lm" /* AMD LahfSahf */, "cmp_legacy", "svm", "extapic" /* AMD ExtApicSpace */,
> >>      "cr8legacy" /* AMD AltMovCr8 */, "abm", "sse4a", "misalignsse",
> >>      "3dnowprefetch", "osvw", "ibs", "xop",
> >>-    "skinit", "wdt", NULL, NULL,
> >>-    "fma4", NULL, "cvt16", "nodeid_msr",
> >>-    NULL, NULL, NULL, NULL,
> >>-    NULL, NULL, NULL, NULL,
> >>+    "skinit", "wdt", NULL, "lwp",
> >>+    "fma4", "tce", NULL, "nodeid_msr",
> >
> >You removed cvt16, here.
> 
> On purpose, cvt16 is dead. It seems to have been advertised in the
> documentation for some time, but later disappeared. The respective
> instructions are now reported via the F16C flag in the Intel leaf.
> 
> If you want to know more, I can dig deeper and ask some people. But
> the bit is now "reserved" and was never '1' in any silicon. (And was
> introduced by me into QEMU :-(

KVM doesn't report it on GET_SUPPORTED_CPUID, either, so it's impossible
to have any VM running with that bit set, even if was set on some
silicon.

It would be interesting to document that on the commit message, though.

> 
> >
> >All the rest of the flags look OK to me.
> 
> Thanks.
> 
> Regards,
> Andre.
> 
>

Patch

diff --git a/target-i386/cpu.c b/target-i386/cpu.c
index f3708e6..49f9561 100644
--- a/target-i386/cpu.c
+++ b/target-i386/cpu.c
@@ -59,7 +59,7 @@  static const char *ext_feature_name[] = {
     NULL, "pcid", "dca", "sse4.1|sse4_1",
     "sse4.2|sse4_2", "x2apic", "movbe", "popcnt",
     "tsc-deadline", "aes", "xsave", "osxsave",
-    "avx", NULL, NULL, "hypervisor",
+    "avx", "f16c", "rdrand", "hypervisor",
 };
 /* Feature names that are already defined on feature_name[] but are set on
  * CPUID[8000_0001].EDX on AMD CPUs don't have their names on
@@ -79,10 +79,10 @@  static const char *ext3_feature_name[] = {
     "lahf_lm" /* AMD LahfSahf */, "cmp_legacy", "svm", "extapic" /* AMD ExtApicSpace */,
     "cr8legacy" /* AMD AltMovCr8 */, "abm", "sse4a", "misalignsse",
     "3dnowprefetch", "osvw", "ibs", "xop",
-    "skinit", "wdt", NULL, NULL,
-    "fma4", NULL, "cvt16", "nodeid_msr",
-    NULL, NULL, NULL, NULL,
-    NULL, NULL, NULL, NULL,
+    "skinit", "wdt", NULL, "lwp",
+    "fma4", "tce", NULL, "nodeid_msr",
+    NULL, "tbm", "topoext", "perfctr_core",
+    "perfctr_nb", NULL, NULL, NULL,
     NULL, NULL, NULL, NULL,
 };
 
@@ -105,9 +105,9 @@  static const char *svm_feature_name[] = {
 };
 
 static const char *cpuid_7_0_ebx_feature_name[] = {
-    NULL, NULL, NULL, NULL, NULL, NULL, NULL, "smep",
-    NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
-    NULL, NULL, NULL, NULL, "smap", NULL, NULL, NULL,
+    "fsgsbase", NULL, NULL, "bmi1", "hle", "avx2", NULL, "smep",
+    "bmi2", "erms", "invpcid", "rtm", NULL, NULL, NULL, NULL,
+    NULL, NULL, "rdseed", "adx", "smap", NULL, NULL, NULL,
     NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
 };
 
diff --git a/target-i386/cpu.h b/target-i386/cpu.h
index 871c270..e496b5b 100644
--- a/target-i386/cpu.h
+++ b/target-i386/cpu.h
@@ -403,6 +403,7 @@ 
 #define CPUID_EXT_TM2      (1 << 8)
 #define CPUID_EXT_SSSE3    (1 << 9)
 #define CPUID_EXT_CID      (1 << 10)
+#define CPUID_EXT_FMA      (1 << 12)
 #define CPUID_EXT_CX16     (1 << 13)
 #define CPUID_EXT_XTPR     (1 << 14)
 #define CPUID_EXT_PDCM     (1 << 15)
@@ -417,6 +418,8 @@ 
 #define CPUID_EXT_XSAVE    (1 << 26)
 #define CPUID_EXT_OSXSAVE  (1 << 27)
 #define CPUID_EXT_AVX      (1 << 28)
+#define CPUID_EXT_F16C     (1 << 29)
+#define CPUID_EXT_RDRAND   (1 << 30)
 #define CPUID_EXT_HYPERVISOR  (1 << 31)
 
 #define CPUID_EXT2_FPU     (1 << 0)
@@ -472,7 +475,15 @@ 
 #define CPUID_EXT3_IBS     (1 << 10)
 #define CPUID_EXT3_XOP     (1 << 11)
 #define CPUID_EXT3_SKINIT  (1 << 12)
+#define CPUID_EXT3_WDT     (1 << 13)
+#define CPUID_EXT3_LWP     (1 << 15)
 #define CPUID_EXT3_FMA4    (1 << 16)
+#define CPUID_EXT3_TCE     (1 << 17)
+#define CPUID_EXT3_NODEID  (1 << 19)
+#define CPUID_EXT3_TBM     (1 << 21)
+#define CPUID_EXT3_TOPOEXT (1 << 22)
+#define CPUID_EXT3_PERFCORE (1 << 23)
+#define CPUID_EXT3_PERFNB  (1 << 24)
 
 #define CPUID_SVM_NPT          (1 << 0)
 #define CPUID_SVM_LBRV         (1 << 1)
@@ -485,7 +496,17 @@ 
 #define CPUID_SVM_PAUSEFILTER  (1 << 10)
 #define CPUID_SVM_PFTHRESHOLD  (1 << 12)
 
+#define CPUID_7_0_EBX_FSGSBASE (1 << 0)
+#define CPUID_7_0_EBX_BMI1     (1 << 3)
+#define CPUID_7_0_EBX_HLE      (1 << 4)
+#define CPUID_7_0_EBX_AVX2     (1 << 5)
 #define CPUID_7_0_EBX_SMEP     (1 << 7)
+#define CPUID_7_0_EBX_BMI2     (1 << 8)
+#define CPUID_7_0_EBX_ERMS     (1 << 9)
+#define CPUID_7_0_EBX_INVPCID  (1 << 10)
+#define CPUID_7_0_EBX_RTM      (1 << 11)
+#define CPUID_7_0_EBX_RDSEED   (1 << 18)
+#define CPUID_7_0_EBX_ADX      (1 << 19)
 #define CPUID_7_0_EBX_SMAP     (1 << 20)
 
 #define CPUID_VENDOR_INTEL_1 0x756e6547 /* "Genu" */