From patchwork Tue Oct 16 15:56:33 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Meissner X-Patchwork-Id: 191826 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) by ozlabs.org (Postfix) with SMTP id 473C62C00A3 for ; Wed, 17 Oct 2012 02:57:35 +1100 (EST) Comment: DKIM? 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Violators will be prosecuted; Tue, 16 Oct 2012 11:56:58 -0400 Received: from d01relay02.pok.ibm.com (d01relay02.pok.ibm.com [9.56.227.234]) by d01dlp03.pok.ibm.com (Postfix) with ESMTP id BE989C90098 for ; Tue, 16 Oct 2012 11:56:50 -0400 (EDT) Received: from d01av02.pok.ibm.com (d01av02.pok.ibm.com [9.56.224.216]) by d01relay02.pok.ibm.com (8.13.8/8.13.8/NCO v10.0) with ESMTP id q9GFuoHV267118 for ; Tue, 16 Oct 2012 11:56:51 -0400 Received: from d01av02.pok.ibm.com (loopback [127.0.0.1]) by d01av02.pok.ibm.com (8.14.4/8.13.1/NCO v10.0 AVout) with ESMTP id q9GFung1006798 for ; Tue, 16 Oct 2012 12:56:50 -0300 Received: from ibm-tiger.the-meissners.org ([9.33.48.180]) by d01av02.pok.ibm.com (8.14.4/8.13.1/NCO v10.0 AVin) with ESMTP id q9GFunwx005607; Tue, 16 Oct 2012 12:56:49 -0300 Received: by ibm-tiger.the-meissners.org (Postfix, from userid 500) id 390F9415D9; Tue, 16 Oct 2012 11:56:33 -0400 (EDT) Date: Tue, 16 Oct 2012 11:56:33 -0400 From: Michael Meissner To: Michael Meissner , David Edelsohn , gcc-patches@gcc.gnu.org, bergner@vnet.ibm.com, segher@kernel.crashing.org, iain@codesourcery.com, andreast-list@fgznet.ch Subject: Re: [PATCH] Rs6000 infrastructure cleanup (switches), revised patch #2f Message-ID: <20121016155632.GA14729@ibm-tiger.the-meissners.org> Mail-Followup-To: Michael Meissner , David Edelsohn , gcc-patches@gcc.gnu.org, bergner@vnet.ibm.com, segher@kernel.crashing.org, iain@codesourcery.com, andreast-list@fgznet.ch References: <20120912224303.GA19348@ibm-tiger.the-meissners.org> <20120917195131.GA22648@ibm-tiger.the-meissners.org> <20120920195755.GA18581@ibm-tiger.the-meissners.org> <20120927224228.GA24889@ibm-tiger.the-meissners.org> <20121005194921.GA20004@ibm-tiger.the-meissners.org> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20121005194921.GA20004@ibm-tiger.the-meissners.org> User-Agent: Mutt/1.5.20 (2009-12-10) X-Content-Scanned: Fidelis XPS MAILER x-cbid: 12101615-8974-0000-0000-00000FA610E6 X-IBM-ISS-SpamDetectors: X-IBM-ISS-DetailInfo: BY=3.00000294; HX=3.00000196; KW=3.00000007; PH=3.00000001; SC=3.00000008; SDB=6.00183002; UDB=6.00041452; UTC=2012-10-16 15:57:04 X-IsSubscribed: yes Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org While Joseph and I are iterating on global changes to the options machinery, David had said patch #2b was ok for just powerpc specific changes. I took patch #2b, and adjusted it for the 3 patches I already checked in. I rewrote the ChangeLog entries to try and be more explicit in what was going on. This bootstraped and had no regressions. Is this ok to check in? 2012-10-16 Michael Meissner * config/rs6000/rs6000.opt (rs6000_isa_flags): New flag word to replace target_flags that gives us 63 possible switches. (x_rs6000_isa_flags): Save area for rs6000_isa_flags. (x_rs6000_isa_flags_explicit): Save area for rs6000_isa_flags_explicit. (rs6000_target_flags_explicit): Delete in favor of x_rs6000_isa_flags_explicit. (-mpowerpc64): Change all switches that used to be in target_flags to now be in rs6000_isa_flags. In using rs6000_isa_flags, the options machinary will generate names of the form OPITON_ instead of TARGET_ and OPTION_MASK_ instead of MASK_. (-mpowerpc-gpopt): Likewise. (-mpowerpc-gfxopt): Likewise. (-mmfcrf): Likewise. (-mpopcntb): Likewise. (-mfprnd): Likewise. (-mcmpb): Likewise. (-mmfpgpr): Likewise. (-maltivec): Likewise. (-mhard-dfp): Likewise. (-mmulhw): Likewise. (-mdlmzb): Likewise. (-mmultiple): Likewise. (-mstring): Likewise. (-msoft-float): Likewise. (-mhard-float): Likewise. (-mpopcntd): Likewise. (-mvsx): Likewise. (-mno-update): Likewise. (-mupdate): Likewise. (-mrecip-precision): Likewise. (-mminimal-toc): Likewise. (-misel): Likewise. * config/rs6000/aix64.opt (-maix64): Likewise. (-maix32): Likewise. * config/rs6000/sysv4.opt (-mstrict-align): Likewise. (-mrelocatable): Likewise. (-mlittle-endian): Likewise. (-mlittle): Likewise. (-mbig-endian): LIkewise. (-mbig): Likewise. (-meabi): Likewise. (-m64): Likewise. (-m32): Likewise. * config/rs6000/darwin.opt (-m64): Likewise. (-m32): Likewise. * config/rs6000/rs6000-cpus.def (ISA_2_1_MASKS): Move the various masks used in rs6000.c here, since they are more logically in this file. Convert from being enums to just #defines, since the types of these masks is now HOST_WIDE_INT instead of int. For POWERPC_MASKS, add MASK_SOFT_FLOAT, since the only use case or'ed in the mask. Change the use in rs6000.c not to do the OR of MASK_SOFT_FLOAT. (ISA_2_1_MASKS): Likewise. (ISA_2_2_MASKS): Likewise. (ISA_2_4_MASKS): Likewise. (ISA_2_5_MASKS_EMBEDDED): Likewise. (ISA_2_5_MASKS_SERVER): Likewise. (POWERPC_7400_MASK): Likewise. (POWERPC_MASKS): Likewise. * config/rs6000/rs6000.c (ISA_2_1_MASKS): Likewise. (ISA_2_1_MASKS): Likewise. (ISA_2_2_MASKS): Likewise. (ISA_2_4_MASKS): Likewise. (ISA_2_5_MASKS_EMBEDDED): Likewise. (ISA_2_5_MASKS_SERVER): Likewise. (POWERPC_7400_MASK): Likewise. (POWERPC_MASKS): Likewise. (rs6000_option_override_internal): Likewise. * config/rs6000/rs6000.c (darwin_rs6000_override_options): Change all uses of target_flags to rs6000_isa_flags. Change all uses of target_flags_explicit to rs6000_isa_flags_explicit. Change the use of MASK_ to OPTION_MASK_ that options.h defines when we use a secondary flags word. Save/restore/print the new flags word when switching contexts with different target attributes. (rs6000_option_override_internal): Likewise. (rs6000_darwin_file_start): Likewise. (rs6000_opt_masks): Likewise. (rs6000_inner_target_options): Likewise. (rs6000_pragma_target_parse): Likewise. (rs6000_set_current_function): Likewise. (rs6000_function_specific_save): Likewise. (rs6000_function_specific_restore): Likewise. (rs6000_function_specific_print): Likewise. (rs6000_can_inline_p): Likewise. * config/rs6000/rs6000-c.c (rs6000_target_modify_macros): Likewise. (rs6000_cpu_cpp_builtins): Likewise. * common/config/rs6000/rs6000-driver.c (rs6000_handle_option): Likewise. * config/rs6000/rs6000.h (OPTION_MFCRF): Replace TARGET_ with OPTION_ if the assembler doesn't support mfcrf, popcntb, fprnd, cmpb, mfpgpr, dfp, popcntd instructions. (TARGET_MFCRF): Likewise. (OPTION_POPCNTB): Likewise. (TARGET_POPCNTB): Likewise. (OPTION_FPRND): Likewise. (TARGET_FPRND): Likewise. (OPTION_CMPB): Likewise. (TARGET_CMPB): Likewise. (OPTION_HARD_DFP): Likewise. (TARGET_HARD_DFP): Likewise. (OPTION_POPCNTD): Likewise. (TARGET_POPCNTD): LIkewise. (TARGET_ALTIVEC): In moving to using Var(...) for all of the isa switches, the options machinery now uses OPTION_ instead of TARGET_ for whether the switch was set, OPTION_MASK_ instead of MASK_ for the mask name. Use #define to map the old name into the new name. For switches that are defined in aix64.opt, sysv4.opt, and darwin.opt, only do the definition if those switches were defined. (TARGET_CMPB): Likewise. (TARGET_DFP): Likewise. (TARGET_DLMZB): Likewise. (TARGET_EABI): Likewise. (TARGET_FPRND): Likewise. (TARGET_HARD_FLOAT): Likewise. (TARGET_ISEL): Likewise. (TARGET_MFCRF): Likewise. (TARGET_MFPGPR): Likewise. (TARGET_MULHW): Likewise. (TARGET_MULTIPLE): Likewise. (TARGET_NO_UPDATE): Likewise. (TARGET_POPCNTB): Likewise. (TARGET_POPCNTD): Likewise. (TARGET_PPC_GFXOPT): Likewise. (TARGET_PPC_GPOPT): Likewise. (TARGET_RECIP_PRECISION): Likewise. (TARGET_SOFT_FLOAT): Likewise. (TARGET_STRICT_ALIGN): Likewise. (TARGET_STRING): Likewise. (TARGET_UPDATE): Likewise. (TARGET_VSX): Likewise. (MASK_ALTIVEC): Likewise. (MASK_CMPB): Likewise. (MASK_DFP): Likewise. (MASK_DLMZB): Likewise. (MASK_EABI): Likewise. (MASK_FPRND): Likewise. (MASK_HARD_FLOAT): Likewise. (MASK_ISEL): Likewise. (MASK_MFCRF): Likewise. (MASK_MFPGPR): Likewise. (MASK_MULHW): Likewise. (MASK_MULTIPLE): Likewise. (MASK_NO_UPDATE): Likewise. (MASK_POPCNTB): Likewise. (MASK_POPCNTD): Likewise. (MASK_PPC_GFXOPT): Likewise. (MASK_PPC_GPOPT): Likewise. (MASK_RECIP_PRECISION): Likewise. (MASK_SOFT_FLOAT): Likewise. (MASK_STRICT_ALIGN): Likewise. (MASK_STRING): Likewise. (MASK_UPDATE): Likewise. (MASK_VSX): Likewise. (TARGET_POWERPC64): Likewise. (MASK_POWERPC64): Likewise. (TARGET_64BIT): Likewise. (MASK_64BIT): Likewise. (TARGET_RELOCATABLE): Likewise. (MASK_RELOCATABLE): Likewise. (TARGET_LITTLE_ENDIAN): Likewise. (MASK_LITTLE_ENDIAN): Likewise. (TARGET_MINIMAL_TOC): Likewise. (MASK_MINIMAL_TOC): Likewise. (TARGET_REGNAMES): Likewise. (MASK_REGNAMES): Likewise. (TARGET_PROTOTYPE): Likewise. (MASK_PROTOTYPE): Likewise. (rs6000_isa_flags_explicit): Define in terms of the global_options_set structure. * gcc/config/rs6000/aix43.h (SUBTARGET_OVERRIDE_OPTIONS): Change use of target_flags to rs6000_isa_flags, target_flags_explicit to rs6000_isa_flags_explicit, and MASK_ to OPTION_MASK_. * gcc/config/rs6000/aix51.h (SUBTARGET_OVERRIDE_OPTIONS): Likewise. * gcc/config/rs6000/aix52.h (SUBTARGET_OVERRIDE_OPTIONS): Likewise. * gcc/config/rs6000/aix53.h (SUBTARGET_OVERRIDE_OPTIONS): Likewise. * gcc/config/rs6000/aix61.h (SUBTARGET_OVERRIDE_OPTIONS): Likewise. * gcc/config/rs6000/freebsd64.h (RELOCATABLE_NEEDS_FIXUP): Likewise. (SUBSUBTARGET_OVERRIDE_OPTIONS): Likewise. * gcc/config/rs6000/freebsd.h (RELOCATABLE_NEEDS_FIXUP): Likewise. * gcc/config/rs6000/linux64.h (RELOCATABLE_NEEDS_FIXUP): Likewise. (SUBSUBTARGET_OVERRIDE_OPTIONS): Likewise. (OPTION_LITTLE_ENDIAN): Likewise. (OPTION_RELOCATABLE): Likewise. (OPTION_EABI): Likewise. (OPTION_PROTOTYPE): Likewise. * gcc/config/rs6000/linux.h (RELOCATABLE_NEEDS_FIXUP): Likewise. * gcc/config/rs6000/option-defaults.h (OPTION_MASK_64BIT): Likewise. (OPT_ARCH32): Likewise. (OPT_ARCH64): Likewise. * gcc/config/rs6000/sysv4.h (TARGET_TOC): Likewise. (SUBTARGET_OVERRIDE_OPTIONS): Likewise. (SUBSUBTARGET_OVERRIDE_OPTIONS): Likewise. (TARGET_OS_SYSV_CPP_BUILTINS): Likewise. * config/rs6000/t-rs6000 (rs6000.o): Add rs6000-cpus.def as a dependency. Index: gcc/config/rs6000/rs6000.opt =================================================================== --- gcc/config/rs6000/rs6000.opt (revision 192474) +++ gcc/config/rs6000/rs6000.opt (working copy) @@ -22,6 +22,17 @@ HeaderInclude config/rs6000/rs6000-opts.h +;; ISA flag bits (on/off) +Variable +HOST_WIDE_INT rs6000_isa_flags = TARGET_DEFAULT + +TargetSave +HOST_WIDE_INT x_rs6000_isa_flags + +;; Miscellaneous flag bits that were set explicitly by the user +TargetSave +HOST_WIDE_INT x_rs6000_isa_flags_explicit + ;; Current processor TargetVariable enum processor_type rs6000_cpu = PROCESSOR_PPC603 @@ -86,80 +97,76 @@ HOST_WIDE_INT rs6000_builtin_mask TargetVariable unsigned int rs6000_debug -;; Save for target_flags_explicit -TargetSave -int rs6000_target_flags_explicit - ;; This option existed in the past, but now is always on. mpowerpc Target RejectNegative Undocumented Ignore mpowerpc64 -Target Report Mask(POWERPC64) +Target Report Mask(POWERPC64) Var(rs6000_isa_flags) Use PowerPC-64 instruction set mpowerpc-gpopt -Target Report Mask(PPC_GPOPT) Save +Target Report Mask(PPC_GPOPT) Var(rs6000_isa_flags) Use PowerPC General Purpose group optional instructions mpowerpc-gfxopt -Target Report Mask(PPC_GFXOPT) Save +Target Report Mask(PPC_GFXOPT) Var(rs6000_isa_flags) Use PowerPC Graphics group optional instructions mmfcrf -Target Report Mask(MFCRF) Save +Target Report Mask(MFCRF) Var(rs6000_isa_flags) Use PowerPC V2.01 single field mfcr instruction mpopcntb -Target Report Mask(POPCNTB) Save +Target Report Mask(POPCNTB) Var(rs6000_isa_flags) Use PowerPC V2.02 popcntb instruction mfprnd -Target Report Mask(FPRND) Save +Target Report Mask(FPRND) Var(rs6000_isa_flags) Use PowerPC V2.02 floating point rounding instructions mcmpb -Target Report Mask(CMPB) Save +Target Report Mask(CMPB) Var(rs6000_isa_flags) Use PowerPC V2.05 compare bytes instruction mmfpgpr -Target Report Mask(MFPGPR) Save +Target Report Mask(MFPGPR) Var(rs6000_isa_flags) Use extended PowerPC V2.05 move floating point to/from GPR instructions maltivec -Target Report Mask(ALTIVEC) Save +Target Report Mask(ALTIVEC) Var(rs6000_isa_flags) Use AltiVec instructions mhard-dfp -Target Report Mask(DFP) Save +Target Report Mask(DFP) Var(rs6000_isa_flags) Use decimal floating point instructions mmulhw -Target Report Mask(MULHW) Save +Target Report Mask(MULHW) Var(rs6000_isa_flags) Use 4xx half-word multiply instructions mdlmzb -Target Report Mask(DLMZB) Save +Target Report Mask(DLMZB) Var(rs6000_isa_flags) Use 4xx string-search dlmzb instruction mmultiple -Target Report Mask(MULTIPLE) Save +Target Report Mask(MULTIPLE) Var(rs6000_isa_flags) Generate load/store multiple instructions mstring -Target Report Mask(STRING) Save +Target Report Mask(STRING) Var(rs6000_isa_flags) Generate string instructions for block moves msoft-float -Target Report RejectNegative Mask(SOFT_FLOAT) +Target Report RejectNegative Mask(SOFT_FLOAT) Var(rs6000_isa_flags) Do not use hardware floating point mhard-float -Target Report RejectNegative InverseMask(SOFT_FLOAT, HARD_FLOAT) +Target Report RejectNegative InverseMask(SOFT_FLOAT, HARD_FLOAT) Var(rs6000_isa_flags) Use hardware floating point mpopcntd -Target Report Mask(POPCNTD) Save +Target Report Mask(POPCNTD) Var(rs6000_isa_flags) Use PowerPC V2.06 popcntd instruction mfriz @@ -171,7 +178,7 @@ Target RejectNegative Joined Var(rs6000_ Vector library ABI to use mvsx -Target Report Mask(VSX) Save +Target Report Mask(VSX) Var(rs6000_isa_flags) Use vector/scalar (VSX) instructions mvsx-scalar-double @@ -211,11 +218,11 @@ Target Undocumented Report Var(TARGET_VE ; Explicitly control whether we vectorize the builtins or not. mno-update -Target Report RejectNegative Mask(NO_UPDATE) Save +Target Report RejectNegative Mask(NO_UPDATE) Var(rs6000_isa_flags) Do not generate load/store with update instructions mupdate -Target Report RejectNegative InverseMask(NO_UPDATE, UPDATE) +Target Report RejectNegative InverseMask(NO_UPDATE, UPDATE) Var(rs6000_isa_flags) Generate load/store with update instructions msingle-pic-base @@ -258,7 +265,7 @@ Target Report RejectNegative Joined Var( Generate software reciprocal divide and square root for better throughput. mrecip-precision -Target Report Mask(RECIP_PRECISION) Save +Target Report Mask(RECIP_PRECISION) Var(rs6000_isa_flags) Assume that the reciprocal estimate instructions provide more accuracy. mno-fp-in-toc @@ -285,7 +292,7 @@ Place symbol+offset constants in TOC ; This is at the cost of having 2 extra loads and one extra store per ; function, and one less allocable register. mminimal-toc -Target Report Mask(MINIMAL_TOC) +Target Report Mask(MINIMAL_TOC) Var(rs6000_isa_flags) Use only one TOC entry per procedure mfull-toc @@ -309,7 +316,7 @@ Target Report Var(rs6000_block_move_inli Specify how many bytes should be moved inline before calling out to memcpy/memmove misel -Target Report Mask(ISEL) Save +Target Report Mask(ISEL) Var(rs6000_isa_flags) Generate isel instructions misel=no Index: gcc/config/rs6000/aix64.opt =================================================================== --- gcc/config/rs6000/aix64.opt (revision 192474) +++ gcc/config/rs6000/aix64.opt (working copy) @@ -20,11 +20,11 @@ ; . maix64 -Target Report RejectNegative Negative(maix32) Mask(64BIT) +Target Report RejectNegative Negative(maix32) Mask(64BIT) Var(rs6000_isa_flags) Compile for 64-bit pointers maix32 -Target Report RejectNegative Negative(maix64) InverseMask(64BIT) +Target Report RejectNegative Negative(maix64) InverseMask(64BIT) Var(rs6000_isa_flags) Compile for 32-bit pointers mpe Index: gcc/config/rs6000/sysv4.opt =================================================================== --- gcc/config/rs6000/sysv4.opt (revision 192474) +++ gcc/config/rs6000/sysv4.opt (working copy) @@ -49,12 +49,12 @@ Target Report Var(TARGET_NO_BITFIELD_TYP Align to the base type of the bit-field mstrict-align -Target Report Mask(STRICT_ALIGN) +Target Report Mask(STRICT_ALIGN) Var(rs6000_isa_flags) Align to the base type of the bit-field Don't assume that unaligned accesses are handled by the system mrelocatable -Target Report Mask(RELOCATABLE) +Target Report Mask(RELOCATABLE) Var(rs6000_isa_flags) Produce code relocatable at runtime mrelocatable-lib @@ -62,19 +62,19 @@ Target Produce code relocatable at runtime mlittle-endian -Target Report RejectNegative Mask(LITTLE_ENDIAN) +Target Report RejectNegative Mask(LITTLE_ENDIAN) Var(rs6000_isa_flags) Produce little endian code mlittle -Target Report RejectNegative Mask(LITTLE_ENDIAN) +Target Report RejectNegative Mask(LITTLE_ENDIAN) Var(rs6000_isa_flags) Produce little endian code mbig-endian -Target Report RejectNegative InverseMask(LITTLE_ENDIAN) +Target Report RejectNegative InverseMask(LITTLE_ENDIAN) Var(rs6000_isa_flags) Produce big endian code mbig -Target Report RejectNegative InverseMask(LITTLE_ENDIAN) +Target Report RejectNegative InverseMask(LITTLE_ENDIAN) Var(rs6000_isa_flags) Produce big endian code ;; FIXME: This does nothing. What should be done? @@ -96,7 +96,7 @@ Target RejectNegative no description yet meabi -Target Report Mask(EABI) +Target Report Mask(EABI) Var(rs6000_isa_flags) Use EABI mbit-word @@ -138,11 +138,11 @@ Target RejectNegative no description yet m64 -Target Report RejectNegative Negative(m32) Mask(64BIT) +Target Report RejectNegative Negative(m32) Mask(64BIT) Var(rs6000_isa_flags) Generate 64-bit code m32 -Target Report RejectNegative Negative(m64) InverseMask(64BIT) +Target Report RejectNegative Negative(m64) InverseMask(64BIT) Var(rs6000_isa_flags) Generate 32-bit code mnewlib Index: gcc/config/rs6000/darwin.opt =================================================================== --- gcc/config/rs6000/darwin.opt (revision 192474) +++ gcc/config/rs6000/darwin.opt (working copy) @@ -34,9 +34,9 @@ findirect-data Driver RejectNegative Alias(mfix-and-continue) m64 -Target RejectNegative Negative(m32) Mask(64BIT) +Target RejectNegative Negative(m32) Mask(64BIT) Var(rs6000_isa_flags) Generate 64-bit code m32 -Target RejectNegative Negative(m64) InverseMask(64BIT) +Target RejectNegative Negative(m64) InverseMask(64BIT) Var(rs6000_isa_flags) Generate 32-bit code Index: gcc/config/rs6000/rs6000-cpus.def =================================================================== --- gcc/config/rs6000/rs6000-cpus.def (revision 192474) +++ gcc/config/rs6000/rs6000-cpus.def (working copy) @@ -18,6 +18,57 @@ along with GCC; see the file COPYING3. If not see . */ +/* ISA masks. */ +#ifndef ISA_2_1_MASKS +#define ISA_2_1_MASKS OPTION_MASK_MFCRF +#define ISA_2_2_MASKS (ISA_2_1_MASKS | OPTION_MASK_POPCNTB) +#define ISA_2_4_MASKS (ISA_2_2_MASKS | OPTION_MASK_FPRND) + + /* For ISA 2.05, do not add MFPGPR, since it isn't in ISA 2.06, and don't add + ALTIVEC, since in general it isn't a win on power6. In ISA 2.04, fsel, + fre, fsqrt, etc. were no longer documented as optional. Group masks by + server and embedded. */ +#define ISA_2_5_MASKS_EMBEDDED (ISA_2_2_MASKS \ + | OPTION_MASK_CMPB \ + | OPTION_MASK_RECIP_PRECISION \ + | OPTION_MASK_PPC_GFXOPT \ + | OPTION_MASK_PPC_GPOPT) + +#define ISA_2_5_MASKS_SERVER (ISA_2_5_MASKS_EMBEDDED | OPTION_MASK_DFP) + + /* For ISA 2.06, don't add ISEL, since in general it isn't a win, but + altivec is a win so enable it. */ +#define ISA_2_6_MASKS_EMBEDDED (ISA_2_5_MASKS_EMBEDDED | OPTION_MASK_POPCNTD) +#define ISA_2_6_MASKS_SERVER (ISA_2_5_MASKS_SERVER \ + | OPTION_MASK_POPCNTD \ + | OPTION_MASK_ALTIVEC \ + | OPTION_MASK_VSX) + +#define POWERPC_7400_MASK (OPTION_MASK_PPC_GFXOPT | OPTION_MASK_ALTIVEC) + +/* Mask of all options to set the default isa flags based on -mcpu=. */ +#define POWERPC_MASKS (OPTION_MASK_ALTIVEC \ + | OPTION_MASK_CMPB \ + | OPTION_MASK_DFP \ + | OPTION_MASK_DLMZB \ + | OPTION_MASK_FPRND \ + | OPTION_MASK_ISEL \ + | OPTION_MASK_MFCRF \ + | OPTION_MASK_MFPGPR \ + | OPTION_MASK_MULHW \ + | OPTION_MASK_NO_UPDATE \ + | OPTION_MASK_POPCNTB \ + | OPTION_MASK_POPCNTD \ + | OPTION_MASK_POWERPC64 \ + | OPTION_MASK_PPC_GFXOPT \ + | OPTION_MASK_PPC_GPOPT \ + | OPTION_MASK_RECIP_PRECISION \ + | OPTION_MASK_SOFT_FLOAT \ + | OPTION_MASK_STRICT_ALIGN \ + | OPTION_MASK_VSX) + +#endif + /* This table occasionally claims that a processor does not support a particular feature even though it does, but the feature is slower than the alternative. Thus, it shouldn't be relied on as a complete description of Index: gcc/config/rs6000/rs6000.c =================================================================== --- gcc/config/rs6000/rs6000.c (revision 192474) +++ gcc/config/rs6000/rs6000.c (working copy) @@ -1121,7 +1121,8 @@ static const struct attribute_spec rs600 { NULL, 0, 0, false, false, false, NULL, false } }; -#ifndef MASK_STRICT_ALIGN +#ifndef OPTION_MASK_STRICT_ALIGN +#define OPTION_MASK_STRICT_ALIGN 0 #define MASK_STRICT_ALIGN 0 #endif #ifndef TARGET_PROFILE_KERNEL @@ -1464,48 +1465,7 @@ static const struct attribute_spec rs600 #define TARGET_VECTORIZE_VEC_PERM_CONST_OK rs6000_vectorize_vec_perm_const_ok -/* Simplifications for entries below. */ - -enum { - POWERPC_7400_MASK = MASK_PPC_GFXOPT | MASK_ALTIVEC -}; - -/* Some OSs don't support saving the high part of 64-bit registers on context - switch. Other OSs don't support saving Altivec registers. On those OSs, we - don't touch the MASK_POWERPC64 or MASK_ALTIVEC settings; if the user wants - either, the user must explicitly specify them and we won't interfere with - the user's specification. */ - -enum { - POWERPC_MASKS = (MASK_PPC_GPOPT | MASK_STRICT_ALIGN - | MASK_PPC_GFXOPT | MASK_POWERPC64 | MASK_ALTIVEC - | MASK_MFCRF | MASK_POPCNTB | MASK_FPRND | MASK_MULHW - | MASK_DLMZB | MASK_CMPB | MASK_MFPGPR | MASK_DFP - | MASK_POPCNTD | MASK_VSX | MASK_ISEL | MASK_NO_UPDATE - | MASK_RECIP_PRECISION) -}; - -/* Masks for instructions set at various powerpc ISAs. */ -enum { - ISA_2_1_MASKS = MASK_MFCRF, - ISA_2_2_MASKS = (ISA_2_1_MASKS | MASK_POPCNTB), - ISA_2_4_MASKS = (ISA_2_2_MASKS | MASK_FPRND), - - /* For ISA 2.05, do not add MFPGPR, since it isn't in ISA 2.06, and don't add - ALTIVEC, since in general it isn't a win on power6. In ISA 2.04, fsel, - fre, fsqrt, etc. were no longer documented as optional. Group masks by - server and embedded. */ - ISA_2_5_MASKS_EMBEDDED = (ISA_2_2_MASKS | MASK_CMPB | MASK_RECIP_PRECISION - | MASK_PPC_GFXOPT | MASK_PPC_GPOPT), - ISA_2_5_MASKS_SERVER = (ISA_2_5_MASKS_EMBEDDED | MASK_DFP), - - /* For ISA 2.06, don't add ISEL, since in general it isn't a win, but - altivec is a win so enable it. */ - ISA_2_6_MASKS_EMBEDDED = (ISA_2_5_MASKS_EMBEDDED | MASK_POPCNTD), - ISA_2_6_MASKS_SERVER = (ISA_2_5_MASKS_SERVER | MASK_POPCNTD | MASK_ALTIVEC - | MASK_VSX) -}; - +/* Processor table. */ struct rs6000_ptt { const char *const name; /* Canonical processor name. */ @@ -2357,21 +2317,21 @@ darwin_rs6000_override_options (void) if (TARGET_64BIT && ! TARGET_POWERPC64) { - target_flags |= MASK_POWERPC64; + rs6000_isa_flags |= OPTION_MASK_POWERPC64; warning (0, "-m64 requires PowerPC64 architecture, enabling"); } if (flag_mkernel) { rs6000_default_long_calls = 1; - target_flags |= MASK_SOFT_FLOAT; + rs6000_isa_flags |= OPTION_MASK_SOFT_FLOAT; } /* Make -m64 imply -maltivec. Darwin's 64-bit ABI includes Altivec. */ if (!flag_mkernel && !flag_apple_kext && TARGET_64BIT - && ! (target_flags_explicit & MASK_ALTIVEC)) - target_flags |= MASK_ALTIVEC; + && ! (rs6000_isa_flags_explicit & OPTION_MASK_ALTIVEC)) + rs6000_isa_flags |= OPTION_MASK_ALTIVEC; /* Unless the user (not the configurer) has explicitly overridden it with -mcpu=G3 or -mno-altivec, then 10.5+ targets default to @@ -2379,10 +2339,10 @@ darwin_rs6000_override_options (void) if (!flag_mkernel && !flag_apple_kext && strverscmp (darwin_macosx_version_min, "10.5") >= 0 - && ! (target_flags_explicit & MASK_ALTIVEC) + && ! (rs6000_isa_flags_explicit & OPTION_MASK_ALTIVEC) && ! global_options_set.x_rs6000_cpu_index) { - target_flags |= MASK_ALTIVEC; + rs6000_isa_flags |= OPTION_MASK_ALTIVEC; } } #endif @@ -2463,18 +2423,24 @@ rs6000_option_override_internal (bool gl rs6000_pointer_size = 32; } - set_masks = POWERPC_MASKS | MASK_SOFT_FLOAT; + /* Some OSs don't support saving the high part of 64-bit registers on context + switch. Other OSs don't support saving Altivec registers. On those OSs, + we don't touch the OPTION_MASK_POWERPC64 or OPTION_MASK_ALTIVEC settings; + if the user wants either, the user must explicitly specify them and we + won't interfere with the user's specification. */ + + set_masks = POWERPC_MASKS; #ifdef OS_MISSING_POWERPC64 if (OS_MISSING_POWERPC64) - set_masks &= ~MASK_POWERPC64; + set_masks &= ~OPTION_MASK_POWERPC64; #endif #ifdef OS_MISSING_ALTIVEC if (OS_MISSING_ALTIVEC) - set_masks &= ~MASK_ALTIVEC; + set_masks &= ~(OPTION_MASK_ALTIVEC | OPTION_MASK_VSX); #endif /* Don't override by the processor default if given explicitly. */ - set_masks &= ~target_flags_explicit; + set_masks &= ~rs6000_isa_flags_explicit; /* Process the -mcpu= and -mtune= argument. If the user changed the cpu in a target attribute or pragma, but did not specify a tuning @@ -2512,13 +2478,18 @@ rs6000_option_override_internal (bool gl TARGET_DEFAULT. */ if (have_cpu) { - target_flags &= ~set_masks; - target_flags |= (processor_target_table[cpu_index].target_enable - & set_masks); + rs6000_isa_flags &= ~set_masks; + rs6000_isa_flags |= (processor_target_table[cpu_index].target_enable + & set_masks); } else - target_flags |= (processor_target_table[cpu_index].target_enable - & ~target_flags_explicit); + rs6000_isa_flags |= (processor_target_table[cpu_index].target_enable + & ~rs6000_isa_flags_explicit); + + /* If no -mcpu=, inherit any default options that were cleared via + POWERPC_MASKS. */ + if (!have_cpu) + rs6000_isa_flags |= (TARGET_DEFAULT & ~rs6000_isa_flags_explicit); if (rs6000_tune_index >= 0) tune_index = rs6000_tune_index; @@ -2603,7 +2574,8 @@ rs6000_option_override_internal (bool gl use instructions that would be microcoded on the Cell, use the load/store multiple and string instructions. */ if (BYTES_BIG_ENDIAN && optimize_size && rs6000_gen_cell_microcode) - target_flags |= ~target_flags_explicit & (MASK_MULTIPLE | MASK_STRING); + rs6000_isa_flags |= ~rs6000_isa_flags_explicit & (OPTION_MASK_MULTIPLE + | OPTION_MASK_STRING); /* Don't allow -mmultiple or -mstring on little endian systems unless the cpu is a 750, because the hardware doesn't support the @@ -2615,15 +2587,15 @@ rs6000_option_override_internal (bool gl { if (TARGET_MULTIPLE) { - target_flags &= ~MASK_MULTIPLE; - if ((target_flags_explicit & MASK_MULTIPLE) != 0) + rs6000_isa_flags &= ~OPTION_MASK_MULTIPLE; + if ((rs6000_isa_flags_explicit & OPTION_MASK_MULTIPLE) != 0) warning (0, "-mmultiple is not supported on little endian systems"); } if (TARGET_STRING) { - target_flags &= ~MASK_STRING; - if ((target_flags_explicit & MASK_STRING) != 0) + rs6000_isa_flags &= ~OPTION_MASK_STRING; + if ((rs6000_isa_flags_explicit & OPTION_MASK_STRING) != 0) warning (0, "-mstring is not supported on little endian systems"); } } @@ -2635,10 +2607,10 @@ rs6000_option_override_internal (bool gl if (!TARGET_HARD_FLOAT || !TARGET_FPRS || !TARGET_SINGLE_FLOAT || !TARGET_DOUBLE_FLOAT) { - if (target_flags_explicit & MASK_VSX) + if (rs6000_isa_flags_explicit & OPTION_MASK_VSX) msg = N_("-mvsx requires hardware floating point"); else - target_flags &= ~ MASK_VSX; + rs6000_isa_flags &= ~ OPTION_MASK_VSX; } else if (TARGET_PAIRED_FLOAT) msg = N_("-mvsx and -mpaired are incompatible"); @@ -2649,9 +2621,10 @@ rs6000_option_override_internal (bool gl msg = N_("-mvsx used with little endian code"); else if (TARGET_AVOID_XFORM > 0) msg = N_("-mvsx needs indexed addressing"); - else if (!TARGET_ALTIVEC && (target_flags_explicit & MASK_ALTIVEC)) + else if (!TARGET_ALTIVEC && (rs6000_isa_flags_explicit + & OPTION_MASK_ALTIVEC)) { - if (target_flags_explicit & MASK_VSX) + if (rs6000_isa_flags_explicit & OPTION_MASK_VSX) msg = N_("-mvsx and -mno-altivec are incompatible"); else msg = N_("-mno-altivec disables vsx"); @@ -2660,27 +2633,27 @@ rs6000_option_override_internal (bool gl if (msg) { warning (0, msg); - target_flags &= ~ MASK_VSX; - target_flags_explicit |= MASK_VSX; + rs6000_isa_flags &= ~ OPTION_MASK_VSX; + rs6000_isa_flags_explicit |= OPTION_MASK_VSX; } } /* For the newer switches (vsx, dfp, etc.) set some of the older options, unless the user explicitly used the -mno-