From patchwork Tue Oct 16 09:32:17 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 191783 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id EC3522C0084 for ; Tue, 16 Oct 2012 21:45:03 +1100 (EST) Received: from localhost ([::1]:53514 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TO3Wm-0004Yb-G4 for incoming@patchwork.ozlabs.org; Tue, 16 Oct 2012 05:33:32 -0400 Received: from eggs.gnu.org ([208.118.235.92]:40017) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TO3WW-0003u4-9D for qemu-devel@nongnu.org; Tue, 16 Oct 2012 05:33:23 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1TO3WJ-00011R-AR for qemu-devel@nongnu.org; Tue, 16 Oct 2012 05:33:12 -0400 Received: from mail-pb0-f45.google.com ([209.85.160.45]:36225) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TO3WI-0000jg-TA for qemu-devel@nongnu.org; Tue, 16 Oct 2012 05:33:03 -0400 Received: by mail-pb0-f45.google.com with SMTP id rp2so5757304pbb.4 for ; Tue, 16 Oct 2012 02:33:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=sender:from:to:cc:subject:date:message-id:x-mailer:in-reply-to :references; bh=ojwB8T7rFXQqj5bwUTCXxpaMU9ziNfqrtOCCueDgl64=; b=PkLCMkQIXyM15hASLN7enG1l/l5bDdq4j8hbH8TBpWf8bG8zJynIMsGT0f5Jw1u/dp mR67k502HKGj3jwghS6ZpP0ZzXQ2dBGVnkpWoSRqdtm2Q3JMmX/b9KNn6+KZH+X8vZPu Dm403wAJ+dHvCOS9nP61M/yj3SxnYHyz0MnlCpfqWazq9XVmP/vUedk/dV/BVGQ2Yv3x wW6TSeWRT9LzMnyi57HzHe80V+eXKhk2uKDlcuO/dqnD3guG0tuvbQPN/2G3DW93uKWW 0tNYQ+wwkkVaKW4AEee8ERSOmW6ooD1Qt4hzZYzG2NAt2TMX8o6XBH04gRvKfY1fsmH8 GmiQ== Received: by 10.66.87.132 with SMTP id ay4mr39786159pab.82.1350379982094; Tue, 16 Oct 2012 02:33:02 -0700 (PDT) Received: from pebble.twiddle.home ([1.141.46.32]) by mx.google.com with ESMTPS id n7sm10568078pav.26.2012.10.16.02.32.59 (version=TLSv1/SSLv3 cipher=OTHER); Tue, 16 Oct 2012 02:33:01 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 16 Oct 2012 19:32:17 +1000 Message-Id: <1350379951-17615-7-git-send-email-rth@twiddle.net> X-Mailer: git-send-email 1.7.11.7 In-Reply-To: <1350379951-17615-1-git-send-email-rth@twiddle.net> References: <1350379951-17615-1-git-send-email-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 209.85.160.45 Cc: blauwirbel@gmail.com Subject: [Qemu-devel] [PATCH 06/20] target-sparc: Finish conversion to gen_load_gpr X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org All users of gen_movl_{reg_TN,TN_reg} are removed. At the same time, make cpu_val a local variable for load/store disassembly. Signed-off-by: Richard Henderson --- target-sparc/translate.c | 58 +++++++++++++++++------------------------------- 1 file changed, 20 insertions(+), 38 deletions(-) diff --git a/target-sparc/translate.c b/target-sparc/translate.c index 8a2e914..3c9b0e3 100644 --- a/target-sparc/translate.c +++ b/target-sparc/translate.c @@ -48,7 +48,7 @@ static TCGv cpu_y; #ifndef CONFIG_USER_ONLY static TCGv cpu_tbr; #endif -static TCGv cpu_cond, cpu_dst, cpu_addr, cpu_val; +static TCGv cpu_cond, cpu_dst, cpu_addr; #ifdef TARGET_SPARC64 static TCGv_i32 cpu_xcc, cpu_asi, cpu_fprs; static TCGv cpu_gsr; @@ -308,28 +308,6 @@ static inline TCGv gen_dest_gpr(DisasContext *dc, int reg) } } -static inline void gen_movl_reg_TN(int reg, TCGv tn) -{ - if (reg == 0) - tcg_gen_movi_tl(tn, 0); - else if (reg < 8) - tcg_gen_mov_tl(tn, cpu_gregs[reg]); - else { - tcg_gen_ld_tl(tn, cpu_regwptr, (reg - 8) * sizeof(target_ulong)); - } -} - -static inline void gen_movl_TN_reg(int reg, TCGv tn) -{ - if (reg == 0) - return; - else if (reg < 8) - tcg_gen_mov_tl(cpu_gregs[reg], tn); - else { - tcg_gen_st_tl(tn, cpu_regwptr, (reg - 8) * sizeof(target_ulong)); - } -} - static inline void gen_goto_tb(DisasContext *s, int tb_num, target_ulong pc, target_ulong npc) { @@ -2127,24 +2105,28 @@ static inline void gen_stda_asi(DisasContext *dc, TCGv hi, TCGv addr, tcg_temp_free_i32(r_asi); } -static inline void gen_cas_asi(DisasContext *dc, TCGv dst, TCGv addr, +static inline void gen_cas_asi(DisasContext *dc, TCGv addr, TCGv val2, int insn, int rd) { - TCGv r_val1 = gen_load_gpr(dc, rd); + TCGv val1 = gen_load_gpr(dc, rd); + TCGv dst = gen_dest_gpr(dc, rd); TCGv_i32 r_asi = gen_get_asi(insn, addr); - gen_helper_cas_asi(dst, cpu_env, addr, r_val1, val2, r_asi); + gen_helper_cas_asi(dst, cpu_env, addr, val1, val2, r_asi); tcg_temp_free_i32(r_asi); + gen_store_gpr(dc, rd, dst); } -static inline void gen_casx_asi(DisasContext *dc, TCGv dst, TCGv addr, +static inline void gen_casx_asi(DisasContext *dc, TCGv addr, TCGv val2, int insn, int rd) { - TCGv r_val1 = gen_load_gpr(dc, rd); + TCGv val1 = gen_load_gpr(dc, rd); + TCGv dst = gen_dest_gpr(dc, rd); TCGv_i32 r_asi = gen_get_asi(insn, addr); - gen_helper_casx_asi(dst, cpu_env, addr, r_val1, val2, r_asi); + gen_helper_casx_asi(dst, cpu_env, addr, val1, val2, r_asi); tcg_temp_free_i32(r_asi); + gen_store_gpr(dc, rd, dst); } #elif !defined(CONFIG_USER_ONLY) @@ -4638,6 +4620,8 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn) if (xop < 4 || (xop > 7 && xop < 0x14 && xop != 0x0e) || (xop > 0x17 && xop <= 0x1d ) || (xop > 0x2c && xop <= 0x33) || xop == 0x1f || xop == 0x3d) { + TCGv cpu_val = gen_dest_gpr(dc, rd); + switch (xop) { case 0x0: /* ld, V9 lduw, load unsigned word */ gen_address_mask(dc, cpu_addr); @@ -4903,7 +4887,8 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn) } } else if (xop < 8 || (xop >= 0x14 && xop < 0x18) || xop == 0xe || xop == 0x1e) { - gen_movl_reg_TN(rd, cpu_val); + TCGv cpu_val = gen_load_gpr(dc, rd); + switch (xop) { case 0x4: /* st, store word */ gen_address_mask(dc, cpu_addr); @@ -4922,6 +4907,7 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn) goto illegal_insn; else { TCGv_i32 r_const; + TCGv lo; save_state(dc); gen_address_mask(dc, cpu_addr); @@ -4929,8 +4915,8 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn) /* XXX remove alignment check */ gen_helper_check_align(cpu_env, cpu_addr, r_const); tcg_temp_free_i32(r_const); - gen_movl_reg_TN(rd + 1, cpu_tmp0); - tcg_gen_concat_tl_i64(cpu_tmp64, cpu_tmp0, cpu_val); + lo = gen_load_gpr(dc, rd + 1); + tcg_gen_concat_tl_i64(cpu_tmp64, lo, cpu_val); tcg_gen_qemu_st64(cpu_tmp64, cpu_addr, dc->mem_idx); } break; @@ -5088,12 +5074,10 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn) gen_stf_asi(cpu_addr, insn, 8, DFPREG(rd)); break; case 0x3c: /* V9 casa */ - gen_cas_asi(dc, cpu_val, cpu_addr, cpu_src2, insn, rd); - gen_store_gpr(dc, rd, cpu_val); + gen_cas_asi(dc, cpu_addr, cpu_src2, insn, rd); break; case 0x3e: /* V9 casxa */ - gen_casx_asi(dc, cpu_val, cpu_addr, cpu_src2, insn, rd); - gen_store_gpr(dc, rd, cpu_val); + gen_casx_asi(dc, cpu_addr, cpu_src2, insn, rd); break; #else case 0x34: /* stc */ @@ -5269,14 +5253,12 @@ static inline void gen_intermediate_code_internal(TranslationBlock * tb, cpu_tmp32 = tcg_temp_new_i32(); cpu_tmp64 = tcg_temp_new_i64(); cpu_dst = tcg_temp_new(); - cpu_val = tcg_temp_new(); cpu_addr = tcg_temp_new(); disas_sparc_insn(dc, insn); num_insns++; tcg_temp_free(cpu_addr); - tcg_temp_free(cpu_val); tcg_temp_free(cpu_dst); tcg_temp_free_i64(cpu_tmp64); tcg_temp_free_i32(cpu_tmp32);