From patchwork Tue Oct 16 09:32:15 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 191772 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id E80A62C0089 for ; Tue, 16 Oct 2012 21:21:46 +1100 (EST) Received: from localhost ([::1]:53527 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TO3Wr-0004Yq-36 for incoming@patchwork.ozlabs.org; Tue, 16 Oct 2012 05:33:37 -0400 Received: from eggs.gnu.org ([208.118.235.92]:39992) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TO3WO-0003eW-4F for qemu-devel@nongnu.org; Tue, 16 Oct 2012 05:33:14 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1TO3WD-0000yX-6o for qemu-devel@nongnu.org; Tue, 16 Oct 2012 05:33:06 -0400 Received: from mail-da0-f45.google.com ([209.85.210.45]:48469) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TO3WC-0000rm-W5 for qemu-devel@nongnu.org; Tue, 16 Oct 2012 05:32:57 -0400 Received: by mail-da0-f45.google.com with SMTP id n15so3065165dad.4 for ; Tue, 16 Oct 2012 02:32:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=sender:from:to:cc:subject:date:message-id:x-mailer:in-reply-to :references; bh=lKtHyzSGHPAb8G3ovePrmdENRKM0UUGtppyK3+x31I4=; b=q7C1IdMKIUP8Xc82hdpQiBMT3PpT7YRME7BvE0hfX1D/e9yWC8ETD7epNeyk4ZjNgG UDJGx7yo6BAbxMJEMMcXFku68CqQGXeailDpeWT4xbCCtkIu418FkPwuSOcLcC702BGn MkoPTB5Nz4R49c048wPd7R0Eo+cL+2F9yx9wTxzCBg7UGOU6Rjvp0YaT5qci+Lnfc4v/ U93x+j49JKtquOdIPd5ITyiUFCrOj8MPYRBMmveCkrbKv8h4Pct66RyrUfX6cbR1r6wS wIhkTI0ZvW8R6E70xbiXnDaBV6mfMsyWWb5Bs1hViA+iBE+1QO2coZz6S3VLxba0kz1V GX4A== Received: by 10.68.232.71 with SMTP id tm7mr45263616pbc.118.1350379976624; Tue, 16 Oct 2012 02:32:56 -0700 (PDT) Received: from pebble.twiddle.home ([1.141.46.32]) by mx.google.com with ESMTPS id n7sm10568078pav.26.2012.10.16.02.32.54 (version=TLSv1/SSLv3 cipher=OTHER); Tue, 16 Oct 2012 02:32:56 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 16 Oct 2012 19:32:15 +1000 Message-Id: <1350379951-17615-5-git-send-email-rth@twiddle.net> X-Mailer: git-send-email 1.7.11.7 In-Reply-To: <1350379951-17615-1-git-send-email-rth@twiddle.net> References: <1350379951-17615-1-git-send-email-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 209.85.210.45 Cc: blauwirbel@gmail.com Subject: [Qemu-devel] [PATCH 04/20] target-sparc: Convert asi helpers to gen_*_gpr X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Push the DisasContext down so that we can use gen_load/store_gpr in sode gen_ldda_asi, gen_stda_ast, gen_cas_asi, gen_casx_asi. Signed-off-by: Richard Henderson --- target-sparc/translate.c | 61 +++++++++++++++++++++++++----------------------- 1 file changed, 32 insertions(+), 29 deletions(-) diff --git a/target-sparc/translate.c b/target-sparc/translate.c index 760cfd6..f4ab6cc 100644 --- a/target-sparc/translate.c +++ b/target-sparc/translate.c @@ -2101,7 +2101,8 @@ static inline void gen_swap_asi(TCGv dst, TCGv addr, int insn) tcg_gen_trunc_i64_tl(dst, cpu_tmp64); } -static inline void gen_ldda_asi(TCGv hi, TCGv addr, int insn, int rd) +static inline void gen_ldda_asi(DisasContext *dc, TCGv hi, TCGv addr, + int insn, int rd) { TCGv_i32 r_asi, r_rd; @@ -2112,12 +2113,13 @@ static inline void gen_ldda_asi(TCGv hi, TCGv addr, int insn, int rd) tcg_temp_free_i32(r_asi); } -static inline void gen_stda_asi(TCGv hi, TCGv addr, int insn, int rd) +static inline void gen_stda_asi(DisasContext *dc, TCGv hi, TCGv addr, + int insn, int rd) { TCGv_i32 r_asi, r_size; + TCGv lo = gen_load_gpr(dc, rd + 1); - gen_movl_reg_TN(rd + 1, cpu_tmp0); - tcg_gen_concat_tl_i64(cpu_tmp64, cpu_tmp0, hi); + tcg_gen_concat_tl_i64(cpu_tmp64, lo, hi); r_asi = gen_get_asi(insn, addr); r_size = tcg_const_i32(8); gen_helper_st_asi(cpu_env, addr, cpu_tmp64, r_asi, r_size); @@ -2125,28 +2127,23 @@ static inline void gen_stda_asi(TCGv hi, TCGv addr, int insn, int rd) tcg_temp_free_i32(r_asi); } -static inline void gen_cas_asi(TCGv dst, TCGv addr, TCGv val2, int insn, - int rd) +static inline void gen_cas_asi(DisasContext *dc, TCGv dst, TCGv addr, + TCGv val2, int insn, int rd) { - TCGv r_val1; - TCGv_i32 r_asi; + TCGv r_val1 = gen_load_gpr(dc, rd); + TCGv_i32 r_asi = gen_get_asi(insn, addr); - r_val1 = tcg_temp_new(); - gen_movl_reg_TN(rd, r_val1); - r_asi = gen_get_asi(insn, addr); gen_helper_cas_asi(dst, cpu_env, addr, r_val1, val2, r_asi); tcg_temp_free_i32(r_asi); - tcg_temp_free(r_val1); } -static inline void gen_casx_asi(TCGv dst, TCGv addr, TCGv val2, int insn, - int rd) +static inline void gen_casx_asi(DisasContext *dc, TCGv dst, TCGv addr, + TCGv val2, int insn, int rd) { - TCGv_i32 r_asi; + TCGv r_val1 = gen_load_gpr(dc, rd); + TCGv_i32 r_asi = gen_get_asi(insn, addr); - gen_movl_reg_TN(rd, cpu_tmp64); - r_asi = gen_get_asi(insn, addr); - gen_helper_casx_asi(dst, cpu_env, addr, cpu_tmp64, val2, r_asi); + gen_helper_casx_asi(dst, cpu_env, addr, r_val1, val2, r_asi); tcg_temp_free_i32(r_asi); } @@ -2198,9 +2195,11 @@ static inline void gen_swap_asi(TCGv dst, TCGv addr, int insn) tcg_gen_trunc_i64_tl(dst, cpu_tmp64); } -static inline void gen_ldda_asi(TCGv hi, TCGv addr, int insn, int rd) +static inline void gen_ldda_asi(DisasContext *dc, TCGv hi, TCGv addr, + int insn, int rd) { TCGv_i32 r_asi, r_size, r_sign; + TCGv t; r_asi = tcg_const_i32(GET_FIELD(insn, 19, 26)); r_size = tcg_const_i32(8); @@ -2209,19 +2208,23 @@ static inline void gen_ldda_asi(TCGv hi, TCGv addr, int insn, int rd) tcg_temp_free(r_sign); tcg_temp_free(r_size); tcg_temp_free(r_asi); - tcg_gen_trunc_i64_tl(cpu_tmp0, cpu_tmp64); - gen_movl_TN_reg(rd + 1, cpu_tmp0); + + t = gen_dest_gpr(dc, rd + 1); + tcg_gen_trunc_i64_tl(t, cpu_tmp64); + gen_store_gpr(dc, rd + 1, t); + tcg_gen_shri_i64(cpu_tmp64, cpu_tmp64, 32); tcg_gen_trunc_i64_tl(hi, cpu_tmp64); - gen_movl_TN_reg(rd, hi); + gen_store_gpr(dc, rd, hi); } -static inline void gen_stda_asi(TCGv hi, TCGv addr, int insn, int rd) +static inline void gen_stda_asi(DisasContext *dc, TCGv hi, TCGv addr, + int insn, int rd) { TCGv_i32 r_asi, r_size; + TCGv lo = gen_load_gpr(dc, rd + 1); - gen_movl_reg_TN(rd + 1, cpu_tmp0); - tcg_gen_concat_tl_i64(cpu_tmp64, cpu_tmp0, hi); + tcg_gen_concat_tl_i64(cpu_tmp64, lo, hi); r_asi = tcg_const_i32(GET_FIELD(insn, 19, 26)); r_size = tcg_const_i32(8); gen_helper_st_asi(cpu_env, addr, cpu_tmp64, r_asi, r_size); @@ -4738,7 +4741,7 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn) if (rd & 1) goto illegal_insn; save_state(dc); - gen_ldda_asi(cpu_val, cpu_addr, insn, rd); + gen_ldda_asi(dc, cpu_val, cpu_addr, insn, rd); goto skip_move; case 0x19: /* ldsba, load signed byte alternate */ #ifndef TARGET_SPARC64 @@ -4976,7 +4979,7 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn) goto illegal_insn; else { save_state(dc); - gen_stda_asi(cpu_val, cpu_addr, insn, rd); + gen_stda_asi(dc, cpu_val, cpu_addr, insn, rd); } break; #endif @@ -5085,11 +5088,11 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn) gen_stf_asi(cpu_addr, insn, 8, DFPREG(rd)); break; case 0x3c: /* V9 casa */ - gen_cas_asi(cpu_val, cpu_addr, cpu_src2, insn, rd); + gen_cas_asi(dc, cpu_val, cpu_addr, cpu_src2, insn, rd); gen_store_gpr(dc, rd, cpu_val); break; case 0x3e: /* V9 casxa */ - gen_casx_asi(cpu_val, cpu_addr, cpu_src2, insn, rd); + gen_casx_asi(dc, cpu_val, cpu_addr, cpu_src2, insn, rd); gen_store_gpr(dc, rd, cpu_val); break; #else