From patchwork Tue Oct 16 09:32:19 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 191771 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 463152C0084 for ; Tue, 16 Oct 2012 21:21:02 +1100 (EST) Received: from localhost ([::1]:53534 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TO3X3-0004a1-QX for incoming@patchwork.ozlabs.org; Tue, 16 Oct 2012 05:33:49 -0400 Received: from eggs.gnu.org ([208.118.235.92]:40043) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TO3WY-00045D-Ny for qemu-devel@nongnu.org; Tue, 16 Oct 2012 05:33:20 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1TO3WS-000148-S3 for qemu-devel@nongnu.org; Tue, 16 Oct 2012 05:33:16 -0400 Received: from mail-pa0-f45.google.com ([209.85.220.45]:64050) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TO3WS-00013K-1q for qemu-devel@nongnu.org; Tue, 16 Oct 2012 05:33:12 -0400 Received: by mail-pa0-f45.google.com with SMTP id fb10so5685873pad.4 for ; Tue, 16 Oct 2012 02:33:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=sender:from:to:cc:subject:date:message-id:x-mailer:in-reply-to :references; bh=zmszLn0ivT2e9i5K0r0UbnqTgyur/IwwXjkPxmAPqEk=; b=dxLCuTTrD5GAYyKz8Y9WpKLwpIWggwaJ3VUiGNmgeLg3t6jeBrAfDYvY2AyRw8gLmR 20g0vTCdv2Phi+ikmQFwEeRBrU/ylpm6JCHxP8l6D9i5S96+Amz7NxbZsk4dPioh6J3U leZ1qYeY9bKn7NpaxrttTs25qtJTJY+Is4BI9CBNHMkmjuTXaRVqj57ppc7s57iMei0Y KCl5DA0UM6YPt0Js9sSJ3kMgzrm84UjtyWUdNKF66mAKxCf2KA9IhuhsIVs07fCSZUjx NP+OItGDsT8q0MIH/brQszl8G85yrpZ5+VFnjEFI2FgZCS82QhG7MM6V2zWiOQaEmmqE biXg== Received: by 10.68.190.71 with SMTP id go7mr45453617pbc.66.1350379987395; Tue, 16 Oct 2012 02:33:07 -0700 (PDT) Received: from pebble.twiddle.home ([1.141.46.32]) by mx.google.com with ESMTPS id n7sm10568078pav.26.2012.10.16.02.33.05 (version=TLSv1/SSLv3 cipher=OTHER); Tue, 16 Oct 2012 02:33:06 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 16 Oct 2012 19:32:19 +1000 Message-Id: <1350379951-17615-9-git-send-email-rth@twiddle.net> X-Mailer: git-send-email 1.7.11.7 In-Reply-To: <1350379951-17615-1-git-send-email-rth@twiddle.net> References: <1350379951-17615-1-git-send-email-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 209.85.220.45 Cc: blauwirbel@gmail.com Subject: [Qemu-devel] [PATCH 08/20] target-sparc: Make the cpu_addr variable local to load/store handling X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Signed-off-by: Richard Henderson --- target-sparc/translate.c | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/target-sparc/translate.c b/target-sparc/translate.c index 2a95c1f..e3e4256 100644 --- a/target-sparc/translate.c +++ b/target-sparc/translate.c @@ -48,7 +48,7 @@ static TCGv cpu_y; #ifndef CONFIG_USER_ONLY static TCGv cpu_tbr; #endif -static TCGv cpu_cond, cpu_dst, cpu_addr; +static TCGv cpu_cond, cpu_dst; #ifdef TARGET_SPARC64 static TCGv_i32 cpu_xcc, cpu_asi, cpu_fprs; static TCGv cpu_gsr; @@ -4596,20 +4596,22 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn) case 3: /* load/store instructions */ { unsigned int xop = GET_FIELD(insn, 7, 12); + /* ??? gen_address_mask prevents us from using a source + register directly. Always generate a temporary. */ + TCGv cpu_addr = get_temp_tl(dc); - cpu_src1 = get_src1(dc, insn); - if (xop == 0x3c || xop == 0x3e) { // V9 casa/casxa - tcg_gen_mov_tl(cpu_addr, cpu_src1); + tcg_gen_mov_tl(cpu_addr, get_src1(dc, insn)); + if (xop == 0x3c || xop == 0x3e) { + /* V9 casa/casxa : no offset */ } else if (IS_IMM) { /* immediate */ simm = GET_FIELDs(insn, 19, 31); - tcg_gen_addi_tl(cpu_addr, cpu_src1, simm); + if (simm != 0) { + tcg_gen_addi_tl(cpu_addr, cpu_addr, simm); + } } else { /* register */ rs2 = GET_FIELD(insn, 27, 31); if (rs2 != 0) { - cpu_src2 = gen_load_gpr(dc, rs2); - tcg_gen_add_tl(cpu_addr, cpu_src1, cpu_src2); - } else { - tcg_gen_mov_tl(cpu_addr, cpu_src1); + tcg_gen_add_tl(cpu_addr, cpu_addr, gen_load_gpr(dc, rs2)); } } if (xop < 4 || (xop > 7 && xop < 0x14 && xop != 0x0e) || @@ -5251,12 +5253,10 @@ static inline void gen_intermediate_code_internal(TranslationBlock * tb, cpu_tmp32 = tcg_temp_new_i32(); cpu_tmp64 = tcg_temp_new_i64(); cpu_dst = tcg_temp_new(); - cpu_addr = tcg_temp_new(); disas_sparc_insn(dc, insn); num_insns++; - tcg_temp_free(cpu_addr); tcg_temp_free(cpu_dst); tcg_temp_free_i64(cpu_tmp64); tcg_temp_free_i32(cpu_tmp32);